1# SPDX-License-Identifier: GPL-2.0-only
  2#
  3# Memory devices
  4#
  5
  6menuconfig MEMORY
  7	bool "Memory Controller drivers"
  8	help
  9	  This option allows to enable specific memory controller drivers,
 10	  useful mostly on embedded systems.  These could be controllers
 11	  for DRAM (SDR, DDR), ROM, SRAM and others.  The drivers features
 12	  vary from memory tuning and frequency scaling to enabling
 13	  access to attached peripherals through memory bus.
 14
 15if MEMORY
 16
 17config DDR
 18	bool
 19	help
 20	  Data from JEDEC specs for DDR SDRAM memories,
 21	  particularly the AC timing parameters and addressing
 22	  information. This data is useful for drivers handling
 23	  DDR SDRAM controllers.
 24
 25config ARM_PL172_MPMC
 26	tristate "ARM PL172 MPMC driver"
 27	depends on ARM_AMBA && OF
 28	help
 29	  This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
 30	  If you have an embedded system with an AMBA bus and a PL172
 31	  controller, say Y or M here.
 32
 33config ATMEL_SDRAMC
 34	bool "Atmel (Multi-port DDR-)SDRAM Controller"
 35	default y if ARCH_AT91
 36	depends on ARCH_AT91 || COMPILE_TEST
 37	depends on OF
 38	help
 39	  This driver is for Atmel SDRAM Controller or Atmel Multi-port
 40	  DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
 41	  Starting with the at91sam9g45, this controller supports SDR, DDR and
 42	  LP-DDR memories.
 43
 44config ATMEL_EBI
 45	bool "Atmel EBI driver"
 46	default y if ARCH_AT91
 47	depends on ARCH_AT91 || COMPILE_TEST
 48	depends on OF
 49	select MFD_SYSCON
 50	select MFD_ATMEL_SMC
 51	help
 52	  Driver for Atmel EBI controller.
 53	  Used to configure the EBI (external bus interface) when the device-
 54	  tree is used. This bus supports NANDs, external ethernet controller,
 55	  SRAMs, ATA devices, etc.
 56
 57config BRCMSTB_DPFE
 58	tristate "Broadcom STB DPFE driver"
 59	default ARCH_BRCMSTB
 60	depends on ARCH_BRCMSTB || COMPILE_TEST
 61	help
 62	  This driver provides access to the DPFE interface of Broadcom
 63	  STB SoCs. The firmware running on the DCPU inside the DDR PHY can
 64	  provide current information about the system's RAM, for instance
 65	  the DRAM refresh rate. This can be used as an indirect indicator
 66	  for the DRAM's temperature. Slower refresh rate means cooler RAM,
 67	  higher refresh rate means hotter RAM.
 68
 69config BRCMSTB_MEMC
 70	tristate "Broadcom STB MEMC driver"
 71	default ARCH_BRCMSTB
 72	depends on ARCH_BRCMSTB || COMPILE_TEST
 73	help
 74	  This driver provides a way to configure the Broadcom STB memory
 75	  controller and specifically control the Self Refresh Power Down
 76	  (SRPD) inactivity timeout.
 77
 78config BT1_L2_CTL
 79	bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
 80	depends on MIPS_BAIKAL_T1 || COMPILE_TEST
 81	select MFD_SYSCON
 82	help
 83	  Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
 84	  resides Coherency Manager v2 with embedded 1MB L2-cache. It's
 85	  possible to tune the L2 cache performance up by setting the data,
 86	  tags and way-select latencies of RAM access. This driver provides a
 87	  dt properties-based and sysfs interface for it.
 88
 89config TI_AEMIF
 90	tristate "Texas Instruments AEMIF driver"
 91	depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
 92	depends on OF
 93	help
 94	  This driver is for the AEMIF module available in Texas Instruments
 95	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
 96	  is intended to provide a glue-less interface to a variety of
 97	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
 98	  of 256M bytes of any of these memories can be accessed at a given
 99	  time via four chip selects with 64M byte access per chip select.
100
101config TI_EMIF
102	tristate "Texas Instruments EMIF driver"
103	depends on ARCH_OMAP2PLUS || COMPILE_TEST
104	select DDR
105	help
106	  This driver is for the EMIF module available in Texas Instruments
107	  SoCs. EMIF is an SDRAM controller that, based on its revision,
108	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
109	  This driver takes care of only LPDDR2 memories presently. The
110	  functions of the driver includes re-configuring AC timing
111	  parameters and other settings during frequency, voltage and
112	  temperature changes
113
114config OMAP_GPMC
115	tristate "Texas Instruments OMAP SoC GPMC driver"
116	depends on OF_ADDRESS
117	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
118	select GPIOLIB
119	help
120	  This driver is for the General Purpose Memory Controller (GPMC)
121	  present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
122	  interfacing to a variety of asynchronous as well as synchronous
123	  memory drives like NOR, NAND, OneNAND, SRAM.
124
125config OMAP_GPMC_DEBUG
126	bool "Enable GPMC debug output and skip reset of GPMC during init"
127	depends on OMAP_GPMC
128	help
129	  Enables verbose debugging mostly to decode the bootloader provided
130	  timings. To preserve the bootloader provided timings, the reset
131	  of GPMC is skipped during init. Enable this during development to
132	  configure devices connected to the GPMC bus.
133
134	  NOTE: In addition to matching the register setup with the bootloader
135	  you also need to match the GPMC FCLK frequency used by the
136	  bootloader or else the GPMC timings won't be identical with the
137	  bootloader timings.
138
139config TI_EMIF_SRAM
140	tristate "Texas Instruments EMIF SRAM driver"
141	depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
142	depends on SRAM
143	help
144	  This driver is for the EMIF module available on Texas Instruments
145	  AM33XX and AM43XX SoCs and is required for PM. Certain parts of
146	  the EMIF PM code must run from on-chip SRAM late in the suspend
147	  sequence so this driver provides several relocatable PM functions
148	  for the SoC PM code to use.
149
150config FPGA_DFL_EMIF
151	tristate "FPGA DFL EMIF Driver"
152	depends on FPGA_DFL && HAS_IOMEM
153	help
154	  This driver is for the EMIF private feature implemented under
155	  FPGA Device Feature List (DFL) framework. It is used to expose
156	  memory interface status information as well as memory clearing
157	  control.
158
159config MVEBU_DEVBUS
160	bool "Marvell EBU Device Bus Controller"
161	default y if PLAT_ORION
162	depends on PLAT_ORION || COMPILE_TEST
163	depends on OF
164	help
165	  This driver is for the Device Bus controller available in some
166	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
167	  Armada 370 and Armada XP. This controller allows to handle flash
168	  devices such as NOR, NAND, SRAM, and FPGA.
169
170config FSL_CORENET_CF
171	tristate "Freescale CoreNet Error Reporting"
172	depends on FSL_SOC_BOOKE || COMPILE_TEST
173	help
174	  Say Y for reporting of errors from the Freescale CoreNet
175	  Coherency Fabric.  Errors reported include accesses to
176	  physical addresses that mapped by no local access window
177	  (LAW) or an invalid LAW, as well as bad cache state that
178	  represents a coherency violation.
179
180config FSL_IFC
181	bool "Freescale IFC driver" if COMPILE_TEST
182	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
183	depends on HAS_IOMEM
184
185config JZ4780_NEMC
186	bool "Ingenic JZ4780 SoC NEMC driver"
 
187	depends on MIPS || COMPILE_TEST
188	depends on HAS_IOMEM && OF
189	help
190	  This driver is for the NAND/External Memory Controller (NEMC) in
191	  the Ingenic JZ4780. This controller is used to handle external
192	  memory devices such as NAND and SRAM.
193
194config MTK_SMI
195	tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
196	depends on ARCH_MEDIATEK || COMPILE_TEST
197	help
198	  This driver is for the Memory Controller module in MediaTek SoCs,
199	  mainly help enable/disable iommu and control the power domain and
200	  clocks for each local arbiter.
201
202config DA8XX_DDRCTL
203	bool "Texas Instruments da8xx DDR2/mDDR driver"
204	depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
205	help
206	  This driver is for the DDR2/mDDR Memory Controller present on
207	  Texas Instruments da8xx SoCs. It's used to tweak various memory
208	  controller configuration options.
209
210config PL353_SMC
211	tristate "ARM PL35X Static Memory Controller(SMC) driver"
212	default y if ARM
213	depends on ARM || COMPILE_TEST
214	depends on ARM_AMBA
215	help
216	  This driver is for the ARM PL351/PL353 Static Memory
217	  Controller(SMC) module.
218
219config RENESAS_RPCIF
220	tristate "Renesas RPC-IF driver"
221	depends on ARCH_RENESAS || COMPILE_TEST
222	select REGMAP_MMIO
223	select RESET_CONTROLLER
224	help
225	  This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
226	  either SPI host or HyperFlash. You'll have to select individual
227	  components under the corresponding menu.
228
229config STM32_FMC2_EBI
230	tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
231	depends on MACH_STM32MP157 || COMPILE_TEST
232	select MFD_SYSCON
233	help
234	  Select this option to enable the STM32 FMC2 External Bus Interface
235	  controller. This driver configures the transactions with external
236	  devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
237	  SOCs containing the FMC2 External Bus Interface.
238
239source "drivers/memory/samsung/Kconfig"
240source "drivers/memory/tegra/Kconfig"
241
242endif

  1# SPDX-License-Identifier: GPL-2.0-only
  2#
  3# Memory devices
  4#
  5
  6menuconfig MEMORY
  7	bool "Memory Controller drivers"
 
 
 
 
 
 
  8
  9if MEMORY
 10
 11config DDR
 12	bool
 13	help
 14	  Data from JEDEC specs for DDR SDRAM memories,
 15	  particularly the AC timing parameters and addressing
 16	  information. This data is useful for drivers handling
 17	  DDR SDRAM controllers.
 18
 19config ARM_PL172_MPMC
 20	tristate "ARM PL172 MPMC driver"
 21	depends on ARM_AMBA && OF
 22	help
 23	  This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
 24	  If you have an embedded system with an AMBA bus and a PL172
 25	  controller, say Y or M here.
 26
 27config ATMEL_SDRAMC
 28	bool "Atmel (Multi-port DDR-)SDRAM Controller"
 29	default y
 30	depends on ARCH_AT91 && OF
 
 31	help
 32	  This driver is for Atmel SDRAM Controller or Atmel Multi-port
 33	  DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
 34	  Starting with the at91sam9g45, this controller supports SDR, DDR and
 35	  LP-DDR memories.
 36
 37config ATMEL_EBI
 38	bool "Atmel EBI driver"
 39	default y
 40	depends on ARCH_AT91 && OF
 
 41	select MFD_SYSCON
 42	select MFD_ATMEL_SMC
 43	help
 44	  Driver for Atmel EBI controller.
 45	  Used to configure the EBI (external bus interface) when the device-
 46	  tree is used. This bus supports NANDs, external ethernet controller,
 47	  SRAMs, ATA devices, etc.
 48
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 49config TI_AEMIF
 50	tristate "Texas Instruments AEMIF driver"
 51	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
 
 52	help
 53	  This driver is for the AEMIF module available in Texas Instruments
 54	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
 55	  is intended to provide a glue-less interface to a variety of
 56	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
 57	  of 256M bytes of any of these memories can be accessed at a given
 58	  time via four chip selects with 64M byte access per chip select.
 59
 60config TI_EMIF
 61	tristate "Texas Instruments EMIF driver"
 62	depends on ARCH_OMAP2PLUS
 63	select DDR
 64	help
 65	  This driver is for the EMIF module available in Texas Instruments
 66	  SoCs. EMIF is an SDRAM controller that, based on its revision,
 67	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
 68	  This driver takes care of only LPDDR2 memories presently. The
 69	  functions of the driver includes re-configuring AC timing
 70	  parameters and other settings during frequency, voltage and
 71	  temperature changes
 72
 73config OMAP_GPMC
 74	bool
 
 
 75	select GPIOLIB
 76	help
 77	  This driver is for the General Purpose Memory Controller (GPMC)
 78	  present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
 79	  interfacing to a variety of asynchronous as well as synchronous
 80	  memory drives like NOR, NAND, OneNAND, SRAM.
 81
 82config OMAP_GPMC_DEBUG
 83	bool "Enable GPMC debug output and skip reset of GPMC during init"
 84	depends on OMAP_GPMC
 85	help
 86	  Enables verbose debugging mostly to decode the bootloader provided
 87	  timings. To preserve the bootloader provided timings, the reset
 88	  of GPMC is skipped during init. Enable this during development to
 89	  configure devices connected to the GPMC bus.
 90
 91	  NOTE: In addition to matching the register setup with the bootloader
 92	  you also need to match the GPMC FCLK frequency used by the
 93	  bootloader or else the GPMC timings won't be identical with the
 94	  bootloader timings.
 95
 96config TI_EMIF_SRAM
 97	tristate "Texas Instruments EMIF SRAM driver"
 98	depends on (SOC_AM33XX || SOC_AM43XX) && SRAM
 
 99	help
100	  This driver is for the EMIF module available on Texas Instruments
101	  AM33XX and AM43XX SoCs and is required for PM. Certain parts of
102	  the EMIF PM code must run from on-chip SRAM late in the suspend
103	  sequence so this driver provides several relocatable PM functions
104	  for the SoC PM code to use.
105
 
 
 
 
 
 
 
 
 
106config MVEBU_DEVBUS
107	bool "Marvell EBU Device Bus Controller"
108	default y
109	depends on PLAT_ORION && OF
 
110	help
111	  This driver is for the Device Bus controller available in some
112	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
113	  Armada 370 and Armada XP. This controller allows to handle flash
114	  devices such as NOR, NAND, SRAM, and FPGA.
115
116config FSL_CORENET_CF
117	tristate "Freescale CoreNet Error Reporting"
118	depends on FSL_SOC_BOOKE
119	help
120	  Say Y for reporting of errors from the Freescale CoreNet
121	  Coherency Fabric.  Errors reported include accesses to
122	  physical addresses that mapped by no local access window
123	  (LAW) or an invalid LAW, as well as bad cache state that
124	  represents a coherency violation.
125
126config FSL_IFC
127	bool
128	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
129	depends on HAS_IOMEM
130
131config JZ4780_NEMC
132	bool "Ingenic JZ4780 SoC NEMC driver"
133	default y
134	depends on MIPS || COMPILE_TEST
135	depends on HAS_IOMEM && OF
136	help
137	  This driver is for the NAND/External Memory Controller (NEMC) in
138	  the Ingenic JZ4780. This controller is used to handle external
139	  memory devices such as NAND and SRAM.
140
141config MTK_SMI
142	bool
143	depends on ARCH_MEDIATEK || COMPILE_TEST
144	help
145	  This driver is for the Memory Controller module in MediaTek SoCs,
146	  mainly help enable/disable iommu and control the power domain and
147	  clocks for each local arbiter.
148
149config DA8XX_DDRCTL
150	bool "Texas Instruments da8xx DDR2/mDDR driver"
151	depends on ARCH_DAVINCI_DA8XX
152	help
153	  This driver is for the DDR2/mDDR Memory Controller present on
154	  Texas Instruments da8xx SoCs. It's used to tweak various memory
155	  controller configuration options.
156
157config PL353_SMC
158	tristate "ARM PL35X Static Memory Controller(SMC) driver"
159	default y
160	depends on ARM
161	depends on ARM_AMBA
162	help
163	  This driver is for the ARM PL351/PL353 Static Memory
164	  Controller(SMC) module.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
165
166source "drivers/memory/samsung/Kconfig"
167source "drivers/memory/tegra/Kconfig"
168
169endif