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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_PRIV_H
7#define _CORESIGHT_PRIV_H
8
9#include <linux/amba/bus.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/coresight.h>
13#include <linux/pm_runtime.h>
14
15/*
16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
18 * Trace registers in PFTv1.1
19 */
20#define CORESIGHT_ITCTRL 0xf00
21#define CORESIGHT_CLAIMSET 0xfa0
22#define CORESIGHT_CLAIMCLR 0xfa4
23#define CORESIGHT_LAR 0xfb0
24#define CORESIGHT_LSR 0xfb4
25#define CORESIGHT_DEVARCH 0xfbc
26#define CORESIGHT_AUTHSTATUS 0xfb8
27#define CORESIGHT_DEVID 0xfc8
28#define CORESIGHT_DEVTYPE 0xfcc
29
30
31/*
32 * Coresight device CLAIM protocol.
33 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
34 */
35#define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
36
37#define TIMEOUT_US 100
38#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
39
40#define ETM_MODE_EXCL_KERN BIT(30)
41#define ETM_MODE_EXCL_USER BIT(31)
42struct cs_pair_attribute {
43 struct device_attribute attr;
44 u32 lo_off;
45 u32 hi_off;
46};
47
48struct cs_off_attribute {
49 struct device_attribute attr;
50 u32 off;
51};
52
53extern ssize_t coresight_simple_show32(struct device *_dev,
54 struct device_attribute *attr, char *buf);
55extern ssize_t coresight_simple_show_pair(struct device *_dev,
56 struct device_attribute *attr, char *buf);
57
58#define coresight_simple_reg32(name, offset) \
59 (&((struct cs_off_attribute[]) { \
60 { \
61 __ATTR(name, 0444, coresight_simple_show32, NULL), \
62 offset \
63 } \
64 })[0].attr.attr)
65
66#define coresight_simple_reg64(name, lo_off, hi_off) \
67 (&((struct cs_pair_attribute[]) { \
68 { \
69 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
70 lo_off, hi_off \
71 } \
72 })[0].attr.attr)
73
74extern const u32 coresight_barrier_pkt[4];
75#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
76
77enum etm_addr_type {
78 ETM_ADDR_TYPE_NONE,
79 ETM_ADDR_TYPE_SINGLE,
80 ETM_ADDR_TYPE_RANGE,
81 ETM_ADDR_TYPE_START,
82 ETM_ADDR_TYPE_STOP,
83};
84
85enum cs_mode {
86 CS_MODE_DISABLED,
87 CS_MODE_SYSFS,
88 CS_MODE_PERF,
89};
90
91/**
92 * struct cs_buffer - keep track of a recording session' specifics
93 * @cur: index of the current buffer
94 * @nr_pages: max number of pages granted to us
95 * @pid: PID this cs_buffer belongs to
96 * @offset: offset within the current buffer
97 * @data_size: how much we collected in this run
98 * @snapshot: is this run in snapshot mode
99 * @data_pages: a handle the ring buffer
100 */
101struct cs_buffers {
102 unsigned int cur;
103 unsigned int nr_pages;
104 pid_t pid;
105 unsigned long offset;
106 local_t data_size;
107 bool snapshot;
108 void **data_pages;
109};
110
111static inline void coresight_insert_barrier_packet(void *buf)
112{
113 if (buf)
114 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
115}
116
117static inline void CS_LOCK(void __iomem *addr)
118{
119 do {
120 /* Wait for things to settle */
121 mb();
122 writel_relaxed(0x0, addr + CORESIGHT_LAR);
123 } while (0);
124}
125
126static inline void CS_UNLOCK(void __iomem *addr)
127{
128 do {
129 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
130 /* Make sure everyone has seen this */
131 mb();
132 } while (0);
133}
134
135void coresight_disable_path(struct list_head *path);
136int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
137struct coresight_device *coresight_get_sink(struct list_head *path);
138struct coresight_device *
139coresight_get_enabled_sink(struct coresight_device *source);
140struct coresight_device *coresight_get_sink_by_id(u32 id);
141struct coresight_device *
142coresight_find_default_sink(struct coresight_device *csdev);
143struct list_head *coresight_build_path(struct coresight_device *csdev,
144 struct coresight_device *sink);
145void coresight_release_path(struct list_head *path);
146int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
147void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
148int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
149void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
150int coresight_make_links(struct coresight_device *orig,
151 struct coresight_connection *conn,
152 struct coresight_device *target);
153void coresight_remove_links(struct coresight_device *orig,
154 struct coresight_connection *conn);
155
156#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
157extern int etm_readl_cp14(u32 off, unsigned int *val);
158extern int etm_writel_cp14(u32 off, u32 val);
159#else
160static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
161static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
162#endif
163
164struct cti_assoc_op {
165 void (*add)(struct coresight_device *csdev);
166 void (*remove)(struct coresight_device *csdev);
167};
168
169extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
170extern void coresight_remove_cti_ops(void);
171
172/*
173 * Macros and inline functions to handle CoreSight UCI data and driver
174 * private data in AMBA ID table entries, and extract data values.
175 */
176
177/* coresight AMBA ID, no UCI, no driver data: id table entry */
178#define CS_AMBA_ID(pid) \
179 { \
180 .id = pid, \
181 .mask = 0x000fffff, \
182 }
183
184/* coresight AMBA ID, UCI with driver data only: id table entry. */
185#define CS_AMBA_ID_DATA(pid, dval) \
186 { \
187 .id = pid, \
188 .mask = 0x000fffff, \
189 .data = (void *)&(struct amba_cs_uci_id) \
190 { \
191 .data = (void *)dval, \
192 } \
193 }
194
195/* coresight AMBA ID, full UCI structure: id table entry. */
196#define CS_AMBA_UCI_ID(pid, uci_ptr) \
197 { \
198 .id = pid, \
199 .mask = 0x000fffff, \
200 .data = (void *)uci_ptr \
201 }
202
203/* extract the data value from a UCI structure given amba_id pointer. */
204static inline void *coresight_get_uci_data(const struct amba_id *id)
205{
206 struct amba_cs_uci_id *uci_id = id->data;
207
208 if (!uci_id)
209 return NULL;
210
211 return uci_id->data;
212}
213
214void coresight_release_platform_data(struct coresight_device *csdev,
215 struct coresight_platform_data *pdata);
216struct coresight_device *
217coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
218void coresight_set_assoc_ectdev_mutex(struct coresight_device *csdev,
219 struct coresight_device *ect_csdev);
220
221void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
222struct coresight_device *coresight_get_percpu_sink(int cpu);
223
224#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_PRIV_H
7#define _CORESIGHT_PRIV_H
8
9#include <linux/amba/bus.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/coresight.h>
13#include <linux/pm_runtime.h>
14
15/*
16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
18 * Trace registers in PFTv1.1
19 */
20#define CORESIGHT_ITCTRL 0xf00
21#define CORESIGHT_CLAIMSET 0xfa0
22#define CORESIGHT_CLAIMCLR 0xfa4
23#define CORESIGHT_LAR 0xfb0
24#define CORESIGHT_LSR 0xfb4
25#define CORESIGHT_AUTHSTATUS 0xfb8
26#define CORESIGHT_DEVID 0xfc8
27#define CORESIGHT_DEVTYPE 0xfcc
28
29
30/*
31 * Coresight device CLAIM protocol.
32 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
33 */
34#define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
35
36#define TIMEOUT_US 100
37#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
38
39#define ETM_MODE_EXCL_KERN BIT(30)
40#define ETM_MODE_EXCL_USER BIT(31)
41
42typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
43#define __coresight_simple_func(type, func, name, lo_off, hi_off) \
44static ssize_t name##_show(struct device *_dev, \
45 struct device_attribute *attr, char *buf) \
46{ \
47 type *drvdata = dev_get_drvdata(_dev->parent); \
48 coresight_read_fn fn = func; \
49 u64 val; \
50 pm_runtime_get_sync(_dev->parent); \
51 if (fn) \
52 val = (u64)fn(_dev->parent, lo_off); \
53 else \
54 val = coresight_read_reg_pair(drvdata->base, \
55 lo_off, hi_off); \
56 pm_runtime_put_sync(_dev->parent); \
57 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \
58} \
59static DEVICE_ATTR_RO(name)
60
61#define coresight_simple_func(type, func, name, offset) \
62 __coresight_simple_func(type, func, name, offset, -1)
63#define coresight_simple_reg32(type, name, offset) \
64 __coresight_simple_func(type, NULL, name, offset, -1)
65#define coresight_simple_reg64(type, name, lo_off, hi_off) \
66 __coresight_simple_func(type, NULL, name, lo_off, hi_off)
67
68extern const u32 barrier_pkt[4];
69#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(barrier_pkt))
70
71enum etm_addr_type {
72 ETM_ADDR_TYPE_NONE,
73 ETM_ADDR_TYPE_SINGLE,
74 ETM_ADDR_TYPE_RANGE,
75 ETM_ADDR_TYPE_START,
76 ETM_ADDR_TYPE_STOP,
77};
78
79enum cs_mode {
80 CS_MODE_DISABLED,
81 CS_MODE_SYSFS,
82 CS_MODE_PERF,
83};
84
85/**
86 * struct cs_buffer - keep track of a recording session' specifics
87 * @cur: index of the current buffer
88 * @nr_pages: max number of pages granted to us
89 * @offset: offset within the current buffer
90 * @data_size: how much we collected in this run
91 * @snapshot: is this run in snapshot mode
92 * @data_pages: a handle the ring buffer
93 */
94struct cs_buffers {
95 unsigned int cur;
96 unsigned int nr_pages;
97 unsigned long offset;
98 local_t data_size;
99 bool snapshot;
100 void **data_pages;
101};
102
103static inline void coresight_insert_barrier_packet(void *buf)
104{
105 if (buf)
106 memcpy(buf, barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
107}
108
109
110static inline void CS_LOCK(void __iomem *addr)
111{
112 do {
113 /* Wait for things to settle */
114 mb();
115 writel_relaxed(0x0, addr + CORESIGHT_LAR);
116 } while (0);
117}
118
119static inline void CS_UNLOCK(void __iomem *addr)
120{
121 do {
122 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
123 /* Make sure everyone has seen this */
124 mb();
125 } while (0);
126}
127
128static inline u64
129coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
130{
131 u64 val;
132
133 val = readl_relaxed(addr + lo_offset);
134 val |= (hi_offset < 0) ? 0 :
135 (u64)readl_relaxed(addr + hi_offset) << 32;
136 return val;
137}
138
139static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
140 s32 lo_offset, s32 hi_offset)
141{
142 writel_relaxed((u32)val, addr + lo_offset);
143 if (hi_offset >= 0)
144 writel_relaxed((u32)(val >> 32), addr + hi_offset);
145}
146
147void coresight_disable_path(struct list_head *path);
148int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
149struct coresight_device *coresight_get_sink(struct list_head *path);
150struct coresight_device *coresight_get_enabled_sink(bool reset);
151struct coresight_device *coresight_get_sink_by_id(u32 id);
152struct list_head *coresight_build_path(struct coresight_device *csdev,
153 struct coresight_device *sink);
154void coresight_release_path(struct list_head *path);
155
156#ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
157extern int etm_readl_cp14(u32 off, unsigned int *val);
158extern int etm_writel_cp14(u32 off, u32 val);
159#else
160static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
161static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
162#endif
163
164/*
165 * Macros and inline functions to handle CoreSight UCI data and driver
166 * private data in AMBA ID table entries, and extract data values.
167 */
168
169/* coresight AMBA ID, no UCI, no driver data: id table entry */
170#define CS_AMBA_ID(pid) \
171 { \
172 .id = pid, \
173 .mask = 0x000fffff, \
174 }
175
176/* coresight AMBA ID, UCI with driver data only: id table entry. */
177#define CS_AMBA_ID_DATA(pid, dval) \
178 { \
179 .id = pid, \
180 .mask = 0x000fffff, \
181 .data = (void *)&(struct amba_cs_uci_id) \
182 { \
183 .data = (void *)dval, \
184 } \
185 }
186
187/* coresight AMBA ID, full UCI structure: id table entry. */
188#define CS_AMBA_UCI_ID(pid, uci_ptr) \
189 { \
190 .id = pid, \
191 .mask = 0x000fffff, \
192 .data = (void *)uci_ptr \
193 }
194
195/* extract the data value from a UCI structure given amba_id pointer. */
196static inline void *coresight_get_uci_data(const struct amba_id *id)
197{
198 if (id->data)
199 return ((struct amba_cs_uci_id *)(id->data))->data;
200 return 0;
201}
202
203void coresight_release_platform_data(struct coresight_platform_data *pdata);
204
205#endif