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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 SiFive
4 */
5
6#include <linux/bitops.h>
7#include <linux/device.h>
8#include <linux/errno.h>
9#include <linux/of_irq.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/regmap.h>
16
17#define SIFIVE_GPIO_INPUT_VAL 0x00
18#define SIFIVE_GPIO_INPUT_EN 0x04
19#define SIFIVE_GPIO_OUTPUT_EN 0x08
20#define SIFIVE_GPIO_OUTPUT_VAL 0x0C
21#define SIFIVE_GPIO_RISE_IE 0x18
22#define SIFIVE_GPIO_RISE_IP 0x1C
23#define SIFIVE_GPIO_FALL_IE 0x20
24#define SIFIVE_GPIO_FALL_IP 0x24
25#define SIFIVE_GPIO_HIGH_IE 0x28
26#define SIFIVE_GPIO_HIGH_IP 0x2C
27#define SIFIVE_GPIO_LOW_IE 0x30
28#define SIFIVE_GPIO_LOW_IP 0x34
29#define SIFIVE_GPIO_OUTPUT_XOR 0x40
30
31#define SIFIVE_GPIO_MAX 32
32
33struct sifive_gpio {
34 void __iomem *base;
35 struct gpio_chip gc;
36 struct regmap *regs;
37 unsigned long irq_state;
38 unsigned int trigger[SIFIVE_GPIO_MAX];
39 unsigned int irq_number[SIFIVE_GPIO_MAX];
40};
41
42static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
43{
44 unsigned long flags;
45 unsigned int trigger;
46
47 raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
48 trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
49 regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
50 (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
51 regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
52 (trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
53 regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
54 (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
55 regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
56 (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
57 raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
58}
59
60static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
61{
62 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
63 struct sifive_gpio *chip = gpiochip_get_data(gc);
64 int offset = irqd_to_hwirq(d);
65
66 if (offset < 0 || offset >= gc->ngpio)
67 return -EINVAL;
68
69 chip->trigger[offset] = trigger;
70 sifive_gpio_set_ie(chip, offset);
71 return 0;
72}
73
74static void sifive_gpio_irq_enable(struct irq_data *d)
75{
76 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
77 struct sifive_gpio *chip = gpiochip_get_data(gc);
78 irq_hw_number_t hwirq = irqd_to_hwirq(d);
79 int offset = hwirq % SIFIVE_GPIO_MAX;
80 u32 bit = BIT(offset);
81 unsigned long flags;
82
83 gpiochip_enable_irq(gc, hwirq);
84 irq_chip_enable_parent(d);
85
86 /* Switch to input */
87 gc->direction_input(gc, offset);
88
89 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
90 /* Clear any sticky pending interrupts */
91 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
92 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
93 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
94 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
95 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
96
97 /* Enable interrupts */
98 assign_bit(offset, &chip->irq_state, 1);
99 sifive_gpio_set_ie(chip, offset);
100}
101
102static void sifive_gpio_irq_disable(struct irq_data *d)
103{
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105 struct sifive_gpio *chip = gpiochip_get_data(gc);
106 irq_hw_number_t hwirq = irqd_to_hwirq(d);
107 int offset = hwirq % SIFIVE_GPIO_MAX;
108
109 assign_bit(offset, &chip->irq_state, 0);
110 sifive_gpio_set_ie(chip, offset);
111 irq_chip_disable_parent(d);
112 gpiochip_disable_irq(gc, hwirq);
113}
114
115static void sifive_gpio_irq_eoi(struct irq_data *d)
116{
117 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
118 struct sifive_gpio *chip = gpiochip_get_data(gc);
119 int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
120 u32 bit = BIT(offset);
121 unsigned long flags;
122
123 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
124 /* Clear all pending interrupts */
125 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
126 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
127 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
128 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
129 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
130
131 irq_chip_eoi_parent(d);
132}
133
134static int sifive_gpio_irq_set_affinity(struct irq_data *data,
135 const struct cpumask *dest,
136 bool force)
137{
138 if (data->parent_data)
139 return irq_chip_set_affinity_parent(data, dest, force);
140
141 return -EINVAL;
142}
143
144static const struct irq_chip sifive_gpio_irqchip = {
145 .name = "sifive-gpio",
146 .irq_set_type = sifive_gpio_irq_set_type,
147 .irq_mask = irq_chip_mask_parent,
148 .irq_unmask = irq_chip_unmask_parent,
149 .irq_enable = sifive_gpio_irq_enable,
150 .irq_disable = sifive_gpio_irq_disable,
151 .irq_eoi = sifive_gpio_irq_eoi,
152 .irq_set_affinity = sifive_gpio_irq_set_affinity,
153 .flags = IRQCHIP_IMMUTABLE,
154 GPIOCHIP_IRQ_RESOURCE_HELPERS,
155};
156
157static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
158 unsigned int child,
159 unsigned int child_type,
160 unsigned int *parent,
161 unsigned int *parent_type)
162{
163 struct sifive_gpio *chip = gpiochip_get_data(gc);
164 struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);
165
166 *parent_type = IRQ_TYPE_NONE;
167 *parent = irqd_to_hwirq(d);
168
169 return 0;
170}
171
172static const struct regmap_config sifive_gpio_regmap_config = {
173 .reg_bits = 32,
174 .reg_stride = 4,
175 .val_bits = 32,
176 .fast_io = true,
177 .disable_locking = true,
178};
179
180static int sifive_gpio_probe(struct platform_device *pdev)
181{
182 struct device *dev = &pdev->dev;
183 struct device_node *node = pdev->dev.of_node;
184 struct device_node *irq_parent;
185 struct irq_domain *parent;
186 struct gpio_irq_chip *girq;
187 struct sifive_gpio *chip;
188 int ret, ngpio, i;
189
190 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
191 if (!chip)
192 return -ENOMEM;
193
194 chip->base = devm_platform_ioremap_resource(pdev, 0);
195 if (IS_ERR(chip->base)) {
196 dev_err(dev, "failed to allocate device memory\n");
197 return PTR_ERR(chip->base);
198 }
199
200 chip->regs = devm_regmap_init_mmio(dev, chip->base,
201 &sifive_gpio_regmap_config);
202 if (IS_ERR(chip->regs))
203 return PTR_ERR(chip->regs);
204
205 ngpio = of_irq_count(node);
206 if (ngpio > SIFIVE_GPIO_MAX) {
207 dev_err(dev, "Too many GPIO interrupts (max=%d)\n",
208 SIFIVE_GPIO_MAX);
209 return -ENXIO;
210 }
211
212 irq_parent = of_irq_find_parent(node);
213 if (!irq_parent) {
214 dev_err(dev, "no IRQ parent node\n");
215 return -ENODEV;
216 }
217 parent = irq_find_host(irq_parent);
218 of_node_put(irq_parent);
219 if (!parent) {
220 dev_err(dev, "no IRQ parent domain\n");
221 return -ENODEV;
222 }
223
224 for (i = 0; i < ngpio; i++)
225 chip->irq_number[i] = platform_get_irq(pdev, i);
226
227 ret = bgpio_init(&chip->gc, dev, 4,
228 chip->base + SIFIVE_GPIO_INPUT_VAL,
229 chip->base + SIFIVE_GPIO_OUTPUT_VAL,
230 NULL,
231 chip->base + SIFIVE_GPIO_OUTPUT_EN,
232 chip->base + SIFIVE_GPIO_INPUT_EN,
233 BGPIOF_READ_OUTPUT_REG_SET);
234 if (ret) {
235 dev_err(dev, "unable to init generic GPIO\n");
236 return ret;
237 }
238
239 /* Disable all GPIO interrupts before enabling parent interrupts */
240 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
241 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
242 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
243 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
244 chip->irq_state = 0;
245
246 chip->gc.base = -1;
247 chip->gc.ngpio = ngpio;
248 chip->gc.label = dev_name(dev);
249 chip->gc.parent = dev;
250 chip->gc.owner = THIS_MODULE;
251 girq = &chip->gc.irq;
252 gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
253 girq->fwnode = of_node_to_fwnode(node);
254 girq->parent_domain = parent;
255 girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
256 girq->handler = handle_bad_irq;
257 girq->default_type = IRQ_TYPE_NONE;
258
259 platform_set_drvdata(pdev, chip);
260 return gpiochip_add_data(&chip->gc, chip);
261}
262
263static const struct of_device_id sifive_gpio_match[] = {
264 { .compatible = "sifive,gpio0" },
265 { .compatible = "sifive,fu540-c000-gpio" },
266 { },
267};
268
269static struct platform_driver sifive_gpio_driver = {
270 .probe = sifive_gpio_probe,
271 .driver = {
272 .name = "sifive_gpio",
273 .of_match_table = of_match_ptr(sifive_gpio_match),
274 },
275};
276builtin_platform_driver(sifive_gpio_driver)