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1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
3 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
6
7enum qcom_scm_convention {
8 SMC_CONVENTION_UNKNOWN,
9 SMC_CONVENTION_LEGACY,
10 SMC_CONVENTION_ARM_32,
11 SMC_CONVENTION_ARM_64,
12};
13
14extern enum qcom_scm_convention qcom_scm_convention;
15
16#define MAX_QCOM_SCM_ARGS 10
17#define MAX_QCOM_SCM_RETS 3
18
19enum qcom_scm_arg_types {
20 QCOM_SCM_VAL,
21 QCOM_SCM_RO,
22 QCOM_SCM_RW,
23 QCOM_SCM_BUFVAL,
24};
25
26#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
27 (((a) & 0x3) << 4) | \
28 (((b) & 0x3) << 6) | \
29 (((c) & 0x3) << 8) | \
30 (((d) & 0x3) << 10) | \
31 (((e) & 0x3) << 12) | \
32 (((f) & 0x3) << 14) | \
33 (((g) & 0x3) << 16) | \
34 (((h) & 0x3) << 18) | \
35 (((i) & 0x3) << 20) | \
36 (((j) & 0x3) << 22) | \
37 ((num) & 0xf))
38
39#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
40
41
42/**
43 * struct qcom_scm_desc
44 * @arginfo: Metadata describing the arguments in args[]
45 * @args: The array of arguments for the secure syscall
46 */
47struct qcom_scm_desc {
48 u32 svc;
49 u32 cmd;
50 u32 arginfo;
51 u64 args[MAX_QCOM_SCM_ARGS];
52 u32 owner;
53};
54
55/**
56 * struct qcom_scm_res
57 * @result: The values returned by the secure syscall
58 */
59struct qcom_scm_res {
60 u64 result[MAX_QCOM_SCM_RETS];
61};
62
63#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
64extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
65 enum qcom_scm_convention qcom_convention,
66 struct qcom_scm_res *res, bool atomic);
67#define scm_smc_call(dev, desc, res, atomic) \
68 __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
69
70#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
71extern int scm_legacy_call_atomic(struct device *dev,
72 const struct qcom_scm_desc *desc,
73 struct qcom_scm_res *res);
74extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
75 struct qcom_scm_res *res);
76
77#define QCOM_SCM_SVC_BOOT 0x01
78#define QCOM_SCM_BOOT_SET_ADDR 0x01
79#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
80#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
81#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
82#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
83#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
84#define QCOM_SCM_BOOT_MAX_CPUS 4
85#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0)
86#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1)
87#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2)
88
89#define QCOM_SCM_SVC_PIL 0x02
90#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
91#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
92#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
93#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
94#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
95#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
96
97#define QCOM_SCM_SVC_IO 0x05
98#define QCOM_SCM_IO_READ 0x01
99#define QCOM_SCM_IO_WRITE 0x02
100
101#define QCOM_SCM_SVC_INFO 0x06
102#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
103
104#define QCOM_SCM_SVC_MP 0x0c
105#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
106#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
107#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
108#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05
109#define QCOM_SCM_MP_VIDEO_VAR 0x08
110#define QCOM_SCM_MP_ASSIGN 0x16
111
112#define QCOM_SCM_SVC_OCMEM 0x0f
113#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
114#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
115
116#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
117#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
118#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
119
120#define QCOM_SCM_SVC_HDCP 0x11
121#define QCOM_SCM_HDCP_INVOKE 0x01
122
123#define QCOM_SCM_SVC_LMH 0x13
124#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
125#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
126
127#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
128#define QCOM_SCM_SMMU_PT_FORMAT 0x01
129#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
130#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
131
132/* common error codes */
133#define QCOM_SCM_V2_EBUSY -12
134#define QCOM_SCM_ENOMEM -5
135#define QCOM_SCM_EOPNOTSUPP -4
136#define QCOM_SCM_EINVAL_ADDR -3
137#define QCOM_SCM_EINVAL_ARG -2
138#define QCOM_SCM_ERROR -1
139#define QCOM_SCM_INTERRUPTED 1
140
141static inline int qcom_scm_remap_error(int err)
142{
143 switch (err) {
144 case QCOM_SCM_ERROR:
145 return -EIO;
146 case QCOM_SCM_EINVAL_ADDR:
147 case QCOM_SCM_EINVAL_ARG:
148 return -EINVAL;
149 case QCOM_SCM_EOPNOTSUPP:
150 return -EOPNOTSUPP;
151 case QCOM_SCM_ENOMEM:
152 return -ENOMEM;
153 case QCOM_SCM_V2_EBUSY:
154 return -EBUSY;
155 }
156 return -EINVAL;
157}
158
159#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
3 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
6
7#define QCOM_SCM_SVC_BOOT 0x1
8#define QCOM_SCM_BOOT_ADDR 0x1
9#define QCOM_SCM_SET_DLOAD_MODE 0x10
10#define QCOM_SCM_BOOT_ADDR_MC 0x11
11#define QCOM_SCM_SET_REMOTE_STATE 0xa
12extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
13extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
14
15#define QCOM_SCM_FLAG_HLOS 0x01
16#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
17#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
18extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
19 const cpumask_t *cpus);
20extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
21
22#define QCOM_SCM_CMD_TERMINATE_PC 0x2
23#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
24#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
25extern void __qcom_scm_cpu_power_down(u32 flags);
26
27#define QCOM_SCM_SVC_IO 0x5
28#define QCOM_SCM_IO_READ 0x1
29#define QCOM_SCM_IO_WRITE 0x2
30extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
31extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
32
33#define QCOM_SCM_SVC_INFO 0x6
34#define QCOM_IS_CALL_AVAIL_CMD 0x1
35extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
36 u32 cmd_id);
37
38#define QCOM_SCM_SVC_HDCP 0x11
39#define QCOM_SCM_CMD_HDCP 0x01
40extern int __qcom_scm_hdcp_req(struct device *dev,
41 struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
42
43extern void __qcom_scm_init(void);
44
45#define QCOM_SCM_SVC_PIL 0x2
46#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1
47#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2
48#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
49#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6
50#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7
51#define QCOM_SCM_PAS_MSS_RESET 0xa
52extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
53extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
54 dma_addr_t metadata_phys);
55extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
56 phys_addr_t addr, phys_addr_t size);
57extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
58extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
59extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
60
61/* common error codes */
62#define QCOM_SCM_V2_EBUSY -12
63#define QCOM_SCM_ENOMEM -5
64#define QCOM_SCM_EOPNOTSUPP -4
65#define QCOM_SCM_EINVAL_ADDR -3
66#define QCOM_SCM_EINVAL_ARG -2
67#define QCOM_SCM_ERROR -1
68#define QCOM_SCM_INTERRUPTED 1
69
70static inline int qcom_scm_remap_error(int err)
71{
72 switch (err) {
73 case QCOM_SCM_ERROR:
74 return -EIO;
75 case QCOM_SCM_EINVAL_ADDR:
76 case QCOM_SCM_EINVAL_ARG:
77 return -EINVAL;
78 case QCOM_SCM_EOPNOTSUPP:
79 return -EOPNOTSUPP;
80 case QCOM_SCM_ENOMEM:
81 return -ENOMEM;
82 case QCOM_SCM_V2_EBUSY:
83 return -EBUSY;
84 }
85 return -EINVAL;
86}
87
88#define QCOM_SCM_SVC_MP 0xc
89#define QCOM_SCM_RESTORE_SEC_CFG 2
90extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
91 u32 spare);
92#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3
93#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4
94extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
95 size_t *size);
96extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
97 u32 size, u32 spare);
98#define QCOM_MEM_PROT_ASSIGN_ID 0x16
99extern int __qcom_scm_assign_mem(struct device *dev,
100 phys_addr_t mem_region, size_t mem_sz,
101 phys_addr_t src, size_t src_sz,
102 phys_addr_t dest, size_t dest_sz);
103
104#endif