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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DMA driver for Xilinx ZynqMP DMA Engine
4 *
5 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
6 */
7
8#include <linux/bitops.h>
9#include <linux/dma-mapping.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of_dma.h>
15#include <linux/of_platform.h>
16#include <linux/slab.h>
17#include <linux/clk.h>
18#include <linux/io-64-nonatomic-lo-hi.h>
19#include <linux/pm_runtime.h>
20
21#include "../dmaengine.h"
22
23/* Register Offsets */
24#define ZYNQMP_DMA_ISR 0x100
25#define ZYNQMP_DMA_IMR 0x104
26#define ZYNQMP_DMA_IER 0x108
27#define ZYNQMP_DMA_IDS 0x10C
28#define ZYNQMP_DMA_CTRL0 0x110
29#define ZYNQMP_DMA_CTRL1 0x114
30#define ZYNQMP_DMA_DATA_ATTR 0x120
31#define ZYNQMP_DMA_DSCR_ATTR 0x124
32#define ZYNQMP_DMA_SRC_DSCR_WRD0 0x128
33#define ZYNQMP_DMA_SRC_DSCR_WRD1 0x12C
34#define ZYNQMP_DMA_SRC_DSCR_WRD2 0x130
35#define ZYNQMP_DMA_SRC_DSCR_WRD3 0x134
36#define ZYNQMP_DMA_DST_DSCR_WRD0 0x138
37#define ZYNQMP_DMA_DST_DSCR_WRD1 0x13C
38#define ZYNQMP_DMA_DST_DSCR_WRD2 0x140
39#define ZYNQMP_DMA_DST_DSCR_WRD3 0x144
40#define ZYNQMP_DMA_SRC_START_LSB 0x158
41#define ZYNQMP_DMA_SRC_START_MSB 0x15C
42#define ZYNQMP_DMA_DST_START_LSB 0x160
43#define ZYNQMP_DMA_DST_START_MSB 0x164
44#define ZYNQMP_DMA_TOTAL_BYTE 0x188
45#define ZYNQMP_DMA_RATE_CTRL 0x18C
46#define ZYNQMP_DMA_IRQ_SRC_ACCT 0x190
47#define ZYNQMP_DMA_IRQ_DST_ACCT 0x194
48#define ZYNQMP_DMA_CTRL2 0x200
49
50/* Interrupt registers bit field definitions */
51#define ZYNQMP_DMA_DONE BIT(10)
52#define ZYNQMP_DMA_AXI_WR_DATA BIT(9)
53#define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
54#define ZYNQMP_DMA_AXI_RD_DST_DSCR BIT(7)
55#define ZYNQMP_DMA_AXI_RD_SRC_DSCR BIT(6)
56#define ZYNQMP_DMA_IRQ_DST_ACCT_ERR BIT(5)
57#define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR BIT(4)
58#define ZYNQMP_DMA_BYTE_CNT_OVRFL BIT(3)
59#define ZYNQMP_DMA_DST_DSCR_DONE BIT(2)
60#define ZYNQMP_DMA_INV_APB BIT(0)
61
62/* Control 0 register bit field definitions */
63#define ZYNQMP_DMA_OVR_FETCH BIT(7)
64#define ZYNQMP_DMA_POINT_TYPE_SG BIT(6)
65#define ZYNQMP_DMA_RATE_CTRL_EN BIT(3)
66
67/* Control 1 register bit field definitions */
68#define ZYNQMP_DMA_SRC_ISSUE GENMASK(4, 0)
69
70/* Data Attribute register bit field definitions */
71#define ZYNQMP_DMA_ARBURST GENMASK(27, 26)
72#define ZYNQMP_DMA_ARCACHE GENMASK(25, 22)
73#define ZYNQMP_DMA_ARCACHE_OFST 22
74#define ZYNQMP_DMA_ARQOS GENMASK(21, 18)
75#define ZYNQMP_DMA_ARQOS_OFST 18
76#define ZYNQMP_DMA_ARLEN GENMASK(17, 14)
77#define ZYNQMP_DMA_ARLEN_OFST 14
78#define ZYNQMP_DMA_AWBURST GENMASK(13, 12)
79#define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
80#define ZYNQMP_DMA_AWCACHE_OFST 8
81#define ZYNQMP_DMA_AWQOS GENMASK(7, 4)
82#define ZYNQMP_DMA_AWQOS_OFST 4
83#define ZYNQMP_DMA_AWLEN GENMASK(3, 0)
84#define ZYNQMP_DMA_AWLEN_OFST 0
85
86/* Descriptor Attribute register bit field definitions */
87#define ZYNQMP_DMA_AXCOHRNT BIT(8)
88#define ZYNQMP_DMA_AXCACHE GENMASK(7, 4)
89#define ZYNQMP_DMA_AXCACHE_OFST 4
90#define ZYNQMP_DMA_AXQOS GENMASK(3, 0)
91#define ZYNQMP_DMA_AXQOS_OFST 0
92
93/* Control register 2 bit field definitions */
94#define ZYNQMP_DMA_ENABLE BIT(0)
95
96/* Buffer Descriptor definitions */
97#define ZYNQMP_DMA_DESC_CTRL_STOP 0x10
98#define ZYNQMP_DMA_DESC_CTRL_COMP_INT 0x4
99#define ZYNQMP_DMA_DESC_CTRL_SIZE_256 0x2
100#define ZYNQMP_DMA_DESC_CTRL_COHRNT 0x1
101
102/* Interrupt Mask specific definitions */
103#define ZYNQMP_DMA_INT_ERR (ZYNQMP_DMA_AXI_RD_DATA | \
104 ZYNQMP_DMA_AXI_WR_DATA | \
105 ZYNQMP_DMA_AXI_RD_DST_DSCR | \
106 ZYNQMP_DMA_AXI_RD_SRC_DSCR | \
107 ZYNQMP_DMA_INV_APB)
108#define ZYNQMP_DMA_INT_OVRFL (ZYNQMP_DMA_BYTE_CNT_OVRFL | \
109 ZYNQMP_DMA_IRQ_SRC_ACCT_ERR | \
110 ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
111#define ZYNQMP_DMA_INT_DONE (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE)
112#define ZYNQMP_DMA_INT_EN_DEFAULT_MASK (ZYNQMP_DMA_INT_DONE | \
113 ZYNQMP_DMA_INT_ERR | \
114 ZYNQMP_DMA_INT_OVRFL | \
115 ZYNQMP_DMA_DST_DSCR_DONE)
116
117/* Max number of descriptors per channel */
118#define ZYNQMP_DMA_NUM_DESCS 32
119
120/* Max transfer size per descriptor */
121#define ZYNQMP_DMA_MAX_TRANS_LEN 0x40000000
122
123/* Max burst lengths */
124#define ZYNQMP_DMA_MAX_DST_BURST_LEN 32768U
125#define ZYNQMP_DMA_MAX_SRC_BURST_LEN 32768U
126
127/* Reset values for data attributes */
128#define ZYNQMP_DMA_AXCACHE_VAL 0xF
129
130#define ZYNQMP_DMA_SRC_ISSUE_RST_VAL 0x1F
131
132#define ZYNQMP_DMA_IDS_DEFAULT_MASK 0xFFF
133
134/* Bus width in bits */
135#define ZYNQMP_DMA_BUS_WIDTH_64 64
136#define ZYNQMP_DMA_BUS_WIDTH_128 128
137
138#define ZDMA_PM_TIMEOUT 100
139
140#define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
141
142#define to_chan(chan) container_of(chan, struct zynqmp_dma_chan, \
143 common)
144#define tx_to_desc(tx) container_of(tx, struct zynqmp_dma_desc_sw, \
145 async_tx)
146
147/**
148 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
149 * @addr: Buffer address
150 * @size: Size of the buffer
151 * @ctrl: Control word
152 * @nxtdscraddr: Next descriptor base address
153 * @rsvd: Reserved field and for Hw internal use.
154 */
155struct zynqmp_dma_desc_ll {
156 u64 addr;
157 u32 size;
158 u32 ctrl;
159 u64 nxtdscraddr;
160 u64 rsvd;
161};
162
163/**
164 * struct zynqmp_dma_desc_sw - Per Transaction structure
165 * @src: Source address for simple mode dma
166 * @dst: Destination address for simple mode dma
167 * @len: Transfer length for simple mode dma
168 * @node: Node in the channel descriptor list
169 * @tx_list: List head for the current transfer
170 * @async_tx: Async transaction descriptor
171 * @src_v: Virtual address of the src descriptor
172 * @src_p: Physical address of the src descriptor
173 * @dst_v: Virtual address of the dst descriptor
174 * @dst_p: Physical address of the dst descriptor
175 */
176struct zynqmp_dma_desc_sw {
177 u64 src;
178 u64 dst;
179 u32 len;
180 struct list_head node;
181 struct list_head tx_list;
182 struct dma_async_tx_descriptor async_tx;
183 struct zynqmp_dma_desc_ll *src_v;
184 dma_addr_t src_p;
185 struct zynqmp_dma_desc_ll *dst_v;
186 dma_addr_t dst_p;
187};
188
189/**
190 * struct zynqmp_dma_chan - Driver specific DMA channel structure
191 * @zdev: Driver specific device structure
192 * @regs: Control registers offset
193 * @lock: Descriptor operation lock
194 * @pending_list: Descriptors waiting
195 * @free_list: Descriptors free
196 * @active_list: Descriptors active
197 * @sw_desc_pool: SW descriptor pool
198 * @done_list: Complete descriptors
199 * @common: DMA common channel
200 * @desc_pool_v: Statically allocated descriptor base
201 * @desc_pool_p: Physical allocated descriptor base
202 * @desc_free_cnt: Descriptor available count
203 * @dev: The dma device
204 * @irq: Channel IRQ
205 * @is_dmacoherent: Tells whether dma operations are coherent or not
206 * @tasklet: Cleanup work after irq
207 * @idle : Channel status;
208 * @desc_size: Size of the low level descriptor
209 * @err: Channel has errors
210 * @bus_width: Bus width
211 * @src_burst_len: Source burst length
212 * @dst_burst_len: Dest burst length
213 */
214struct zynqmp_dma_chan {
215 struct zynqmp_dma_device *zdev;
216 void __iomem *regs;
217 spinlock_t lock;
218 struct list_head pending_list;
219 struct list_head free_list;
220 struct list_head active_list;
221 struct zynqmp_dma_desc_sw *sw_desc_pool;
222 struct list_head done_list;
223 struct dma_chan common;
224 void *desc_pool_v;
225 dma_addr_t desc_pool_p;
226 u32 desc_free_cnt;
227 struct device *dev;
228 int irq;
229 bool is_dmacoherent;
230 struct tasklet_struct tasklet;
231 bool idle;
232 size_t desc_size;
233 bool err;
234 u32 bus_width;
235 u32 src_burst_len;
236 u32 dst_burst_len;
237};
238
239/**
240 * struct zynqmp_dma_device - DMA device structure
241 * @dev: Device Structure
242 * @common: DMA device structure
243 * @chan: Driver specific DMA channel
244 * @clk_main: Pointer to main clock
245 * @clk_apb: Pointer to apb clock
246 */
247struct zynqmp_dma_device {
248 struct device *dev;
249 struct dma_device common;
250 struct zynqmp_dma_chan *chan;
251 struct clk *clk_main;
252 struct clk *clk_apb;
253};
254
255static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
256 u64 value)
257{
258 lo_hi_writeq(value, chan->regs + reg);
259}
260
261/**
262 * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
263 * @chan: ZynqMP DMA DMA channel pointer
264 * @desc: Transaction descriptor pointer
265 */
266static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
267 struct zynqmp_dma_desc_sw *desc)
268{
269 dma_addr_t addr;
270
271 addr = desc->src_p;
272 zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
273 addr = desc->dst_p;
274 zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
275}
276
277/**
278 * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
279 * @chan: ZynqMP DMA channel pointer
280 * @desc: Hw descriptor pointer
281 */
282static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
283 void *desc)
284{
285 struct zynqmp_dma_desc_ll *hw = (struct zynqmp_dma_desc_ll *)desc;
286
287 hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP;
288 hw++;
289 hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP;
290}
291
292/**
293 * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
294 * @chan: ZynqMP DMA channel pointer
295 * @sdesc: Hw descriptor pointer
296 * @src: Source buffer address
297 * @dst: Destination buffer address
298 * @len: Transfer length
299 * @prev: Previous hw descriptor pointer
300 */
301static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
302 struct zynqmp_dma_desc_ll *sdesc,
303 dma_addr_t src, dma_addr_t dst, size_t len,
304 struct zynqmp_dma_desc_ll *prev)
305{
306 struct zynqmp_dma_desc_ll *ddesc = sdesc + 1;
307
308 sdesc->size = ddesc->size = len;
309 sdesc->addr = src;
310 ddesc->addr = dst;
311
312 sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256;
313 if (chan->is_dmacoherent) {
314 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
315 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
316 }
317
318 if (prev) {
319 dma_addr_t addr = chan->desc_pool_p +
320 ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
321 ddesc = prev + 1;
322 prev->nxtdscraddr = addr;
323 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
324 }
325}
326
327/**
328 * zynqmp_dma_init - Initialize the channel
329 * @chan: ZynqMP DMA channel pointer
330 */
331static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
332{
333 u32 val;
334
335 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
336 val = readl(chan->regs + ZYNQMP_DMA_ISR);
337 writel(val, chan->regs + ZYNQMP_DMA_ISR);
338
339 if (chan->is_dmacoherent) {
340 val = ZYNQMP_DMA_AXCOHRNT;
341 val = (val & ~ZYNQMP_DMA_AXCACHE) |
342 (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AXCACHE_OFST);
343 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
344 }
345
346 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
347 if (chan->is_dmacoherent) {
348 val = (val & ~ZYNQMP_DMA_ARCACHE) |
349 (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_ARCACHE_OFST);
350 val = (val & ~ZYNQMP_DMA_AWCACHE) |
351 (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AWCACHE_OFST);
352 }
353 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
354
355 /* Clearing the interrupt account rgisters */
356 val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
357 val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
358
359 chan->idle = true;
360}
361
362/**
363 * zynqmp_dma_tx_submit - Submit DMA transaction
364 * @tx: Async transaction descriptor pointer
365 *
366 * Return: cookie value
367 */
368static dma_cookie_t zynqmp_dma_tx_submit(struct dma_async_tx_descriptor *tx)
369{
370 struct zynqmp_dma_chan *chan = to_chan(tx->chan);
371 struct zynqmp_dma_desc_sw *desc, *new;
372 dma_cookie_t cookie;
373 unsigned long irqflags;
374
375 new = tx_to_desc(tx);
376 spin_lock_irqsave(&chan->lock, irqflags);
377 cookie = dma_cookie_assign(tx);
378
379 if (!list_empty(&chan->pending_list)) {
380 desc = list_last_entry(&chan->pending_list,
381 struct zynqmp_dma_desc_sw, node);
382 if (!list_empty(&desc->tx_list))
383 desc = list_last_entry(&desc->tx_list,
384 struct zynqmp_dma_desc_sw, node);
385 desc->src_v->nxtdscraddr = new->src_p;
386 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
387 desc->dst_v->nxtdscraddr = new->dst_p;
388 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
389 }
390
391 list_add_tail(&new->node, &chan->pending_list);
392 spin_unlock_irqrestore(&chan->lock, irqflags);
393
394 return cookie;
395}
396
397/**
398 * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
399 * @chan: ZynqMP DMA channel pointer
400 *
401 * Return: The sw descriptor
402 */
403static struct zynqmp_dma_desc_sw *
404zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
405{
406 struct zynqmp_dma_desc_sw *desc;
407 unsigned long irqflags;
408
409 spin_lock_irqsave(&chan->lock, irqflags);
410 desc = list_first_entry(&chan->free_list,
411 struct zynqmp_dma_desc_sw, node);
412 list_del(&desc->node);
413 spin_unlock_irqrestore(&chan->lock, irqflags);
414
415 INIT_LIST_HEAD(&desc->tx_list);
416 /* Clear the src and dst descriptor memory */
417 memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
418 memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
419
420 return desc;
421}
422
423/**
424 * zynqmp_dma_free_descriptor - Issue pending transactions
425 * @chan: ZynqMP DMA channel pointer
426 * @sdesc: Transaction descriptor pointer
427 */
428static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
429 struct zynqmp_dma_desc_sw *sdesc)
430{
431 struct zynqmp_dma_desc_sw *child, *next;
432
433 chan->desc_free_cnt++;
434 list_move_tail(&sdesc->node, &chan->free_list);
435 list_for_each_entry_safe(child, next, &sdesc->tx_list, node) {
436 chan->desc_free_cnt++;
437 list_move_tail(&child->node, &chan->free_list);
438 }
439}
440
441/**
442 * zynqmp_dma_free_desc_list - Free descriptors list
443 * @chan: ZynqMP DMA channel pointer
444 * @list: List to parse and delete the descriptor
445 */
446static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
447 struct list_head *list)
448{
449 struct zynqmp_dma_desc_sw *desc, *next;
450
451 list_for_each_entry_safe(desc, next, list, node)
452 zynqmp_dma_free_descriptor(chan, desc);
453}
454
455/**
456 * zynqmp_dma_alloc_chan_resources - Allocate channel resources
457 * @dchan: DMA channel
458 *
459 * Return: Number of descriptors on success and failure value on error
460 */
461static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan)
462{
463 struct zynqmp_dma_chan *chan = to_chan(dchan);
464 struct zynqmp_dma_desc_sw *desc;
465 int i, ret;
466
467 ret = pm_runtime_resume_and_get(chan->dev);
468 if (ret < 0)
469 return ret;
470
471 chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
472 GFP_KERNEL);
473 if (!chan->sw_desc_pool)
474 return -ENOMEM;
475
476 chan->idle = true;
477 chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
478
479 INIT_LIST_HEAD(&chan->free_list);
480
481 for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
482 desc = chan->sw_desc_pool + i;
483 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
484 desc->async_tx.tx_submit = zynqmp_dma_tx_submit;
485 list_add_tail(&desc->node, &chan->free_list);
486 }
487
488 chan->desc_pool_v = dma_alloc_coherent(chan->dev,
489 (2 * ZYNQMP_DMA_DESC_SIZE(chan) *
490 ZYNQMP_DMA_NUM_DESCS),
491 &chan->desc_pool_p, GFP_KERNEL);
492 if (!chan->desc_pool_v)
493 return -ENOMEM;
494
495 for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
496 desc = chan->sw_desc_pool + i;
497 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
498 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
499 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1);
500 desc->src_p = chan->desc_pool_p +
501 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
502 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
503 }
504
505 return ZYNQMP_DMA_NUM_DESCS;
506}
507
508/**
509 * zynqmp_dma_start - Start DMA channel
510 * @chan: ZynqMP DMA channel pointer
511 */
512static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
513{
514 writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
515 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
516 chan->idle = false;
517 writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
518}
519
520/**
521 * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
522 * @chan: ZynqMP DMA channel pointer
523 * @status: Interrupt status value
524 */
525static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
526{
527 if (status & ZYNQMP_DMA_BYTE_CNT_OVRFL)
528 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
529 if (status & ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
530 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
531 if (status & ZYNQMP_DMA_IRQ_SRC_ACCT_ERR)
532 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
533}
534
535static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
536{
537 u32 val, burst_val;
538
539 val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
540 val |= ZYNQMP_DMA_POINT_TYPE_SG;
541 writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
542
543 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
544 burst_val = __ilog2_u32(chan->src_burst_len);
545 val = (val & ~ZYNQMP_DMA_ARLEN) |
546 ((burst_val << ZYNQMP_DMA_ARLEN_OFST) & ZYNQMP_DMA_ARLEN);
547 burst_val = __ilog2_u32(chan->dst_burst_len);
548 val = (val & ~ZYNQMP_DMA_AWLEN) |
549 ((burst_val << ZYNQMP_DMA_AWLEN_OFST) & ZYNQMP_DMA_AWLEN);
550 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
551}
552
553/**
554 * zynqmp_dma_device_config - Zynqmp dma device configuration
555 * @dchan: DMA channel
556 * @config: DMA device config
557 *
558 * Return: 0 always
559 */
560static int zynqmp_dma_device_config(struct dma_chan *dchan,
561 struct dma_slave_config *config)
562{
563 struct zynqmp_dma_chan *chan = to_chan(dchan);
564
565 chan->src_burst_len = clamp(config->src_maxburst, 1U,
566 ZYNQMP_DMA_MAX_SRC_BURST_LEN);
567 chan->dst_burst_len = clamp(config->dst_maxburst, 1U,
568 ZYNQMP_DMA_MAX_DST_BURST_LEN);
569
570 return 0;
571}
572
573/**
574 * zynqmp_dma_start_transfer - Initiate the new transfer
575 * @chan: ZynqMP DMA channel pointer
576 */
577static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
578{
579 struct zynqmp_dma_desc_sw *desc;
580
581 if (!chan->idle)
582 return;
583
584 zynqmp_dma_config(chan);
585
586 desc = list_first_entry_or_null(&chan->pending_list,
587 struct zynqmp_dma_desc_sw, node);
588 if (!desc)
589 return;
590
591 list_splice_tail_init(&chan->pending_list, &chan->active_list);
592 zynqmp_dma_update_desc_to_ctrlr(chan, desc);
593 zynqmp_dma_start(chan);
594}
595
596
597/**
598 * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
599 * @chan: ZynqMP DMA channel
600 */
601static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
602{
603 struct zynqmp_dma_desc_sw *desc, *next;
604 unsigned long irqflags;
605
606 spin_lock_irqsave(&chan->lock, irqflags);
607
608 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
609 struct dmaengine_desc_callback cb;
610
611 dmaengine_desc_get_callback(&desc->async_tx, &cb);
612 if (dmaengine_desc_callback_valid(&cb)) {
613 spin_unlock_irqrestore(&chan->lock, irqflags);
614 dmaengine_desc_callback_invoke(&cb, NULL);
615 spin_lock_irqsave(&chan->lock, irqflags);
616 }
617
618 /* Run any dependencies, then free the descriptor */
619 zynqmp_dma_free_descriptor(chan, desc);
620 }
621
622 spin_unlock_irqrestore(&chan->lock, irqflags);
623}
624
625/**
626 * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
627 * @chan: ZynqMP DMA channel pointer
628 */
629static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
630{
631 struct zynqmp_dma_desc_sw *desc;
632
633 desc = list_first_entry_or_null(&chan->active_list,
634 struct zynqmp_dma_desc_sw, node);
635 if (!desc)
636 return;
637 list_del(&desc->node);
638 dma_cookie_complete(&desc->async_tx);
639 list_add_tail(&desc->node, &chan->done_list);
640}
641
642/**
643 * zynqmp_dma_issue_pending - Issue pending transactions
644 * @dchan: DMA channel pointer
645 */
646static void zynqmp_dma_issue_pending(struct dma_chan *dchan)
647{
648 struct zynqmp_dma_chan *chan = to_chan(dchan);
649 unsigned long irqflags;
650
651 spin_lock_irqsave(&chan->lock, irqflags);
652 zynqmp_dma_start_transfer(chan);
653 spin_unlock_irqrestore(&chan->lock, irqflags);
654}
655
656/**
657 * zynqmp_dma_free_descriptors - Free channel descriptors
658 * @chan: ZynqMP DMA channel pointer
659 */
660static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
661{
662 unsigned long irqflags;
663
664 spin_lock_irqsave(&chan->lock, irqflags);
665 zynqmp_dma_free_desc_list(chan, &chan->active_list);
666 zynqmp_dma_free_desc_list(chan, &chan->pending_list);
667 zynqmp_dma_free_desc_list(chan, &chan->done_list);
668 spin_unlock_irqrestore(&chan->lock, irqflags);
669}
670
671/**
672 * zynqmp_dma_free_chan_resources - Free channel resources
673 * @dchan: DMA channel pointer
674 */
675static void zynqmp_dma_free_chan_resources(struct dma_chan *dchan)
676{
677 struct zynqmp_dma_chan *chan = to_chan(dchan);
678
679 zynqmp_dma_free_descriptors(chan);
680 dma_free_coherent(chan->dev,
681 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
682 chan->desc_pool_v, chan->desc_pool_p);
683 kfree(chan->sw_desc_pool);
684 pm_runtime_mark_last_busy(chan->dev);
685 pm_runtime_put_autosuspend(chan->dev);
686}
687
688/**
689 * zynqmp_dma_reset - Reset the channel
690 * @chan: ZynqMP DMA channel pointer
691 */
692static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
693{
694 unsigned long irqflags;
695
696 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
697
698 spin_lock_irqsave(&chan->lock, irqflags);
699 zynqmp_dma_complete_descriptor(chan);
700 spin_unlock_irqrestore(&chan->lock, irqflags);
701 zynqmp_dma_chan_desc_cleanup(chan);
702 zynqmp_dma_free_descriptors(chan);
703
704 zynqmp_dma_init(chan);
705}
706
707/**
708 * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
709 * @irq: IRQ number
710 * @data: Pointer to the ZynqMP DMA channel structure
711 *
712 * Return: IRQ_HANDLED/IRQ_NONE
713 */
714static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
715{
716 struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
717 u32 isr, imr, status;
718 irqreturn_t ret = IRQ_NONE;
719
720 isr = readl(chan->regs + ZYNQMP_DMA_ISR);
721 imr = readl(chan->regs + ZYNQMP_DMA_IMR);
722 status = isr & ~imr;
723
724 writel(isr, chan->regs + ZYNQMP_DMA_ISR);
725 if (status & ZYNQMP_DMA_INT_DONE) {
726 tasklet_schedule(&chan->tasklet);
727 ret = IRQ_HANDLED;
728 }
729
730 if (status & ZYNQMP_DMA_DONE)
731 chan->idle = true;
732
733 if (status & ZYNQMP_DMA_INT_ERR) {
734 chan->err = true;
735 tasklet_schedule(&chan->tasklet);
736 dev_err(chan->dev, "Channel %p has errors\n", chan);
737 ret = IRQ_HANDLED;
738 }
739
740 if (status & ZYNQMP_DMA_INT_OVRFL) {
741 zynqmp_dma_handle_ovfl_int(chan, status);
742 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
743 ret = IRQ_HANDLED;
744 }
745
746 return ret;
747}
748
749/**
750 * zynqmp_dma_do_tasklet - Schedule completion tasklet
751 * @t: Pointer to the ZynqMP DMA channel structure
752 */
753static void zynqmp_dma_do_tasklet(struct tasklet_struct *t)
754{
755 struct zynqmp_dma_chan *chan = from_tasklet(chan, t, tasklet);
756 u32 count;
757 unsigned long irqflags;
758
759 if (chan->err) {
760 zynqmp_dma_reset(chan);
761 chan->err = false;
762 return;
763 }
764
765 spin_lock_irqsave(&chan->lock, irqflags);
766 count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
767 while (count) {
768 zynqmp_dma_complete_descriptor(chan);
769 count--;
770 }
771 spin_unlock_irqrestore(&chan->lock, irqflags);
772
773 zynqmp_dma_chan_desc_cleanup(chan);
774
775 if (chan->idle) {
776 spin_lock_irqsave(&chan->lock, irqflags);
777 zynqmp_dma_start_transfer(chan);
778 spin_unlock_irqrestore(&chan->lock, irqflags);
779 }
780}
781
782/**
783 * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
784 * @dchan: DMA channel pointer
785 *
786 * Return: Always '0'
787 */
788static int zynqmp_dma_device_terminate_all(struct dma_chan *dchan)
789{
790 struct zynqmp_dma_chan *chan = to_chan(dchan);
791
792 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
793 zynqmp_dma_free_descriptors(chan);
794
795 return 0;
796}
797
798/**
799 * zynqmp_dma_synchronize - Synchronizes the termination of a transfers to the current context.
800 * @dchan: DMA channel pointer
801 */
802static void zynqmp_dma_synchronize(struct dma_chan *dchan)
803{
804 struct zynqmp_dma_chan *chan = to_chan(dchan);
805
806 tasklet_kill(&chan->tasklet);
807}
808
809/**
810 * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
811 * @dchan: DMA channel
812 * @dma_dst: Destination buffer address
813 * @dma_src: Source buffer address
814 * @len: Transfer length
815 * @flags: transfer ack flags
816 *
817 * Return: Async transaction descriptor on success and NULL on failure
818 */
819static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
820 struct dma_chan *dchan, dma_addr_t dma_dst,
821 dma_addr_t dma_src, size_t len, ulong flags)
822{
823 struct zynqmp_dma_chan *chan;
824 struct zynqmp_dma_desc_sw *new, *first = NULL;
825 void *desc = NULL, *prev = NULL;
826 size_t copy;
827 u32 desc_cnt;
828 unsigned long irqflags;
829
830 chan = to_chan(dchan);
831
832 desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN);
833
834 spin_lock_irqsave(&chan->lock, irqflags);
835 if (desc_cnt > chan->desc_free_cnt) {
836 spin_unlock_irqrestore(&chan->lock, irqflags);
837 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
838 return NULL;
839 }
840 chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
841 spin_unlock_irqrestore(&chan->lock, irqflags);
842
843 do {
844 /* Allocate and populate the descriptor */
845 new = zynqmp_dma_get_descriptor(chan);
846
847 copy = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
848 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
849 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
850 dma_dst, copy, prev);
851 prev = desc;
852 len -= copy;
853 dma_src += copy;
854 dma_dst += copy;
855 if (!first)
856 first = new;
857 else
858 list_add_tail(&new->node, &first->tx_list);
859 } while (len);
860
861 zynqmp_dma_desc_config_eod(chan, desc);
862 async_tx_ack(&first->async_tx);
863 first->async_tx.flags = (enum dma_ctrl_flags)flags;
864 return &first->async_tx;
865}
866
867/**
868 * zynqmp_dma_chan_remove - Channel remove function
869 * @chan: ZynqMP DMA channel pointer
870 */
871static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
872{
873 if (!chan)
874 return;
875
876 if (chan->irq)
877 devm_free_irq(chan->zdev->dev, chan->irq, chan);
878 tasklet_kill(&chan->tasklet);
879 list_del(&chan->common.device_node);
880}
881
882/**
883 * zynqmp_dma_chan_probe - Per Channel Probing
884 * @zdev: Driver specific device structure
885 * @pdev: Pointer to the platform_device structure
886 *
887 * Return: '0' on success and failure value on error
888 */
889static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
890 struct platform_device *pdev)
891{
892 struct zynqmp_dma_chan *chan;
893 struct resource *res;
894 struct device_node *node = pdev->dev.of_node;
895 int err;
896
897 chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
898 if (!chan)
899 return -ENOMEM;
900 chan->dev = zdev->dev;
901 chan->zdev = zdev;
902
903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
904 chan->regs = devm_ioremap_resource(&pdev->dev, res);
905 if (IS_ERR(chan->regs))
906 return PTR_ERR(chan->regs);
907
908 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
909 chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN;
910 chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN;
911 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
912 if (err < 0) {
913 dev_err(&pdev->dev, "missing xlnx,bus-width property\n");
914 return err;
915 }
916
917 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
918 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
919 dev_err(zdev->dev, "invalid bus-width value");
920 return -EINVAL;
921 }
922
923 chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent");
924 zdev->chan = chan;
925 tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet);
926 spin_lock_init(&chan->lock);
927 INIT_LIST_HEAD(&chan->active_list);
928 INIT_LIST_HEAD(&chan->pending_list);
929 INIT_LIST_HEAD(&chan->done_list);
930 INIT_LIST_HEAD(&chan->free_list);
931
932 dma_cookie_init(&chan->common);
933 chan->common.device = &zdev->common;
934 list_add_tail(&chan->common.device_node, &zdev->common.channels);
935
936 zynqmp_dma_init(chan);
937 chan->irq = platform_get_irq(pdev, 0);
938 if (chan->irq < 0)
939 return -ENXIO;
940 err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
941 "zynqmp-dma", chan);
942 if (err)
943 return err;
944
945 chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
946 chan->idle = true;
947 return 0;
948}
949
950/**
951 * of_zynqmp_dma_xlate - Translation function
952 * @dma_spec: Pointer to DMA specifier as found in the device tree
953 * @ofdma: Pointer to DMA controller data
954 *
955 * Return: DMA channel pointer on success and NULL on error
956 */
957static struct dma_chan *of_zynqmp_dma_xlate(struct of_phandle_args *dma_spec,
958 struct of_dma *ofdma)
959{
960 struct zynqmp_dma_device *zdev = ofdma->of_dma_data;
961
962 return dma_get_slave_channel(&zdev->chan->common);
963}
964
965/**
966 * zynqmp_dma_suspend - Suspend method for the driver
967 * @dev: Address of the device structure
968 *
969 * Put the driver into low power mode.
970 * Return: 0 on success and failure value on error
971 */
972static int __maybe_unused zynqmp_dma_suspend(struct device *dev)
973{
974 if (!device_may_wakeup(dev))
975 return pm_runtime_force_suspend(dev);
976
977 return 0;
978}
979
980/**
981 * zynqmp_dma_resume - Resume from suspend
982 * @dev: Address of the device structure
983 *
984 * Resume operation after suspend.
985 * Return: 0 on success and failure value on error
986 */
987static int __maybe_unused zynqmp_dma_resume(struct device *dev)
988{
989 if (!device_may_wakeup(dev))
990 return pm_runtime_force_resume(dev);
991
992 return 0;
993}
994
995/**
996 * zynqmp_dma_runtime_suspend - Runtime suspend method for the driver
997 * @dev: Address of the device structure
998 *
999 * Put the driver into low power mode.
1000 * Return: 0 always
1001 */
1002static int __maybe_unused zynqmp_dma_runtime_suspend(struct device *dev)
1003{
1004 struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
1005
1006 clk_disable_unprepare(zdev->clk_main);
1007 clk_disable_unprepare(zdev->clk_apb);
1008
1009 return 0;
1010}
1011
1012/**
1013 * zynqmp_dma_runtime_resume - Runtime suspend method for the driver
1014 * @dev: Address of the device structure
1015 *
1016 * Put the driver into low power mode.
1017 * Return: 0 always
1018 */
1019static int __maybe_unused zynqmp_dma_runtime_resume(struct device *dev)
1020{
1021 struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
1022 int err;
1023
1024 err = clk_prepare_enable(zdev->clk_main);
1025 if (err) {
1026 dev_err(dev, "Unable to enable main clock.\n");
1027 return err;
1028 }
1029
1030 err = clk_prepare_enable(zdev->clk_apb);
1031 if (err) {
1032 dev_err(dev, "Unable to enable apb clock.\n");
1033 clk_disable_unprepare(zdev->clk_main);
1034 return err;
1035 }
1036
1037 return 0;
1038}
1039
1040static const struct dev_pm_ops zynqmp_dma_dev_pm_ops = {
1041 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dma_suspend, zynqmp_dma_resume)
1042 SET_RUNTIME_PM_OPS(zynqmp_dma_runtime_suspend,
1043 zynqmp_dma_runtime_resume, NULL)
1044};
1045
1046/**
1047 * zynqmp_dma_probe - Driver probe function
1048 * @pdev: Pointer to the platform_device structure
1049 *
1050 * Return: '0' on success and failure value on error
1051 */
1052static int zynqmp_dma_probe(struct platform_device *pdev)
1053{
1054 struct zynqmp_dma_device *zdev;
1055 struct dma_device *p;
1056 int ret;
1057
1058 zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL);
1059 if (!zdev)
1060 return -ENOMEM;
1061
1062 zdev->dev = &pdev->dev;
1063 INIT_LIST_HEAD(&zdev->common.channels);
1064
1065 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1066 dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
1067
1068 p = &zdev->common;
1069 p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy;
1070 p->device_terminate_all = zynqmp_dma_device_terminate_all;
1071 p->device_synchronize = zynqmp_dma_synchronize;
1072 p->device_issue_pending = zynqmp_dma_issue_pending;
1073 p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources;
1074 p->device_free_chan_resources = zynqmp_dma_free_chan_resources;
1075 p->device_tx_status = dma_cookie_status;
1076 p->device_config = zynqmp_dma_device_config;
1077 p->dev = &pdev->dev;
1078
1079 zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main");
1080 if (IS_ERR(zdev->clk_main))
1081 return dev_err_probe(&pdev->dev, PTR_ERR(zdev->clk_main),
1082 "main clock not found.\n");
1083
1084 zdev->clk_apb = devm_clk_get(&pdev->dev, "clk_apb");
1085 if (IS_ERR(zdev->clk_apb))
1086 return dev_err_probe(&pdev->dev, PTR_ERR(zdev->clk_apb),
1087 "apb clock not found.\n");
1088
1089 platform_set_drvdata(pdev, zdev);
1090 pm_runtime_set_autosuspend_delay(zdev->dev, ZDMA_PM_TIMEOUT);
1091 pm_runtime_use_autosuspend(zdev->dev);
1092 pm_runtime_enable(zdev->dev);
1093 ret = pm_runtime_resume_and_get(zdev->dev);
1094 if (ret < 0) {
1095 dev_err(&pdev->dev, "device wakeup failed.\n");
1096 pm_runtime_disable(zdev->dev);
1097 }
1098 if (!pm_runtime_enabled(zdev->dev)) {
1099 ret = zynqmp_dma_runtime_resume(zdev->dev);
1100 if (ret)
1101 return ret;
1102 }
1103
1104 ret = zynqmp_dma_chan_probe(zdev, pdev);
1105 if (ret) {
1106 dev_err_probe(&pdev->dev, ret, "Probing channel failed\n");
1107 goto err_disable_pm;
1108 }
1109
1110 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1111 p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1112
1113 ret = dma_async_device_register(&zdev->common);
1114 if (ret) {
1115 dev_err(zdev->dev, "failed to register the dma device\n");
1116 goto free_chan_resources;
1117 }
1118
1119 ret = of_dma_controller_register(pdev->dev.of_node,
1120 of_zynqmp_dma_xlate, zdev);
1121 if (ret) {
1122 dev_err_probe(&pdev->dev, ret, "Unable to register DMA to DT\n");
1123 dma_async_device_unregister(&zdev->common);
1124 goto free_chan_resources;
1125 }
1126
1127 pm_runtime_mark_last_busy(zdev->dev);
1128 pm_runtime_put_sync_autosuspend(zdev->dev);
1129
1130 return 0;
1131
1132free_chan_resources:
1133 zynqmp_dma_chan_remove(zdev->chan);
1134err_disable_pm:
1135 if (!pm_runtime_enabled(zdev->dev))
1136 zynqmp_dma_runtime_suspend(zdev->dev);
1137 pm_runtime_disable(zdev->dev);
1138 return ret;
1139}
1140
1141/**
1142 * zynqmp_dma_remove - Driver remove function
1143 * @pdev: Pointer to the platform_device structure
1144 *
1145 * Return: Always '0'
1146 */
1147static int zynqmp_dma_remove(struct platform_device *pdev)
1148{
1149 struct zynqmp_dma_device *zdev = platform_get_drvdata(pdev);
1150
1151 of_dma_controller_free(pdev->dev.of_node);
1152 dma_async_device_unregister(&zdev->common);
1153
1154 zynqmp_dma_chan_remove(zdev->chan);
1155 pm_runtime_disable(zdev->dev);
1156 if (!pm_runtime_enabled(zdev->dev))
1157 zynqmp_dma_runtime_suspend(zdev->dev);
1158
1159 return 0;
1160}
1161
1162static const struct of_device_id zynqmp_dma_of_match[] = {
1163 { .compatible = "xlnx,zynqmp-dma-1.0", },
1164 {}
1165};
1166MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
1167
1168static struct platform_driver zynqmp_dma_driver = {
1169 .driver = {
1170 .name = "xilinx-zynqmp-dma",
1171 .of_match_table = zynqmp_dma_of_match,
1172 .pm = &zynqmp_dma_dev_pm_ops,
1173 },
1174 .probe = zynqmp_dma_probe,
1175 .remove = zynqmp_dma_remove,
1176};
1177
1178module_platform_driver(zynqmp_dma_driver);
1179
1180MODULE_LICENSE("GPL");
1181MODULE_AUTHOR("Xilinx, Inc.");
1182MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DMA driver for Xilinx ZynqMP DMA Engine
4 *
5 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
6 */
7
8#include <linux/bitops.h>
9#include <linux/dmapool.h>
10#include <linux/dma/xilinx_dma.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of_address.h>
16#include <linux/of_dma.h>
17#include <linux/of_irq.h>
18#include <linux/of_platform.h>
19#include <linux/slab.h>
20#include <linux/clk.h>
21#include <linux/io-64-nonatomic-lo-hi.h>
22#include <linux/pm_runtime.h>
23
24#include "../dmaengine.h"
25
26/* Register Offsets */
27#define ZYNQMP_DMA_ISR 0x100
28#define ZYNQMP_DMA_IMR 0x104
29#define ZYNQMP_DMA_IER 0x108
30#define ZYNQMP_DMA_IDS 0x10C
31#define ZYNQMP_DMA_CTRL0 0x110
32#define ZYNQMP_DMA_CTRL1 0x114
33#define ZYNQMP_DMA_DATA_ATTR 0x120
34#define ZYNQMP_DMA_DSCR_ATTR 0x124
35#define ZYNQMP_DMA_SRC_DSCR_WRD0 0x128
36#define ZYNQMP_DMA_SRC_DSCR_WRD1 0x12C
37#define ZYNQMP_DMA_SRC_DSCR_WRD2 0x130
38#define ZYNQMP_DMA_SRC_DSCR_WRD3 0x134
39#define ZYNQMP_DMA_DST_DSCR_WRD0 0x138
40#define ZYNQMP_DMA_DST_DSCR_WRD1 0x13C
41#define ZYNQMP_DMA_DST_DSCR_WRD2 0x140
42#define ZYNQMP_DMA_DST_DSCR_WRD3 0x144
43#define ZYNQMP_DMA_SRC_START_LSB 0x158
44#define ZYNQMP_DMA_SRC_START_MSB 0x15C
45#define ZYNQMP_DMA_DST_START_LSB 0x160
46#define ZYNQMP_DMA_DST_START_MSB 0x164
47#define ZYNQMP_DMA_TOTAL_BYTE 0x188
48#define ZYNQMP_DMA_RATE_CTRL 0x18C
49#define ZYNQMP_DMA_IRQ_SRC_ACCT 0x190
50#define ZYNQMP_DMA_IRQ_DST_ACCT 0x194
51#define ZYNQMP_DMA_CTRL2 0x200
52
53/* Interrupt registers bit field definitions */
54#define ZYNQMP_DMA_DONE BIT(10)
55#define ZYNQMP_DMA_AXI_WR_DATA BIT(9)
56#define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
57#define ZYNQMP_DMA_AXI_RD_DST_DSCR BIT(7)
58#define ZYNQMP_DMA_AXI_RD_SRC_DSCR BIT(6)
59#define ZYNQMP_DMA_IRQ_DST_ACCT_ERR BIT(5)
60#define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR BIT(4)
61#define ZYNQMP_DMA_BYTE_CNT_OVRFL BIT(3)
62#define ZYNQMP_DMA_DST_DSCR_DONE BIT(2)
63#define ZYNQMP_DMA_INV_APB BIT(0)
64
65/* Control 0 register bit field definitions */
66#define ZYNQMP_DMA_OVR_FETCH BIT(7)
67#define ZYNQMP_DMA_POINT_TYPE_SG BIT(6)
68#define ZYNQMP_DMA_RATE_CTRL_EN BIT(3)
69
70/* Control 1 register bit field definitions */
71#define ZYNQMP_DMA_SRC_ISSUE GENMASK(4, 0)
72
73/* Data Attribute register bit field definitions */
74#define ZYNQMP_DMA_ARBURST GENMASK(27, 26)
75#define ZYNQMP_DMA_ARCACHE GENMASK(25, 22)
76#define ZYNQMP_DMA_ARCACHE_OFST 22
77#define ZYNQMP_DMA_ARQOS GENMASK(21, 18)
78#define ZYNQMP_DMA_ARQOS_OFST 18
79#define ZYNQMP_DMA_ARLEN GENMASK(17, 14)
80#define ZYNQMP_DMA_ARLEN_OFST 14
81#define ZYNQMP_DMA_AWBURST GENMASK(13, 12)
82#define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
83#define ZYNQMP_DMA_AWCACHE_OFST 8
84#define ZYNQMP_DMA_AWQOS GENMASK(7, 4)
85#define ZYNQMP_DMA_AWQOS_OFST 4
86#define ZYNQMP_DMA_AWLEN GENMASK(3, 0)
87#define ZYNQMP_DMA_AWLEN_OFST 0
88
89/* Descriptor Attribute register bit field definitions */
90#define ZYNQMP_DMA_AXCOHRNT BIT(8)
91#define ZYNQMP_DMA_AXCACHE GENMASK(7, 4)
92#define ZYNQMP_DMA_AXCACHE_OFST 4
93#define ZYNQMP_DMA_AXQOS GENMASK(3, 0)
94#define ZYNQMP_DMA_AXQOS_OFST 0
95
96/* Control register 2 bit field definitions */
97#define ZYNQMP_DMA_ENABLE BIT(0)
98
99/* Buffer Descriptor definitions */
100#define ZYNQMP_DMA_DESC_CTRL_STOP 0x10
101#define ZYNQMP_DMA_DESC_CTRL_COMP_INT 0x4
102#define ZYNQMP_DMA_DESC_CTRL_SIZE_256 0x2
103#define ZYNQMP_DMA_DESC_CTRL_COHRNT 0x1
104
105/* Interrupt Mask specific definitions */
106#define ZYNQMP_DMA_INT_ERR (ZYNQMP_DMA_AXI_RD_DATA | \
107 ZYNQMP_DMA_AXI_WR_DATA | \
108 ZYNQMP_DMA_AXI_RD_DST_DSCR | \
109 ZYNQMP_DMA_AXI_RD_SRC_DSCR | \
110 ZYNQMP_DMA_INV_APB)
111#define ZYNQMP_DMA_INT_OVRFL (ZYNQMP_DMA_BYTE_CNT_OVRFL | \
112 ZYNQMP_DMA_IRQ_SRC_ACCT_ERR | \
113 ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
114#define ZYNQMP_DMA_INT_DONE (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE)
115#define ZYNQMP_DMA_INT_EN_DEFAULT_MASK (ZYNQMP_DMA_INT_DONE | \
116 ZYNQMP_DMA_INT_ERR | \
117 ZYNQMP_DMA_INT_OVRFL | \
118 ZYNQMP_DMA_DST_DSCR_DONE)
119
120/* Max number of descriptors per channel */
121#define ZYNQMP_DMA_NUM_DESCS 32
122
123/* Max transfer size per descriptor */
124#define ZYNQMP_DMA_MAX_TRANS_LEN 0x40000000
125
126/* Reset values for data attributes */
127#define ZYNQMP_DMA_AXCACHE_VAL 0xF
128#define ZYNQMP_DMA_ARLEN_RST_VAL 0xF
129#define ZYNQMP_DMA_AWLEN_RST_VAL 0xF
130
131#define ZYNQMP_DMA_SRC_ISSUE_RST_VAL 0x1F
132
133#define ZYNQMP_DMA_IDS_DEFAULT_MASK 0xFFF
134
135/* Bus width in bits */
136#define ZYNQMP_DMA_BUS_WIDTH_64 64
137#define ZYNQMP_DMA_BUS_WIDTH_128 128
138
139#define ZDMA_PM_TIMEOUT 100
140
141#define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
142
143#define to_chan(chan) container_of(chan, struct zynqmp_dma_chan, \
144 common)
145#define tx_to_desc(tx) container_of(tx, struct zynqmp_dma_desc_sw, \
146 async_tx)
147
148/**
149 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
150 * @addr: Buffer address
151 * @size: Size of the buffer
152 * @ctrl: Control word
153 * @nxtdscraddr: Next descriptor base address
154 * @rsvd: Reserved field and for Hw internal use.
155 */
156struct zynqmp_dma_desc_ll {
157 u64 addr;
158 u32 size;
159 u32 ctrl;
160 u64 nxtdscraddr;
161 u64 rsvd;
162};
163
164/**
165 * struct zynqmp_dma_desc_sw - Per Transaction structure
166 * @src: Source address for simple mode dma
167 * @dst: Destination address for simple mode dma
168 * @len: Transfer length for simple mode dma
169 * @node: Node in the channel descriptor list
170 * @tx_list: List head for the current transfer
171 * @async_tx: Async transaction descriptor
172 * @src_v: Virtual address of the src descriptor
173 * @src_p: Physical address of the src descriptor
174 * @dst_v: Virtual address of the dst descriptor
175 * @dst_p: Physical address of the dst descriptor
176 */
177struct zynqmp_dma_desc_sw {
178 u64 src;
179 u64 dst;
180 u32 len;
181 struct list_head node;
182 struct list_head tx_list;
183 struct dma_async_tx_descriptor async_tx;
184 struct zynqmp_dma_desc_ll *src_v;
185 dma_addr_t src_p;
186 struct zynqmp_dma_desc_ll *dst_v;
187 dma_addr_t dst_p;
188};
189
190/**
191 * struct zynqmp_dma_chan - Driver specific DMA channel structure
192 * @zdev: Driver specific device structure
193 * @regs: Control registers offset
194 * @lock: Descriptor operation lock
195 * @pending_list: Descriptors waiting
196 * @free_list: Descriptors free
197 * @active_list: Descriptors active
198 * @sw_desc_pool: SW descriptor pool
199 * @done_list: Complete descriptors
200 * @common: DMA common channel
201 * @desc_pool_v: Statically allocated descriptor base
202 * @desc_pool_p: Physical allocated descriptor base
203 * @desc_free_cnt: Descriptor available count
204 * @dev: The dma device
205 * @irq: Channel IRQ
206 * @is_dmacoherent: Tells whether dma operations are coherent or not
207 * @tasklet: Cleanup work after irq
208 * @idle : Channel status;
209 * @desc_size: Size of the low level descriptor
210 * @err: Channel has errors
211 * @bus_width: Bus width
212 * @src_burst_len: Source burst length
213 * @dst_burst_len: Dest burst length
214 */
215struct zynqmp_dma_chan {
216 struct zynqmp_dma_device *zdev;
217 void __iomem *regs;
218 spinlock_t lock;
219 struct list_head pending_list;
220 struct list_head free_list;
221 struct list_head active_list;
222 struct zynqmp_dma_desc_sw *sw_desc_pool;
223 struct list_head done_list;
224 struct dma_chan common;
225 void *desc_pool_v;
226 dma_addr_t desc_pool_p;
227 u32 desc_free_cnt;
228 struct device *dev;
229 int irq;
230 bool is_dmacoherent;
231 struct tasklet_struct tasklet;
232 bool idle;
233 u32 desc_size;
234 bool err;
235 u32 bus_width;
236 u32 src_burst_len;
237 u32 dst_burst_len;
238};
239
240/**
241 * struct zynqmp_dma_device - DMA device structure
242 * @dev: Device Structure
243 * @common: DMA device structure
244 * @chan: Driver specific DMA channel
245 * @clk_main: Pointer to main clock
246 * @clk_apb: Pointer to apb clock
247 */
248struct zynqmp_dma_device {
249 struct device *dev;
250 struct dma_device common;
251 struct zynqmp_dma_chan *chan;
252 struct clk *clk_main;
253 struct clk *clk_apb;
254};
255
256static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
257 u64 value)
258{
259 lo_hi_writeq(value, chan->regs + reg);
260}
261
262/**
263 * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
264 * @chan: ZynqMP DMA DMA channel pointer
265 * @desc: Transaction descriptor pointer
266 */
267static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
268 struct zynqmp_dma_desc_sw *desc)
269{
270 dma_addr_t addr;
271
272 addr = desc->src_p;
273 zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
274 addr = desc->dst_p;
275 zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
276}
277
278/**
279 * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
280 * @chan: ZynqMP DMA channel pointer
281 * @desc: Hw descriptor pointer
282 */
283static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
284 void *desc)
285{
286 struct zynqmp_dma_desc_ll *hw = (struct zynqmp_dma_desc_ll *)desc;
287
288 hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP;
289 hw++;
290 hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP;
291}
292
293/**
294 * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
295 * @chan: ZynqMP DMA channel pointer
296 * @sdesc: Hw descriptor pointer
297 * @src: Source buffer address
298 * @dst: Destination buffer address
299 * @len: Transfer length
300 * @prev: Previous hw descriptor pointer
301 */
302static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
303 struct zynqmp_dma_desc_ll *sdesc,
304 dma_addr_t src, dma_addr_t dst, size_t len,
305 struct zynqmp_dma_desc_ll *prev)
306{
307 struct zynqmp_dma_desc_ll *ddesc = sdesc + 1;
308
309 sdesc->size = ddesc->size = len;
310 sdesc->addr = src;
311 ddesc->addr = dst;
312
313 sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256;
314 if (chan->is_dmacoherent) {
315 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
316 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
317 }
318
319 if (prev) {
320 dma_addr_t addr = chan->desc_pool_p +
321 ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
322 ddesc = prev + 1;
323 prev->nxtdscraddr = addr;
324 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
325 }
326}
327
328/**
329 * zynqmp_dma_init - Initialize the channel
330 * @chan: ZynqMP DMA channel pointer
331 */
332static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
333{
334 u32 val;
335
336 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
337 val = readl(chan->regs + ZYNQMP_DMA_ISR);
338 writel(val, chan->regs + ZYNQMP_DMA_ISR);
339
340 if (chan->is_dmacoherent) {
341 val = ZYNQMP_DMA_AXCOHRNT;
342 val = (val & ~ZYNQMP_DMA_AXCACHE) |
343 (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AXCACHE_OFST);
344 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
345 }
346
347 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
348 if (chan->is_dmacoherent) {
349 val = (val & ~ZYNQMP_DMA_ARCACHE) |
350 (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_ARCACHE_OFST);
351 val = (val & ~ZYNQMP_DMA_AWCACHE) |
352 (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AWCACHE_OFST);
353 }
354 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
355
356 /* Clearing the interrupt account rgisters */
357 val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
358 val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
359
360 chan->idle = true;
361}
362
363/**
364 * zynqmp_dma_tx_submit - Submit DMA transaction
365 * @tx: Async transaction descriptor pointer
366 *
367 * Return: cookie value
368 */
369static dma_cookie_t zynqmp_dma_tx_submit(struct dma_async_tx_descriptor *tx)
370{
371 struct zynqmp_dma_chan *chan = to_chan(tx->chan);
372 struct zynqmp_dma_desc_sw *desc, *new;
373 dma_cookie_t cookie;
374 unsigned long irqflags;
375
376 new = tx_to_desc(tx);
377 spin_lock_irqsave(&chan->lock, irqflags);
378 cookie = dma_cookie_assign(tx);
379
380 if (!list_empty(&chan->pending_list)) {
381 desc = list_last_entry(&chan->pending_list,
382 struct zynqmp_dma_desc_sw, node);
383 if (!list_empty(&desc->tx_list))
384 desc = list_last_entry(&desc->tx_list,
385 struct zynqmp_dma_desc_sw, node);
386 desc->src_v->nxtdscraddr = new->src_p;
387 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
388 desc->dst_v->nxtdscraddr = new->dst_p;
389 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
390 }
391
392 list_add_tail(&new->node, &chan->pending_list);
393 spin_unlock_irqrestore(&chan->lock, irqflags);
394
395 return cookie;
396}
397
398/**
399 * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
400 * @chan: ZynqMP DMA channel pointer
401 *
402 * Return: The sw descriptor
403 */
404static struct zynqmp_dma_desc_sw *
405zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
406{
407 struct zynqmp_dma_desc_sw *desc;
408 unsigned long irqflags;
409
410 spin_lock_irqsave(&chan->lock, irqflags);
411 desc = list_first_entry(&chan->free_list,
412 struct zynqmp_dma_desc_sw, node);
413 list_del(&desc->node);
414 spin_unlock_irqrestore(&chan->lock, irqflags);
415
416 INIT_LIST_HEAD(&desc->tx_list);
417 /* Clear the src and dst descriptor memory */
418 memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
419 memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
420
421 return desc;
422}
423
424/**
425 * zynqmp_dma_free_descriptor - Issue pending transactions
426 * @chan: ZynqMP DMA channel pointer
427 * @sdesc: Transaction descriptor pointer
428 */
429static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
430 struct zynqmp_dma_desc_sw *sdesc)
431{
432 struct zynqmp_dma_desc_sw *child, *next;
433
434 chan->desc_free_cnt++;
435 list_add_tail(&sdesc->node, &chan->free_list);
436 list_for_each_entry_safe(child, next, &sdesc->tx_list, node) {
437 chan->desc_free_cnt++;
438 list_move_tail(&child->node, &chan->free_list);
439 }
440}
441
442/**
443 * zynqmp_dma_free_desc_list - Free descriptors list
444 * @chan: ZynqMP DMA channel pointer
445 * @list: List to parse and delete the descriptor
446 */
447static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
448 struct list_head *list)
449{
450 struct zynqmp_dma_desc_sw *desc, *next;
451
452 list_for_each_entry_safe(desc, next, list, node)
453 zynqmp_dma_free_descriptor(chan, desc);
454}
455
456/**
457 * zynqmp_dma_alloc_chan_resources - Allocate channel resources
458 * @dchan: DMA channel
459 *
460 * Return: Number of descriptors on success and failure value on error
461 */
462static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan)
463{
464 struct zynqmp_dma_chan *chan = to_chan(dchan);
465 struct zynqmp_dma_desc_sw *desc;
466 int i, ret;
467
468 ret = pm_runtime_get_sync(chan->dev);
469 if (ret < 0)
470 return ret;
471
472 chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
473 GFP_KERNEL);
474 if (!chan->sw_desc_pool)
475 return -ENOMEM;
476
477 chan->idle = true;
478 chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
479
480 INIT_LIST_HEAD(&chan->free_list);
481
482 for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
483 desc = chan->sw_desc_pool + i;
484 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
485 desc->async_tx.tx_submit = zynqmp_dma_tx_submit;
486 list_add_tail(&desc->node, &chan->free_list);
487 }
488
489 chan->desc_pool_v = dma_alloc_coherent(chan->dev,
490 (2 * chan->desc_size * ZYNQMP_DMA_NUM_DESCS),
491 &chan->desc_pool_p, GFP_KERNEL);
492 if (!chan->desc_pool_v)
493 return -ENOMEM;
494
495 for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
496 desc = chan->sw_desc_pool + i;
497 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
498 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
499 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1);
500 desc->src_p = chan->desc_pool_p +
501 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
502 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
503 }
504
505 return ZYNQMP_DMA_NUM_DESCS;
506}
507
508/**
509 * zynqmp_dma_start - Start DMA channel
510 * @chan: ZynqMP DMA channel pointer
511 */
512static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
513{
514 writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
515 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
516 chan->idle = false;
517 writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
518}
519
520/**
521 * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
522 * @chan: ZynqMP DMA channel pointer
523 * @status: Interrupt status value
524 */
525static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
526{
527 if (status & ZYNQMP_DMA_BYTE_CNT_OVRFL)
528 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
529 if (status & ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
530 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
531 if (status & ZYNQMP_DMA_IRQ_SRC_ACCT_ERR)
532 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
533}
534
535static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
536{
537 u32 val;
538
539 val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
540 val |= ZYNQMP_DMA_POINT_TYPE_SG;
541 writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
542
543 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
544 val = (val & ~ZYNQMP_DMA_ARLEN) |
545 (chan->src_burst_len << ZYNQMP_DMA_ARLEN_OFST);
546 val = (val & ~ZYNQMP_DMA_AWLEN) |
547 (chan->dst_burst_len << ZYNQMP_DMA_AWLEN_OFST);
548 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
549}
550
551/**
552 * zynqmp_dma_device_config - Zynqmp dma device configuration
553 * @dchan: DMA channel
554 * @config: DMA device config
555 *
556 * Return: 0 always
557 */
558static int zynqmp_dma_device_config(struct dma_chan *dchan,
559 struct dma_slave_config *config)
560{
561 struct zynqmp_dma_chan *chan = to_chan(dchan);
562
563 chan->src_burst_len = config->src_maxburst;
564 chan->dst_burst_len = config->dst_maxburst;
565
566 return 0;
567}
568
569/**
570 * zynqmp_dma_start_transfer - Initiate the new transfer
571 * @chan: ZynqMP DMA channel pointer
572 */
573static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
574{
575 struct zynqmp_dma_desc_sw *desc;
576
577 if (!chan->idle)
578 return;
579
580 zynqmp_dma_config(chan);
581
582 desc = list_first_entry_or_null(&chan->pending_list,
583 struct zynqmp_dma_desc_sw, node);
584 if (!desc)
585 return;
586
587 list_splice_tail_init(&chan->pending_list, &chan->active_list);
588 zynqmp_dma_update_desc_to_ctrlr(chan, desc);
589 zynqmp_dma_start(chan);
590}
591
592
593/**
594 * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
595 * @chan: ZynqMP DMA channel
596 */
597static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
598{
599 struct zynqmp_dma_desc_sw *desc, *next;
600
601 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
602 dma_async_tx_callback callback;
603 void *callback_param;
604
605 list_del(&desc->node);
606
607 callback = desc->async_tx.callback;
608 callback_param = desc->async_tx.callback_param;
609 if (callback) {
610 spin_unlock(&chan->lock);
611 callback(callback_param);
612 spin_lock(&chan->lock);
613 }
614
615 /* Run any dependencies, then free the descriptor */
616 zynqmp_dma_free_descriptor(chan, desc);
617 }
618}
619
620/**
621 * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
622 * @chan: ZynqMP DMA channel pointer
623 */
624static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
625{
626 struct zynqmp_dma_desc_sw *desc;
627
628 desc = list_first_entry_or_null(&chan->active_list,
629 struct zynqmp_dma_desc_sw, node);
630 if (!desc)
631 return;
632 list_del(&desc->node);
633 dma_cookie_complete(&desc->async_tx);
634 list_add_tail(&desc->node, &chan->done_list);
635}
636
637/**
638 * zynqmp_dma_issue_pending - Issue pending transactions
639 * @dchan: DMA channel pointer
640 */
641static void zynqmp_dma_issue_pending(struct dma_chan *dchan)
642{
643 struct zynqmp_dma_chan *chan = to_chan(dchan);
644 unsigned long irqflags;
645
646 spin_lock_irqsave(&chan->lock, irqflags);
647 zynqmp_dma_start_transfer(chan);
648 spin_unlock_irqrestore(&chan->lock, irqflags);
649}
650
651/**
652 * zynqmp_dma_free_descriptors - Free channel descriptors
653 * @chan: ZynqMP DMA channel pointer
654 */
655static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
656{
657 zynqmp_dma_free_desc_list(chan, &chan->active_list);
658 zynqmp_dma_free_desc_list(chan, &chan->pending_list);
659 zynqmp_dma_free_desc_list(chan, &chan->done_list);
660}
661
662/**
663 * zynqmp_dma_free_chan_resources - Free channel resources
664 * @dchan: DMA channel pointer
665 */
666static void zynqmp_dma_free_chan_resources(struct dma_chan *dchan)
667{
668 struct zynqmp_dma_chan *chan = to_chan(dchan);
669 unsigned long irqflags;
670
671 spin_lock_irqsave(&chan->lock, irqflags);
672 zynqmp_dma_free_descriptors(chan);
673 spin_unlock_irqrestore(&chan->lock, irqflags);
674 dma_free_coherent(chan->dev,
675 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
676 chan->desc_pool_v, chan->desc_pool_p);
677 kfree(chan->sw_desc_pool);
678 pm_runtime_mark_last_busy(chan->dev);
679 pm_runtime_put_autosuspend(chan->dev);
680}
681
682/**
683 * zynqmp_dma_reset - Reset the channel
684 * @chan: ZynqMP DMA channel pointer
685 */
686static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
687{
688 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
689
690 zynqmp_dma_complete_descriptor(chan);
691 zynqmp_dma_chan_desc_cleanup(chan);
692 zynqmp_dma_free_descriptors(chan);
693 zynqmp_dma_init(chan);
694}
695
696/**
697 * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
698 * @irq: IRQ number
699 * @data: Pointer to the ZynqMP DMA channel structure
700 *
701 * Return: IRQ_HANDLED/IRQ_NONE
702 */
703static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
704{
705 struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
706 u32 isr, imr, status;
707 irqreturn_t ret = IRQ_NONE;
708
709 isr = readl(chan->regs + ZYNQMP_DMA_ISR);
710 imr = readl(chan->regs + ZYNQMP_DMA_IMR);
711 status = isr & ~imr;
712
713 writel(isr, chan->regs + ZYNQMP_DMA_ISR);
714 if (status & ZYNQMP_DMA_INT_DONE) {
715 tasklet_schedule(&chan->tasklet);
716 ret = IRQ_HANDLED;
717 }
718
719 if (status & ZYNQMP_DMA_DONE)
720 chan->idle = true;
721
722 if (status & ZYNQMP_DMA_INT_ERR) {
723 chan->err = true;
724 tasklet_schedule(&chan->tasklet);
725 dev_err(chan->dev, "Channel %p has errors\n", chan);
726 ret = IRQ_HANDLED;
727 }
728
729 if (status & ZYNQMP_DMA_INT_OVRFL) {
730 zynqmp_dma_handle_ovfl_int(chan, status);
731 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
732 ret = IRQ_HANDLED;
733 }
734
735 return ret;
736}
737
738/**
739 * zynqmp_dma_do_tasklet - Schedule completion tasklet
740 * @data: Pointer to the ZynqMP DMA channel structure
741 */
742static void zynqmp_dma_do_tasklet(unsigned long data)
743{
744 struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
745 u32 count;
746 unsigned long irqflags;
747
748 spin_lock_irqsave(&chan->lock, irqflags);
749
750 if (chan->err) {
751 zynqmp_dma_reset(chan);
752 chan->err = false;
753 goto unlock;
754 }
755
756 count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
757
758 while (count) {
759 zynqmp_dma_complete_descriptor(chan);
760 zynqmp_dma_chan_desc_cleanup(chan);
761 count--;
762 }
763
764 if (chan->idle)
765 zynqmp_dma_start_transfer(chan);
766
767unlock:
768 spin_unlock_irqrestore(&chan->lock, irqflags);
769}
770
771/**
772 * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
773 * @dchan: DMA channel pointer
774 *
775 * Return: Always '0'
776 */
777static int zynqmp_dma_device_terminate_all(struct dma_chan *dchan)
778{
779 struct zynqmp_dma_chan *chan = to_chan(dchan);
780 unsigned long irqflags;
781
782 spin_lock_irqsave(&chan->lock, irqflags);
783 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
784 zynqmp_dma_free_descriptors(chan);
785 spin_unlock_irqrestore(&chan->lock, irqflags);
786
787 return 0;
788}
789
790/**
791 * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
792 * @dchan: DMA channel
793 * @dma_dst: Destination buffer address
794 * @dma_src: Source buffer address
795 * @len: Transfer length
796 * @flags: transfer ack flags
797 *
798 * Return: Async transaction descriptor on success and NULL on failure
799 */
800static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
801 struct dma_chan *dchan, dma_addr_t dma_dst,
802 dma_addr_t dma_src, size_t len, ulong flags)
803{
804 struct zynqmp_dma_chan *chan;
805 struct zynqmp_dma_desc_sw *new, *first = NULL;
806 void *desc = NULL, *prev = NULL;
807 size_t copy;
808 u32 desc_cnt;
809 unsigned long irqflags;
810
811 chan = to_chan(dchan);
812
813 desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN);
814
815 spin_lock_irqsave(&chan->lock, irqflags);
816 if (desc_cnt > chan->desc_free_cnt) {
817 spin_unlock_irqrestore(&chan->lock, irqflags);
818 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
819 return NULL;
820 }
821 chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
822 spin_unlock_irqrestore(&chan->lock, irqflags);
823
824 do {
825 /* Allocate and populate the descriptor */
826 new = zynqmp_dma_get_descriptor(chan);
827
828 copy = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
829 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
830 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
831 dma_dst, copy, prev);
832 prev = desc;
833 len -= copy;
834 dma_src += copy;
835 dma_dst += copy;
836 if (!first)
837 first = new;
838 else
839 list_add_tail(&new->node, &first->tx_list);
840 } while (len);
841
842 zynqmp_dma_desc_config_eod(chan, desc);
843 async_tx_ack(&first->async_tx);
844 first->async_tx.flags = flags;
845 return &first->async_tx;
846}
847
848/**
849 * zynqmp_dma_chan_remove - Channel remove function
850 * @chan: ZynqMP DMA channel pointer
851 */
852static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
853{
854 if (!chan)
855 return;
856
857 if (chan->irq)
858 devm_free_irq(chan->zdev->dev, chan->irq, chan);
859 tasklet_kill(&chan->tasklet);
860 list_del(&chan->common.device_node);
861}
862
863/**
864 * zynqmp_dma_chan_probe - Per Channel Probing
865 * @zdev: Driver specific device structure
866 * @pdev: Pointer to the platform_device structure
867 *
868 * Return: '0' on success and failure value on error
869 */
870static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
871 struct platform_device *pdev)
872{
873 struct zynqmp_dma_chan *chan;
874 struct resource *res;
875 struct device_node *node = pdev->dev.of_node;
876 int err;
877
878 chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
879 if (!chan)
880 return -ENOMEM;
881 chan->dev = zdev->dev;
882 chan->zdev = zdev;
883
884 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
885 chan->regs = devm_ioremap_resource(&pdev->dev, res);
886 if (IS_ERR(chan->regs))
887 return PTR_ERR(chan->regs);
888
889 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
890 chan->dst_burst_len = ZYNQMP_DMA_AWLEN_RST_VAL;
891 chan->src_burst_len = ZYNQMP_DMA_ARLEN_RST_VAL;
892 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
893 if (err < 0) {
894 dev_err(&pdev->dev, "missing xlnx,bus-width property\n");
895 return err;
896 }
897
898 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
899 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
900 dev_err(zdev->dev, "invalid bus-width value");
901 return -EINVAL;
902 }
903
904 chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent");
905 zdev->chan = chan;
906 tasklet_init(&chan->tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
907 spin_lock_init(&chan->lock);
908 INIT_LIST_HEAD(&chan->active_list);
909 INIT_LIST_HEAD(&chan->pending_list);
910 INIT_LIST_HEAD(&chan->done_list);
911 INIT_LIST_HEAD(&chan->free_list);
912
913 dma_cookie_init(&chan->common);
914 chan->common.device = &zdev->common;
915 list_add_tail(&chan->common.device_node, &zdev->common.channels);
916
917 zynqmp_dma_init(chan);
918 chan->irq = platform_get_irq(pdev, 0);
919 if (chan->irq < 0)
920 return -ENXIO;
921 err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
922 "zynqmp-dma", chan);
923 if (err)
924 return err;
925
926 chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
927 chan->idle = true;
928 return 0;
929}
930
931/**
932 * of_zynqmp_dma_xlate - Translation function
933 * @dma_spec: Pointer to DMA specifier as found in the device tree
934 * @ofdma: Pointer to DMA controller data
935 *
936 * Return: DMA channel pointer on success and NULL on error
937 */
938static struct dma_chan *of_zynqmp_dma_xlate(struct of_phandle_args *dma_spec,
939 struct of_dma *ofdma)
940{
941 struct zynqmp_dma_device *zdev = ofdma->of_dma_data;
942
943 return dma_get_slave_channel(&zdev->chan->common);
944}
945
946/**
947 * zynqmp_dma_suspend - Suspend method for the driver
948 * @dev: Address of the device structure
949 *
950 * Put the driver into low power mode.
951 * Return: 0 on success and failure value on error
952 */
953static int __maybe_unused zynqmp_dma_suspend(struct device *dev)
954{
955 if (!device_may_wakeup(dev))
956 return pm_runtime_force_suspend(dev);
957
958 return 0;
959}
960
961/**
962 * zynqmp_dma_resume - Resume from suspend
963 * @dev: Address of the device structure
964 *
965 * Resume operation after suspend.
966 * Return: 0 on success and failure value on error
967 */
968static int __maybe_unused zynqmp_dma_resume(struct device *dev)
969{
970 if (!device_may_wakeup(dev))
971 return pm_runtime_force_resume(dev);
972
973 return 0;
974}
975
976/**
977 * zynqmp_dma_runtime_suspend - Runtime suspend method for the driver
978 * @dev: Address of the device structure
979 *
980 * Put the driver into low power mode.
981 * Return: 0 always
982 */
983static int __maybe_unused zynqmp_dma_runtime_suspend(struct device *dev)
984{
985 struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
986
987 clk_disable_unprepare(zdev->clk_main);
988 clk_disable_unprepare(zdev->clk_apb);
989
990 return 0;
991}
992
993/**
994 * zynqmp_dma_runtime_resume - Runtime suspend method for the driver
995 * @dev: Address of the device structure
996 *
997 * Put the driver into low power mode.
998 * Return: 0 always
999 */
1000static int __maybe_unused zynqmp_dma_runtime_resume(struct device *dev)
1001{
1002 struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
1003 int err;
1004
1005 err = clk_prepare_enable(zdev->clk_main);
1006 if (err) {
1007 dev_err(dev, "Unable to enable main clock.\n");
1008 return err;
1009 }
1010
1011 err = clk_prepare_enable(zdev->clk_apb);
1012 if (err) {
1013 dev_err(dev, "Unable to enable apb clock.\n");
1014 clk_disable_unprepare(zdev->clk_main);
1015 return err;
1016 }
1017
1018 return 0;
1019}
1020
1021static const struct dev_pm_ops zynqmp_dma_dev_pm_ops = {
1022 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dma_suspend, zynqmp_dma_resume)
1023 SET_RUNTIME_PM_OPS(zynqmp_dma_runtime_suspend,
1024 zynqmp_dma_runtime_resume, NULL)
1025};
1026
1027/**
1028 * zynqmp_dma_probe - Driver probe function
1029 * @pdev: Pointer to the platform_device structure
1030 *
1031 * Return: '0' on success and failure value on error
1032 */
1033static int zynqmp_dma_probe(struct platform_device *pdev)
1034{
1035 struct zynqmp_dma_device *zdev;
1036 struct dma_device *p;
1037 int ret;
1038
1039 zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL);
1040 if (!zdev)
1041 return -ENOMEM;
1042
1043 zdev->dev = &pdev->dev;
1044 INIT_LIST_HEAD(&zdev->common.channels);
1045
1046 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1047 dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
1048
1049 p = &zdev->common;
1050 p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy;
1051 p->device_terminate_all = zynqmp_dma_device_terminate_all;
1052 p->device_issue_pending = zynqmp_dma_issue_pending;
1053 p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources;
1054 p->device_free_chan_resources = zynqmp_dma_free_chan_resources;
1055 p->device_tx_status = dma_cookie_status;
1056 p->device_config = zynqmp_dma_device_config;
1057 p->dev = &pdev->dev;
1058
1059 zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main");
1060 if (IS_ERR(zdev->clk_main)) {
1061 dev_err(&pdev->dev, "main clock not found.\n");
1062 return PTR_ERR(zdev->clk_main);
1063 }
1064
1065 zdev->clk_apb = devm_clk_get(&pdev->dev, "clk_apb");
1066 if (IS_ERR(zdev->clk_apb)) {
1067 dev_err(&pdev->dev, "apb clock not found.\n");
1068 return PTR_ERR(zdev->clk_apb);
1069 }
1070
1071 platform_set_drvdata(pdev, zdev);
1072 pm_runtime_set_autosuspend_delay(zdev->dev, ZDMA_PM_TIMEOUT);
1073 pm_runtime_use_autosuspend(zdev->dev);
1074 pm_runtime_enable(zdev->dev);
1075 pm_runtime_get_sync(zdev->dev);
1076 if (!pm_runtime_enabled(zdev->dev)) {
1077 ret = zynqmp_dma_runtime_resume(zdev->dev);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 ret = zynqmp_dma_chan_probe(zdev, pdev);
1083 if (ret) {
1084 dev_err(&pdev->dev, "Probing channel failed\n");
1085 goto err_disable_pm;
1086 }
1087
1088 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1089 p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1090
1091 dma_async_device_register(&zdev->common);
1092
1093 ret = of_dma_controller_register(pdev->dev.of_node,
1094 of_zynqmp_dma_xlate, zdev);
1095 if (ret) {
1096 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
1097 dma_async_device_unregister(&zdev->common);
1098 goto free_chan_resources;
1099 }
1100
1101 pm_runtime_mark_last_busy(zdev->dev);
1102 pm_runtime_put_sync_autosuspend(zdev->dev);
1103
1104 dev_info(&pdev->dev, "ZynqMP DMA driver Probe success\n");
1105
1106 return 0;
1107
1108free_chan_resources:
1109 zynqmp_dma_chan_remove(zdev->chan);
1110err_disable_pm:
1111 if (!pm_runtime_enabled(zdev->dev))
1112 zynqmp_dma_runtime_suspend(zdev->dev);
1113 pm_runtime_disable(zdev->dev);
1114 return ret;
1115}
1116
1117/**
1118 * zynqmp_dma_remove - Driver remove function
1119 * @pdev: Pointer to the platform_device structure
1120 *
1121 * Return: Always '0'
1122 */
1123static int zynqmp_dma_remove(struct platform_device *pdev)
1124{
1125 struct zynqmp_dma_device *zdev = platform_get_drvdata(pdev);
1126
1127 of_dma_controller_free(pdev->dev.of_node);
1128 dma_async_device_unregister(&zdev->common);
1129
1130 zynqmp_dma_chan_remove(zdev->chan);
1131 pm_runtime_disable(zdev->dev);
1132 if (!pm_runtime_enabled(zdev->dev))
1133 zynqmp_dma_runtime_suspend(zdev->dev);
1134
1135 return 0;
1136}
1137
1138static const struct of_device_id zynqmp_dma_of_match[] = {
1139 { .compatible = "xlnx,zynqmp-dma-1.0", },
1140 {}
1141};
1142MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
1143
1144static struct platform_driver zynqmp_dma_driver = {
1145 .driver = {
1146 .name = "xilinx-zynqmp-dma",
1147 .of_match_table = zynqmp_dma_of_match,
1148 .pm = &zynqmp_dma_dev_pm_ops,
1149 },
1150 .probe = zynqmp_dma_probe,
1151 .remove = zynqmp_dma_remove,
1152};
1153
1154module_platform_driver(zynqmp_dma_driver);
1155
1156MODULE_LICENSE("GPL");
1157MODULE_AUTHOR("Xilinx, Inc.");
1158MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");