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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_LAPIC_H
3#define __KVM_X86_LAPIC_H
4
5#include <kvm/iodev.h>
6
7#include <linux/kvm_host.h>
8
9#include "hyperv.h"
10#include "smm.h"
11
12#define KVM_APIC_INIT 0
13#define KVM_APIC_SIPI 1
14
15#define APIC_SHORT_MASK 0xc0000
16#define APIC_DEST_NOSHORT 0x0
17#define APIC_DEST_MASK 0x800
18
19#define APIC_BUS_CYCLE_NS 1
20#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
21
22#define APIC_BROADCAST 0xFF
23#define X2APIC_BROADCAST 0xFFFFFFFFul
24
25enum lapic_mode {
26 LAPIC_MODE_DISABLED = 0,
27 LAPIC_MODE_INVALID = X2APIC_ENABLE,
28 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
29 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
30};
31
32enum lapic_lvt_entry {
33 LVT_TIMER,
34 LVT_THERMAL_MONITOR,
35 LVT_PERFORMANCE_COUNTER,
36 LVT_LINT0,
37 LVT_LINT1,
38 LVT_ERROR,
39 LVT_CMCI,
40
41 KVM_APIC_MAX_NR_LVT_ENTRIES,
42};
43
44#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
45
46struct kvm_timer {
47 struct hrtimer timer;
48 s64 period; /* unit: ns */
49 ktime_t target_expiration;
50 u32 timer_mode;
51 u32 timer_mode_mask;
52 u64 tscdeadline;
53 u64 expired_tscdeadline;
54 u32 timer_advance_ns;
55 atomic_t pending; /* accumulated triggered timers */
56 bool hv_timer_in_use;
57};
58
59struct kvm_lapic {
60 unsigned long base_address;
61 struct kvm_io_device dev;
62 struct kvm_timer lapic_timer;
63 u32 divide_count;
64 struct kvm_vcpu *vcpu;
65 bool apicv_active;
66 bool sw_enabled;
67 bool irr_pending;
68 bool lvt0_in_nmi_mode;
69 /* Number of bits set in ISR. */
70 s16 isr_count;
71 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
72 int highest_isr_cache;
73 /**
74 * APIC register page. The layout matches the register layout seen by
75 * the guest 1:1, because it is accessed by the vmx microcode.
76 * Note: Only one register, the TPR, is used by the microcode.
77 */
78 void *regs;
79 gpa_t vapic_addr;
80 struct gfn_to_hva_cache vapic_cache;
81 unsigned long pending_events;
82 unsigned int sipi_vector;
83 int nr_lvt_entries;
84};
85
86struct dest_map;
87
88int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
89void kvm_free_lapic(struct kvm_vcpu *vcpu);
90
91int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
92int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
93int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
94int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
95void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
96u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
97void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
98void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
99void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
100u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
101void kvm_recalculate_apic_map(struct kvm *kvm);
102void kvm_apic_set_version(struct kvm_vcpu *vcpu);
103void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
104bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
105 int shorthand, unsigned int dest, int dest_mode);
106int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
107void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
108bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
109bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
110void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
111int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
112 struct dest_map *dest_map);
113int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
114void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
115
116bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
117 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
118void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
119
120u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
121int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
122int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
123int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
124enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
125int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
126
127u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
128void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
129
130void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
131void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
132
133int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
134void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
135void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
136
137int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
138int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
139int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
140
141int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
142int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
143
144int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
145void kvm_lapic_exit(void);
146
147#define VEC_POS(v) ((v) & (32 - 1))
148#define REG_POS(v) (((v) >> 5) << 4)
149
150static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
151{
152 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
153}
154
155static inline void kvm_lapic_set_vector(int vec, void *bitmap)
156{
157 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
158}
159
160static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
161{
162 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
163 /*
164 * irr_pending must be true if any interrupt is pending; set it after
165 * APIC_IRR to avoid race with apic_clear_irr
166 */
167 apic->irr_pending = true;
168}
169
170static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
171{
172 return *((u32 *) (regs + reg_off));
173}
174
175static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
176{
177 return __kvm_lapic_get_reg(apic->regs, reg_off);
178}
179
180DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
181
182static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
183{
184 if (static_branch_unlikely(&kvm_has_noapic_vcpu))
185 return vcpu->arch.apic;
186 return true;
187}
188
189extern struct static_key_false_deferred apic_hw_disabled;
190
191static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
192{
193 if (static_branch_unlikely(&apic_hw_disabled.key))
194 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
195 return true;
196}
197
198extern struct static_key_false_deferred apic_sw_disabled;
199
200static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
201{
202 if (static_branch_unlikely(&apic_sw_disabled.key))
203 return apic->sw_enabled;
204 return true;
205}
206
207static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
208{
209 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
210}
211
212static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
213{
214 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
215}
216
217static inline int apic_x2apic_mode(struct kvm_lapic *apic)
218{
219 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
220}
221
222static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
223{
224 return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
225}
226
227static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
228{
229 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
230}
231
232static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
233{
234 return !is_smm(vcpu) &&
235 !static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
236}
237
238static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
239{
240 return (irq->delivery_mode == APIC_DM_LOWEST ||
241 irq->msi_redir_hint);
242}
243
244static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
245{
246 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
247}
248
249bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
250
251void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
252
253void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
254 unsigned long *vcpu_bitmap);
255
256bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
257 struct kvm_vcpu **dest_vcpu);
258int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
259 const unsigned long *bitmap, u32 bitmap_size);
260void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
261void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
262void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
263bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
264void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
265bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
266
267static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
268{
269 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270}
271
272static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
273{
274 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
275}
276
277#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_LAPIC_H
3#define __KVM_X86_LAPIC_H
4
5#include <kvm/iodev.h>
6
7#include <linux/kvm_host.h>
8
9#define KVM_APIC_INIT 0
10#define KVM_APIC_SIPI 1
11#define KVM_APIC_LVT_NUM 6
12
13#define KVM_APIC_SHORT_MASK 0xc0000
14#define KVM_APIC_DEST_MASK 0x800
15
16#define APIC_BUS_CYCLE_NS 1
17#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
18
19enum lapic_mode {
20 LAPIC_MODE_DISABLED = 0,
21 LAPIC_MODE_INVALID = X2APIC_ENABLE,
22 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
23 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
24};
25
26struct kvm_timer {
27 struct hrtimer timer;
28 s64 period; /* unit: ns */
29 ktime_t target_expiration;
30 u32 timer_mode;
31 u32 timer_mode_mask;
32 u64 tscdeadline;
33 u64 expired_tscdeadline;
34 u32 timer_advance_ns;
35 s64 advance_expire_delta;
36 atomic_t pending; /* accumulated triggered timers */
37 bool hv_timer_in_use;
38};
39
40struct kvm_lapic {
41 unsigned long base_address;
42 struct kvm_io_device dev;
43 struct kvm_timer lapic_timer;
44 u32 divide_count;
45 struct kvm_vcpu *vcpu;
46 bool sw_enabled;
47 bool irr_pending;
48 bool lvt0_in_nmi_mode;
49 /* Number of bits set in ISR. */
50 s16 isr_count;
51 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
52 int highest_isr_cache;
53 /**
54 * APIC register page. The layout matches the register layout seen by
55 * the guest 1:1, because it is accessed by the vmx microcode.
56 * Note: Only one register, the TPR, is used by the microcode.
57 */
58 void *regs;
59 gpa_t vapic_addr;
60 struct gfn_to_hva_cache vapic_cache;
61 unsigned long pending_events;
62 unsigned int sipi_vector;
63};
64
65struct dest_map;
66
67int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
68void kvm_free_lapic(struct kvm_vcpu *vcpu);
69
70int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
71int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
72int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
73void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
74void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
75u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
76void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
77void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
78void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
79u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
80void kvm_apic_set_version(struct kvm_vcpu *vcpu);
81int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
82int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
83 void *data);
84bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
85 int short_hand, unsigned int dest, int dest_mode);
86
87bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
88bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
89void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
90int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
91 struct dest_map *dest_map);
92int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
93
94bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
95 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
96
97u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
98int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
99int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
100int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
101enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
102int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
103
104u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
105void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
106
107void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
108void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
109
110int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
111void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
112void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
113
114int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
115int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
116
117int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
118int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
119
120static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
121{
122 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
123}
124
125int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
126void kvm_lapic_init(void);
127void kvm_lapic_exit(void);
128
129#define VEC_POS(v) ((v) & (32 - 1))
130#define REG_POS(v) (((v) >> 5) << 4)
131
132static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
133{
134 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
135}
136
137static inline void kvm_lapic_set_vector(int vec, void *bitmap)
138{
139 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
140}
141
142static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
143{
144 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
145 /*
146 * irr_pending must be true if any interrupt is pending; set it after
147 * APIC_IRR to avoid race with apic_clear_irr
148 */
149 apic->irr_pending = true;
150}
151
152static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
153{
154 return *((u32 *) (apic->regs + reg_off));
155}
156
157static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
158{
159 *((u32 *) (apic->regs + reg_off)) = val;
160}
161
162extern struct static_key kvm_no_apic_vcpu;
163
164static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
165{
166 if (static_key_false(&kvm_no_apic_vcpu))
167 return vcpu->arch.apic;
168 return true;
169}
170
171extern struct static_key_deferred apic_hw_disabled;
172
173static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
174{
175 if (static_key_false(&apic_hw_disabled.key))
176 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
177 return MSR_IA32_APICBASE_ENABLE;
178}
179
180extern struct static_key_deferred apic_sw_disabled;
181
182static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
183{
184 if (static_key_false(&apic_sw_disabled.key))
185 return apic->sw_enabled;
186 return true;
187}
188
189static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
190{
191 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
192}
193
194static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
195{
196 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
197}
198
199static inline int apic_x2apic_mode(struct kvm_lapic *apic)
200{
201 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
202}
203
204static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
205{
206 return vcpu->arch.apic && vcpu->arch.apicv_active;
207}
208
209static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
210{
211 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
212}
213
214static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
215{
216 return (irq->delivery_mode == APIC_DM_LOWEST ||
217 irq->msi_redir_hint);
218}
219
220static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
221{
222 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
223}
224
225bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
226
227void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
228
229bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
230 struct kvm_vcpu **dest_vcpu);
231int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
232 const unsigned long *bitmap, u32 bitmap_size);
233void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
234void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
235void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
236bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
237void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
238bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu);
239
240static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
241{
242 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
243}
244
245static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
246{
247 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
248}
249
250#endif