Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * S390 low-level entry points.
4 *
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 */
10
11#include <linux/init.h>
12#include <linux/linkage.h>
13#include <asm/asm-extable.h>
14#include <asm/alternative-asm.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/dwarf.h>
18#include <asm/errno.h>
19#include <asm/ptrace.h>
20#include <asm/thread_info.h>
21#include <asm/asm-offsets.h>
22#include <asm/unistd.h>
23#include <asm/page.h>
24#include <asm/sigp.h>
25#include <asm/irq.h>
26#include <asm/vx-insn.h>
27#include <asm/setup.h>
28#include <asm/nmi.h>
29#include <asm/export.h>
30#include <asm/nospec-insn.h>
31
32STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
33STACK_SIZE = 1 << STACK_SHIFT
34STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
35
36_LPP_OFFSET = __LC_LPP
37
38 .macro STBEAR address
39 ALTERNATIVE "nop", ".insn s,0xb2010000,\address", 193
40 .endm
41
42 .macro LBEAR address
43 ALTERNATIVE "nop", ".insn s,0xb2000000,\address", 193
44 .endm
45
46 .macro LPSWEY address,lpswe
47 ALTERNATIVE "b \lpswe; nopr", ".insn siy,0xeb0000000071,\address,0", 193
48 .endm
49
50 .macro MBEAR reg
51 ALTERNATIVE "brcl 0,0", __stringify(mvc __PT_LAST_BREAK(8,\reg),__LC_LAST_BREAK), 193
52 .endm
53
54 .macro CHECK_STACK savearea
55#ifdef CONFIG_CHECK_STACK
56 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
57 lghi %r14,\savearea
58 jz stack_overflow
59#endif
60 .endm
61
62 .macro CHECK_VMAP_STACK savearea,oklabel
63#ifdef CONFIG_VMAP_STACK
64 lgr %r14,%r15
65 nill %r14,0x10000 - STACK_SIZE
66 oill %r14,STACK_INIT
67 clg %r14,__LC_KERNEL_STACK
68 je \oklabel
69 clg %r14,__LC_ASYNC_STACK
70 je \oklabel
71 clg %r14,__LC_MCCK_STACK
72 je \oklabel
73 clg %r14,__LC_NODAT_STACK
74 je \oklabel
75 clg %r14,__LC_RESTART_STACK
76 je \oklabel
77 lghi %r14,\savearea
78 j stack_overflow
79#else
80 j \oklabel
81#endif
82 .endm
83
84 /*
85 * The TSTMSK macro generates a test-under-mask instruction by
86 * calculating the memory offset for the specified mask value.
87 * Mask value can be any constant. The macro shifts the mask
88 * value to calculate the memory offset for the test-under-mask
89 * instruction.
90 */
91 .macro TSTMSK addr, mask, size=8, bytepos=0
92 .if (\bytepos < \size) && (\mask >> 8)
93 .if (\mask & 0xff)
94 .error "Mask exceeds byte boundary"
95 .endif
96 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
97 .exitm
98 .endif
99 .ifeq \mask
100 .error "Mask must not be zero"
101 .endif
102 off = \size - \bytepos - 1
103 tm off+\addr, \mask
104 .endm
105
106 .macro BPOFF
107 ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,12,0", 82
108 .endm
109
110 .macro BPON
111 ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,13,0", 82
112 .endm
113
114 .macro BPENTER tif_ptr,tif_mask
115 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .insn rrf,0xb2e80000,0,0,13,0", \
116 "j .+12; nop; nop", 82
117 .endm
118
119 .macro BPEXIT tif_ptr,tif_mask
120 TSTMSK \tif_ptr,\tif_mask
121 ALTERNATIVE "jz .+8; .insn rrf,0xb2e80000,0,0,12,0", \
122 "jnz .+8; .insn rrf,0xb2e80000,0,0,13,0", 82
123 .endm
124
125#if IS_ENABLED(CONFIG_KVM)
126 /*
127 * The OUTSIDE macro jumps to the provided label in case the value
128 * in the provided register is outside of the provided range. The
129 * macro is useful for checking whether a PSW stored in a register
130 * pair points inside or outside of a block of instructions.
131 * @reg: register to check
132 * @start: start of the range
133 * @end: end of the range
134 * @outside_label: jump here if @reg is outside of [@start..@end)
135 */
136 .macro OUTSIDE reg,start,end,outside_label
137 lgr %r14,\reg
138 larl %r13,\start
139 slgr %r14,%r13
140#ifdef CONFIG_AS_IS_LLVM
141 clgfrl %r14,.Lrange_size\@
142#else
143 clgfi %r14,\end - \start
144#endif
145 jhe \outside_label
146#ifdef CONFIG_AS_IS_LLVM
147 .section .rodata, "a"
148 .align 4
149.Lrange_size\@:
150 .long \end - \start
151 .previous
152#endif
153 .endm
154
155 .macro SIEEXIT
156 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
157 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
158 lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
159 larl %r9,sie_exit # skip forward to sie_exit
160 .endm
161#endif
162
163 GEN_BR_THUNK %r14
164
165 .section .kprobes.text, "ax"
166.Ldummy:
167 /*
168 * This nop exists only in order to avoid that __bpon starts at
169 * the beginning of the kprobes text section. In that case we would
170 * have several symbols at the same address. E.g. objdump would take
171 * an arbitrary symbol name when disassembling this code.
172 * With the added nop in between the __bpon symbol is unique
173 * again.
174 */
175 nop 0
176
177ENTRY(__bpon)
178 .globl __bpon
179 BPON
180 BR_EX %r14
181ENDPROC(__bpon)
182
183/*
184 * Scheduler resume function, called by switch_to
185 * gpr2 = (task_struct *) prev
186 * gpr3 = (task_struct *) next
187 * Returns:
188 * gpr2 = prev
189 */
190ENTRY(__switch_to)
191 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
192 lghi %r4,__TASK_stack
193 lghi %r1,__TASK_thread
194 llill %r5,STACK_INIT
195 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
196 lg %r15,0(%r4,%r3) # start of kernel stack of next
197 agr %r15,%r5 # end of kernel stack of next
198 stg %r3,__LC_CURRENT # store task struct of next
199 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
200 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
201 aghi %r3,__TASK_pid
202 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
203 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
204 ALTERNATIVE "nop", "lpp _LPP_OFFSET", 40
205 BR_EX %r14
206ENDPROC(__switch_to)
207
208#if IS_ENABLED(CONFIG_KVM)
209/*
210 * __sie64a calling convention:
211 * %r2 pointer to sie control block phys
212 * %r3 pointer to sie control block virt
213 * %r4 guest register save area
214 */
215ENTRY(__sie64a)
216 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
217 lg %r12,__LC_CURRENT
218 stg %r2,__SF_SIE_CONTROL_PHYS(%r15) # save sie block physical..
219 stg %r3,__SF_SIE_CONTROL(%r15) # ...and virtual addresses
220 stg %r4,__SF_SIE_SAVEAREA(%r15) # save guest register save area
221 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
222 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
223 lmg %r0,%r13,0(%r4) # load guest gprs 0-13
224 lg %r14,__LC_GMAP # get gmap pointer
225 ltgr %r14,%r14
226 jz .Lsie_gmap
227 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
228.Lsie_gmap:
229 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
230 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
231 tm __SIE_PROG20+3(%r14),3 # last exit...
232 jnz .Lsie_skip
233 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
234 jo .Lsie_skip # exit if fp/vx regs changed
235 lg %r14,__SF_SIE_CONTROL_PHYS(%r15) # get sie block phys addr
236 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
237.Lsie_entry:
238 sie 0(%r14)
239# Let the next instruction be NOP to avoid triggering a machine check
240# and handling it in a guest as result of the instruction execution.
241 nopr 7
242.Lsie_leave:
243 BPOFF
244 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
245.Lsie_skip:
246 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
247 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
248 lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
249.Lsie_done:
250# some program checks are suppressing. C code (e.g. do_protection_exception)
251# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
252# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
253# Other instructions between __sie64a and .Lsie_done should not cause program
254# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
255.Lrewind_pad6:
256 nopr 7
257.Lrewind_pad4:
258 nopr 7
259.Lrewind_pad2:
260 nopr 7
261 .globl sie_exit
262sie_exit:
263 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
264 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
265 xgr %r0,%r0 # clear guest registers to
266 xgr %r1,%r1 # prevent speculative use
267 xgr %r3,%r3
268 xgr %r4,%r4
269 xgr %r5,%r5
270 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
271 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
272 BR_EX %r14
273.Lsie_fault:
274 lghi %r14,-EFAULT
275 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
276 j sie_exit
277
278 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
279 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
280 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
281 EX_TABLE(sie_exit,.Lsie_fault)
282ENDPROC(__sie64a)
283EXPORT_SYMBOL(__sie64a)
284EXPORT_SYMBOL(sie_exit)
285#endif
286
287/*
288 * SVC interrupt handler routine. System calls are synchronous events and
289 * are entered with interrupts disabled.
290 */
291
292ENTRY(system_call)
293 stpt __LC_SYS_ENTER_TIMER
294 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
295 BPOFF
296 lghi %r14,0
297.Lsysc_per:
298 STBEAR __LC_LAST_BREAK
299 lctlg %c1,%c1,__LC_KERNEL_ASCE
300 lg %r12,__LC_CURRENT
301 lg %r15,__LC_KERNEL_STACK
302 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
303 stmg %r0,%r7,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
304 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
305 # clear user controlled register to prevent speculative use
306 xgr %r0,%r0
307 xgr %r1,%r1
308 xgr %r4,%r4
309 xgr %r5,%r5
310 xgr %r6,%r6
311 xgr %r7,%r7
312 xgr %r8,%r8
313 xgr %r9,%r9
314 xgr %r10,%r10
315 xgr %r11,%r11
316 la %r2,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
317 mvc __PT_R8(64,%r2),__LC_SAVE_AREA_SYNC
318 MBEAR %r2
319 lgr %r3,%r14
320 brasl %r14,__do_syscall
321 lctlg %c1,%c1,__LC_USER_ASCE
322 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
323 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
324 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
325 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
326 stpt __LC_EXIT_TIMER
327 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
328ENDPROC(system_call)
329
330#
331# a new process exits the kernel with ret_from_fork
332#
333ENTRY(ret_from_fork)
334 lgr %r3,%r11
335 brasl %r14,__ret_from_fork
336 lctlg %c1,%c1,__LC_USER_ASCE
337 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
338 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
339 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
340 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
341 stpt __LC_EXIT_TIMER
342 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
343ENDPROC(ret_from_fork)
344
345/*
346 * Program check handler routine
347 */
348
349ENTRY(pgm_check_handler)
350 stpt __LC_SYS_ENTER_TIMER
351 BPOFF
352 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
353 lg %r12,__LC_CURRENT
354 lghi %r10,0
355 lmg %r8,%r9,__LC_PGM_OLD_PSW
356 tmhh %r8,0x0001 # coming from user space?
357 jno .Lpgm_skip_asce
358 lctlg %c1,%c1,__LC_KERNEL_ASCE
359 j 3f # -> fault in user space
360.Lpgm_skip_asce:
361#if IS_ENABLED(CONFIG_KVM)
362 # cleanup critical section for program checks in __sie64a
363 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,1f
364 SIEEXIT
365 lghi %r10,_PIF_GUEST_FAULT
366#endif
3671: tmhh %r8,0x4000 # PER bit set in old PSW ?
368 jnz 2f # -> enabled, can't be a double fault
369 tm __LC_PGM_ILC+3,0x80 # check for per exception
370 jnz .Lpgm_svcper # -> single stepped svc
3712: CHECK_STACK __LC_SAVE_AREA_SYNC
372 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
373 # CHECK_VMAP_STACK branches to stack_overflow or 4f
374 CHECK_VMAP_STACK __LC_SAVE_AREA_SYNC,4f
3753: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
376 lg %r15,__LC_KERNEL_STACK
3774: la %r11,STACK_FRAME_OVERHEAD(%r15)
378 stg %r10,__PT_FLAGS(%r11)
379 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
380 stmg %r0,%r7,__PT_R0(%r11)
381 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
382 mvc __PT_LAST_BREAK(8,%r11),__LC_PGM_LAST_BREAK
383 stmg %r8,%r9,__PT_PSW(%r11)
384
385 # clear user controlled registers to prevent speculative use
386 xgr %r0,%r0
387 xgr %r1,%r1
388 xgr %r3,%r3
389 xgr %r4,%r4
390 xgr %r5,%r5
391 xgr %r6,%r6
392 xgr %r7,%r7
393 lgr %r2,%r11
394 brasl %r14,__do_pgm_check
395 tmhh %r8,0x0001 # returning to user space?
396 jno .Lpgm_exit_kernel
397 lctlg %c1,%c1,__LC_USER_ASCE
398 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
399 stpt __LC_EXIT_TIMER
400.Lpgm_exit_kernel:
401 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
402 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
403 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
404 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
405
406#
407# single stepped system call
408#
409.Lpgm_svcper:
410 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
411 larl %r14,.Lsysc_per
412 stg %r14,__LC_RETURN_PSW+8
413 lghi %r14,1
414 LBEAR __LC_PGM_LAST_BREAK
415 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE # branch to .Lsysc_per
416ENDPROC(pgm_check_handler)
417
418/*
419 * Interrupt handler macro used for external and IO interrupts.
420 */
421.macro INT_HANDLER name,lc_old_psw,handler
422ENTRY(\name)
423 stckf __LC_INT_CLOCK
424 stpt __LC_SYS_ENTER_TIMER
425 STBEAR __LC_LAST_BREAK
426 BPOFF
427 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
428 lg %r12,__LC_CURRENT
429 lmg %r8,%r9,\lc_old_psw
430 tmhh %r8,0x0001 # interrupting from user ?
431 jnz 1f
432#if IS_ENABLED(CONFIG_KVM)
433 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,0f
434 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
435 SIEEXIT
436#endif
4370: CHECK_STACK __LC_SAVE_AREA_ASYNC
438 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
439 j 2f
4401: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
441 lctlg %c1,%c1,__LC_KERNEL_ASCE
442 lg %r15,__LC_KERNEL_STACK
4432: xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
444 la %r11,STACK_FRAME_OVERHEAD(%r15)
445 stmg %r0,%r7,__PT_R0(%r11)
446 # clear user controlled registers to prevent speculative use
447 xgr %r0,%r0
448 xgr %r1,%r1
449 xgr %r3,%r3
450 xgr %r4,%r4
451 xgr %r5,%r5
452 xgr %r6,%r6
453 xgr %r7,%r7
454 xgr %r10,%r10
455 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
456 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
457 MBEAR %r11
458 stmg %r8,%r9,__PT_PSW(%r11)
459 lgr %r2,%r11 # pass pointer to pt_regs
460 brasl %r14,\handler
461 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
462 tmhh %r8,0x0001 # returning to user ?
463 jno 2f
464 lctlg %c1,%c1,__LC_USER_ASCE
465 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
466 stpt __LC_EXIT_TIMER
4672: LBEAR __PT_LAST_BREAK(%r11)
468 lmg %r0,%r15,__PT_R0(%r11)
469 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
470ENDPROC(\name)
471.endm
472
473INT_HANDLER ext_int_handler,__LC_EXT_OLD_PSW,do_ext_irq
474INT_HANDLER io_int_handler,__LC_IO_OLD_PSW,do_io_irq
475
476/*
477 * Load idle PSW.
478 */
479ENTRY(psw_idle)
480 stg %r14,(__SF_GPRS+8*8)(%r15)
481 stg %r3,__SF_EMPTY(%r15)
482 larl %r1,psw_idle_exit
483 stg %r1,__SF_EMPTY+8(%r15)
484 larl %r1,smp_cpu_mtid
485 llgf %r1,0(%r1)
486 ltgr %r1,%r1
487 jz .Lpsw_idle_stcctm
488 .insn rsy,0xeb0000000017,%r1,5,__MT_CYCLES_ENTER(%r2)
489.Lpsw_idle_stcctm:
490 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
491 BPON
492 stckf __CLOCK_IDLE_ENTER(%r2)
493 stpt __TIMER_IDLE_ENTER(%r2)
494 lpswe __SF_EMPTY(%r15)
495.globl psw_idle_exit
496psw_idle_exit:
497 BR_EX %r14
498ENDPROC(psw_idle)
499
500/*
501 * Machine check handler routines
502 */
503ENTRY(mcck_int_handler)
504 stckf __LC_MCCK_CLOCK
505 BPOFF
506 la %r1,4095 # validate r1
507 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
508 LBEAR __LC_LAST_BREAK_SAVE_AREA-4095(%r1) # validate bear
509 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
510 lg %r12,__LC_CURRENT
511 lmg %r8,%r9,__LC_MCK_OLD_PSW
512 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
513 jo .Lmcck_panic # yes -> rest of mcck code invalid
514 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
515 jno .Lmcck_panic # control registers invalid -> panic
516 la %r14,4095
517 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
518 ptlb
519 lghi %r14,__LC_CPU_TIMER_SAVE_AREA
520 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
521 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
522 jo 3f
523 la %r14,__LC_SYS_ENTER_TIMER
524 clc 0(8,%r14),__LC_EXIT_TIMER
525 jl 1f
526 la %r14,__LC_EXIT_TIMER
5271: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
528 jl 2f
529 la %r14,__LC_LAST_UPDATE_TIMER
5302: spt 0(%r14)
531 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
5323: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
533 jno .Lmcck_panic
534 tmhh %r8,0x0001 # interrupting from user ?
535 jnz .Lmcck_user
536 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
537 jno .Lmcck_panic
538#if IS_ENABLED(CONFIG_KVM)
539 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,.Lmcck_stack
540 OUTSIDE %r9,.Lsie_entry,.Lsie_leave,4f
541 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
5424: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
543 SIEEXIT
544 j .Lmcck_stack
545#endif
546.Lmcck_user:
547 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
548.Lmcck_stack:
549 lg %r15,__LC_MCCK_STACK
550 la %r11,STACK_FRAME_OVERHEAD(%r15)
551 stctg %c1,%c1,__PT_CR1(%r11)
552 lctlg %c1,%c1,__LC_KERNEL_ASCE
553 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
554 lghi %r14,__LC_GPREGS_SAVE_AREA+64
555 stmg %r0,%r7,__PT_R0(%r11)
556 # clear user controlled registers to prevent speculative use
557 xgr %r0,%r0
558 xgr %r1,%r1
559 xgr %r3,%r3
560 xgr %r4,%r4
561 xgr %r5,%r5
562 xgr %r6,%r6
563 xgr %r7,%r7
564 xgr %r10,%r10
565 mvc __PT_R8(64,%r11),0(%r14)
566 stmg %r8,%r9,__PT_PSW(%r11)
567 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
568 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
569 lgr %r2,%r11 # pass pointer to pt_regs
570 brasl %r14,s390_do_machine_check
571 cghi %r2,0
572 je .Lmcck_return
573 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
574 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
575 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
576 la %r11,STACK_FRAME_OVERHEAD(%r1)
577 lgr %r2,%r11
578 lgr %r15,%r1
579 brasl %r14,s390_handle_mcck
580.Lmcck_return:
581 lctlg %c1,%c1,__PT_CR1(%r11)
582 lmg %r0,%r10,__PT_R0(%r11)
583 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
584 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
585 jno 0f
586 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
587 stpt __LC_EXIT_TIMER
5880: ALTERNATIVE "nop", __stringify(lghi %r12,__LC_LAST_BREAK_SAVE_AREA),193
589 LBEAR 0(%r12)
590 lmg %r11,%r15,__PT_R11(%r11)
591 LPSWEY __LC_RETURN_MCCK_PSW,__LC_RETURN_MCCK_LPSWE
592
593.Lmcck_panic:
594 /*
595 * Iterate over all possible CPU addresses in the range 0..0xffff
596 * and stop each CPU using signal processor. Use compare and swap
597 * to allow just one CPU-stopper and prevent concurrent CPUs from
598 * stopping each other while leaving the others running.
599 */
600 lhi %r5,0
601 lhi %r6,1
602 larl %r7,.Lstop_lock
603 cs %r5,%r6,0(%r7) # single CPU-stopper only
604 jnz 4f
605 larl %r7,.Lthis_cpu
606 stap 0(%r7) # this CPU address
607 lh %r4,0(%r7)
608 nilh %r4,0
609 lhi %r0,1
610 sll %r0,16 # CPU counter
611 lhi %r3,0 # next CPU address
6120: cr %r3,%r4
613 je 2f
6141: sigp %r1,%r3,SIGP_STOP # stop next CPU
615 brc SIGP_CC_BUSY,1b
6162: ahi %r3,1
617 brct %r0,0b
6183: sigp %r1,%r4,SIGP_STOP # stop this CPU
619 brc SIGP_CC_BUSY,3b
6204: j 4b
621ENDPROC(mcck_int_handler)
622
623ENTRY(restart_int_handler)
624 ALTERNATIVE "nop", "lpp _LPP_OFFSET", 40
625 stg %r15,__LC_SAVE_AREA_RESTART
626 TSTMSK __LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4
627 jz 0f
628 la %r15,4095
629 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r15)
6300: larl %r15,.Lstosm_tmp
631 stosm 0(%r15),0x04 # turn dat on, keep irqs off
632 lg %r15,__LC_RESTART_STACK
633 xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
634 stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
635 mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
636 mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW
637 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
638 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
639 lg %r2,__LC_RESTART_DATA
640 lgf %r3,__LC_RESTART_SOURCE
641 ltgr %r3,%r3 # test source cpu address
642 jm 1f # negative -> skip source stop
6430: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
644 brc 10,0b # wait for status stored
6451: basr %r14,%r1 # call function
646 stap __SF_EMPTY(%r15) # store cpu address
647 llgh %r3,__SF_EMPTY(%r15)
6482: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
649 brc 2,2b
6503: j 3b
651ENDPROC(restart_int_handler)
652
653 .section .kprobes.text, "ax"
654
655#if defined(CONFIG_CHECK_STACK) || defined(CONFIG_VMAP_STACK)
656/*
657 * The synchronous or the asynchronous stack overflowed. We are dead.
658 * No need to properly save the registers, we are going to panic anyway.
659 * Setup a pt_regs so that show_trace can provide a good call trace.
660 */
661ENTRY(stack_overflow)
662 lg %r15,__LC_NODAT_STACK # change to panic stack
663 la %r11,STACK_FRAME_OVERHEAD(%r15)
664 stmg %r0,%r7,__PT_R0(%r11)
665 stmg %r8,%r9,__PT_PSW(%r11)
666 mvc __PT_R8(64,%r11),0(%r14)
667 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
668 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
669 lgr %r2,%r11 # pass pointer to pt_regs
670 jg kernel_stack_overflow
671ENDPROC(stack_overflow)
672#endif
673
674 .section .data, "aw"
675 .align 4
676.Lstop_lock: .long 0
677.Lthis_cpu: .short 0
678.Lstosm_tmp: .byte 0
679 .section .rodata, "a"
680#define SYSCALL(esame,emu) .quad __s390x_ ## esame
681 .globl sys_call_table
682sys_call_table:
683#include "asm/syscall_table.h"
684#undef SYSCALL
685
686#ifdef CONFIG_COMPAT
687
688#define SYSCALL(esame,emu) .quad __s390_ ## emu
689 .globl sys_call_table_emu
690sys_call_table_emu:
691#include "asm/syscall_table.h"
692#undef SYSCALL
693#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * S390 low-level entry points.
4 *
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
10 */
11
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/alternative-asm.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/ctl_reg.h>
18#include <asm/dwarf.h>
19#include <asm/errno.h>
20#include <asm/ptrace.h>
21#include <asm/thread_info.h>
22#include <asm/asm-offsets.h>
23#include <asm/unistd.h>
24#include <asm/page.h>
25#include <asm/sigp.h>
26#include <asm/irq.h>
27#include <asm/vx-insn.h>
28#include <asm/setup.h>
29#include <asm/nmi.h>
30#include <asm/export.h>
31#include <asm/nospec-insn.h>
32
33__PT_R0 = __PT_GPRS
34__PT_R1 = __PT_GPRS + 8
35__PT_R2 = __PT_GPRS + 16
36__PT_R3 = __PT_GPRS + 24
37__PT_R4 = __PT_GPRS + 32
38__PT_R5 = __PT_GPRS + 40
39__PT_R6 = __PT_GPRS + 48
40__PT_R7 = __PT_GPRS + 56
41__PT_R8 = __PT_GPRS + 64
42__PT_R9 = __PT_GPRS + 72
43__PT_R10 = __PT_GPRS + 80
44__PT_R11 = __PT_GPRS + 88
45__PT_R12 = __PT_GPRS + 96
46__PT_R13 = __PT_GPRS + 104
47__PT_R14 = __PT_GPRS + 112
48__PT_R15 = __PT_GPRS + 120
49
50STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
51STACK_SIZE = 1 << STACK_SHIFT
52STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
53
54_TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
55 _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
56_TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
57 _TIF_SYSCALL_TRACEPOINT)
58_CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
59 _CIF_ASCE_SECONDARY | _CIF_FPU)
60_PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
61
62_LPP_OFFSET = __LC_LPP
63
64#define BASED(name) name-cleanup_critical(%r13)
65
66 .macro TRACE_IRQS_ON
67#ifdef CONFIG_TRACE_IRQFLAGS
68 basr %r2,%r0
69 brasl %r14,trace_hardirqs_on_caller
70#endif
71 .endm
72
73 .macro TRACE_IRQS_OFF
74#ifdef CONFIG_TRACE_IRQFLAGS
75 basr %r2,%r0
76 brasl %r14,trace_hardirqs_off_caller
77#endif
78 .endm
79
80 .macro LOCKDEP_SYS_EXIT
81#ifdef CONFIG_LOCKDEP
82 tm __PT_PSW+1(%r11),0x01 # returning to user ?
83 jz .+10
84 brasl %r14,lockdep_sys_exit
85#endif
86 .endm
87
88 .macro CHECK_STACK savearea
89#ifdef CONFIG_CHECK_STACK
90 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
91 lghi %r14,\savearea
92 jz stack_overflow
93#endif
94 .endm
95
96 .macro CHECK_VMAP_STACK savearea,oklabel
97#ifdef CONFIG_VMAP_STACK
98 lgr %r14,%r15
99 nill %r14,0x10000 - STACK_SIZE
100 oill %r14,STACK_INIT
101 clg %r14,__LC_KERNEL_STACK
102 je \oklabel
103 clg %r14,__LC_ASYNC_STACK
104 je \oklabel
105 clg %r14,__LC_NODAT_STACK
106 je \oklabel
107 clg %r14,__LC_RESTART_STACK
108 je \oklabel
109 lghi %r14,\savearea
110 j stack_overflow
111#else
112 j \oklabel
113#endif
114 .endm
115
116 .macro SWITCH_ASYNC savearea,timer
117 tmhh %r8,0x0001 # interrupting from user ?
118 jnz 1f
119 lgr %r14,%r9
120 slg %r14,BASED(.Lcritical_start)
121 clg %r14,BASED(.Lcritical_length)
122 jhe 0f
123 lghi %r11,\savearea # inside critical section, do cleanup
124 brasl %r14,cleanup_critical
125 tmhh %r8,0x0001 # retest problem state after cleanup
126 jnz 1f
1270: lg %r14,__LC_ASYNC_STACK # are we already on the target stack?
128 slgr %r14,%r15
129 srag %r14,%r14,STACK_SHIFT
130 jnz 2f
131 CHECK_STACK \savearea
132 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
133 j 3f
1341: UPDATE_VTIME %r14,%r15,\timer
135 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1362: lg %r15,__LC_ASYNC_STACK # load async stack
1373: la %r11,STACK_FRAME_OVERHEAD(%r15)
138 .endm
139
140 .macro UPDATE_VTIME w1,w2,enter_timer
141 lg \w1,__LC_EXIT_TIMER
142 lg \w2,__LC_LAST_UPDATE_TIMER
143 slg \w1,\enter_timer
144 slg \w2,__LC_EXIT_TIMER
145 alg \w1,__LC_USER_TIMER
146 alg \w2,__LC_SYSTEM_TIMER
147 stg \w1,__LC_USER_TIMER
148 stg \w2,__LC_SYSTEM_TIMER
149 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
150 .endm
151
152 .macro REENABLE_IRQS
153 stg %r8,__LC_RETURN_PSW
154 ni __LC_RETURN_PSW,0xbf
155 ssm __LC_RETURN_PSW
156 .endm
157
158 .macro STCK savearea
159#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
160 .insn s,0xb27c0000,\savearea # store clock fast
161#else
162 .insn s,0xb2050000,\savearea # store clock
163#endif
164 .endm
165
166 /*
167 * The TSTMSK macro generates a test-under-mask instruction by
168 * calculating the memory offset for the specified mask value.
169 * Mask value can be any constant. The macro shifts the mask
170 * value to calculate the memory offset for the test-under-mask
171 * instruction.
172 */
173 .macro TSTMSK addr, mask, size=8, bytepos=0
174 .if (\bytepos < \size) && (\mask >> 8)
175 .if (\mask & 0xff)
176 .error "Mask exceeds byte boundary"
177 .endif
178 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
179 .exitm
180 .endif
181 .ifeq \mask
182 .error "Mask must not be zero"
183 .endif
184 off = \size - \bytepos - 1
185 tm off+\addr, \mask
186 .endm
187
188 .macro BPOFF
189 ALTERNATIVE "", ".long 0xb2e8c000", 82
190 .endm
191
192 .macro BPON
193 ALTERNATIVE "", ".long 0xb2e8d000", 82
194 .endm
195
196 .macro BPENTER tif_ptr,tif_mask
197 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \
198 "", 82
199 .endm
200
201 .macro BPEXIT tif_ptr,tif_mask
202 TSTMSK \tif_ptr,\tif_mask
203 ALTERNATIVE "jz .+8; .long 0xb2e8c000", \
204 "jnz .+8; .long 0xb2e8d000", 82
205 .endm
206
207 GEN_BR_THUNK %r9
208 GEN_BR_THUNK %r14
209 GEN_BR_THUNK %r14,%r11
210
211 .section .kprobes.text, "ax"
212.Ldummy:
213 /*
214 * This nop exists only in order to avoid that __switch_to starts at
215 * the beginning of the kprobes text section. In that case we would
216 * have several symbols at the same address. E.g. objdump would take
217 * an arbitrary symbol name when disassembling this code.
218 * With the added nop in between the __switch_to symbol is unique
219 * again.
220 */
221 nop 0
222
223ENTRY(__bpon)
224 .globl __bpon
225 BPON
226 BR_EX %r14
227ENDPROC(__bpon)
228
229/*
230 * Scheduler resume function, called by switch_to
231 * gpr2 = (task_struct *) prev
232 * gpr3 = (task_struct *) next
233 * Returns:
234 * gpr2 = prev
235 */
236ENTRY(__switch_to)
237 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
238 lghi %r4,__TASK_stack
239 lghi %r1,__TASK_thread
240 llill %r5,STACK_INIT
241 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
242 lg %r15,0(%r4,%r3) # start of kernel stack of next
243 agr %r15,%r5 # end of kernel stack of next
244 stg %r3,__LC_CURRENT # store task struct of next
245 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
246 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
247 aghi %r3,__TASK_pid
248 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
249 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
250 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
251 BR_EX %r14
252ENDPROC(__switch_to)
253
254.L__critical_start:
255
256#if IS_ENABLED(CONFIG_KVM)
257/*
258 * sie64a calling convention:
259 * %r2 pointer to sie control block
260 * %r3 guest register save area
261 */
262ENTRY(sie64a)
263 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
264 lg %r12,__LC_CURRENT
265 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
266 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
267 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
268 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
269 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
270 jno .Lsie_load_guest_gprs
271 brasl %r14,load_fpu_regs # load guest fp/vx regs
272.Lsie_load_guest_gprs:
273 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
274 lg %r14,__LC_GMAP # get gmap pointer
275 ltgr %r14,%r14
276 jz .Lsie_gmap
277 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
278.Lsie_gmap:
279 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
280 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
281 tm __SIE_PROG20+3(%r14),3 # last exit...
282 jnz .Lsie_skip
283 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
284 jo .Lsie_skip # exit if fp/vx regs changed
285 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
286.Lsie_entry:
287 sie 0(%r14)
288.Lsie_exit:
289 BPOFF
290 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
291.Lsie_skip:
292 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
293 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
294.Lsie_done:
295# some program checks are suppressing. C code (e.g. do_protection_exception)
296# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
297# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
298# Other instructions between sie64a and .Lsie_done should not cause program
299# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
300# See also .Lcleanup_sie
301.Lrewind_pad6:
302 nopr 7
303.Lrewind_pad4:
304 nopr 7
305.Lrewind_pad2:
306 nopr 7
307 .globl sie_exit
308sie_exit:
309 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
310 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
311 xgr %r0,%r0 # clear guest registers to
312 xgr %r1,%r1 # prevent speculative use
313 xgr %r2,%r2
314 xgr %r3,%r3
315 xgr %r4,%r4
316 xgr %r5,%r5
317 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
318 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
319 BR_EX %r14
320.Lsie_fault:
321 lghi %r14,-EFAULT
322 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
323 j sie_exit
324
325 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
326 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
327 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
328 EX_TABLE(sie_exit,.Lsie_fault)
329ENDPROC(sie64a)
330EXPORT_SYMBOL(sie64a)
331EXPORT_SYMBOL(sie_exit)
332#endif
333
334/*
335 * SVC interrupt handler routine. System calls are synchronous events and
336 * are executed with interrupts enabled.
337 */
338
339ENTRY(system_call)
340 stpt __LC_SYNC_ENTER_TIMER
341.Lsysc_stmg:
342 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
343 BPOFF
344 lg %r12,__LC_CURRENT
345 lghi %r13,__TASK_thread
346 lghi %r14,_PIF_SYSCALL
347.Lsysc_per:
348 lg %r15,__LC_KERNEL_STACK
349 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
350.Lsysc_vtime:
351 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
352 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
353 stmg %r0,%r7,__PT_R0(%r11)
354 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
355 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
356 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
357 stg %r14,__PT_FLAGS(%r11)
358.Lsysc_do_svc:
359 # clear user controlled register to prevent speculative use
360 xgr %r0,%r0
361 # load address of system call table
362 lg %r10,__THREAD_sysc_table(%r13,%r12)
363 llgh %r8,__PT_INT_CODE+2(%r11)
364 slag %r8,%r8,3 # shift and test for svc 0
365 jnz .Lsysc_nr_ok
366 # svc 0: system call number in %r1
367 llgfr %r1,%r1 # clear high word in r1
368 cghi %r1,NR_syscalls
369 jnl .Lsysc_nr_ok
370 sth %r1,__PT_INT_CODE+2(%r11)
371 slag %r8,%r1,3
372.Lsysc_nr_ok:
373 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
374 stg %r2,__PT_ORIG_GPR2(%r11)
375 stg %r7,STACK_FRAME_OVERHEAD(%r15)
376 lg %r9,0(%r8,%r10) # get system call add.
377 TSTMSK __TI_flags(%r12),_TIF_TRACE
378 jnz .Lsysc_tracesys
379 BASR_EX %r14,%r9 # call sys_xxxx
380 stg %r2,__PT_R2(%r11) # store return value
381
382.Lsysc_return:
383#ifdef CONFIG_DEBUG_RSEQ
384 lgr %r2,%r11
385 brasl %r14,rseq_syscall
386#endif
387 LOCKDEP_SYS_EXIT
388.Lsysc_tif:
389 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
390 jnz .Lsysc_work
391 TSTMSK __TI_flags(%r12),_TIF_WORK
392 jnz .Lsysc_work # check for work
393 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
394 jnz .Lsysc_work
395 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
396.Lsysc_restore:
397 lg %r14,__LC_VDSO_PER_CPU
398 lmg %r0,%r10,__PT_R0(%r11)
399 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
400.Lsysc_exit_timer:
401 stpt __LC_EXIT_TIMER
402 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
403 lmg %r11,%r15,__PT_R11(%r11)
404 lpswe __LC_RETURN_PSW
405.Lsysc_done:
406
407#
408# One of the work bits is on. Find out which one.
409#
410.Lsysc_work:
411 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
412 jo .Lsysc_mcck_pending
413 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
414 jo .Lsysc_reschedule
415 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
416 jo .Lsysc_syscall_restart
417#ifdef CONFIG_UPROBES
418 TSTMSK __TI_flags(%r12),_TIF_UPROBE
419 jo .Lsysc_uprobe_notify
420#endif
421 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
422 jo .Lsysc_guarded_storage
423 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
424 jo .Lsysc_singlestep
425#ifdef CONFIG_LIVEPATCH
426 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
427 jo .Lsysc_patch_pending # handle live patching just before
428 # signals and possible syscall restart
429#endif
430 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
431 jo .Lsysc_syscall_restart
432 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
433 jo .Lsysc_sigpending
434 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
435 jo .Lsysc_notify_resume
436 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
437 jo .Lsysc_vxrs
438 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
439 jnz .Lsysc_asce
440 j .Lsysc_return # beware of critical section cleanup
441
442#
443# _TIF_NEED_RESCHED is set, call schedule
444#
445.Lsysc_reschedule:
446 larl %r14,.Lsysc_return
447 jg schedule
448
449#
450# _CIF_MCCK_PENDING is set, call handler
451#
452.Lsysc_mcck_pending:
453 larl %r14,.Lsysc_return
454 jg s390_handle_mcck # TIF bit will be cleared by handler
455
456#
457# _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
458#
459.Lsysc_asce:
460 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
461 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
462 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
463 jz .Lsysc_return
464#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
465 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
466 jnz .Lsysc_set_fs_fixup
467 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
468 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
469 j .Lsysc_return
470.Lsysc_set_fs_fixup:
471#endif
472 larl %r14,.Lsysc_return
473 jg set_fs_fixup
474
475#
476# CIF_FPU is set, restore floating-point controls and floating-point registers.
477#
478.Lsysc_vxrs:
479 larl %r14,.Lsysc_return
480 jg load_fpu_regs
481
482#
483# _TIF_SIGPENDING is set, call do_signal
484#
485.Lsysc_sigpending:
486 lgr %r2,%r11 # pass pointer to pt_regs
487 brasl %r14,do_signal
488 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
489 jno .Lsysc_return
490.Lsysc_do_syscall:
491 lghi %r13,__TASK_thread
492 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
493 lghi %r1,0 # svc 0 returns -ENOSYS
494 j .Lsysc_do_svc
495
496#
497# _TIF_NOTIFY_RESUME is set, call do_notify_resume
498#
499.Lsysc_notify_resume:
500 lgr %r2,%r11 # pass pointer to pt_regs
501 larl %r14,.Lsysc_return
502 jg do_notify_resume
503
504#
505# _TIF_UPROBE is set, call uprobe_notify_resume
506#
507#ifdef CONFIG_UPROBES
508.Lsysc_uprobe_notify:
509 lgr %r2,%r11 # pass pointer to pt_regs
510 larl %r14,.Lsysc_return
511 jg uprobe_notify_resume
512#endif
513
514#
515# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
516#
517.Lsysc_guarded_storage:
518 lgr %r2,%r11 # pass pointer to pt_regs
519 larl %r14,.Lsysc_return
520 jg gs_load_bc_cb
521#
522# _TIF_PATCH_PENDING is set, call klp_update_patch_state
523#
524#ifdef CONFIG_LIVEPATCH
525.Lsysc_patch_pending:
526 lg %r2,__LC_CURRENT # pass pointer to task struct
527 larl %r14,.Lsysc_return
528 jg klp_update_patch_state
529#endif
530
531#
532# _PIF_PER_TRAP is set, call do_per_trap
533#
534.Lsysc_singlestep:
535 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
536 lgr %r2,%r11 # pass pointer to pt_regs
537 larl %r14,.Lsysc_return
538 jg do_per_trap
539
540#
541# _PIF_SYSCALL_RESTART is set, repeat the current system call
542#
543.Lsysc_syscall_restart:
544 ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
545 lmg %r1,%r7,__PT_R1(%r11) # load svc arguments
546 lg %r2,__PT_ORIG_GPR2(%r11)
547 j .Lsysc_do_svc
548
549#
550# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
551# and after the system call
552#
553.Lsysc_tracesys:
554 lgr %r2,%r11 # pass pointer to pt_regs
555 la %r3,0
556 llgh %r0,__PT_INT_CODE+2(%r11)
557 stg %r0,__PT_R2(%r11)
558 brasl %r14,do_syscall_trace_enter
559 lghi %r0,NR_syscalls
560 clgr %r0,%r2
561 jnh .Lsysc_tracenogo
562 sllg %r8,%r2,3
563 lg %r9,0(%r8,%r10)
564.Lsysc_tracego:
565 lmg %r3,%r7,__PT_R3(%r11)
566 stg %r7,STACK_FRAME_OVERHEAD(%r15)
567 lg %r2,__PT_ORIG_GPR2(%r11)
568 BASR_EX %r14,%r9 # call sys_xxx
569 stg %r2,__PT_R2(%r11) # store return value
570.Lsysc_tracenogo:
571 TSTMSK __TI_flags(%r12),_TIF_TRACE
572 jz .Lsysc_return
573 lgr %r2,%r11 # pass pointer to pt_regs
574 larl %r14,.Lsysc_return
575 jg do_syscall_trace_exit
576ENDPROC(system_call)
577
578#
579# a new process exits the kernel with ret_from_fork
580#
581ENTRY(ret_from_fork)
582 la %r11,STACK_FRAME_OVERHEAD(%r15)
583 lg %r12,__LC_CURRENT
584 brasl %r14,schedule_tail
585 TRACE_IRQS_ON
586 ssm __LC_SVC_NEW_PSW # reenable interrupts
587 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
588 jne .Lsysc_tracenogo
589 # it's a kernel thread
590 lmg %r9,%r10,__PT_R9(%r11) # load gprs
591 la %r2,0(%r10)
592 BASR_EX %r14,%r9
593 j .Lsysc_tracenogo
594ENDPROC(ret_from_fork)
595
596ENTRY(kernel_thread_starter)
597 la %r2,0(%r10)
598 BASR_EX %r14,%r9
599 j .Lsysc_tracenogo
600ENDPROC(kernel_thread_starter)
601
602/*
603 * Program check handler routine
604 */
605
606ENTRY(pgm_check_handler)
607 stpt __LC_SYNC_ENTER_TIMER
608 BPOFF
609 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
610 lg %r10,__LC_LAST_BREAK
611 lg %r12,__LC_CURRENT
612 lghi %r11,0
613 larl %r13,cleanup_critical
614 lmg %r8,%r9,__LC_PGM_OLD_PSW
615 tmhh %r8,0x0001 # test problem state bit
616 jnz 2f # -> fault in user space
617#if IS_ENABLED(CONFIG_KVM)
618 # cleanup critical section for program checks in sie64a
619 lgr %r14,%r9
620 slg %r14,BASED(.Lsie_critical_start)
621 clg %r14,BASED(.Lsie_critical_length)
622 jhe 0f
623 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
624 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
625 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
626 larl %r9,sie_exit # skip forward to sie_exit
627 lghi %r11,_PIF_GUEST_FAULT
628#endif
6290: tmhh %r8,0x4000 # PER bit set in old PSW ?
630 jnz 1f # -> enabled, can't be a double fault
631 tm __LC_PGM_ILC+3,0x80 # check for per exception
632 jnz .Lpgm_svcper # -> single stepped svc
6331: CHECK_STACK __LC_SAVE_AREA_SYNC
634 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
635 # CHECK_VMAP_STACK branches to stack_overflow or 4f
636 CHECK_VMAP_STACK __LC_SAVE_AREA_SYNC,4f
6372: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
638 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
639 lg %r15,__LC_KERNEL_STACK
640 lgr %r14,%r12
641 aghi %r14,__TASK_thread # pointer to thread_struct
642 lghi %r13,__LC_PGM_TDB
643 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
644 jz 3f
645 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
6463: stg %r10,__THREAD_last_break(%r14)
6474: lgr %r13,%r11
648 la %r11,STACK_FRAME_OVERHEAD(%r15)
649 stmg %r0,%r7,__PT_R0(%r11)
650 # clear user controlled registers to prevent speculative use
651 xgr %r0,%r0
652 xgr %r1,%r1
653 xgr %r2,%r2
654 xgr %r3,%r3
655 xgr %r4,%r4
656 xgr %r5,%r5
657 xgr %r6,%r6
658 xgr %r7,%r7
659 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
660 stmg %r8,%r9,__PT_PSW(%r11)
661 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
662 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
663 stg %r13,__PT_FLAGS(%r11)
664 stg %r10,__PT_ARGS(%r11)
665 tm __LC_PGM_ILC+3,0x80 # check for per exception
666 jz 5f
667 tmhh %r8,0x0001 # kernel per event ?
668 jz .Lpgm_kprobe
669 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
670 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
671 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
672 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
6735: REENABLE_IRQS
674 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
675 larl %r1,pgm_check_table
676 llgh %r10,__PT_INT_CODE+2(%r11)
677 nill %r10,0x007f
678 sll %r10,3
679 je .Lpgm_return
680 lg %r9,0(%r10,%r1) # load address of handler routine
681 lgr %r2,%r11 # pass pointer to pt_regs
682 BASR_EX %r14,%r9 # branch to interrupt-handler
683.Lpgm_return:
684 LOCKDEP_SYS_EXIT
685 tm __PT_PSW+1(%r11),0x01 # returning to user ?
686 jno .Lsysc_restore
687 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
688 jo .Lsysc_do_syscall
689 j .Lsysc_tif
690
691#
692# PER event in supervisor state, must be kprobes
693#
694.Lpgm_kprobe:
695 REENABLE_IRQS
696 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
697 lgr %r2,%r11 # pass pointer to pt_regs
698 brasl %r14,do_per_trap
699 j .Lpgm_return
700
701#
702# single stepped system call
703#
704.Lpgm_svcper:
705 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
706 lghi %r13,__TASK_thread
707 larl %r14,.Lsysc_per
708 stg %r14,__LC_RETURN_PSW+8
709 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
710 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
711ENDPROC(pgm_check_handler)
712
713/*
714 * IO interrupt handler routine
715 */
716ENTRY(io_int_handler)
717 STCK __LC_INT_CLOCK
718 stpt __LC_ASYNC_ENTER_TIMER
719 BPOFF
720 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
721 lg %r12,__LC_CURRENT
722 larl %r13,cleanup_critical
723 lmg %r8,%r9,__LC_IO_OLD_PSW
724 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
725 stmg %r0,%r7,__PT_R0(%r11)
726 # clear user controlled registers to prevent speculative use
727 xgr %r0,%r0
728 xgr %r1,%r1
729 xgr %r2,%r2
730 xgr %r3,%r3
731 xgr %r4,%r4
732 xgr %r5,%r5
733 xgr %r6,%r6
734 xgr %r7,%r7
735 xgr %r10,%r10
736 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
737 stmg %r8,%r9,__PT_PSW(%r11)
738 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
739 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
740 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
741 jo .Lio_restore
742 TRACE_IRQS_OFF
743 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
744.Lio_loop:
745 lgr %r2,%r11 # pass pointer to pt_regs
746 lghi %r3,IO_INTERRUPT
747 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
748 jz .Lio_call
749 lghi %r3,THIN_INTERRUPT
750.Lio_call:
751 brasl %r14,do_IRQ
752 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
753 jz .Lio_return
754 tpi 0
755 jz .Lio_return
756 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
757 j .Lio_loop
758.Lio_return:
759 LOCKDEP_SYS_EXIT
760 TRACE_IRQS_ON
761.Lio_tif:
762 TSTMSK __TI_flags(%r12),_TIF_WORK
763 jnz .Lio_work # there is work to do (signals etc.)
764 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
765 jnz .Lio_work
766.Lio_restore:
767 lg %r14,__LC_VDSO_PER_CPU
768 lmg %r0,%r10,__PT_R0(%r11)
769 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
770 tm __PT_PSW+1(%r11),0x01 # returning to user ?
771 jno .Lio_exit_kernel
772 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
773.Lio_exit_timer:
774 stpt __LC_EXIT_TIMER
775 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
776.Lio_exit_kernel:
777 lmg %r11,%r15,__PT_R11(%r11)
778 lpswe __LC_RETURN_PSW
779.Lio_done:
780
781#
782# There is work todo, find out in which context we have been interrupted:
783# 1) if we return to user space we can do all _TIF_WORK work
784# 2) if we return to kernel code and kvm is enabled check if we need to
785# modify the psw to leave SIE
786# 3) if we return to kernel code and preemptive scheduling is enabled check
787# the preemption counter and if it is zero call preempt_schedule_irq
788# Before any work can be done, a switch to the kernel stack is required.
789#
790.Lio_work:
791 tm __PT_PSW+1(%r11),0x01 # returning to user ?
792 jo .Lio_work_user # yes -> do resched & signal
793#ifdef CONFIG_PREEMPT
794 # check for preemptive scheduling
795 icm %r0,15,__LC_PREEMPT_COUNT
796 jnz .Lio_restore # preemption is disabled
797 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
798 jno .Lio_restore
799 # switch to kernel stack
800 lg %r1,__PT_R15(%r11)
801 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
802 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
803 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
804 la %r11,STACK_FRAME_OVERHEAD(%r1)
805 lgr %r15,%r1
806 # TRACE_IRQS_ON already done at .Lio_return, call
807 # TRACE_IRQS_OFF to keep things symmetrical
808 TRACE_IRQS_OFF
809 brasl %r14,preempt_schedule_irq
810 j .Lio_return
811#else
812 j .Lio_restore
813#endif
814
815#
816# Need to do work before returning to userspace, switch to kernel stack
817#
818.Lio_work_user:
819 lg %r1,__LC_KERNEL_STACK
820 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
821 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
822 la %r11,STACK_FRAME_OVERHEAD(%r1)
823 lgr %r15,%r1
824
825#
826# One of the work bits is on. Find out which one.
827#
828.Lio_work_tif:
829 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
830 jo .Lio_mcck_pending
831 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
832 jo .Lio_reschedule
833#ifdef CONFIG_LIVEPATCH
834 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
835 jo .Lio_patch_pending
836#endif
837 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
838 jo .Lio_sigpending
839 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
840 jo .Lio_notify_resume
841 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
842 jo .Lio_guarded_storage
843 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
844 jo .Lio_vxrs
845 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
846 jnz .Lio_asce
847 j .Lio_return # beware of critical section cleanup
848
849#
850# _CIF_MCCK_PENDING is set, call handler
851#
852.Lio_mcck_pending:
853 # TRACE_IRQS_ON already done at .Lio_return
854 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
855 TRACE_IRQS_OFF
856 j .Lio_return
857
858#
859# _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
860#
861.Lio_asce:
862 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
863 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
864 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
865 jz .Lio_return
866#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
867 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
868 jnz .Lio_set_fs_fixup
869 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
870 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
871 j .Lio_return
872.Lio_set_fs_fixup:
873#endif
874 larl %r14,.Lio_return
875 jg set_fs_fixup
876
877#
878# CIF_FPU is set, restore floating-point controls and floating-point registers.
879#
880.Lio_vxrs:
881 larl %r14,.Lio_return
882 jg load_fpu_regs
883
884#
885# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
886#
887.Lio_guarded_storage:
888 # TRACE_IRQS_ON already done at .Lio_return
889 ssm __LC_SVC_NEW_PSW # reenable interrupts
890 lgr %r2,%r11 # pass pointer to pt_regs
891 brasl %r14,gs_load_bc_cb
892 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
893 TRACE_IRQS_OFF
894 j .Lio_return
895
896#
897# _TIF_NEED_RESCHED is set, call schedule
898#
899.Lio_reschedule:
900 # TRACE_IRQS_ON already done at .Lio_return
901 ssm __LC_SVC_NEW_PSW # reenable interrupts
902 brasl %r14,schedule # call scheduler
903 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
904 TRACE_IRQS_OFF
905 j .Lio_return
906
907#
908# _TIF_PATCH_PENDING is set, call klp_update_patch_state
909#
910#ifdef CONFIG_LIVEPATCH
911.Lio_patch_pending:
912 lg %r2,__LC_CURRENT # pass pointer to task struct
913 larl %r14,.Lio_return
914 jg klp_update_patch_state
915#endif
916
917#
918# _TIF_SIGPENDING or is set, call do_signal
919#
920.Lio_sigpending:
921 # TRACE_IRQS_ON already done at .Lio_return
922 ssm __LC_SVC_NEW_PSW # reenable interrupts
923 lgr %r2,%r11 # pass pointer to pt_regs
924 brasl %r14,do_signal
925 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
926 TRACE_IRQS_OFF
927 j .Lio_return
928
929#
930# _TIF_NOTIFY_RESUME or is set, call do_notify_resume
931#
932.Lio_notify_resume:
933 # TRACE_IRQS_ON already done at .Lio_return
934 ssm __LC_SVC_NEW_PSW # reenable interrupts
935 lgr %r2,%r11 # pass pointer to pt_regs
936 brasl %r14,do_notify_resume
937 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
938 TRACE_IRQS_OFF
939 j .Lio_return
940ENDPROC(io_int_handler)
941
942/*
943 * External interrupt handler routine
944 */
945ENTRY(ext_int_handler)
946 STCK __LC_INT_CLOCK
947 stpt __LC_ASYNC_ENTER_TIMER
948 BPOFF
949 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
950 lg %r12,__LC_CURRENT
951 larl %r13,cleanup_critical
952 lmg %r8,%r9,__LC_EXT_OLD_PSW
953 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
954 stmg %r0,%r7,__PT_R0(%r11)
955 # clear user controlled registers to prevent speculative use
956 xgr %r0,%r0
957 xgr %r1,%r1
958 xgr %r2,%r2
959 xgr %r3,%r3
960 xgr %r4,%r4
961 xgr %r5,%r5
962 xgr %r6,%r6
963 xgr %r7,%r7
964 xgr %r10,%r10
965 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
966 stmg %r8,%r9,__PT_PSW(%r11)
967 lghi %r1,__LC_EXT_PARAMS2
968 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
969 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
970 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
971 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
972 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
973 jo .Lio_restore
974 TRACE_IRQS_OFF
975 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
976 lgr %r2,%r11 # pass pointer to pt_regs
977 lghi %r3,EXT_INTERRUPT
978 brasl %r14,do_IRQ
979 j .Lio_return
980ENDPROC(ext_int_handler)
981
982/*
983 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
984 */
985ENTRY(psw_idle)
986 stg %r3,__SF_EMPTY(%r15)
987 larl %r1,.Lpsw_idle_lpsw+4
988 stg %r1,__SF_EMPTY+8(%r15)
989 larl %r1,smp_cpu_mtid
990 llgf %r1,0(%r1)
991 ltgr %r1,%r1
992 jz .Lpsw_idle_stcctm
993 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
994.Lpsw_idle_stcctm:
995 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
996 BPON
997 STCK __CLOCK_IDLE_ENTER(%r2)
998 stpt __TIMER_IDLE_ENTER(%r2)
999.Lpsw_idle_lpsw:
1000 lpswe __SF_EMPTY(%r15)
1001 BR_EX %r14
1002.Lpsw_idle_end:
1003ENDPROC(psw_idle)
1004
1005/*
1006 * Store floating-point controls and floating-point or vector register
1007 * depending whether the vector facility is available. A critical section
1008 * cleanup assures that the registers are stored even if interrupted for
1009 * some other work. The CIF_FPU flag is set to trigger a lazy restore
1010 * of the register contents at return from io or a system call.
1011 */
1012ENTRY(save_fpu_regs)
1013 lg %r2,__LC_CURRENT
1014 aghi %r2,__TASK_thread
1015 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1016 jo .Lsave_fpu_regs_exit
1017 stfpc __THREAD_FPU_fpc(%r2)
1018 lg %r3,__THREAD_FPU_regs(%r2)
1019 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1020 jz .Lsave_fpu_regs_fp # no -> store FP regs
1021 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
1022 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
1023 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
1024.Lsave_fpu_regs_fp:
1025 std 0,0(%r3)
1026 std 1,8(%r3)
1027 std 2,16(%r3)
1028 std 3,24(%r3)
1029 std 4,32(%r3)
1030 std 5,40(%r3)
1031 std 6,48(%r3)
1032 std 7,56(%r3)
1033 std 8,64(%r3)
1034 std 9,72(%r3)
1035 std 10,80(%r3)
1036 std 11,88(%r3)
1037 std 12,96(%r3)
1038 std 13,104(%r3)
1039 std 14,112(%r3)
1040 std 15,120(%r3)
1041.Lsave_fpu_regs_done:
1042 oi __LC_CPU_FLAGS+7,_CIF_FPU
1043.Lsave_fpu_regs_exit:
1044 BR_EX %r14
1045.Lsave_fpu_regs_end:
1046ENDPROC(save_fpu_regs)
1047EXPORT_SYMBOL(save_fpu_regs)
1048
1049/*
1050 * Load floating-point controls and floating-point or vector registers.
1051 * A critical section cleanup assures that the register contents are
1052 * loaded even if interrupted for some other work.
1053 *
1054 * There are special calling conventions to fit into sysc and io return work:
1055 * %r15: <kernel stack>
1056 * The function requires:
1057 * %r4
1058 */
1059load_fpu_regs:
1060 lg %r4,__LC_CURRENT
1061 aghi %r4,__TASK_thread
1062 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1063 jno .Lload_fpu_regs_exit
1064 lfpc __THREAD_FPU_fpc(%r4)
1065 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1066 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
1067 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
1068 VLM %v0,%v15,0,%r4
1069 VLM %v16,%v31,256,%r4
1070 j .Lload_fpu_regs_done
1071.Lload_fpu_regs_fp:
1072 ld 0,0(%r4)
1073 ld 1,8(%r4)
1074 ld 2,16(%r4)
1075 ld 3,24(%r4)
1076 ld 4,32(%r4)
1077 ld 5,40(%r4)
1078 ld 6,48(%r4)
1079 ld 7,56(%r4)
1080 ld 8,64(%r4)
1081 ld 9,72(%r4)
1082 ld 10,80(%r4)
1083 ld 11,88(%r4)
1084 ld 12,96(%r4)
1085 ld 13,104(%r4)
1086 ld 14,112(%r4)
1087 ld 15,120(%r4)
1088.Lload_fpu_regs_done:
1089 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
1090.Lload_fpu_regs_exit:
1091 BR_EX %r14
1092.Lload_fpu_regs_end:
1093ENDPROC(load_fpu_regs)
1094
1095.L__critical_end:
1096
1097/*
1098 * Machine check handler routines
1099 */
1100ENTRY(mcck_int_handler)
1101 STCK __LC_MCCK_CLOCK
1102 BPOFF
1103 la %r1,4095 # validate r1
1104 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
1105 sckc __LC_CLOCK_COMPARATOR # validate comparator
1106 lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1107 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1108 lg %r12,__LC_CURRENT
1109 larl %r13,cleanup_critical
1110 lmg %r8,%r9,__LC_MCK_OLD_PSW
1111 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1112 jo .Lmcck_panic # yes -> rest of mcck code invalid
1113 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
1114 jno .Lmcck_panic # control registers invalid -> panic
1115 la %r14,4095
1116 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1117 ptlb
1118 lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1119 nill %r11,0xfc00 # MCESA_ORIGIN_MASK
1120 TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1121 jno 0f
1122 TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID
1123 jno 0f
1124 .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
11250: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1126 TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID
1127 jo 0f
1128 sr %r14,%r14
11290: sfpc %r14
1130 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1131 jo 0f
1132 lghi %r14,__LC_FPREGS_SAVE_AREA
1133 ld %f0,0(%r14)
1134 ld %f1,8(%r14)
1135 ld %f2,16(%r14)
1136 ld %f3,24(%r14)
1137 ld %f4,32(%r14)
1138 ld %f5,40(%r14)
1139 ld %f6,48(%r14)
1140 ld %f7,56(%r14)
1141 ld %f8,64(%r14)
1142 ld %f9,72(%r14)
1143 ld %f10,80(%r14)
1144 ld %f11,88(%r14)
1145 ld %f12,96(%r14)
1146 ld %f13,104(%r14)
1147 ld %f14,112(%r14)
1148 ld %f15,120(%r14)
1149 j 1f
11500: VLM %v0,%v15,0,%r11
1151 VLM %v16,%v31,256,%r11
11521: lghi %r14,__LC_CPU_TIMER_SAVE_AREA
1153 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1154 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1155 jo 3f
1156 la %r14,__LC_SYNC_ENTER_TIMER
1157 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
1158 jl 0f
1159 la %r14,__LC_ASYNC_ENTER_TIMER
11600: clc 0(8,%r14),__LC_EXIT_TIMER
1161 jl 1f
1162 la %r14,__LC_EXIT_TIMER
11631: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
1164 jl 2f
1165 la %r14,__LC_LAST_UPDATE_TIMER
11662: spt 0(%r14)
1167 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
11683: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1169 jno .Lmcck_panic
1170 tmhh %r8,0x0001 # interrupting from user ?
1171 jnz 4f
1172 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1173 jno .Lmcck_panic
11744: ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
1175 SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1176.Lmcck_skip:
1177 lghi %r14,__LC_GPREGS_SAVE_AREA+64
1178 stmg %r0,%r7,__PT_R0(%r11)
1179 # clear user controlled registers to prevent speculative use
1180 xgr %r0,%r0
1181 xgr %r1,%r1
1182 xgr %r2,%r2
1183 xgr %r3,%r3
1184 xgr %r4,%r4
1185 xgr %r5,%r5
1186 xgr %r6,%r6
1187 xgr %r7,%r7
1188 xgr %r10,%r10
1189 mvc __PT_R8(64,%r11),0(%r14)
1190 stmg %r8,%r9,__PT_PSW(%r11)
1191 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1192 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1193 lgr %r2,%r11 # pass pointer to pt_regs
1194 brasl %r14,s390_do_machine_check
1195 tm __PT_PSW+1(%r11),0x01 # returning to user ?
1196 jno .Lmcck_return
1197 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
1198 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1199 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1200 la %r11,STACK_FRAME_OVERHEAD(%r1)
1201 lgr %r15,%r1
1202 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
1203 jno .Lmcck_return
1204 TRACE_IRQS_OFF
1205 brasl %r14,s390_handle_mcck
1206 TRACE_IRQS_ON
1207.Lmcck_return:
1208 lg %r14,__LC_VDSO_PER_CPU
1209 lmg %r0,%r10,__PT_R0(%r11)
1210 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1211 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1212 jno 0f
1213 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
1214 stpt __LC_EXIT_TIMER
1215 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
12160: lmg %r11,%r15,__PT_R11(%r11)
1217 lpswe __LC_RETURN_MCCK_PSW
1218
1219.Lmcck_panic:
1220 lg %r15,__LC_NODAT_STACK
1221 la %r11,STACK_FRAME_OVERHEAD(%r15)
1222 j .Lmcck_skip
1223ENDPROC(mcck_int_handler)
1224
1225#
1226# PSW restart interrupt handler
1227#
1228ENTRY(restart_int_handler)
1229 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
1230 stg %r15,__LC_SAVE_AREA_RESTART
1231 lg %r15,__LC_RESTART_STACK
1232 xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
1233 stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
1234 mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1235 mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW
1236 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1237 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1238 lg %r2,__LC_RESTART_DATA
1239 lg %r3,__LC_RESTART_SOURCE
1240 ltgr %r3,%r3 # test source cpu address
1241 jm 1f # negative -> skip source stop
12420: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
1243 brc 10,0b # wait for status stored
12441: basr %r14,%r1 # call function
1245 stap __SF_EMPTY(%r15) # store cpu address
1246 llgh %r3,__SF_EMPTY(%r15)
12472: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
1248 brc 2,2b
12493: j 3b
1250ENDPROC(restart_int_handler)
1251
1252 .section .kprobes.text, "ax"
1253
1254#if defined(CONFIG_CHECK_STACK) || defined(CONFIG_VMAP_STACK)
1255/*
1256 * The synchronous or the asynchronous stack overflowed. We are dead.
1257 * No need to properly save the registers, we are going to panic anyway.
1258 * Setup a pt_regs so that show_trace can provide a good call trace.
1259 */
1260ENTRY(stack_overflow)
1261 lg %r15,__LC_NODAT_STACK # change to panic stack
1262 la %r11,STACK_FRAME_OVERHEAD(%r15)
1263 stmg %r0,%r7,__PT_R0(%r11)
1264 stmg %r8,%r9,__PT_PSW(%r11)
1265 mvc __PT_R8(64,%r11),0(%r14)
1266 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1267 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1268 lgr %r2,%r11 # pass pointer to pt_regs
1269 jg kernel_stack_overflow
1270ENDPROC(stack_overflow)
1271#endif
1272
1273ENTRY(cleanup_critical)
1274#if IS_ENABLED(CONFIG_KVM)
1275 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1276 jl 0f
1277 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1278 jl .Lcleanup_sie
1279#endif
1280 clg %r9,BASED(.Lcleanup_table) # system_call
1281 jl 0f
1282 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1283 jl .Lcleanup_system_call
1284 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1285 jl 0f
1286 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1287 jl .Lcleanup_sysc_tif
1288 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1289 jl .Lcleanup_sysc_restore
1290 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1291 jl 0f
1292 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1293 jl .Lcleanup_io_tif
1294 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1295 jl .Lcleanup_io_restore
1296 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1297 jl 0f
1298 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1299 jl .Lcleanup_idle
1300 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1301 jl 0f
1302 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1303 jl .Lcleanup_save_fpu_regs
1304 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1305 jl 0f
1306 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1307 jl .Lcleanup_load_fpu_regs
13080: BR_EX %r14,%r11
1309ENDPROC(cleanup_critical)
1310
1311 .align 8
1312.Lcleanup_table:
1313 .quad system_call
1314 .quad .Lsysc_do_svc
1315 .quad .Lsysc_tif
1316 .quad .Lsysc_restore
1317 .quad .Lsysc_done
1318 .quad .Lio_tif
1319 .quad .Lio_restore
1320 .quad .Lio_done
1321 .quad psw_idle
1322 .quad .Lpsw_idle_end
1323 .quad save_fpu_regs
1324 .quad .Lsave_fpu_regs_end
1325 .quad load_fpu_regs
1326 .quad .Lload_fpu_regs_end
1327
1328#if IS_ENABLED(CONFIG_KVM)
1329.Lcleanup_table_sie:
1330 .quad .Lsie_gmap
1331 .quad .Lsie_done
1332
1333.Lcleanup_sie:
1334 cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt?
1335 je 1f
1336 slg %r9,BASED(.Lsie_crit_mcck_start)
1337 clg %r9,BASED(.Lsie_crit_mcck_length)
1338 jh 1f
1339 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
13401: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1341 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
1342 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1343 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1344 larl %r9,sie_exit # skip forward to sie_exit
1345 BR_EX %r14,%r11
1346#endif
1347
1348.Lcleanup_system_call:
1349 # check if stpt has been executed
1350 clg %r9,BASED(.Lcleanup_system_call_insn)
1351 jh 0f
1352 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1353 cghi %r11,__LC_SAVE_AREA_ASYNC
1354 je 0f
1355 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
13560: # check if stmg has been executed
1357 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1358 jh 0f
1359 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
13600: # check if base register setup + TIF bit load has been done
1361 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1362 jhe 0f
1363 # set up saved register r12 task struct pointer
1364 stg %r12,32(%r11)
1365 # set up saved register r13 __TASK_thread offset
1366 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
13670: # check if the user time update has been done
1368 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1369 jh 0f
1370 lg %r15,__LC_EXIT_TIMER
1371 slg %r15,__LC_SYNC_ENTER_TIMER
1372 alg %r15,__LC_USER_TIMER
1373 stg %r15,__LC_USER_TIMER
13740: # check if the system time update has been done
1375 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1376 jh 0f
1377 lg %r15,__LC_LAST_UPDATE_TIMER
1378 slg %r15,__LC_EXIT_TIMER
1379 alg %r15,__LC_SYSTEM_TIMER
1380 stg %r15,__LC_SYSTEM_TIMER
13810: # update accounting time stamp
1382 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1383 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1384 # set up saved register r11
1385 lg %r15,__LC_KERNEL_STACK
1386 la %r9,STACK_FRAME_OVERHEAD(%r15)
1387 stg %r9,24(%r11) # r11 pt_regs pointer
1388 # fill pt_regs
1389 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1390 stmg %r0,%r7,__PT_R0(%r9)
1391 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1392 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1393 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1394 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1395 # setup saved register r15
1396 stg %r15,56(%r11) # r15 stack pointer
1397 # set new psw address and exit
1398 larl %r9,.Lsysc_do_svc
1399 BR_EX %r14,%r11
1400.Lcleanup_system_call_insn:
1401 .quad system_call
1402 .quad .Lsysc_stmg
1403 .quad .Lsysc_per
1404 .quad .Lsysc_vtime+36
1405 .quad .Lsysc_vtime+42
1406.Lcleanup_system_call_const:
1407 .quad __TASK_thread
1408
1409.Lcleanup_sysc_tif:
1410 larl %r9,.Lsysc_tif
1411 BR_EX %r14,%r11
1412
1413.Lcleanup_sysc_restore:
1414 # check if stpt has been executed
1415 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1416 jh 0f
1417 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1418 cghi %r11,__LC_SAVE_AREA_ASYNC
1419 je 0f
1420 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
14210: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
1422 je 1f
1423 lg %r9,24(%r11) # get saved pointer to pt_regs
1424 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1425 mvc 0(64,%r11),__PT_R8(%r9)
1426 lmg %r0,%r7,__PT_R0(%r9)
14271: lmg %r8,%r9,__LC_RETURN_PSW
1428 BR_EX %r14,%r11
1429.Lcleanup_sysc_restore_insn:
1430 .quad .Lsysc_exit_timer
1431 .quad .Lsysc_done - 4
1432
1433.Lcleanup_io_tif:
1434 larl %r9,.Lio_tif
1435 BR_EX %r14,%r11
1436
1437.Lcleanup_io_restore:
1438 # check if stpt has been executed
1439 clg %r9,BASED(.Lcleanup_io_restore_insn)
1440 jh 0f
1441 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
14420: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
1443 je 1f
1444 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1445 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1446 mvc 0(64,%r11),__PT_R8(%r9)
1447 lmg %r0,%r7,__PT_R0(%r9)
14481: lmg %r8,%r9,__LC_RETURN_PSW
1449 BR_EX %r14,%r11
1450.Lcleanup_io_restore_insn:
1451 .quad .Lio_exit_timer
1452 .quad .Lio_done - 4
1453
1454.Lcleanup_idle:
1455 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1456 # copy interrupt clock & cpu timer
1457 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1458 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1459 cghi %r11,__LC_SAVE_AREA_ASYNC
1460 je 0f
1461 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1462 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
14630: # check if stck & stpt have been executed
1464 clg %r9,BASED(.Lcleanup_idle_insn)
1465 jhe 1f
1466 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1467 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
14681: # calculate idle cycles
1469 clg %r9,BASED(.Lcleanup_idle_insn)
1470 jl 3f
1471 larl %r1,smp_cpu_mtid
1472 llgf %r1,0(%r1)
1473 ltgr %r1,%r1
1474 jz 3f
1475 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1476 larl %r3,mt_cycles
1477 ag %r3,__LC_PERCPU_OFFSET
1478 la %r4,__SF_EMPTY+16(%r15)
14792: lg %r0,0(%r3)
1480 slg %r0,0(%r4)
1481 alg %r0,64(%r4)
1482 stg %r0,0(%r3)
1483 la %r3,8(%r3)
1484 la %r4,8(%r4)
1485 brct %r1,2b
14863: # account system time going idle
1487 lg %r9,__LC_STEAL_TIMER
1488 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1489 slg %r9,__LC_LAST_UPDATE_CLOCK
1490 stg %r9,__LC_STEAL_TIMER
1491 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1492 lg %r9,__LC_SYSTEM_TIMER
1493 alg %r9,__LC_LAST_UPDATE_TIMER
1494 slg %r9,__TIMER_IDLE_ENTER(%r2)
1495 stg %r9,__LC_SYSTEM_TIMER
1496 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1497 # prepare return psw
1498 nihh %r8,0xfcfd # clear irq & wait state bits
1499 lg %r9,48(%r11) # return from psw_idle
1500 BR_EX %r14,%r11
1501.Lcleanup_idle_insn:
1502 .quad .Lpsw_idle_lpsw
1503
1504.Lcleanup_save_fpu_regs:
1505 larl %r9,save_fpu_regs
1506 BR_EX %r14,%r11
1507
1508.Lcleanup_load_fpu_regs:
1509 larl %r9,load_fpu_regs
1510 BR_EX %r14,%r11
1511
1512/*
1513 * Integer constants
1514 */
1515 .align 8
1516.Lcritical_start:
1517 .quad .L__critical_start
1518.Lcritical_length:
1519 .quad .L__critical_end - .L__critical_start
1520#if IS_ENABLED(CONFIG_KVM)
1521.Lsie_critical_start:
1522 .quad .Lsie_gmap
1523.Lsie_critical_length:
1524 .quad .Lsie_done - .Lsie_gmap
1525.Lsie_crit_mcck_start:
1526 .quad .Lsie_entry
1527.Lsie_crit_mcck_length:
1528 .quad .Lsie_skip - .Lsie_entry
1529#endif
1530 .section .rodata, "a"
1531#define SYSCALL(esame,emu) .quad __s390x_ ## esame
1532 .globl sys_call_table
1533sys_call_table:
1534#include "asm/syscall_table.h"
1535#undef SYSCALL
1536
1537#ifdef CONFIG_COMPAT
1538
1539#define SYSCALL(esame,emu) .quad __s390_ ## emu
1540 .globl sys_call_table_emu
1541sys_call_table_emu:
1542#include "asm/syscall_table.h"
1543#undef SYSCALL
1544#endif