1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * OMAP Secure API infrastructure.
  4 *
  5 * Copyright (C) 2011 Texas Instruments, Inc.
  6 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
  7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
  8 * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
  9 */
 10
 11#include <linux/arm-smccc.h>
 12#include <linux/cpu_pm.h>
 13#include <linux/kernel.h>
 14#include <linux/init.h>
 15#include <linux/io.h>
 16#include <linux/memblock.h>
 17#include <linux/of.h>
 18
 19#include <asm/cacheflush.h>
 20#include <asm/memblock.h>
 21
 22#include "common.h"
 23#include "omap-secure.h"
 24#include "soc.h"
 25
 26static phys_addr_t omap_secure_memblock_base;
 27
 28bool optee_available;
 29
 30#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
 31	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
 32	ARM_SMCCC_OWNER_SIP, (func_num))
 33
 34static void __init omap_optee_init_check(void)
 35{
 36	struct device_node *np;
 37
 38	/*
 39	 * We only check that the OP-TEE node is present and available. The
 40	 * OP-TEE kernel driver is not needed for the type of interaction made
 41	 * with OP-TEE here so the driver's status is not checked.
 42	 */
 43	np = of_find_node_by_path("/firmware/optee");
 44	if (np && of_device_is_available(np))
 45		optee_available = true;
 46	of_node_put(np);
 47}
 48
 49/**
 50 * omap_sec_dispatcher: Routine to dispatch low power secure
 51 * service routines
 52 * @idx: The HAL API index
 53 * @flag: The flag indicating criticality of operation
 54 * @nargs: Number of valid arguments out of four.
 55 * @arg1, arg2, arg3 args4: Parameters passed to secure API
 56 *
 57 * Return the non-zero error value on failure.
 58 */
 59u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
 60							 u32 arg3, u32 arg4)
 61{
 62	static u32 buf[NR_CPUS][5];
 63	u32 *param;
 64	int cpu;
 65	u32 ret;
 66
 67	cpu = get_cpu();
 68	param = buf[cpu];
 69
 70	param[0] = nargs;
 71	param[1] = arg1;
 72	param[2] = arg2;
 73	param[3] = arg3;
 74	param[4] = arg4;
 75
 76	/*
 77	 * Secure API needs physical address
 78	 * pointer for the parameters
 79	 */
 80	flush_cache_all();
 81	outer_clean_range(__pa(param), __pa(param + 5));
 82	ret = omap_smc2(idx, flag, __pa(param));
 83
 84	put_cpu();
 85
 86	return ret;
 87}
 88
 89void omap_smccc_smc(u32 fn, u32 arg)
 90{
 91	struct arm_smccc_res res;
 92
 93	arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
 94		      0, 0, 0, 0, 0, 0, &res);
 95	WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
 96}
 97
 98void omap_smc1(u32 fn, u32 arg)
 99{
100	/*
101	 * If this platform has OP-TEE installed we use ARM SMC calls
102	 * otherwise fall back to the OMAP ROM style calls.
103	 */
104	if (optee_available)
105		omap_smccc_smc(fn, arg);
106	else
107		_omap_smc1(fn, arg);
108}
109
110/* Allocate the memory to save secure ram */
111int __init omap_secure_ram_reserve_memblock(void)
112{
113	u32 size = OMAP_SECURE_RAM_STORAGE;
114
115	size = ALIGN(size, SECTION_SIZE);
116	omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
117
118	return 0;
119}
120
121phys_addr_t omap_secure_ram_mempool_base(void)
122{
123	return omap_secure_memblock_base;
124}
125
126#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
127u32 omap3_save_secure_ram(void *addr, int size)
128{
129	static u32 param[5];
130	u32 ret;
 
131
132	if (size != OMAP3_SAVE_SECURE_RAM_SZ)
133		return OMAP3_SAVE_SECURE_RAM_SZ;
134
135	param[0] = 4;		/* Number of arguments */
136	param[1] = __pa(addr);	/* Physical address for saving */
137	param[2] = 0;
138	param[3] = 1;
139	param[4] = 1;
140
141	ret = save_secure_ram_context(__pa(param));
142
143	return ret;
144}
145#endif
146
147/**
148 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
149 * @idx: The PPA API index
150 * @process: Process ID
151 * @flag: The flag indicating criticality of operation
152 * @nargs: Number of valid arguments out of four.
153 * @arg1, arg2, arg3 args4: Parameters passed to secure API
154 *
155 * Return the non-zero error value on failure.
156 *
157 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
158 *       it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
159 */
160u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
161			   u32 arg1, u32 arg2, u32 arg3, u32 arg4)
162{
163	static u32 param[5];
164	u32 ret;
 
165
166	param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
167	param[1] = arg1;
168	param[2] = arg2;
169	param[3] = arg3;
170	param[4] = arg4;
171
172	/*
173	 * Secure API needs physical address
174	 * pointer for the parameters
175	 */
176	local_irq_disable();
177	local_fiq_disable();
178	flush_cache_all();
179	outer_clean_range(__pa(param), __pa(param + 5));
180	ret = omap_smc3(idx, process, flag, __pa(param));
181	flush_cache_all();
182	local_fiq_enable();
183	local_irq_enable();
184
185	return ret;
186}
187
188/**
189 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
190 *  @set_bits: bits to set in ACR
191 *  @clr_bits: bits to clear in ACR
192 *
193 * Return the non-zero error value on failure.
194*/
195u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
196{
197	u32 acr;
198
199	/* Read ACR */
200	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
201	acr &= ~clear_bits;
202	acr |= set_bits;
203
204	return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
205				      0,
206				      FLAG_START_CRITICAL,
207				      1, acr, 0, 0, 0);
208}
209
210/**
211 * rx51_secure_rng_call: Routine for HW random generator
212 */
213u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
214{
215	return rx51_secure_dispatcher(RX51_PPA_HWRNG,
216				      0,
217				      NO_FLAG,
218				      3, ptr, count, flag, 0);
219}
220
221void __init omap_secure_init(void)
222{
223	omap_optee_init_check();
224}
225
226/*
227 * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
228 * address after MMU has been re-enabled after CPU1 has been woken up again.
229 * Otherwise the ROM code will attempt to use the earlier physical return
230 * address that got set with MMU off when waking up CPU1. Only used on secure
231 * devices.
232 */
233static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
234{
235	switch (cmd) {
236	case CPU_CLUSTER_PM_EXIT:
237		omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
238				       FLAG_START_CRITICAL,
239				       0, 0, 0, 0, 0);
240		break;
241	default:
242		break;
243	}
244
245	return NOTIFY_OK;
246}
247
248static struct notifier_block secure_notifier_block = {
249	.notifier_call = cpu_notifier,
250};
251
252static int __init secure_pm_init(void)
253{
254	if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
255		return 0;
256
257	cpu_pm_register_notifier(&secure_notifier_block);
258
259	return 0;
260}
261omap_arch_initcall(secure_pm_init);

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * OMAP Secure API infrastructure.
  4 *
  5 * Copyright (C) 2011 Texas Instruments, Inc.
  6 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
  7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
  8 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
  9 */
 10
 
 
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13#include <linux/io.h>
 14#include <linux/memblock.h>
 
 15
 16#include <asm/cacheflush.h>
 17#include <asm/memblock.h>
 18
 
 19#include "omap-secure.h"
 
 20
 21static phys_addr_t omap_secure_memblock_base;
 22
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 23/**
 24 * omap_sec_dispatcher: Routine to dispatch low power secure
 25 * service routines
 26 * @idx: The HAL API index
 27 * @flag: The flag indicating criticality of operation
 28 * @nargs: Number of valid arguments out of four.
 29 * @arg1, arg2, arg3 args4: Parameters passed to secure API
 30 *
 31 * Return the non-zero error value on failure.
 32 */
 33u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
 34							 u32 arg3, u32 arg4)
 35{
 
 
 
 36	u32 ret;
 37	u32 param[5];
 
 
 38
 39	param[0] = nargs;
 40	param[1] = arg1;
 41	param[2] = arg2;
 42	param[3] = arg3;
 43	param[4] = arg4;
 44
 45	/*
 46	 * Secure API needs physical address
 47	 * pointer for the parameters
 48	 */
 49	flush_cache_all();
 50	outer_clean_range(__pa(param), __pa(param + 5));
 51	ret = omap_smc2(idx, flag, __pa(param));
 52
 
 
 53	return ret;
 54}
 55
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 56/* Allocate the memory to save secure ram */
 57int __init omap_secure_ram_reserve_memblock(void)
 58{
 59	u32 size = OMAP_SECURE_RAM_STORAGE;
 60
 61	size = ALIGN(size, SECTION_SIZE);
 62	omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
 63
 64	return 0;
 65}
 66
 67phys_addr_t omap_secure_ram_mempool_base(void)
 68{
 69	return omap_secure_memblock_base;
 70}
 71
 72#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 73u32 omap3_save_secure_ram(void __iomem *addr, int size)
 74{
 
 75	u32 ret;
 76	u32 param[5];
 77
 78	if (size != OMAP3_SAVE_SECURE_RAM_SZ)
 79		return OMAP3_SAVE_SECURE_RAM_SZ;
 80
 81	param[0] = 4;		/* Number of arguments */
 82	param[1] = __pa(addr);	/* Physical address for saving */
 83	param[2] = 0;
 84	param[3] = 1;
 85	param[4] = 1;
 86
 87	ret = save_secure_ram_context(__pa(param));
 88
 89	return ret;
 90}
 91#endif
 92
 93/**
 94 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
 95 * @idx: The PPA API index
 96 * @process: Process ID
 97 * @flag: The flag indicating criticality of operation
 98 * @nargs: Number of valid arguments out of four.
 99 * @arg1, arg2, arg3 args4: Parameters passed to secure API
100 *
101 * Return the non-zero error value on failure.
102 *
103 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
104 *       it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
105 */
106u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
107			   u32 arg1, u32 arg2, u32 arg3, u32 arg4)
108{
 
109	u32 ret;
110	u32 param[5];
111
112	param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
113	param[1] = arg1;
114	param[2] = arg2;
115	param[3] = arg3;
116	param[4] = arg4;
117
118	/*
119	 * Secure API needs physical address
120	 * pointer for the parameters
121	 */
122	local_irq_disable();
123	local_fiq_disable();
124	flush_cache_all();
125	outer_clean_range(__pa(param), __pa(param + 5));
126	ret = omap_smc3(idx, process, flag, __pa(param));
127	flush_cache_all();
128	local_fiq_enable();
129	local_irq_enable();
130
131	return ret;
132}
133
134/**
135 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
136 *  @set_bits: bits to set in ACR
137 *  @clr_bits: bits to clear in ACR
138 *
139 * Return the non-zero error value on failure.
140*/
141u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
142{
143	u32 acr;
144
145	/* Read ACR */
146	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
147	acr &= ~clear_bits;
148	acr |= set_bits;
149
150	return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
151				      0,
152				      FLAG_START_CRITICAL,
153				      1, acr, 0, 0, 0);
154}
155
156/**
157 * rx51_secure_rng_call: Routine for HW random generator
158 */
159u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
160{
161	return rx51_secure_dispatcher(RX51_PPA_HWRNG,
162				      0,
163				      NO_FLAG,
164				      3, ptr, count, flag, 0);
165}