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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier LD4 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "socionext,uniphier-ld4";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 reg = <0>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 };
27 };
28
29 psci {
30 compatible = "arm,psci-0.2";
31 method = "smc";
32 };
33
34 clocks {
35 refclk: ref {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <24576000>;
39 };
40
41 arm_timer_clk: arm-timer {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <50000000>;
45 };
46 };
47
48 soc {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53 interrupt-parent = <&intc>;
54
55 l2: cache-controller@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
59 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
61 cache-unified;
62 cache-size = <(512 * 1024)>;
63 cache-sets = <256>;
64 cache-line-size = <128>;
65 cache-level = <2>;
66 };
67
68 spi: spi@54006000 {
69 compatible = "socionext,uniphier-scssi";
70 status = "disabled";
71 reg = <0x54006000 0x100>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_spi0>;
77 clocks = <&peri_clk 11>;
78 resets = <&peri_rst 11>;
79 };
80
81 serial0: serial@54006800 {
82 compatible = "socionext,uniphier-uart";
83 status = "disabled";
84 reg = <0x54006800 0x40>;
85 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_uart0>;
88 clocks = <&peri_clk 0>;
89 resets = <&peri_rst 0>;
90 };
91
92 serial1: serial@54006900 {
93 compatible = "socionext,uniphier-uart";
94 status = "disabled";
95 reg = <0x54006900 0x40>;
96 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart1>;
99 clocks = <&peri_clk 1>;
100 resets = <&peri_rst 1>;
101 };
102
103 serial2: serial@54006a00 {
104 compatible = "socionext,uniphier-uart";
105 status = "disabled";
106 reg = <0x54006a00 0x40>;
107 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart2>;
110 clocks = <&peri_clk 2>;
111 resets = <&peri_rst 2>;
112 };
113
114 serial3: serial@54006b00 {
115 compatible = "socionext,uniphier-uart";
116 status = "disabled";
117 reg = <0x54006b00 0x40>;
118 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart3>;
121 clocks = <&peri_clk 3>;
122 resets = <&peri_rst 3>;
123 };
124
125 gpio: gpio@55000000 {
126 compatible = "socionext,uniphier-gpio";
127 reg = <0x55000000 0x200>;
128 interrupt-parent = <&aidet>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinctrl 0 0 0>;
134 gpio-ranges-group-names = "gpio_range";
135 ngpios = <136>;
136 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
137 };
138
139 i2c0: i2c@58400000 {
140 compatible = "socionext,uniphier-i2c";
141 status = "disabled";
142 reg = <0x58400000 0x40>;
143 #address-cells = <1>;
144 #size-cells = <0>;
145 interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_i2c0>;
148 clocks = <&peri_clk 4>;
149 resets = <&peri_rst 4>;
150 clock-frequency = <100000>;
151 };
152
153 i2c1: i2c@58480000 {
154 compatible = "socionext,uniphier-i2c";
155 status = "disabled";
156 reg = <0x58480000 0x40>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1>;
162 clocks = <&peri_clk 5>;
163 resets = <&peri_rst 5>;
164 clock-frequency = <100000>;
165 };
166
167 /* chip-internal connection for DMD */
168 i2c2: i2c@58500000 {
169 compatible = "socionext,uniphier-i2c";
170 reg = <0x58500000 0x40>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c2>;
176 clocks = <&peri_clk 6>;
177 resets = <&peri_rst 6>;
178 clock-frequency = <400000>;
179 };
180
181 i2c3: i2c@58580000 {
182 compatible = "socionext,uniphier-i2c";
183 status = "disabled";
184 reg = <0x58580000 0x40>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c3>;
190 clocks = <&peri_clk 7>;
191 resets = <&peri_rst 7>;
192 clock-frequency = <100000>;
193 };
194
195 system_bus: system-bus@58c00000 {
196 compatible = "socionext,uniphier-system-bus";
197 status = "disabled";
198 reg = <0x58c00000 0x400>;
199 #address-cells = <2>;
200 #size-cells = <1>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_system_bus>;
203 };
204
205 smpctrl@59801000 {
206 compatible = "socionext,uniphier-smpctrl";
207 reg = <0x59801000 0x400>;
208 };
209
210 mioctrl@59810000 {
211 compatible = "socionext,uniphier-ld4-mioctrl",
212 "simple-mfd", "syscon";
213 reg = <0x59810000 0x800>;
214
215 mio_clk: clock {
216 compatible = "socionext,uniphier-ld4-mio-clock";
217 #clock-cells = <1>;
218 };
219
220 mio_rst: reset {
221 compatible = "socionext,uniphier-ld4-mio-reset";
222 #reset-cells = <1>;
223 };
224 };
225
226 perictrl@59820000 {
227 compatible = "socionext,uniphier-ld4-perictrl",
228 "simple-mfd", "syscon";
229 reg = <0x59820000 0x200>;
230
231 peri_clk: clock {
232 compatible = "socionext,uniphier-ld4-peri-clock";
233 #clock-cells = <1>;
234 };
235
236 peri_rst: reset {
237 compatible = "socionext,uniphier-ld4-peri-reset";
238 #reset-cells = <1>;
239 };
240 };
241
242 dmac: dma-controller@5a000000 {
243 compatible = "socionext,uniphier-mio-dmac";
244 reg = <0x5a000000 0x1000>;
245 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&mio_clk 7>;
253 resets = <&mio_rst 7>;
254 #dma-cells = <1>;
255 };
256
257 sd: mmc@5a400000 {
258 compatible = "socionext,uniphier-sd-v2.91";
259 status = "disabled";
260 reg = <0x5a400000 0x200>;
261 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default", "uhs";
263 pinctrl-0 = <&pinctrl_sd>;
264 pinctrl-1 = <&pinctrl_sd_uhs>;
265 clocks = <&mio_clk 0>;
266 reset-names = "host", "bridge";
267 resets = <&mio_rst 0>, <&mio_rst 3>;
268 dma-names = "rx-tx";
269 dmas = <&dmac 4>;
270 bus-width = <4>;
271 cap-sd-highspeed;
272 sd-uhs-sdr12;
273 sd-uhs-sdr25;
274 sd-uhs-sdr50;
275 };
276
277 emmc: mmc@5a500000 {
278 compatible = "socionext,uniphier-sd-v2.91";
279 status = "disabled";
280 reg = <0x5a500000 0x200>;
281 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_emmc>;
284 clocks = <&mio_clk 1>;
285 reset-names = "host", "bridge", "hw";
286 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
287 dma-names = "rx-tx";
288 dmas = <&dmac 6>;
289 bus-width = <8>;
290 cap-mmc-highspeed;
291 cap-mmc-hw-reset;
292 non-removable;
293 };
294
295 usb0: usb@5a800100 {
296 compatible = "socionext,uniphier-ehci", "generic-ehci";
297 status = "disabled";
298 reg = <0x5a800100 0x100>;
299 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_usb0>;
302 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
303 <&mio_clk 12>;
304 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
305 <&mio_rst 12>;
306 has-transaction-translator;
307 };
308
309 usb1: usb@5a810100 {
310 compatible = "socionext,uniphier-ehci", "generic-ehci";
311 status = "disabled";
312 reg = <0x5a810100 0x100>;
313 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb1>;
316 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
317 <&mio_clk 13>;
318 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
319 <&mio_rst 13>;
320 has-transaction-translator;
321 };
322
323 usb2: usb@5a820100 {
324 compatible = "socionext,uniphier-ehci", "generic-ehci";
325 status = "disabled";
326 reg = <0x5a820100 0x100>;
327 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usb2>;
330 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
331 <&mio_clk 14>;
332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
333 <&mio_rst 14>;
334 has-transaction-translator;
335 };
336
337 soc-glue@5f800000 {
338 compatible = "socionext,uniphier-ld4-soc-glue",
339 "simple-mfd", "syscon";
340 reg = <0x5f800000 0x2000>;
341
342 pinctrl: pinctrl {
343 compatible = "socionext,uniphier-ld4-pinctrl";
344 };
345 };
346
347 soc-glue@5f900000 {
348 compatible = "socionext,uniphier-ld4-soc-glue-debug",
349 "simple-mfd";
350 #address-cells = <1>;
351 #size-cells = <1>;
352 ranges = <0 0x5f900000 0x2000>;
353
354 efuse@100 {
355 compatible = "socionext,uniphier-efuse";
356 reg = <0x100 0x28>;
357 };
358
359 efuse@130 {
360 compatible = "socionext,uniphier-efuse";
361 reg = <0x130 0x8>;
362 };
363 };
364
365 timer@60000200 {
366 compatible = "arm,cortex-a9-global-timer";
367 reg = <0x60000200 0x20>;
368 interrupts = <GIC_PPI 11
369 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
370 clocks = <&arm_timer_clk>;
371 };
372
373 timer@60000600 {
374 compatible = "arm,cortex-a9-twd-timer";
375 reg = <0x60000600 0x20>;
376 interrupts = <GIC_PPI 13
377 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
378 clocks = <&arm_timer_clk>;
379 };
380
381 intc: interrupt-controller@60001000 {
382 compatible = "arm,cortex-a9-gic";
383 reg = <0x60001000 0x1000>,
384 <0x60000100 0x100>;
385 #interrupt-cells = <3>;
386 interrupt-controller;
387 };
388
389 aidet: interrupt-controller@61830000 {
390 compatible = "socionext,uniphier-ld4-aidet";
391 reg = <0x61830000 0x200>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 sysctrl@61840000 {
397 compatible = "socionext,uniphier-ld4-sysctrl",
398 "simple-mfd", "syscon";
399 reg = <0x61840000 0x10000>;
400
401 sys_clk: clock {
402 compatible = "socionext,uniphier-ld4-clock";
403 #clock-cells = <1>;
404 };
405
406 sys_rst: reset {
407 compatible = "socionext,uniphier-ld4-reset";
408 #reset-cells = <1>;
409 };
410 };
411
412 nand: nand-controller@68000000 {
413 compatible = "socionext,uniphier-denali-nand-v5a";
414 status = "disabled";
415 reg-names = "nand_data", "denali_reg";
416 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_nand>;
422 clock-names = "nand", "nand_x", "ecc";
423 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
424 reset-names = "nand", "reg";
425 resets = <&sys_rst 2>, <&sys_rst 2>;
426 };
427 };
428};
429
430#include "uniphier-pinctrl.dtsi"
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier LD4 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9
10/ {
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
26 };
27
28 psci {
29 compatible = "arm,psci-0.2";
30 method = "smc";
31 };
32
33 clocks {
34 refclk: ref {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24576000>;
38 };
39
40 arm_timer_clk: arm-timer {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
44 };
45 };
46
47 soc {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52 interrupt-parent = <&intc>;
53
54 l2: l2-cache@500c0000 {
55 compatible = "socionext,uniphier-system-cache";
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
59 cache-unified;
60 cache-size = <(512 * 1024)>;
61 cache-sets = <256>;
62 cache-line-size = <128>;
63 cache-level = <2>;
64 };
65
66 spi: spi@54006000 {
67 compatible = "socionext,uniphier-scssi";
68 status = "disabled";
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_spi0>;
73 clocks = <&peri_clk 11>;
74 resets = <&peri_rst 11>;
75 };
76
77 serial0: serial@54006800 {
78 compatible = "socionext,uniphier-uart";
79 status = "disabled";
80 reg = <0x54006800 0x40>;
81 interrupts = <0 33 4>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_uart0>;
84 clocks = <&peri_clk 0>;
85 resets = <&peri_rst 0>;
86 };
87
88 serial1: serial@54006900 {
89 compatible = "socionext,uniphier-uart";
90 status = "disabled";
91 reg = <0x54006900 0x40>;
92 interrupts = <0 35 4>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_uart1>;
95 clocks = <&peri_clk 1>;
96 resets = <&peri_rst 1>;
97 };
98
99 serial2: serial@54006a00 {
100 compatible = "socionext,uniphier-uart";
101 status = "disabled";
102 reg = <0x54006a00 0x40>;
103 interrupts = <0 37 4>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_uart2>;
106 clocks = <&peri_clk 2>;
107 resets = <&peri_rst 2>;
108 };
109
110 serial3: serial@54006b00 {
111 compatible = "socionext,uniphier-uart";
112 status = "disabled";
113 reg = <0x54006b00 0x40>;
114 interrupts = <0 29 4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart3>;
117 clocks = <&peri_clk 3>;
118 resets = <&peri_rst 3>;
119 };
120
121 gpio: gpio@55000000 {
122 compatible = "socionext,uniphier-gpio";
123 reg = <0x55000000 0x200>;
124 interrupt-parent = <&aidet>;
125 interrupt-controller;
126 #interrupt-cells = <2>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 gpio-ranges = <&pinctrl 0 0 0>;
130 gpio-ranges-group-names = "gpio_range";
131 ngpios = <136>;
132 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
133 };
134
135 i2c0: i2c@58400000 {
136 compatible = "socionext,uniphier-i2c";
137 status = "disabled";
138 reg = <0x58400000 0x40>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 interrupts = <0 41 1>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_i2c0>;
144 clocks = <&peri_clk 4>;
145 resets = <&peri_rst 4>;
146 clock-frequency = <100000>;
147 };
148
149 i2c1: i2c@58480000 {
150 compatible = "socionext,uniphier-i2c";
151 status = "disabled";
152 reg = <0x58480000 0x40>;
153 #address-cells = <1>;
154 #size-cells = <0>;
155 interrupts = <0 42 1>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c1>;
158 clocks = <&peri_clk 5>;
159 resets = <&peri_rst 5>;
160 clock-frequency = <100000>;
161 };
162
163 /* chip-internal connection for DMD */
164 i2c2: i2c@58500000 {
165 compatible = "socionext,uniphier-i2c";
166 reg = <0x58500000 0x40>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 interrupts = <0 43 1>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_i2c2>;
172 clocks = <&peri_clk 6>;
173 resets = <&peri_rst 6>;
174 clock-frequency = <400000>;
175 };
176
177 i2c3: i2c@58580000 {
178 compatible = "socionext,uniphier-i2c";
179 status = "disabled";
180 reg = <0x58580000 0x40>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 interrupts = <0 44 1>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_i2c3>;
186 clocks = <&peri_clk 7>;
187 resets = <&peri_rst 7>;
188 clock-frequency = <100000>;
189 };
190
191 system_bus: system-bus@58c00000 {
192 compatible = "socionext,uniphier-system-bus";
193 status = "disabled";
194 reg = <0x58c00000 0x400>;
195 #address-cells = <2>;
196 #size-cells = <1>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_system_bus>;
199 };
200
201 smpctrl@59801000 {
202 compatible = "socionext,uniphier-smpctrl";
203 reg = <0x59801000 0x400>;
204 };
205
206 mioctrl@59810000 {
207 compatible = "socionext,uniphier-ld4-mioctrl",
208 "simple-mfd", "syscon";
209 reg = <0x59810000 0x800>;
210
211 mio_clk: clock {
212 compatible = "socionext,uniphier-ld4-mio-clock";
213 #clock-cells = <1>;
214 };
215
216 mio_rst: reset {
217 compatible = "socionext,uniphier-ld4-mio-reset";
218 #reset-cells = <1>;
219 };
220 };
221
222 perictrl@59820000 {
223 compatible = "socionext,uniphier-ld4-perictrl",
224 "simple-mfd", "syscon";
225 reg = <0x59820000 0x200>;
226
227 peri_clk: clock {
228 compatible = "socionext,uniphier-ld4-peri-clock";
229 #clock-cells = <1>;
230 };
231
232 peri_rst: reset {
233 compatible = "socionext,uniphier-ld4-peri-reset";
234 #reset-cells = <1>;
235 };
236 };
237
238 dmac: dma-controller@5a000000 {
239 compatible = "socionext,uniphier-mio-dmac";
240 reg = <0x5a000000 0x1000>;
241 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
242 <0 71 4>, <0 72 4>, <0 73 4>;
243 clocks = <&mio_clk 7>;
244 resets = <&mio_rst 7>;
245 #dma-cells = <1>;
246 };
247
248 sd: sdhc@5a400000 {
249 compatible = "socionext,uniphier-sd-v2.91";
250 status = "disabled";
251 reg = <0x5a400000 0x200>;
252 interrupts = <0 76 4>;
253 pinctrl-names = "default", "uhs";
254 pinctrl-0 = <&pinctrl_sd>;
255 pinctrl-1 = <&pinctrl_sd_uhs>;
256 clocks = <&mio_clk 0>;
257 reset-names = "host", "bridge";
258 resets = <&mio_rst 0>, <&mio_rst 3>;
259 dma-names = "rx-tx";
260 dmas = <&dmac 4>;
261 bus-width = <4>;
262 cap-sd-highspeed;
263 sd-uhs-sdr12;
264 sd-uhs-sdr25;
265 sd-uhs-sdr50;
266 };
267
268 emmc: sdhc@5a500000 {
269 compatible = "socionext,uniphier-sd-v2.91";
270 status = "disabled";
271 reg = <0x5a500000 0x200>;
272 interrupts = <0 78 4>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_emmc>;
275 clocks = <&mio_clk 1>;
276 reset-names = "host", "bridge", "hw";
277 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
278 dma-names = "rx-tx";
279 dmas = <&dmac 6>;
280 bus-width = <8>;
281 cap-mmc-highspeed;
282 cap-mmc-hw-reset;
283 non-removable;
284 };
285
286 usb0: usb@5a800100 {
287 compatible = "socionext,uniphier-ehci", "generic-ehci";
288 status = "disabled";
289 reg = <0x5a800100 0x100>;
290 interrupts = <0 80 4>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_usb0>;
293 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
294 <&mio_clk 12>;
295 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
296 <&mio_rst 12>;
297 has-transaction-translator;
298 };
299
300 usb1: usb@5a810100 {
301 compatible = "socionext,uniphier-ehci", "generic-ehci";
302 status = "disabled";
303 reg = <0x5a810100 0x100>;
304 interrupts = <0 81 4>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_usb1>;
307 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
308 <&mio_clk 13>;
309 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
310 <&mio_rst 13>;
311 has-transaction-translator;
312 };
313
314 usb2: usb@5a820100 {
315 compatible = "socionext,uniphier-ehci", "generic-ehci";
316 status = "disabled";
317 reg = <0x5a820100 0x100>;
318 interrupts = <0 82 4>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_usb2>;
321 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
322 <&mio_clk 14>;
323 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
324 <&mio_rst 14>;
325 has-transaction-translator;
326 };
327
328 soc-glue@5f800000 {
329 compatible = "socionext,uniphier-ld4-soc-glue",
330 "simple-mfd", "syscon";
331 reg = <0x5f800000 0x2000>;
332
333 pinctrl: pinctrl {
334 compatible = "socionext,uniphier-ld4-pinctrl";
335 };
336 };
337
338 soc-glue@5f900000 {
339 compatible = "socionext,uniphier-ld4-soc-glue-debug",
340 "simple-mfd";
341 #address-cells = <1>;
342 #size-cells = <1>;
343 ranges = <0 0x5f900000 0x2000>;
344
345 efuse@100 {
346 compatible = "socionext,uniphier-efuse";
347 reg = <0x100 0x28>;
348 };
349
350 efuse@130 {
351 compatible = "socionext,uniphier-efuse";
352 reg = <0x130 0x8>;
353 };
354 };
355
356 timer@60000200 {
357 compatible = "arm,cortex-a9-global-timer";
358 reg = <0x60000200 0x20>;
359 interrupts = <1 11 0x104>;
360 clocks = <&arm_timer_clk>;
361 };
362
363 timer@60000600 {
364 compatible = "arm,cortex-a9-twd-timer";
365 reg = <0x60000600 0x20>;
366 interrupts = <1 13 0x104>;
367 clocks = <&arm_timer_clk>;
368 };
369
370 intc: interrupt-controller@60001000 {
371 compatible = "arm,cortex-a9-gic";
372 reg = <0x60001000 0x1000>,
373 <0x60000100 0x100>;
374 #interrupt-cells = <3>;
375 interrupt-controller;
376 };
377
378 aidet: aidet@61830000 {
379 compatible = "socionext,uniphier-ld4-aidet";
380 reg = <0x61830000 0x200>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
384
385 sysctrl@61840000 {
386 compatible = "socionext,uniphier-ld4-sysctrl",
387 "simple-mfd", "syscon";
388 reg = <0x61840000 0x10000>;
389
390 sys_clk: clock {
391 compatible = "socionext,uniphier-ld4-clock";
392 #clock-cells = <1>;
393 };
394
395 sys_rst: reset {
396 compatible = "socionext,uniphier-ld4-reset";
397 #reset-cells = <1>;
398 };
399 };
400
401 nand: nand@68000000 {
402 compatible = "socionext,uniphier-denali-nand-v5a";
403 status = "disabled";
404 reg-names = "nand_data", "denali_reg";
405 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 interrupts = <0 65 4>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_nand>;
411 clock-names = "nand", "nand_x", "ecc";
412 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
413 resets = <&sys_rst 2>;
414 };
415 };
416};
417
418#include "uniphier-pinctrl.dtsi"