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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP34xx/OMAP35xx SoC
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/media/omap3-isp.h>
10
11#include "omap3.dtsi"
12
13/ {
14 cpus {
15 cpu: cpu@0 {
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
18
19 clock-latency = <300000>; /* From legacy driver */
20 #cooling-cells = <2>;
21 };
22 };
23
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
26 syscon = <&scm_conf>;
27
28 opp1-125000000 {
29 opp-hz = /bits/ 64 <125000000>;
30 /*
31 * we currently only select the max voltage from table
32 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
33 * Format is: <target min max>
34 */
35 opp-microvolt = <975000 975000 975000>;
36 /*
37 * first value is silicon revision bit mask
38 * second one 720MHz Device Identification bit mask
39 */
40 opp-supported-hw = <0xffffffff 3>;
41 };
42
43 opp2-250000000 {
44 opp-hz = /bits/ 64 <250000000>;
45 opp-microvolt = <1075000 1075000 1075000>;
46 opp-supported-hw = <0xffffffff 3>;
47 opp-suspend;
48 };
49
50 opp3-500000000 {
51 opp-hz = /bits/ 64 <500000000>;
52 opp-microvolt = <1200000 1200000 1200000>;
53 opp-supported-hw = <0xffffffff 3>;
54 };
55
56 opp4-550000000 {
57 opp-hz = /bits/ 64 <550000000>;
58 opp-microvolt = <1275000 1275000 1275000>;
59 opp-supported-hw = <0xffffffff 3>;
60 };
61
62 opp5-600000000 {
63 opp-hz = /bits/ 64 <600000000>;
64 opp-microvolt = <1350000 1350000 1350000>;
65 opp-supported-hw = <0xffffffff 3>;
66 };
67
68 opp6-720000000 {
69 opp-hz = /bits/ 64 <720000000>;
70 opp-microvolt = <1350000 1350000 1350000>;
71 /* only high-speed grade omap3530 devices */
72 opp-supported-hw = <0xffffffff 2>;
73 turbo-mode;
74 };
75 };
76
77 ocp@68000000 {
78 omap3_pmx_core2: pinmux@480025d8 {
79 compatible = "ti,omap3-padconf", "pinctrl-single";
80 reg = <0x480025d8 0x24>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 #pinctrl-cells = <1>;
84 #interrupt-cells = <1>;
85 interrupt-controller;
86 pinctrl-single,register-width = <16>;
87 pinctrl-single,function-mask = <0xff1f>;
88 };
89
90 isp: isp@480bc000 {
91 compatible = "ti,omap3-isp";
92 reg = <0x480bc000 0x12fc
93 0x480bd800 0x017c>;
94 interrupts = <24>;
95 iommus = <&mmu_isp>;
96 syscon = <&scm_conf 0x6c>;
97 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
98 #clock-cells = <1>;
99 ports {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 };
103 };
104
105 bandgap: bandgap@48002524 {
106 reg = <0x48002524 0x4>;
107 compatible = "ti,omap34xx-bandgap";
108 #thermal-sensor-cells = <0>;
109 };
110
111 target-module@480cb000 {
112 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
113 ti,hwmods = "smartreflex_core";
114 reg = <0x480cb024 0x4>;
115 reg-names = "sysc";
116 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
117 clocks = <&sr2_fck>;
118 clock-names = "fck";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges = <0 0x480cb000 0x001000>;
122
123 smartreflex_core: smartreflex@0 {
124 compatible = "ti,omap3-smartreflex-core";
125 reg = <0 0x400>;
126 interrupts = <19>;
127 };
128 };
129
130 target-module@480c9000 {
131 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
132 ti,hwmods = "smartreflex_mpu_iva";
133 reg = <0x480c9024 0x4>;
134 reg-names = "sysc";
135 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
136 clocks = <&sr1_fck>;
137 clock-names = "fck";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0 0x480c9000 0x001000>;
141
142 smartreflex_mpu_iva: smartreflex@480c9000 {
143 compatible = "ti,omap3-smartreflex-mpu-iva";
144 reg = <0 0x400>;
145 interrupts = <18>;
146 };
147 };
148
149 /*
150 * On omap34xx the OCP registers do not seem to be accessible
151 * at all unlike on 36xx. Maybe SGX is permanently set to
152 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
153 * write-only at 0x50000e10. We detect SGX based on the SGX
154 * revision register instead of the unreadable OCP revision
155 * register. Also note that on early 34xx es1 revision there
156 * are also different clocks, but we do not have any dts users
157 * for it.
158 */
159 sgx_module: target-module@50000000 {
160 compatible = "ti,sysc-omap2", "ti,sysc";
161 reg = <0x50000014 0x4>;
162 reg-names = "rev";
163 clocks = <&sgx_fck>, <&sgx_ick>;
164 clock-names = "fck", "ick";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0 0x50000000 0x4000>;
168
169 /*
170 * Closed source PowerVR driver, no child device
171 * binding or driver in mainline
172 */
173 };
174 };
175
176 thermal_zones: thermal-zones {
177 #include "omap3-cpu-thermal.dtsi"
178 };
179};
180
181&ssi {
182 status = "okay";
183
184 clocks = <&ssi_ssr_fck>,
185 <&ssi_sst_fck>,
186 <&ssi_ick>;
187 clock-names = "ssi_ssr_fck",
188 "ssi_sst_fck",
189 "ssi_ick";
190};
191
192&usb_otg_target {
193 clocks = <&hsotgusb_ick_3430es2>;
194};
195
196/include/ "omap34xx-omap36xx-clocks.dtsi"
197/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
198/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/media/omap3-isp.h>
13
14#include "omap3.dtsi"
15
16/ {
17 cpus {
18 cpu: cpu@0 {
19 /* OMAP343x/OMAP35xx variants OPP1-5 */
20 operating-points = <
21 /* kHz uV */
22 125000 975000
23 250000 1075000
24 500000 1200000
25 550000 1270000
26 600000 1350000
27 >;
28 clock-latency = <300000>; /* From legacy driver */
29 };
30 };
31
32 ocp@68000000 {
33 omap3_pmx_core2: pinmux@480025d8 {
34 compatible = "ti,omap3-padconf", "pinctrl-single";
35 reg = <0x480025d8 0x24>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 #pinctrl-cells = <1>;
39 #interrupt-cells = <1>;
40 interrupt-controller;
41 pinctrl-single,register-width = <16>;
42 pinctrl-single,function-mask = <0xff1f>;
43 };
44
45 isp: isp@480bc000 {
46 compatible = "ti,omap3-isp";
47 reg = <0x480bc000 0x12fc
48 0x480bd800 0x017c>;
49 interrupts = <24>;
50 iommus = <&mmu_isp>;
51 syscon = <&scm_conf 0x6c>;
52 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
53 #clock-cells = <1>;
54 ports {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 };
58 };
59
60 bandgap: bandgap@48002524 {
61 reg = <0x48002524 0x4>;
62 compatible = "ti,omap34xx-bandgap";
63 #thermal-sensor-cells = <0>;
64 };
65
66 target-module@480cb000 {
67 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
68 ti,hwmods = "smartreflex_core";
69 reg = <0x480cb024 0x4>;
70 reg-names = "sysc";
71 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
72 clocks = <&sr2_fck>;
73 clock-names = "fck";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges = <0 0x480cb000 0x001000>;
77
78 smartreflex_core: smartreflex@0 {
79 compatible = "ti,omap3-smartreflex-core";
80 reg = <0 0x400>;
81 interrupts = <19>;
82 };
83 };
84
85 target-module@480c9000 {
86 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
87 ti,hwmods = "smartreflex_mpu_iva";
88 reg = <0x480c9024 0x4>;
89 reg-names = "sysc";
90 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
91 clocks = <&sr1_fck>;
92 clock-names = "fck";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x480c9000 0x001000>;
96
97 smartreflex_mpu_iva: smartreflex@480c9000 {
98 compatible = "ti,omap3-smartreflex-mpu-iva";
99 reg = <0 0x400>;
100 interrupts = <18>;
101 };
102 };
103
104 /*
105 * On omap34xx the OCP registers do not seem to be accessible
106 * at all unlike on 36xx. Maybe SGX is permanently set to
107 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
108 * write-only at 0x50000e10. We detect SGX based on the SGX
109 * revision register instead of the unreadable OCP revision
110 * register. Also note that on early 34xx es1 revision there
111 * are also different clocks, but we do not have any dts users
112 * for it.
113 */
114 sgx_module: target-module@50000000 {
115 compatible = "ti,sysc-omap2", "ti,sysc";
116 reg = <0x50000014 0x4>;
117 reg-names = "rev";
118 clocks = <&sgx_fck>, <&sgx_ick>;
119 clock-names = "fck", "ick";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0 0x50000000 0x4000>;
123
124 /*
125 * Closed source PowerVR driver, no child device
126 * binding or driver in mainline
127 */
128 };
129 };
130
131 thermal_zones: thermal-zones {
132 #include "omap3-cpu-thermal.dtsi"
133 };
134};
135
136&ssi {
137 status = "ok";
138
139 clocks = <&ssi_ssr_fck>,
140 <&ssi_sst_fck>,
141 <&ssi_ick>;
142 clock-names = "ssi_ssr_fck",
143 "ssi_sst_fck",
144 "ssi_ick";
145};
146
147/include/ "omap34xx-omap36xx-clocks.dtsi"
148/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
149/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"