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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include "exynos4.dtsi"
20#include "exynos4-cpu-thermal.dtsi"
21
22/ {
23 compatible = "samsung,exynos4210", "samsung,exynos4";
24
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu-map {
36 cluster0 {
37 core0 {
38 cpu = <&cpu0>;
39 };
40 core1 {
41 cpu = <&cpu1>;
42 };
43 };
44 };
45
46 cpu0: cpu@900 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a9";
49 reg = <0x900>;
50 clocks = <&clock CLK_ARM_CLK>;
51 clock-names = "cpu";
52 clock-latency = <160000>;
53
54 operating-points = <
55 1200000 1250000
56 1000000 1150000
57 800000 1075000
58 500000 975000
59 400000 975000
60 200000 950000
61 >;
62 #cooling-cells = <2>; /* min followed by max */
63 };
64
65 cpu1: cpu@901 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a9";
68 reg = <0x901>;
69 clocks = <&clock CLK_ARM_CLK>;
70 clock-names = "cpu";
71 clock-latency = <160000>;
72
73 operating-points = <
74 1200000 1250000
75 1000000 1150000
76 800000 1075000
77 500000 975000
78 400000 975000
79 200000 950000
80 >;
81 #cooling-cells = <2>; /* min followed by max */
82 };
83 };
84
85 soc: soc {
86 sysram: sram@2020000 {
87 compatible = "mmio-sram";
88 reg = <0x02020000 0x20000>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges = <0 0x02020000 0x20000>;
92
93 smp-sram@0 {
94 compatible = "samsung,exynos4210-sysram";
95 reg = <0x0 0x1000>;
96 };
97
98 smp-sram@1f000 {
99 compatible = "samsung,exynos4210-sysram-ns";
100 reg = <0x1f000 0x1000>;
101 };
102 };
103
104 pd_lcd1: power-domain@10023ca0 {
105 compatible = "samsung,exynos4210-pd";
106 reg = <0x10023CA0 0x20>;
107 #power-domain-cells = <0>;
108 label = "LCD1";
109 };
110
111 l2c: cache-controller@10502000 {
112 compatible = "arm,pl310-cache";
113 reg = <0x10502000 0x1000>;
114 cache-unified;
115 cache-level = <2>;
116 prefetch-data = <1>;
117 prefetch-instr = <1>;
118 arm,tag-latency = <2 2 1>;
119 arm,data-latency = <2 2 1>;
120 };
121
122 mct: timer@10050000 {
123 compatible = "samsung,exynos4210-mct";
124 reg = <0x10050000 0x800>;
125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
126 clock-names = "fin_pll", "mct";
127 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
128 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
129 <&combiner 12 6>,
130 <&combiner 12 7>,
131 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
132 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
133 };
134
135 watchdog: watchdog@10060000 {
136 compatible = "samsung,s3c6410-wdt";
137 reg = <0x10060000 0x100>;
138 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&clock CLK_WDT>;
140 clock-names = "watchdog";
141 };
142
143 clock: clock-controller@10030000 {
144 compatible = "samsung,exynos4210-clock";
145 reg = <0x10030000 0x20000>;
146 #clock-cells = <1>;
147 };
148
149 pinctrl_0: pinctrl@11400000 {
150 compatible = "samsung,exynos4210-pinctrl";
151 reg = <0x11400000 0x1000>;
152 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
153 };
154
155 pinctrl_1: pinctrl@11000000 {
156 compatible = "samsung,exynos4210-pinctrl";
157 reg = <0x11000000 0x1000>;
158 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
159
160 wakup_eint: wakeup-interrupt-controller {
161 compatible = "samsung,exynos4210-wakeup-eint";
162 interrupt-parent = <&gic>;
163 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
164 };
165 };
166
167 pinctrl_2: pinctrl@3860000 {
168 compatible = "samsung,exynos4210-pinctrl";
169 reg = <0x03860000 0x1000>;
170 };
171
172 g2d: g2d@12800000 {
173 compatible = "samsung,s5pv210-g2d";
174 reg = <0x12800000 0x1000>;
175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
177 clock-names = "sclk_fimg2d", "fimg2d";
178 power-domains = <&pd_lcd0>;
179 iommus = <&sysmmu_g2d>;
180 };
181
182 ppmu_acp: ppmu@10ae0000 {
183 compatible = "samsung,exynos-ppmu";
184 reg = <0x10ae0000 0x2000>;
185 status = "disabled";
186 };
187
188 ppmu_lcd1: ppmu@12240000 {
189 compatible = "samsung,exynos-ppmu";
190 reg = <0x12240000 0x2000>;
191 clocks = <&clock CLK_PPMULCD1>;
192 clock-names = "ppmu";
193 status = "disabled";
194 };
195
196 sysmmu_g2d: sysmmu@12a20000 {
197 compatible = "samsung,exynos-sysmmu";
198 reg = <0x12A20000 0x1000>;
199 interrupt-parent = <&combiner>;
200 interrupts = <4 7>;
201 clock-names = "sysmmu", "master";
202 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
203 power-domains = <&pd_lcd0>;
204 #iommu-cells = <0>;
205 };
206
207 sysmmu_fimd1: sysmmu@12220000 {
208 compatible = "samsung,exynos-sysmmu";
209 interrupt-parent = <&combiner>;
210 reg = <0x12220000 0x1000>;
211 interrupts = <5 3>;
212 clock-names = "sysmmu", "master";
213 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
214 power-domains = <&pd_lcd1>;
215 #iommu-cells = <0>;
216 };
217
218 bus_dmc: bus-dmc {
219 compatible = "samsung,exynos-bus";
220 clocks = <&clock CLK_DIV_DMC>;
221 clock-names = "bus";
222 operating-points-v2 = <&bus_dmc_opp_table>;
223 status = "disabled";
224 };
225
226 bus_acp: bus-acp {
227 compatible = "samsung,exynos-bus";
228 clocks = <&clock CLK_DIV_ACP>;
229 clock-names = "bus";
230 operating-points-v2 = <&bus_acp_opp_table>;
231 status = "disabled";
232 };
233
234 bus_peri: bus-peri {
235 compatible = "samsung,exynos-bus";
236 clocks = <&clock CLK_ACLK100>;
237 clock-names = "bus";
238 operating-points-v2 = <&bus_peri_opp_table>;
239 status = "disabled";
240 };
241
242 bus_fsys: bus-fsys {
243 compatible = "samsung,exynos-bus";
244 clocks = <&clock CLK_ACLK133>;
245 clock-names = "bus";
246 operating-points-v2 = <&bus_fsys_opp_table>;
247 status = "disabled";
248 };
249
250 bus_display: bus-display {
251 compatible = "samsung,exynos-bus";
252 clocks = <&clock CLK_ACLK160>;
253 clock-names = "bus";
254 operating-points-v2 = <&bus_display_opp_table>;
255 status = "disabled";
256 };
257
258 bus_lcd0: bus-lcd0 {
259 compatible = "samsung,exynos-bus";
260 clocks = <&clock CLK_ACLK200>;
261 clock-names = "bus";
262 operating-points-v2 = <&bus_leftbus_opp_table>;
263 status = "disabled";
264 };
265
266 bus_leftbus: bus-leftbus {
267 compatible = "samsung,exynos-bus";
268 clocks = <&clock CLK_DIV_GDL>;
269 clock-names = "bus";
270 operating-points-v2 = <&bus_leftbus_opp_table>;
271 status = "disabled";
272 };
273
274 bus_rightbus: bus-rightbus {
275 compatible = "samsung,exynos-bus";
276 clocks = <&clock CLK_DIV_GDR>;
277 clock-names = "bus";
278 operating-points-v2 = <&bus_leftbus_opp_table>;
279 status = "disabled";
280 };
281
282 bus_mfc: bus-mfc {
283 compatible = "samsung,exynos-bus";
284 clocks = <&clock CLK_SCLK_MFC>;
285 clock-names = "bus";
286 operating-points-v2 = <&bus_leftbus_opp_table>;
287 status = "disabled";
288 };
289
290 bus_dmc_opp_table: opp-table1 {
291 compatible = "operating-points-v2";
292 opp-shared;
293
294 opp-134000000 {
295 opp-hz = /bits/ 64 <134000000>;
296 opp-microvolt = <1025000>;
297 };
298 opp-267000000 {
299 opp-hz = /bits/ 64 <267000000>;
300 opp-microvolt = <1050000>;
301 };
302 opp-400000000 {
303 opp-hz = /bits/ 64 <400000000>;
304 opp-microvolt = <1150000>;
305 opp-suspend;
306 };
307 };
308
309 bus_acp_opp_table: opp-table2 {
310 compatible = "operating-points-v2";
311 opp-shared;
312
313 opp-134000000 {
314 opp-hz = /bits/ 64 <134000000>;
315 };
316 opp-160000000 {
317 opp-hz = /bits/ 64 <160000000>;
318 };
319 opp-200000000 {
320 opp-hz = /bits/ 64 <200000000>;
321 };
322 };
323
324 bus_peri_opp_table: opp-table3 {
325 compatible = "operating-points-v2";
326 opp-shared;
327
328 opp-5000000 {
329 opp-hz = /bits/ 64 <5000000>;
330 };
331 opp-100000000 {
332 opp-hz = /bits/ 64 <100000000>;
333 };
334 };
335
336 bus_fsys_opp_table: opp-table4 {
337 compatible = "operating-points-v2";
338 opp-shared;
339
340 opp-10000000 {
341 opp-hz = /bits/ 64 <10000000>;
342 };
343 opp-134000000 {
344 opp-hz = /bits/ 64 <134000000>;
345 };
346 };
347
348 bus_display_opp_table: opp-table5 {
349 compatible = "operating-points-v2";
350 opp-shared;
351
352 opp-100000000 {
353 opp-hz = /bits/ 64 <100000000>;
354 };
355 opp-134000000 {
356 opp-hz = /bits/ 64 <134000000>;
357 };
358 opp-160000000 {
359 opp-hz = /bits/ 64 <160000000>;
360 };
361 };
362
363 bus_leftbus_opp_table: opp-table6 {
364 compatible = "operating-points-v2";
365 opp-shared;
366
367 opp-100000000 {
368 opp-hz = /bits/ 64 <100000000>;
369 };
370 opp-160000000 {
371 opp-hz = /bits/ 64 <160000000>;
372 };
373 opp-200000000 {
374 opp-hz = /bits/ 64 <200000000>;
375 opp-suspend;
376 };
377 };
378 };
379};
380
381&cpu_alert0 {
382 temperature = <85000>; /* millicelsius */
383};
384
385&cpu_alert1 {
386 temperature = <100000>; /* millicelsius */
387};
388
389&cpu_alert2 {
390 temperature = <110000>; /* millicelsius */
391};
392
393&cpu_thermal {
394 polling-delay-passive = <0>;
395 polling-delay = <0>;
396 thermal-sensors = <&tmu 0>;
397};
398
399&gic {
400 cpu-offset = <0x8000>;
401};
402
403&camera {
404 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
405 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
406 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
407};
408
409&combiner {
410 samsung,combiner-nr = <16>;
411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
427};
428
429&fimc_0 {
430 samsung,pix-limits = <4224 8192 1920 4224>;
431 samsung,mainscaler-ext;
432 samsung,cam-if;
433};
434
435&fimc_1 {
436 samsung,pix-limits = <4224 8192 1920 4224>;
437 samsung,mainscaler-ext;
438 samsung,cam-if;
439};
440
441&fimc_2 {
442 samsung,pix-limits = <4224 8192 1920 4224>;
443 samsung,mainscaler-ext;
444 samsung,lcd-wb;
445};
446
447&fimc_3 {
448 samsung,pix-limits = <1920 8192 1366 1920>;
449 samsung,rotators = <0>;
450 samsung,mainscaler-ext;
451 samsung,lcd-wb;
452};
453
454&gpu {
455 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "gp",
466 "gpmmu",
467 "pp0",
468 "ppmmu0",
469 "pp1",
470 "ppmmu1",
471 "pp2",
472 "ppmmu2",
473 "pp3",
474 "ppmmu3";
475 operating-points-v2 = <&gpu_opp_table>;
476
477 gpu_opp_table: opp-table {
478 compatible = "operating-points-v2";
479
480 opp-160000000 {
481 opp-hz = /bits/ 64 <160000000>;
482 opp-microvolt = <950000>;
483 };
484 opp-267000000 {
485 opp-hz = /bits/ 64 <267000000>;
486 opp-microvolt = <1050000>;
487 };
488 };
489};
490
491&mdma1 {
492 power-domains = <&pd_lcd0>;
493};
494
495&mixer {
496 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
497 "sclk_mixer";
498 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
499 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
500 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
501};
502
503&pmu {
504 interrupts = <2 2>, <3 2>;
505 interrupt-affinity = <&cpu0>, <&cpu1>;
506 status = "okay";
507};
508
509&pmu_system_controller {
510 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
511 "clkout4", "clkout8", "clkout9";
512 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
513 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
514 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
515 #clock-cells = <1>;
516};
517
518&rotator {
519 power-domains = <&pd_lcd0>;
520};
521
522&sysmmu_rotator {
523 power-domains = <&pd_lcd0>;
524};
525
526&tmu {
527 compatible = "samsung,exynos4210-tmu";
528 clocks = <&clock CLK_TMU_APBIF>;
529 clock-names = "tmu_apbif";
530};
531
532#include "exynos4210-pinctrl.dtsi"
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include "exynos4.dtsi"
20#include "exynos4-cpu-thermal.dtsi"
21
22/ {
23 compatible = "samsung,exynos4210", "samsung,exynos4";
24
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@900 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0x900>;
39 clocks = <&clock CLK_ARM_CLK>;
40 clock-names = "cpu";
41 clock-latency = <160000>;
42
43 operating-points = <
44 1200000 1250000
45 1000000 1150000
46 800000 1075000
47 500000 975000
48 400000 975000
49 200000 950000
50 >;
51 #cooling-cells = <2>; /* min followed by max */
52 };
53
54 cpu1: cpu@901 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a9";
57 reg = <0x901>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <160000>;
61
62 operating-points = <
63 1200000 1250000
64 1000000 1150000
65 800000 1075000
66 500000 975000
67 400000 975000
68 200000 950000
69 >;
70 #cooling-cells = <2>; /* min followed by max */
71 };
72 };
73
74 soc: soc {
75 sysram: sysram@2020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x20000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x20000>;
81
82 smp-sysram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
86
87 smp-sysram@1f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x1f000 0x1000>;
90 };
91 };
92
93 pd_lcd1: lcd1-power-domain@10023ca0 {
94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10023CA0 0x20>;
96 #power-domain-cells = <0>;
97 label = "LCD1";
98 };
99
100 l2c: l2-cache-controller@10502000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x10502000 0x1000>;
103 cache-unified;
104 cache-level = <2>;
105 arm,tag-latency = <2 2 1>;
106 arm,data-latency = <2 2 1>;
107 };
108
109 mct: mct@10050000 {
110 compatible = "samsung,exynos4210-mct";
111 reg = <0x10050000 0x800>;
112 interrupt-parent = <&mct_map>;
113 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
114 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
115 clock-names = "fin_pll", "mct";
116
117 mct_map: mct-map {
118 #interrupt-cells = <1>;
119 #address-cells = <0>;
120 #size-cells = <0>;
121 interrupt-map =
122 <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
123 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
124 <2 &combiner 12 6>,
125 <3 &combiner 12 7>,
126 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
127 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
128 };
129 };
130
131 watchdog: watchdog@10060000 {
132 compatible = "samsung,s3c6410-wdt";
133 reg = <0x10060000 0x100>;
134 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&clock CLK_WDT>;
136 clock-names = "watchdog";
137 };
138
139 clock: clock-controller@10030000 {
140 compatible = "samsung,exynos4210-clock";
141 reg = <0x10030000 0x20000>;
142 #clock-cells = <1>;
143 };
144
145 pinctrl_0: pinctrl@11400000 {
146 compatible = "samsung,exynos4210-pinctrl";
147 reg = <0x11400000 0x1000>;
148 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
149 };
150
151 pinctrl_1: pinctrl@11000000 {
152 compatible = "samsung,exynos4210-pinctrl";
153 reg = <0x11000000 0x1000>;
154 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
155
156 wakup_eint: wakeup-interrupt-controller {
157 compatible = "samsung,exynos4210-wakeup-eint";
158 interrupt-parent = <&gic>;
159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
160 };
161 };
162
163 pinctrl_2: pinctrl@3860000 {
164 compatible = "samsung,exynos4210-pinctrl";
165 reg = <0x03860000 0x1000>;
166 };
167
168 g2d: g2d@12800000 {
169 compatible = "samsung,s5pv210-g2d";
170 reg = <0x12800000 0x1000>;
171 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
173 clock-names = "sclk_fimg2d", "fimg2d";
174 power-domains = <&pd_lcd0>;
175 iommus = <&sysmmu_g2d>;
176 };
177
178 ppmu_acp: ppmu_acp@10ae0000 {
179 compatible = "samsung,exynos-ppmu";
180 reg = <0x10ae0000 0x2000>;
181 status = "disabled";
182 };
183
184 ppmu_lcd1: ppmu_lcd1@12240000 {
185 compatible = "samsung,exynos-ppmu";
186 reg = <0x12240000 0x2000>;
187 clocks = <&clock CLK_PPMULCD1>;
188 clock-names = "ppmu";
189 status = "disabled";
190 };
191
192 sysmmu_g2d: sysmmu@12a20000 {
193 compatible = "samsung,exynos-sysmmu";
194 reg = <0x12A20000 0x1000>;
195 interrupt-parent = <&combiner>;
196 interrupts = <4 7>;
197 clock-names = "sysmmu", "master";
198 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
199 power-domains = <&pd_lcd0>;
200 #iommu-cells = <0>;
201 };
202
203 sysmmu_fimd1: sysmmu@12220000 {
204 compatible = "samsung,exynos-sysmmu";
205 interrupt-parent = <&combiner>;
206 reg = <0x12220000 0x1000>;
207 interrupts = <5 3>;
208 clock-names = "sysmmu", "master";
209 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
210 power-domains = <&pd_lcd1>;
211 #iommu-cells = <0>;
212 };
213
214 bus_dmc: bus_dmc {
215 compatible = "samsung,exynos-bus";
216 clocks = <&clock CLK_DIV_DMC>;
217 clock-names = "bus";
218 operating-points-v2 = <&bus_dmc_opp_table>;
219 status = "disabled";
220 };
221
222 bus_acp: bus_acp {
223 compatible = "samsung,exynos-bus";
224 clocks = <&clock CLK_DIV_ACP>;
225 clock-names = "bus";
226 operating-points-v2 = <&bus_acp_opp_table>;
227 status = "disabled";
228 };
229
230 bus_peri: bus_peri {
231 compatible = "samsung,exynos-bus";
232 clocks = <&clock CLK_ACLK100>;
233 clock-names = "bus";
234 operating-points-v2 = <&bus_peri_opp_table>;
235 status = "disabled";
236 };
237
238 bus_fsys: bus_fsys {
239 compatible = "samsung,exynos-bus";
240 clocks = <&clock CLK_ACLK133>;
241 clock-names = "bus";
242 operating-points-v2 = <&bus_fsys_opp_table>;
243 status = "disabled";
244 };
245
246 bus_display: bus_display {
247 compatible = "samsung,exynos-bus";
248 clocks = <&clock CLK_ACLK160>;
249 clock-names = "bus";
250 operating-points-v2 = <&bus_display_opp_table>;
251 status = "disabled";
252 };
253
254 bus_lcd0: bus_lcd0 {
255 compatible = "samsung,exynos-bus";
256 clocks = <&clock CLK_ACLK200>;
257 clock-names = "bus";
258 operating-points-v2 = <&bus_leftbus_opp_table>;
259 status = "disabled";
260 };
261
262 bus_leftbus: bus_leftbus {
263 compatible = "samsung,exynos-bus";
264 clocks = <&clock CLK_DIV_GDL>;
265 clock-names = "bus";
266 operating-points-v2 = <&bus_leftbus_opp_table>;
267 status = "disabled";
268 };
269
270 bus_rightbus: bus_rightbus {
271 compatible = "samsung,exynos-bus";
272 clocks = <&clock CLK_DIV_GDR>;
273 clock-names = "bus";
274 operating-points-v2 = <&bus_leftbus_opp_table>;
275 status = "disabled";
276 };
277
278 bus_mfc: bus_mfc {
279 compatible = "samsung,exynos-bus";
280 clocks = <&clock CLK_SCLK_MFC>;
281 clock-names = "bus";
282 operating-points-v2 = <&bus_leftbus_opp_table>;
283 status = "disabled";
284 };
285
286 bus_dmc_opp_table: opp_table1 {
287 compatible = "operating-points-v2";
288 opp-shared;
289
290 opp-134000000 {
291 opp-hz = /bits/ 64 <134000000>;
292 opp-microvolt = <1025000>;
293 };
294 opp-267000000 {
295 opp-hz = /bits/ 64 <267000000>;
296 opp-microvolt = <1050000>;
297 };
298 opp-400000000 {
299 opp-hz = /bits/ 64 <400000000>;
300 opp-microvolt = <1150000>;
301 opp-suspend;
302 };
303 };
304
305 bus_acp_opp_table: opp_table2 {
306 compatible = "operating-points-v2";
307 opp-shared;
308
309 opp-134000000 {
310 opp-hz = /bits/ 64 <134000000>;
311 };
312 opp-160000000 {
313 opp-hz = /bits/ 64 <160000000>;
314 };
315 opp-200000000 {
316 opp-hz = /bits/ 64 <200000000>;
317 };
318 };
319
320 bus_peri_opp_table: opp_table3 {
321 compatible = "operating-points-v2";
322 opp-shared;
323
324 opp-5000000 {
325 opp-hz = /bits/ 64 <5000000>;
326 };
327 opp-100000000 {
328 opp-hz = /bits/ 64 <100000000>;
329 };
330 };
331
332 bus_fsys_opp_table: opp_table4 {
333 compatible = "operating-points-v2";
334 opp-shared;
335
336 opp-10000000 {
337 opp-hz = /bits/ 64 <10000000>;
338 };
339 opp-134000000 {
340 opp-hz = /bits/ 64 <134000000>;
341 };
342 };
343
344 bus_display_opp_table: opp_table5 {
345 compatible = "operating-points-v2";
346 opp-shared;
347
348 opp-100000000 {
349 opp-hz = /bits/ 64 <100000000>;
350 };
351 opp-134000000 {
352 opp-hz = /bits/ 64 <134000000>;
353 };
354 opp-160000000 {
355 opp-hz = /bits/ 64 <160000000>;
356 };
357 };
358
359 bus_leftbus_opp_table: opp_table6 {
360 compatible = "operating-points-v2";
361 opp-shared;
362
363 opp-100000000 {
364 opp-hz = /bits/ 64 <100000000>;
365 };
366 opp-160000000 {
367 opp-hz = /bits/ 64 <160000000>;
368 };
369 opp-200000000 {
370 opp-hz = /bits/ 64 <200000000>;
371 opp-suspend;
372 };
373 };
374 };
375
376 thermal-zones {
377 cpu_thermal: cpu-thermal {
378 polling-delay-passive = <0>;
379 polling-delay = <0>;
380 thermal-sensors = <&tmu 0>;
381
382 trips {
383 cpu_alert0: cpu-alert-0 {
384 temperature = <85000>; /* millicelsius */
385 };
386 cpu_alert1: cpu-alert-1 {
387 temperature = <100000>; /* millicelsius */
388 };
389 cpu_alert2: cpu-alert-2 {
390 temperature = <110000>; /* millicelsius */
391 };
392 };
393 };
394 };
395};
396
397&gic {
398 cpu-offset = <0x8000>;
399};
400
401&camera {
402 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
403 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
404 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
405};
406
407&combiner {
408 samsung,combiner-nr = <16>;
409 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
425};
426
427&fimc_0 {
428 samsung,pix-limits = <4224 8192 1920 4224>;
429 samsung,mainscaler-ext;
430 samsung,cam-if;
431};
432
433&fimc_1 {
434 samsung,pix-limits = <4224 8192 1920 4224>;
435 samsung,mainscaler-ext;
436 samsung,cam-if;
437};
438
439&fimc_2 {
440 samsung,pix-limits = <4224 8192 1920 4224>;
441 samsung,mainscaler-ext;
442 samsung,lcd-wb;
443};
444
445&fimc_3 {
446 samsung,pix-limits = <1920 8192 1366 1920>;
447 samsung,rotators = <0>;
448 samsung,mainscaler-ext;
449 samsung,lcd-wb;
450};
451
452&gpu {
453 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "gp",
464 "gpmmu",
465 "pp0",
466 "ppmmu0",
467 "pp1",
468 "ppmmu1",
469 "pp2",
470 "ppmmu2",
471 "pp3",
472 "ppmmu3";
473 operating-points-v2 = <&gpu_opp_table>;
474
475 gpu_opp_table: opp_table {
476 compatible = "operating-points-v2";
477
478 opp-160000000 {
479 opp-hz = /bits/ 64 <160000000>;
480 opp-microvolt = <950000>;
481 };
482 opp-267000000 {
483 opp-hz = /bits/ 64 <267000000>;
484 opp-microvolt = <1050000>;
485 };
486 };
487};
488
489&mdma1 {
490 power-domains = <&pd_lcd0>;
491};
492
493&mixer {
494 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
495 "sclk_mixer";
496 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
497 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
498 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
499};
500
501&pmu {
502 interrupts = <2 2>, <3 2>;
503 interrupt-affinity = <&cpu0>, <&cpu1>;
504 status = "okay";
505};
506
507&pmu_system_controller {
508 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
509 "clkout4", "clkout8", "clkout9";
510 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
511 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
512 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
513 #clock-cells = <1>;
514};
515
516&rotator {
517 power-domains = <&pd_lcd0>;
518};
519
520&sysmmu_rotator {
521 power-domains = <&pd_lcd0>;
522};
523
524&tmu {
525 compatible = "samsung,exynos4210-tmu";
526 clocks = <&clock CLK_TMU_APBIF>;
527 clock-names = "tmu_apbif";
528 samsung,tmu_gain = <15>;
529 samsung,tmu_reference_voltage = <7>;
530};
531
532#include "exynos4210-pinctrl.dtsi"