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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Rockchip MIPI Synopsys DPHY RX0 driver
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on:
8 *
9 * drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
10 * in https://chromium.googlesource.com/chromiumos/third_party/kernel,
11 * chromeos-4.4 branch.
12 *
13 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
16 */
17
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/mfd/syscon.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/phy/phy.h>
26#include <linux/phy/phy-mipi-dphy.h>
27#include <linux/platform_device.h>
28#include <linux/regmap.h>
29
30#define RK3399_GRF_SOC_CON9 0x6224
31#define RK3399_GRF_SOC_CON21 0x6254
32#define RK3399_GRF_SOC_CON22 0x6258
33#define RK3399_GRF_SOC_CON23 0x625c
34#define RK3399_GRF_SOC_CON24 0x6260
35#define RK3399_GRF_SOC_CON25 0x6264
36#define RK3399_GRF_SOC_STATUS1 0xe2a4
37
38#define CLOCK_LANE_HS_RX_CONTROL 0x34
39#define LANE0_HS_RX_CONTROL 0x44
40#define LANE1_HS_RX_CONTROL 0x54
41#define LANE2_HS_RX_CONTROL 0x84
42#define LANE3_HS_RX_CONTROL 0x94
43#define LANES_THS_SETTLE_CONTROL 0x75
44#define THS_SETTLE_COUNTER_THRESHOLD 0x04
45
46struct hsfreq_range {
47 u16 range_h;
48 u8 cfg_bit;
49};
50
51static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
52 { 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 },
53 { 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 },
54 { 199, 0x22 }, { 219, 0x03 }, { 239, 0x13 }, { 249, 0x23 },
55 { 269, 0x04 }, { 299, 0x14 }, { 329, 0x05 }, { 359, 0x15 },
56 { 399, 0x25 }, { 449, 0x06 }, { 499, 0x16 }, { 549, 0x07 },
57 { 599, 0x17 }, { 649, 0x08 }, { 699, 0x18 }, { 749, 0x09 },
58 { 799, 0x19 }, { 849, 0x29 }, { 899, 0x39 }, { 949, 0x0a },
59 { 999, 0x1a }, { 1049, 0x2a }, { 1099, 0x3a }, { 1149, 0x0b },
60 { 1199, 0x1b }, { 1249, 0x2b }, { 1299, 0x3b }, { 1349, 0x0c },
61 { 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c }
62};
63
64static const char * const rk3399_mipidphy_clks[] = {
65 "dphy-ref",
66 "dphy-cfg",
67 "grf",
68};
69
70enum dphy_reg_id {
71 GRF_DPHY_RX0_TURNDISABLE = 0,
72 GRF_DPHY_RX0_FORCERXMODE,
73 GRF_DPHY_RX0_FORCETXSTOPMODE,
74 GRF_DPHY_RX0_ENABLE,
75 GRF_DPHY_RX0_TESTCLR,
76 GRF_DPHY_RX0_TESTCLK,
77 GRF_DPHY_RX0_TESTEN,
78 GRF_DPHY_RX0_TESTDIN,
79 GRF_DPHY_RX0_TURNREQUEST,
80 GRF_DPHY_RX0_TESTDOUT,
81 GRF_DPHY_TX0_TURNDISABLE,
82 GRF_DPHY_TX0_FORCERXMODE,
83 GRF_DPHY_TX0_FORCETXSTOPMODE,
84 GRF_DPHY_TX0_TURNREQUEST,
85 GRF_DPHY_TX1RX1_TURNDISABLE,
86 GRF_DPHY_TX1RX1_FORCERXMODE,
87 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
88 GRF_DPHY_TX1RX1_ENABLE,
89 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
90 GRF_DPHY_TX1RX1_BASEDIR,
91 GRF_DPHY_TX1RX1_ENABLECLK,
92 GRF_DPHY_TX1RX1_TURNREQUEST,
93 GRF_DPHY_RX1_SRC_SEL,
94 /* rk3288 only */
95 GRF_CON_DISABLE_ISP,
96 GRF_CON_ISP_DPHY_SEL,
97 GRF_DSI_CSI_TESTBUS_SEL,
98 GRF_DVP_V18SEL,
99 /* below is for rk3399 only */
100 GRF_DPHY_RX0_CLK_INV_SEL,
101 GRF_DPHY_RX1_CLK_INV_SEL,
102};
103
104struct dphy_reg {
105 u16 offset;
106 u8 mask;
107 u8 shift;
108};
109
110#define PHY_REG(_offset, _width, _shift) \
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
112
113static const struct dphy_reg rk3399_grf_dphy_regs[] = {
114 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
115 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
116 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
117 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
118 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
119 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
120 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
121 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
122 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
123 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
124 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
125 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
126 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
127 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
128 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
129 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
130 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
131 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
132 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
133 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
134 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
135 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
136 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
137 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
138 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
139};
140
141struct rk_dphy_drv_data {
142 const char * const *clks;
143 unsigned int num_clks;
144 const struct hsfreq_range *hsfreq_ranges;
145 unsigned int num_hsfreq_ranges;
146 const struct dphy_reg *regs;
147};
148
149struct rk_dphy {
150 struct device *dev;
151 struct regmap *grf;
152 struct clk_bulk_data *clks;
153
154 const struct rk_dphy_drv_data *drv_data;
155 struct phy_configure_opts_mipi_dphy config;
156
157 u8 hsfreq;
158};
159
160static inline void rk_dphy_write_grf(struct rk_dphy *priv,
161 unsigned int index, u8 value)
162{
163 const struct dphy_reg *reg = &priv->drv_data->regs[index];
164 /* Update high word */
165 unsigned int val = (value << reg->shift) |
166 (reg->mask << (reg->shift + 16));
167
168 if (WARN_ON(!reg->offset))
169 return;
170 regmap_write(priv->grf, reg->offset, val);
171}
172
173static void rk_dphy_write(struct rk_dphy *priv, u8 test_code, u8 test_data)
174{
175 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_code);
176 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 1);
177 /*
178 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
179 * is latched internally as the current test code. Test data is
180 * programmed internally by rising edge on TESTCLK.
181 * This code assumes that TESTCLK is already 1.
182 */
183 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 0);
184 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 0);
185 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_data);
186 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
187}
188
189static void rk_dphy_enable(struct rk_dphy *priv)
190{
191 rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
192 rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
193
194 /* Disable lane turn around, which is ignored in receive mode */
195 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
196 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
197
198 rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE,
199 GENMASK(priv->config.lanes - 1, 0));
200
201 /* dphy start */
202 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
203 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 1);
204 usleep_range(100, 150);
205 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 0);
206 usleep_range(100, 150);
207
208 /* set clock lane */
209 /* HS hsfreq_range & lane 0 settle bypass */
210 rk_dphy_write(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
211 /* HS RX Control of lane0 */
212 rk_dphy_write(priv, LANE0_HS_RX_CONTROL, priv->hsfreq << 1);
213 /* HS RX Control of lane1 */
214 rk_dphy_write(priv, LANE1_HS_RX_CONTROL, priv->hsfreq << 1);
215 /* HS RX Control of lane2 */
216 rk_dphy_write(priv, LANE2_HS_RX_CONTROL, priv->hsfreq << 1);
217 /* HS RX Control of lane3 */
218 rk_dphy_write(priv, LANE3_HS_RX_CONTROL, priv->hsfreq << 1);
219 /* HS RX Data Lanes Settle State Time Control */
220 rk_dphy_write(priv, LANES_THS_SETTLE_CONTROL,
221 THS_SETTLE_COUNTER_THRESHOLD);
222
223 /* Normal operation */
224 rk_dphy_write(priv, 0x0, 0);
225}
226
227static int rk_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
228{
229 struct rk_dphy *priv = phy_get_drvdata(phy);
230 const struct rk_dphy_drv_data *drv_data = priv->drv_data;
231 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
232 unsigned int hsfreq = 0;
233 unsigned int i;
234 u64 data_rate_mbps;
235 int ret;
236
237 /* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */
238 ret = phy_mipi_dphy_config_validate(config);
239 if (ret)
240 return ret;
241
242 data_rate_mbps = div_u64(config->hs_clk_rate, 1000 * 1000);
243
244 dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
245 config->lanes, data_rate_mbps);
246 for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
247 if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
248 hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
249 break;
250 }
251 }
252 if (!hsfreq)
253 return -EINVAL;
254
255 priv->hsfreq = hsfreq;
256 priv->config = *config;
257 return 0;
258}
259
260static int rk_dphy_power_on(struct phy *phy)
261{
262 struct rk_dphy *priv = phy_get_drvdata(phy);
263 int ret;
264
265 ret = clk_bulk_enable(priv->drv_data->num_clks, priv->clks);
266 if (ret)
267 return ret;
268
269 rk_dphy_enable(priv);
270
271 return 0;
272}
273
274static int rk_dphy_power_off(struct phy *phy)
275{
276 struct rk_dphy *priv = phy_get_drvdata(phy);
277
278 rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, 0);
279 clk_bulk_disable(priv->drv_data->num_clks, priv->clks);
280 return 0;
281}
282
283static int rk_dphy_init(struct phy *phy)
284{
285 struct rk_dphy *priv = phy_get_drvdata(phy);
286
287 return clk_bulk_prepare(priv->drv_data->num_clks, priv->clks);
288}
289
290static int rk_dphy_exit(struct phy *phy)
291{
292 struct rk_dphy *priv = phy_get_drvdata(phy);
293
294 clk_bulk_unprepare(priv->drv_data->num_clks, priv->clks);
295 return 0;
296}
297
298static const struct phy_ops rk_dphy_ops = {
299 .power_on = rk_dphy_power_on,
300 .power_off = rk_dphy_power_off,
301 .init = rk_dphy_init,
302 .exit = rk_dphy_exit,
303 .configure = rk_dphy_configure,
304 .owner = THIS_MODULE,
305};
306
307static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = {
308 .clks = rk3399_mipidphy_clks,
309 .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
310 .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
311 .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
312 .regs = rk3399_grf_dphy_regs,
313};
314
315static const struct of_device_id rk_dphy_dt_ids[] = {
316 {
317 .compatible = "rockchip,rk3399-mipi-dphy-rx0",
318 .data = &rk3399_mipidphy_drv_data,
319 },
320 {}
321};
322MODULE_DEVICE_TABLE(of, rk_dphy_dt_ids);
323
324static int rk_dphy_probe(struct platform_device *pdev)
325{
326 struct device *dev = &pdev->dev;
327 struct device_node *np = dev->of_node;
328 const struct rk_dphy_drv_data *drv_data;
329 struct phy_provider *phy_provider;
330 struct rk_dphy *priv;
331 struct phy *phy;
332 unsigned int i;
333 int ret;
334
335 if (!dev->parent || !dev->parent->of_node)
336 return -ENODEV;
337
338 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
339 if (!priv)
340 return -ENOMEM;
341 priv->dev = dev;
342
343 priv->grf = syscon_node_to_regmap(dev->parent->of_node);
344 if (IS_ERR(priv->grf)) {
345 dev_err(dev, "Can't find GRF syscon\n");
346 return -ENODEV;
347 }
348
349 drv_data = of_device_get_match_data(dev);
350 priv->drv_data = drv_data;
351 priv->clks = devm_kcalloc(&pdev->dev, drv_data->num_clks,
352 sizeof(*priv->clks), GFP_KERNEL);
353 if (!priv->clks)
354 return -ENOMEM;
355 for (i = 0; i < drv_data->num_clks; i++)
356 priv->clks[i].id = drv_data->clks[i];
357 ret = devm_clk_bulk_get(&pdev->dev, drv_data->num_clks, priv->clks);
358 if (ret)
359 return ret;
360
361 phy = devm_phy_create(dev, np, &rk_dphy_ops);
362 if (IS_ERR(phy)) {
363 dev_err(dev, "failed to create phy\n");
364 return PTR_ERR(phy);
365 }
366 phy_set_drvdata(phy, priv);
367
368 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
369
370 return PTR_ERR_OR_ZERO(phy_provider);
371}
372
373static struct platform_driver rk_dphy_driver = {
374 .probe = rk_dphy_probe,
375 .driver = {
376 .name = "rockchip-mipi-dphy-rx0",
377 .of_match_table = rk_dphy_dt_ids,
378 },
379};
380module_platform_driver(rk_dphy_driver);
381
382MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
383MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver");
384MODULE_LICENSE("Dual MIT/GPL");
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Rockchip MIPI Synopsys DPHY RX0 driver
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on:
8 *
9 * drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
10 * in https://chromium.googlesource.com/chromiumos/third_party/kernel,
11 * chromeos-4.4 branch.
12 *
13 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
16 */
17
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/mfd/syscon.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/phy/phy.h>
26#include <linux/phy/phy-mipi-dphy.h>
27#include <linux/platform_device.h>
28#include <linux/regmap.h>
29
30#define RK3399_GRF_SOC_CON9 0x6224
31#define RK3399_GRF_SOC_CON21 0x6254
32#define RK3399_GRF_SOC_CON22 0x6258
33#define RK3399_GRF_SOC_CON23 0x625c
34#define RK3399_GRF_SOC_CON24 0x6260
35#define RK3399_GRF_SOC_CON25 0x6264
36#define RK3399_GRF_SOC_STATUS1 0xe2a4
37
38#define CLOCK_LANE_HS_RX_CONTROL 0x34
39#define LANE0_HS_RX_CONTROL 0x44
40#define LANE1_HS_RX_CONTROL 0x54
41#define LANE2_HS_RX_CONTROL 0x84
42#define LANE3_HS_RX_CONTROL 0x94
43#define LANES_THS_SETTLE_CONTROL 0x75
44#define THS_SETTLE_COUNTER_THRESHOLD 0x04
45
46struct hsfreq_range {
47 u16 range_h;
48 u8 cfg_bit;
49};
50
51static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
52 { 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 },
53 { 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 },
54 { 199, 0x22 }, { 219, 0x03 }, { 239, 0x13 }, { 249, 0x23 },
55 { 269, 0x04 }, { 299, 0x14 }, { 329, 0x05 }, { 359, 0x15 },
56 { 399, 0x25 }, { 449, 0x06 }, { 499, 0x16 }, { 549, 0x07 },
57 { 599, 0x17 }, { 649, 0x08 }, { 699, 0x18 }, { 749, 0x09 },
58 { 799, 0x19 }, { 849, 0x29 }, { 899, 0x39 }, { 949, 0x0a },
59 { 999, 0x1a }, { 1049, 0x2a }, { 1099, 0x3a }, { 1149, 0x0b },
60 { 1199, 0x1b }, { 1249, 0x2b }, { 1299, 0x3b }, { 1349, 0x0c },
61 { 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c }
62};
63
64static const char * const rk3399_mipidphy_clks[] = {
65 "dphy-ref",
66 "dphy-cfg",
67 "grf",
68};
69
70enum dphy_reg_id {
71 GRF_DPHY_RX0_TURNDISABLE = 0,
72 GRF_DPHY_RX0_FORCERXMODE,
73 GRF_DPHY_RX0_FORCETXSTOPMODE,
74 GRF_DPHY_RX0_ENABLE,
75 GRF_DPHY_RX0_TESTCLR,
76 GRF_DPHY_RX0_TESTCLK,
77 GRF_DPHY_RX0_TESTEN,
78 GRF_DPHY_RX0_TESTDIN,
79 GRF_DPHY_RX0_TURNREQUEST,
80 GRF_DPHY_RX0_TESTDOUT,
81 GRF_DPHY_TX0_TURNDISABLE,
82 GRF_DPHY_TX0_FORCERXMODE,
83 GRF_DPHY_TX0_FORCETXSTOPMODE,
84 GRF_DPHY_TX0_TURNREQUEST,
85 GRF_DPHY_TX1RX1_TURNDISABLE,
86 GRF_DPHY_TX1RX1_FORCERXMODE,
87 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
88 GRF_DPHY_TX1RX1_ENABLE,
89 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
90 GRF_DPHY_TX1RX1_BASEDIR,
91 GRF_DPHY_TX1RX1_ENABLECLK,
92 GRF_DPHY_TX1RX1_TURNREQUEST,
93 GRF_DPHY_RX1_SRC_SEL,
94 /* rk3288 only */
95 GRF_CON_DISABLE_ISP,
96 GRF_CON_ISP_DPHY_SEL,
97 GRF_DSI_CSI_TESTBUS_SEL,
98 GRF_DVP_V18SEL,
99 /* below is for rk3399 only */
100 GRF_DPHY_RX0_CLK_INV_SEL,
101 GRF_DPHY_RX1_CLK_INV_SEL,
102};
103
104struct dphy_reg {
105 u16 offset;
106 u8 mask;
107 u8 shift;
108};
109
110#define PHY_REG(_offset, _width, _shift) \
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
112
113static const struct dphy_reg rk3399_grf_dphy_regs[] = {
114 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
115 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
116 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
117 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
118 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
119 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
120 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
121 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
122 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
123 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
124 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
125 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
126 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
127 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
128 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
129 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
130 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
131 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
132 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
133 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
134 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
135 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
136 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
137 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
138 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
139};
140
141struct rk_dphy_drv_data {
142 const char * const *clks;
143 unsigned int num_clks;
144 const struct hsfreq_range *hsfreq_ranges;
145 unsigned int num_hsfreq_ranges;
146 const struct dphy_reg *regs;
147};
148
149struct rk_dphy {
150 struct device *dev;
151 struct regmap *grf;
152 struct clk_bulk_data *clks;
153
154 const struct rk_dphy_drv_data *drv_data;
155 struct phy_configure_opts_mipi_dphy config;
156
157 u8 hsfreq;
158};
159
160static inline void rk_dphy_write_grf(struct rk_dphy *priv,
161 unsigned int index, u8 value)
162{
163 const struct dphy_reg *reg = &priv->drv_data->regs[index];
164 /* Update high word */
165 unsigned int val = (value << reg->shift) |
166 (reg->mask << (reg->shift + 16));
167
168 if (WARN_ON(!reg->offset))
169 return;
170 regmap_write(priv->grf, reg->offset, val);
171}
172
173static void rk_dphy_write(struct rk_dphy *priv, u8 test_code, u8 test_data)
174{
175 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_code);
176 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 1);
177 /*
178 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
179 * is latched internally as the current test code. Test data is
180 * programmed internally by rising edge on TESTCLK.
181 * This code assumes that TESTCLK is already 1.
182 */
183 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 0);
184 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 0);
185 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_data);
186 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
187}
188
189static void rk_dphy_enable(struct rk_dphy *priv)
190{
191 rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
192 rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
193
194 /* Disable lane turn around, which is ignored in receive mode */
195 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
196 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
197
198 rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE,
199 GENMASK(priv->config.lanes - 1, 0));
200
201 /* dphy start */
202 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
203 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 1);
204 usleep_range(100, 150);
205 rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 0);
206 usleep_range(100, 150);
207
208 /* set clock lane */
209 /* HS hsfreq_range & lane 0 settle bypass */
210 rk_dphy_write(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
211 /* HS RX Control of lane0 */
212 rk_dphy_write(priv, LANE0_HS_RX_CONTROL, priv->hsfreq << 1);
213 /* HS RX Control of lane1 */
214 rk_dphy_write(priv, LANE1_HS_RX_CONTROL, priv->hsfreq << 1);
215 /* HS RX Control of lane2 */
216 rk_dphy_write(priv, LANE2_HS_RX_CONTROL, priv->hsfreq << 1);
217 /* HS RX Control of lane3 */
218 rk_dphy_write(priv, LANE3_HS_RX_CONTROL, priv->hsfreq << 1);
219 /* HS RX Data Lanes Settle State Time Control */
220 rk_dphy_write(priv, LANES_THS_SETTLE_CONTROL,
221 THS_SETTLE_COUNTER_THRESHOLD);
222
223 /* Normal operation */
224 rk_dphy_write(priv, 0x0, 0);
225}
226
227static int rk_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
228{
229 struct rk_dphy *priv = phy_get_drvdata(phy);
230 const struct rk_dphy_drv_data *drv_data = priv->drv_data;
231 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
232 unsigned int hsfreq = 0;
233 unsigned int i;
234 u64 data_rate_mbps;
235 int ret;
236
237 /* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */
238 ret = phy_mipi_dphy_config_validate(config);
239 if (ret)
240 return ret;
241
242 data_rate_mbps = div_u64(config->hs_clk_rate, 1000 * 1000);
243
244 dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
245 config->lanes, data_rate_mbps);
246 for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
247 if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
248 hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
249 break;
250 }
251 }
252 if (!hsfreq)
253 return -EINVAL;
254
255 priv->hsfreq = hsfreq;
256 priv->config = *config;
257 return 0;
258}
259
260static int rk_dphy_power_on(struct phy *phy)
261{
262 struct rk_dphy *priv = phy_get_drvdata(phy);
263 int ret;
264
265 ret = clk_bulk_enable(priv->drv_data->num_clks, priv->clks);
266 if (ret)
267 return ret;
268
269 rk_dphy_enable(priv);
270
271 return 0;
272}
273
274static int rk_dphy_power_off(struct phy *phy)
275{
276 struct rk_dphy *priv = phy_get_drvdata(phy);
277
278 rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, 0);
279 clk_bulk_disable(priv->drv_data->num_clks, priv->clks);
280 return 0;
281}
282
283static int rk_dphy_init(struct phy *phy)
284{
285 struct rk_dphy *priv = phy_get_drvdata(phy);
286
287 return clk_bulk_prepare(priv->drv_data->num_clks, priv->clks);
288}
289
290static int rk_dphy_exit(struct phy *phy)
291{
292 struct rk_dphy *priv = phy_get_drvdata(phy);
293
294 clk_bulk_unprepare(priv->drv_data->num_clks, priv->clks);
295 return 0;
296}
297
298static const struct phy_ops rk_dphy_ops = {
299 .power_on = rk_dphy_power_on,
300 .power_off = rk_dphy_power_off,
301 .init = rk_dphy_init,
302 .exit = rk_dphy_exit,
303 .configure = rk_dphy_configure,
304 .owner = THIS_MODULE,
305};
306
307static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = {
308 .clks = rk3399_mipidphy_clks,
309 .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
310 .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
311 .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
312 .regs = rk3399_grf_dphy_regs,
313};
314
315static const struct of_device_id rk_dphy_dt_ids[] = {
316 {
317 .compatible = "rockchip,rk3399-mipi-dphy-rx0",
318 .data = &rk3399_mipidphy_drv_data,
319 },
320 {}
321};
322MODULE_DEVICE_TABLE(of, rk_dphy_dt_ids);
323
324static int rk_dphy_probe(struct platform_device *pdev)
325{
326 struct device *dev = &pdev->dev;
327 struct device_node *np = dev->of_node;
328 const struct rk_dphy_drv_data *drv_data;
329 struct phy_provider *phy_provider;
330 const struct of_device_id *of_id;
331 struct rk_dphy *priv;
332 struct phy *phy;
333 unsigned int i;
334 int ret;
335
336 if (!dev->parent || !dev->parent->of_node)
337 return -ENODEV;
338
339 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
340 if (!priv)
341 return -ENOMEM;
342 priv->dev = dev;
343
344 priv->grf = syscon_node_to_regmap(dev->parent->of_node);
345 if (IS_ERR(priv->grf)) {
346 dev_err(dev, "Can't find GRF syscon\n");
347 return -ENODEV;
348 }
349
350 of_id = of_match_device(rk_dphy_dt_ids, dev);
351 if (!of_id)
352 return -EINVAL;
353
354 drv_data = of_id->data;
355 priv->drv_data = drv_data;
356 priv->clks = devm_kcalloc(&pdev->dev, drv_data->num_clks,
357 sizeof(*priv->clks), GFP_KERNEL);
358 if (!priv->clks)
359 return -ENOMEM;
360 for (i = 0; i < drv_data->num_clks; i++)
361 priv->clks[i].id = drv_data->clks[i];
362 ret = devm_clk_bulk_get(&pdev->dev, drv_data->num_clks, priv->clks);
363 if (ret)
364 return ret;
365
366 phy = devm_phy_create(dev, np, &rk_dphy_ops);
367 if (IS_ERR(phy)) {
368 dev_err(dev, "failed to create phy\n");
369 return PTR_ERR(phy);
370 }
371 phy_set_drvdata(phy, priv);
372
373 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
374
375 return PTR_ERR_OR_ZERO(phy_provider);
376}
377
378static struct platform_driver rk_dphy_driver = {
379 .probe = rk_dphy_probe,
380 .driver = {
381 .name = "rockchip-mipi-dphy-rx0",
382 .of_match_table = rk_dphy_dt_ids,
383 },
384};
385module_platform_driver(rk_dphy_driver);
386
387MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
388MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver");
389MODULE_LICENSE("Dual MIT/GPL");