phy-cadence-sierra.c - drivers/phy/cadence/phy-cadence-sierra.c - Linux diff v6.2

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Cadence Sierra PHY Driver
   4 *
   5 * Copyright (c) 2018 Cadence Design Systems
   6 * Author: Alan Douglas <adouglas@cadence.com>
   7 *
   8 */
   9#include <linux/clk.h>
  10#include <linux/clk-provider.h>
  11#include <linux/delay.h>
  12#include <linux/err.h>
  13#include <linux/io.h>
  14#include <linux/module.h>
  15#include <linux/phy/phy.h>
  16#include <linux/platform_device.h>
  17#include <linux/pm_runtime.h>
  18#include <linux/regmap.h>
  19#include <linux/reset.h>
  20#include <linux/slab.h>
  21#include <linux/of.h>
  22#include <linux/of_platform.h>
  23#include <dt-bindings/phy/phy.h>
  24#include <dt-bindings/phy/phy-cadence.h>
  25
  26#define NUM_SSC_MODE		3
  27#define NUM_PHY_TYPE		4
  28
  29/* PHY register offsets */
  30#define SIERRA_COMMON_CDB_OFFSET			0x0
  31#define SIERRA_MACRO_ID_REG				0x0
  32#define SIERRA_CMN_PLLLC_GEN_PREG			0x42
  33#define SIERRA_CMN_PLLLC_MODE_PREG			0x48
  34#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG		0x49
  35#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG		0x4A
  36#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG		0x4B
  37#define SIERRA_CMN_PLLLC_CLK1_PREG			0x4D
  38#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG		0x4F
  39#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG		0x50
  40#define SIERRA_CMN_PLLLC_DSMCORR_PREG			0x51
  41#define SIERRA_CMN_PLLLC_SS_PREG			0x52
  42#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG		0x53
  43#define SIERRA_CMN_PLLLC_SSTWOPT_PREG			0x54
  44#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG	0x62
  45#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG		0x63
  46#define SIERRA_CMN_REFRCV_PREG				0x98
  47#define SIERRA_CMN_REFRCV1_PREG				0xB8
  48#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC2
  49#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG		0xCA
  50#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG		0xD0
  51#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG	0xE2
  52
  53#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
  54				((0x4000 << (block_offset)) + \
  55				 (((ln) << 9) << (reg_offset)))
  56
  57#define SIERRA_DET_STANDEC_A_PREG			0x000
  58#define SIERRA_DET_STANDEC_B_PREG			0x001
  59#define SIERRA_DET_STANDEC_C_PREG			0x002
  60#define SIERRA_DET_STANDEC_D_PREG			0x003
  61#define SIERRA_DET_STANDEC_E_PREG			0x004
  62#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG		0x008
  63#define SIERRA_PSM_A0IN_TMR_PREG			0x009
  64#define SIERRA_PSM_A3IN_TMR_PREG			0x00C
  65#define SIERRA_PSM_DIAG_PREG				0x015
  66#define SIERRA_PSC_LN_A3_PREG				0x023
  67#define SIERRA_PSC_LN_A4_PREG				0x024
  68#define SIERRA_PSC_LN_IDLE_PREG				0x026
  69#define SIERRA_PSC_TX_A0_PREG				0x028
  70#define SIERRA_PSC_TX_A1_PREG				0x029
  71#define SIERRA_PSC_TX_A2_PREG				0x02A
  72#define SIERRA_PSC_TX_A3_PREG				0x02B
  73#define SIERRA_PSC_RX_A0_PREG				0x030
  74#define SIERRA_PSC_RX_A1_PREG				0x031
  75#define SIERRA_PSC_RX_A2_PREG				0x032
  76#define SIERRA_PSC_RX_A3_PREG				0x033
  77#define SIERRA_PLLCTRL_SUBRATE_PREG			0x03A
  78#define SIERRA_PLLCTRL_GEN_A_PREG			0x03B
  79#define SIERRA_PLLCTRL_GEN_D_PREG			0x03E
  80#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG			0x03F
  81#define SIERRA_PLLCTRL_STATUS_PREG			0x044
  82#define SIERRA_CLKPATH_BIASTRIM_PREG			0x04B
  83#define SIERRA_DFE_BIASTRIM_PREG			0x04C
  84#define SIERRA_DRVCTRL_ATTEN_PREG			0x06A
  85#define SIERRA_DRVCTRL_BOOST_PREG			0x06F
  86#define SIERRA_TX_RCVDET_OVRD_PREG			0x072
  87#define SIERRA_CLKPATHCTRL_TMR_PREG			0x081
  88#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG		0x085
  89#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG		0x086
  90#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG		0x087
  91#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG		0x088
  92#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG		0x08C
  93#define SIERRA_CREQ_CCLKDET_MODE01_PREG			0x08E
  94#define SIERRA_RX_CTLE_CAL_PREG				0x08F
  95#define SIERRA_RX_CTLE_MAINTENANCE_PREG			0x091
  96#define SIERRA_CREQ_FSMCLK_SEL_PREG			0x092
  97#define SIERRA_CREQ_EQ_CTRL_PREG			0x093
  98#define SIERRA_CREQ_SPARE_PREG				0x096
  99#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG		0x097
 100#define SIERRA_CTLELUT_CTRL_PREG			0x098
 101#define SIERRA_DFE_ECMP_RATESEL_PREG			0x0C0
 102#define SIERRA_DFE_SMP_RATESEL_PREG			0x0C1
 103#define SIERRA_DEQ_PHALIGN_CTRL				0x0C4
 104#define SIERRA_DEQ_CONCUR_CTRL1_PREG			0x0C8
 105#define SIERRA_DEQ_CONCUR_CTRL2_PREG			0x0C9
 106#define SIERRA_DEQ_EPIPWR_CTRL2_PREG			0x0CD
 107#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG		0x0CE
 108#define SIERRA_DEQ_ERRCMP_CTRL_PREG			0x0D0
 109#define SIERRA_DEQ_OFFSET_CTRL_PREG			0x0D8
 110#define SIERRA_DEQ_GAIN_CTRL_PREG			0x0E0
 111#define SIERRA_DEQ_VGATUNE_CTRL_PREG			0x0E1
 112#define SIERRA_DEQ_GLUT0				0x0E8
 113#define SIERRA_DEQ_GLUT1				0x0E9
 114#define SIERRA_DEQ_GLUT2				0x0EA
 115#define SIERRA_DEQ_GLUT3				0x0EB
 116#define SIERRA_DEQ_GLUT4				0x0EC
 117#define SIERRA_DEQ_GLUT5				0x0ED
 118#define SIERRA_DEQ_GLUT6				0x0EE
 119#define SIERRA_DEQ_GLUT7				0x0EF
 120#define SIERRA_DEQ_GLUT8				0x0F0
 121#define SIERRA_DEQ_GLUT9				0x0F1
 122#define SIERRA_DEQ_GLUT10				0x0F2
 123#define SIERRA_DEQ_GLUT11				0x0F3
 124#define SIERRA_DEQ_GLUT12				0x0F4
 125#define SIERRA_DEQ_GLUT13				0x0F5
 126#define SIERRA_DEQ_GLUT14				0x0F6
 127#define SIERRA_DEQ_GLUT15				0x0F7
 128#define SIERRA_DEQ_GLUT16				0x0F8
 129#define SIERRA_DEQ_ALUT0				0x108
 130#define SIERRA_DEQ_ALUT1				0x109
 131#define SIERRA_DEQ_ALUT2				0x10A
 132#define SIERRA_DEQ_ALUT3				0x10B
 133#define SIERRA_DEQ_ALUT4				0x10C
 134#define SIERRA_DEQ_ALUT5				0x10D
 135#define SIERRA_DEQ_ALUT6				0x10E
 136#define SIERRA_DEQ_ALUT7				0x10F
 137#define SIERRA_DEQ_ALUT8				0x110
 138#define SIERRA_DEQ_ALUT9				0x111
 139#define SIERRA_DEQ_ALUT10				0x112
 140#define SIERRA_DEQ_ALUT11				0x113
 141#define SIERRA_DEQ_ALUT12				0x114
 142#define SIERRA_DEQ_ALUT13				0x115
 143#define SIERRA_DEQ_DFETAP_CTRL_PREG			0x128
 144#define SIERRA_DEQ_DFETAP0				0x129
 145#define SIERRA_DEQ_DFETAP1				0x12B
 146#define SIERRA_DEQ_DFETAP2				0x12D
 147#define SIERRA_DEQ_DFETAP3				0x12F
 148#define SIERRA_DEQ_DFETAP4				0x131
 149#define SIERRA_DFE_EN_1010_IGNORE_PREG			0x134
 150#define SIERRA_DEQ_PRECUR_PREG				0x138
 151#define SIERRA_DEQ_POSTCUR_PREG				0x140
 152#define SIERRA_DEQ_POSTCUR_DECR_PREG			0x142
 153#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150
 154#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151
 155#define SIERRA_DEQ_TAU_CTRL3_PREG			0x152
 156#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x158
 157#define SIERRA_DEQ_PICTRL_PREG				0x161
 158#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170
 159#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171
 160#define SIERRA_CPICAL_PICNT_MODE1_PREG			0x174
 161#define SIERRA_CPI_OUTBUF_RATESEL_PREG			0x17C
 162#define SIERRA_CPI_RESBIAS_BIN_PREG			0x17E
 163#define SIERRA_CPI_TRIM_PREG				0x17F
 164#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG		0x183
 165#define SIERRA_EPI_CTRL_PREG				0x187
 166#define SIERRA_LFPSDET_SUPPORT_PREG			0x188
 167#define SIERRA_LFPSFILT_NS_PREG				0x18A
 168#define SIERRA_LFPSFILT_RD_PREG				0x18B
 169#define SIERRA_LFPSFILT_MP_PREG				0x18C
 170#define SIERRA_SIGDET_SUPPORT_PREG			0x190
 171#define SIERRA_SDFILT_H2L_A_PREG			0x191
 172#define SIERRA_SDFILT_L2H_PREG				0x193
 173#define SIERRA_RXBUFFER_CTLECTRL_PREG			0x19E
 174#define SIERRA_RXBUFFER_RCDFECTRL_PREG			0x19F
 175#define SIERRA_RXBUFFER_DFECTRL_PREG			0x1A0
 176#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG		0x14F
 177#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150
 178
 179/* PHY PCS common registers */
 180#define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset)	\
 181				     (0xc000 << (block_offset))
 182#define SIERRA_PHY_PIPE_CMN_CTRL1			0x0
 183#define SIERRA_PHY_PLL_CFG				0xe
 184
 185/* PHY PCS lane registers */
 186#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
 187				       ((0xD000 << (block_offset)) +	\
 188				       (((ln) << 8) << (reg_offset)))
 189
 190#define SIERRA_PHY_ISO_LINK_CTRL			0xB
 191
 192/* PHY PMA common registers */
 193#define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset)	\
 194				     (0xE000 << (block_offset))
 195#define SIERRA_PHY_PMA_CMN_CTRL				0x000
 196
 197/* PHY PMA lane registers */
 198#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
 199				       ((0xF000 << (block_offset)) +	\
 200				       (((ln) << 8) << (reg_offset)))
 201
 202#define SIERRA_PHY_PMA_XCVR_CTRL			0x000
 203
 204#define SIERRA_MACRO_ID					0x00007364
 205#define SIERRA_MAX_LANES				16
 206#define PLL_LOCK_TIME					100000
 207
 208#define CDNS_SIERRA_OUTPUT_CLOCKS			3
 209#define CDNS_SIERRA_INPUT_CLOCKS			5
 210enum cdns_sierra_clock_input {
 211	PHY_CLK,
 212	CMN_REFCLK_DIG_DIV,
 213	CMN_REFCLK1_DIG_DIV,
 214	PLL0_REFCLK,
 215	PLL1_REFCLK,
 216};
 217
 218#define SIERRA_NUM_CMN_PLLC				2
 219#define SIERRA_NUM_CMN_PLLC_PARENTS			2
 220
 221static const struct reg_field macro_id_type =
 222				REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 223static const struct reg_field phy_pll_cfg_1 =
 224				REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 225static const struct reg_field pma_cmn_ready =
 226				REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
 227static const struct reg_field pllctrl_lock =
 228				REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
 229static const struct reg_field phy_iso_link_ctrl_1 =
 230				REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
 231static const struct reg_field cmn_plllc_clk1outdiv_preg =
 232				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);
 233static const struct reg_field cmn_plllc_clk1_en_preg =
 234				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12);
 235
 236static const char * const clk_names[] = {
 237	[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
 238	[CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
 239	[CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der",
 240};
 241
 242enum cdns_sierra_cmn_plllc {
 243	CMN_PLLLC,
 244	CMN_PLLLC1,
 245};
 246
 247struct cdns_sierra_pll_mux_reg_fields {
 248	struct reg_field	pfdclk_sel_preg;
 249	struct reg_field	plllc1en_field;
 250	struct reg_field	termen_field;
 251};
 252
 253static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
 254	[CMN_PLLLC] = {
 255		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
 256		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
 257		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
 258	},
 259	[CMN_PLLLC1] = {
 260		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
 261		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
 262		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
 263	},
 264};
 265
 266struct cdns_sierra_pll_mux {
 267	struct clk_hw		hw;
 268	struct regmap_field	*pfdclk_sel_preg;
 269	struct regmap_field	*plllc1en_field;
 270	struct regmap_field	*termen_field;
 271	struct clk_init_data	clk_data;
 272};
 273
 274#define to_cdns_sierra_pll_mux(_hw)	\
 275			container_of(_hw, struct cdns_sierra_pll_mux, hw)
 276
 277static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
 278	[CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK },
 279	[CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },
 280};
 281
 282static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
 283	[CMN_PLLLC] = { 0, 1 },
 284	[CMN_PLLLC1] = { 1, 0 },
 285};
 286
 287struct cdns_sierra_derived_refclk {
 288	struct clk_hw           hw;
 289	struct regmap_field     *cmn_plllc_clk1outdiv_preg;
 290	struct regmap_field     *cmn_plllc_clk1_en_preg;
 291	struct clk_init_data	clk_data;
 292};
 293
 294#define to_cdns_sierra_derived_refclk(_hw)	\
 295			container_of(_hw, struct cdns_sierra_derived_refclk, hw)
 296
 297enum cdns_sierra_phy_type {
 298	TYPE_NONE,
 299	TYPE_PCIE,
 300	TYPE_USB,
 301	TYPE_QSGMII
 302};
 303
 304enum cdns_sierra_ssc_mode {
 305	NO_SSC,
 306	EXTERNAL_SSC,
 307	INTERNAL_SSC
 308};
 309
 310struct cdns_sierra_inst {
 311	struct phy *phy;
 312	enum cdns_sierra_phy_type phy_type;
 313	u32 num_lanes;
 314	u32 mlane;
 315	struct reset_control *lnk_rst;
 316	enum cdns_sierra_ssc_mode ssc_mode;
 317};
 318
 319struct cdns_reg_pairs {
 320	u16 val;
 321	u32 off;
 322};
 323
 324struct cdns_sierra_vals {
 325	const struct cdns_reg_pairs *reg_pairs;
 326	u32 num_regs;
 327};
 328
 329struct cdns_sierra_data {
 330	u32 id_value;
 331	u8 block_offset_shift;
 332	u8 reg_offset_shift;
 333	struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 334					     [NUM_SSC_MODE];
 335	struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 336						[NUM_SSC_MODE];
 337	struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 338					     [NUM_SSC_MODE];
 339	struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 340					    [NUM_SSC_MODE];
 341};
 342
 343struct cdns_regmap_cdb_context {
 344	struct device *dev;
 345	void __iomem *base;
 346	u8 reg_offset_shift;
 347};
 348
 349struct cdns_sierra_phy {
 350	struct device *dev;
 351	const struct cdns_sierra_data *init_data;
 
 352	struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
 353	struct reset_control *phy_rst;
 354	struct reset_control *apb_rst;
 355	struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 356	struct regmap *regmap_phy_pcs_common_cdb;
 357	struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
 358	struct regmap *regmap_phy_pma_common_cdb;
 359	struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
 360	struct regmap *regmap_common_cdb;
 361	struct regmap_field *macro_id_type;
 362	struct regmap_field *phy_pll_cfg_1;
 363	struct regmap_field *pma_cmn_ready;
 364	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
 365	struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
 366	struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
 367	struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
 368	struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
 369	struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
 370	int nsubnodes;
 371	u32 num_lanes;
 372	bool autoconf;
 373	int already_configured;
 374	struct clk_onecell_data clk_data;
 375	struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS];
 376};
 377
 378static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
 379{
 380	struct cdns_regmap_cdb_context *ctx = context;
 381	u32 offset = reg << ctx->reg_offset_shift;
 382
 383	writew(val, ctx->base + offset);
 384
 385	return 0;
 386}
 387
 388static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
 389{
 390	struct cdns_regmap_cdb_context *ctx = context;
 391	u32 offset = reg << ctx->reg_offset_shift;
 392
 393	*val = readw(ctx->base + offset);
 394	return 0;
 395}
 396
 397#define SIERRA_LANE_CDB_REGMAP_CONF(n) \
 398{ \
 399	.name = "sierra_lane" n "_cdb", \
 400	.reg_stride = 1, \
 401	.fast_io = true, \
 402	.reg_write = cdns_regmap_write, \
 403	.reg_read = cdns_regmap_read, \
 404}
 405
 406static const struct regmap_config cdns_sierra_lane_cdb_config[] = {
 407	SIERRA_LANE_CDB_REGMAP_CONF("0"),
 408	SIERRA_LANE_CDB_REGMAP_CONF("1"),
 409	SIERRA_LANE_CDB_REGMAP_CONF("2"),
 410	SIERRA_LANE_CDB_REGMAP_CONF("3"),
 411	SIERRA_LANE_CDB_REGMAP_CONF("4"),
 412	SIERRA_LANE_CDB_REGMAP_CONF("5"),
 413	SIERRA_LANE_CDB_REGMAP_CONF("6"),
 414	SIERRA_LANE_CDB_REGMAP_CONF("7"),
 415	SIERRA_LANE_CDB_REGMAP_CONF("8"),
 416	SIERRA_LANE_CDB_REGMAP_CONF("9"),
 417	SIERRA_LANE_CDB_REGMAP_CONF("10"),
 418	SIERRA_LANE_CDB_REGMAP_CONF("11"),
 419	SIERRA_LANE_CDB_REGMAP_CONF("12"),
 420	SIERRA_LANE_CDB_REGMAP_CONF("13"),
 421	SIERRA_LANE_CDB_REGMAP_CONF("14"),
 422	SIERRA_LANE_CDB_REGMAP_CONF("15"),
 423};
 424
 425static const struct regmap_config cdns_sierra_common_cdb_config = {
 426	.name = "sierra_common_cdb",
 427	.reg_stride = 1,
 428	.fast_io = true,
 429	.reg_write = cdns_regmap_write,
 430	.reg_read = cdns_regmap_read,
 431};
 432
 433static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = {
 434	.name = "sierra_phy_pcs_cmn_cdb",
 435	.reg_stride = 1,
 436	.fast_io = true,
 437	.reg_write = cdns_regmap_write,
 438	.reg_read = cdns_regmap_read,
 439};
 440
 441#define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
 442{ \
 443	.name = "sierra_phy_pcs_lane" n "_cdb", \
 444	.reg_stride = 1, \
 445	.fast_io = true, \
 446	.reg_write = cdns_regmap_write, \
 447	.reg_read = cdns_regmap_read, \
 448}
 449
 450static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = {
 451	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
 452	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
 453	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
 454	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
 455	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"),
 456	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"),
 457	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"),
 458	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"),
 459	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"),
 460	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"),
 461	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"),
 462	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"),
 463	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"),
 464	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"),
 465	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"),
 466	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"),
 467};
 468
 469static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = {
 470	.name = "sierra_phy_pma_cmn_cdb",
 471	.reg_stride = 1,
 472	.fast_io = true,
 473	.reg_write = cdns_regmap_write,
 474	.reg_read = cdns_regmap_read,
 475};
 476
 477#define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \
 478{ \
 479	.name = "sierra_phy_pma_lane" n "_cdb", \
 480	.reg_stride = 1, \
 481	.fast_io = true, \
 482	.reg_write = cdns_regmap_write, \
 483	.reg_read = cdns_regmap_read, \
 484}
 485
 486static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = {
 487	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"),
 488	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"),
 489	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"),
 490	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"),
 491	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"),
 492	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"),
 493	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"),
 494	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"),
 495	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"),
 496	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"),
 497	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"),
 498	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"),
 499	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"),
 500	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"),
 501	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"),
 502	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"),
 503};
 504
 505static int cdns_sierra_phy_init(struct phy *gphy)
 506{
 507	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 508	struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
 509	const struct cdns_sierra_data *init_data = phy->init_data;
 510	struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
 511	enum cdns_sierra_phy_type phy_type = ins->phy_type;
 512	enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
 513	struct cdns_sierra_vals *phy_pma_ln_vals;
 514	const struct cdns_reg_pairs *reg_pairs;
 515	struct cdns_sierra_vals *pcs_cmn_vals;
 516	struct regmap *regmap;
 517	u32 num_regs;
 518	int i, j;
 
 
 519
 520	/* Initialise the PHY registers, unless auto configured */
 521	if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)
 522		return 0;
 523
 524	clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
 525	clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
 526
 527	/* PHY PCS common registers configurations */
 528	pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
 529	if (pcs_cmn_vals) {
 530		reg_pairs = pcs_cmn_vals->reg_pairs;
 531		num_regs = pcs_cmn_vals->num_regs;
 532		regmap = phy->regmap_phy_pcs_common_cdb;
 533		for (i = 0; i < num_regs; i++)
 534			regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
 535	}
 536
 537	/* PHY PMA lane registers configurations */
 538	phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
 539	if (phy_pma_ln_vals) {
 540		reg_pairs = phy_pma_ln_vals->reg_pairs;
 541		num_regs = phy_pma_ln_vals->num_regs;
 542		for (i = 0; i < ins->num_lanes; i++) {
 543			regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
 544			for (j = 0; j < num_regs; j++)
 545				regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
 546		}
 547	}
 548
 549	/* PMA common registers configurations */
 550	pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
 551	if (pma_cmn_vals) {
 552		reg_pairs = pma_cmn_vals->reg_pairs;
 553		num_regs = pma_cmn_vals->num_regs;
 554		regmap = phy->regmap_common_cdb;
 555		for (i = 0; i < num_regs; i++)
 556			regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
 557	}
 558
 559	/* PMA lane registers configurations */
 560	pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
 561	if (pma_ln_vals) {
 562		reg_pairs = pma_ln_vals->reg_pairs;
 563		num_regs = pma_ln_vals->num_regs;
 564		for (i = 0; i < ins->num_lanes; i++) {
 565			regmap = phy->regmap_lane_cdb[i + ins->mlane];
 566			for (j = 0; j < num_regs; j++)
 567				regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
 568		}
 569	}
 570
 571	return 0;
 572}
 573
 574static int cdns_sierra_phy_on(struct phy *gphy)
 575{
 576	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
 577	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 578	struct device *dev = sp->dev;
 579	u32 val;
 580	int ret;
 581
 582	if (sp->nsubnodes == 1) {
 583		/* Take the PHY out of reset */
 584		ret = reset_control_deassert(sp->phy_rst);
 585		if (ret) {
 586			dev_err(dev, "Failed to take the PHY out of reset\n");
 587			return ret;
 588		}
 589	}
 590
 591	/* Take the PHY lane group out of reset */
 592	ret = reset_control_deassert(ins->lnk_rst);
 593	if (ret) {
 594		dev_err(dev, "Failed to take the PHY lane out of reset\n");
 595		return ret;
 596	}
 597
 598	if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
 599		ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
 600						     val, !val, 1000, PLL_LOCK_TIME);
 601		if (ret) {
 602			dev_err(dev, "Timeout waiting for PHY status ready\n");
 603			return ret;
 604		}
 605	}
 606
 607	/*
 608	 * Wait for cmn_ready assertion
 609	 * PHY_PMA_CMN_CTRL[0] == 1
 610	 */
 611	ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
 612					     1000, PLL_LOCK_TIME);
 613	if (ret) {
 614		dev_err(dev, "Timeout waiting for CMN ready\n");
 615		return ret;
 616	}
 617
 618	ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
 619					     val, val, 1000, PLL_LOCK_TIME);
 620	if (ret < 0)
 621		dev_err(dev, "PLL lock of lane failed\n");
 622
 623	return ret;
 624}
 625
 626static int cdns_sierra_phy_off(struct phy *gphy)
 627{
 628	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 629
 630	return reset_control_assert(ins->lnk_rst);
 631}
 632
 633static int cdns_sierra_phy_reset(struct phy *gphy)
 634{
 635	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
 636
 637	reset_control_assert(sp->phy_rst);
 638	reset_control_deassert(sp->phy_rst);
 639	return 0;
 640};
 641
 642static const struct phy_ops ops = {
 643	.init		= cdns_sierra_phy_init,
 644	.power_on	= cdns_sierra_phy_on,
 645	.power_off	= cdns_sierra_phy_off,
 646	.reset		= cdns_sierra_phy_reset,
 647	.owner		= THIS_MODULE,
 648};
 649
 650static int cdns_sierra_noop_phy_on(struct phy *gphy)
 651{
 652	usleep_range(5000, 10000);
 653
 654	return 0;
 655}
 656
 657static const struct phy_ops noop_ops = {
 658	.power_on	= cdns_sierra_noop_phy_on,
 659	.owner		= THIS_MODULE,
 660};
 661
 662static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
 663{
 664	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
 665	struct regmap_field *plllc1en_field = mux->plllc1en_field;
 666	struct regmap_field *termen_field = mux->termen_field;
 667	struct regmap_field *field = mux->pfdclk_sel_preg;
 668	unsigned int val;
 669	int index;
 670
 671	regmap_field_read(field, &val);
 672
 673	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {
 674		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
 675		if (index == 1) {
 676			regmap_field_write(plllc1en_field, 1);
 677			regmap_field_write(termen_field, 1);
 678		}
 679	} else {
 680		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
 681	}
 682
 683	return index;
 684}
 685
 686static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
 687{
 688	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
 689	struct regmap_field *plllc1en_field = mux->plllc1en_field;
 690	struct regmap_field *termen_field = mux->termen_field;
 691	struct regmap_field *field = mux->pfdclk_sel_preg;
 692	int val, ret;
 693
 694	ret = regmap_field_write(plllc1en_field, 0);
 695	ret |= regmap_field_write(termen_field, 0);
 696	if (index == 1) {
 697		ret |= regmap_field_write(plllc1en_field, 1);
 698		ret |= regmap_field_write(termen_field, 1);
 699	}
 700
 701	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
 702		val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index];
 703	else
 704		val = cdns_sierra_pll_mux_table[CMN_PLLLC][index];
 705
 706	ret |= regmap_field_write(field, val);
 707
 708	return ret;
 709}
 710
 711static const struct clk_ops cdns_sierra_pll_mux_ops = {
 712	.set_parent = cdns_sierra_pll_mux_set_parent,
 713	.get_parent = cdns_sierra_pll_mux_get_parent,
 714};
 715
 716static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,
 717					struct regmap_field *pfdclk1_sel_field,
 718					struct regmap_field *plllc1en_field,
 719					struct regmap_field *termen_field,
 720					int clk_index)
 721{
 722	struct cdns_sierra_pll_mux *mux;
 723	struct device *dev = sp->dev;
 724	struct clk_init_data *init;
 725	const char **parent_names;
 726	unsigned int num_parents;
 727	char clk_name[100];
 728	struct clk *clk;
 729	int i;
 730
 731	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 732	if (!mux)
 733		return -ENOMEM;
 734
 735	num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
 736	parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
 737	if (!parent_names)
 738		return -ENOMEM;
 739
 740	for (i = 0; i < num_parents; i++) {
 741		clk = sp->input_clks[pll_mux_parent_index[clk_index][i]];
 742		if (IS_ERR_OR_NULL(clk)) {
 743			dev_err(dev, "No parent clock for PLL mux clocks\n");
 744			return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
 745		}
 746		parent_names[i] = __clk_get_name(clk);
 747	}
 748
 749	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);
 750
 751	init = &mux->clk_data;
 752
 753	init->ops = &cdns_sierra_pll_mux_ops;
 754	init->flags = CLK_SET_RATE_NO_REPARENT;
 755	init->parent_names = parent_names;
 756	init->num_parents = num_parents;
 757	init->name = clk_name;
 758
 759	mux->pfdclk_sel_preg = pfdclk1_sel_field;
 760	mux->plllc1en_field = plllc1en_field;
 761	mux->termen_field = termen_field;
 762	mux->hw.init = init;
 763
 764	clk = devm_clk_register(dev, &mux->hw);
 765	if (IS_ERR(clk))
 766		return PTR_ERR(clk);
 767
 768	sp->output_clks[clk_index] = clk;
 769
 770	return 0;
 771}
 772
 773static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp)
 774{
 775	struct regmap_field *pfdclk1_sel_field;
 776	struct regmap_field *plllc1en_field;
 777	struct regmap_field *termen_field;
 778	struct device *dev = sp->dev;
 779	int ret = 0, i, clk_index;
 780
 781	clk_index = CDNS_SIERRA_PLL_CMNLC;
 782	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) {
 783		pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i];
 784		plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i];
 785		termen_field = sp->cmn_refrcv_refclk_termen_preg[i];
 786
 787		ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field,
 788						   termen_field, clk_index);
 789		if (ret) {
 790			dev_err(dev, "Fail to register cmn plllc mux\n");
 791			return ret;
 792		}
 793	}
 794
 795	return 0;
 796}
 797
 798static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw)
 799{
 800	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
 801
 802	regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1);
 803
 804	/* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */
 805	regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E);
 806
 807	return 0;
 808}
 809
 810static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw)
 811{
 812	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
 813
 814	regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0);
 815}
 816
 817static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw)
 818{
 819	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
 820	int val;
 821
 822	regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val);
 823
 824	return !!val;
 825}
 826
 827static const struct clk_ops cdns_sierra_derived_refclk_ops = {
 828	.enable = cdns_sierra_derived_refclk_enable,
 829	.disable = cdns_sierra_derived_refclk_disable,
 830	.is_enabled = cdns_sierra_derived_refclk_is_enabled,
 831};
 832
 833static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp)
 834{
 835	struct cdns_sierra_derived_refclk *derived_refclk;
 836	struct device *dev = sp->dev;
 837	struct regmap_field *field;
 838	struct clk_init_data *init;
 839	struct regmap *regmap;
 840	char clk_name[100];
 841	struct clk *clk;
 842
 843	derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
 844	if (!derived_refclk)
 845		return -ENOMEM;
 846
 847	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 848		 clk_names[CDNS_SIERRA_DERIVED_REFCLK]);
 849
 850	init = &derived_refclk->clk_data;
 851
 852	init->ops = &cdns_sierra_derived_refclk_ops;
 853	init->flags = 0;
 854	init->name = clk_name;
 855
 856	regmap = sp->regmap_common_cdb;
 857
 858	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg);
 859	if (IS_ERR(field)) {
 860		dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n");
 861		return PTR_ERR(field);
 862	}
 863	derived_refclk->cmn_plllc_clk1outdiv_preg = field;
 864
 865	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg);
 866	if (IS_ERR(field)) {
 867		dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n");
 868		return PTR_ERR(field);
 869	}
 870	derived_refclk->cmn_plllc_clk1_en_preg = field;
 871
 872	derived_refclk->hw.init = init;
 873
 874	clk = devm_clk_register(dev, &derived_refclk->hw);
 875	if (IS_ERR(clk))
 876		return PTR_ERR(clk);
 877
 878	sp->output_clks[CDNS_SIERRA_DERIVED_REFCLK] = clk;
 879
 880	return 0;
 881}
 882
 883static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp)
 884{
 885	struct device *dev = sp->dev;
 886	struct device_node *node = dev->of_node;
 887
 888	of_clk_del_provider(node);
 889}
 890
 891static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp)
 892{
 893	struct device *dev = sp->dev;
 894	struct device_node *node = dev->of_node;
 895	int ret;
 896
 897	ret = cdns_sierra_phy_register_pll_mux(sp);
 898	if (ret) {
 899		dev_err(dev, "Failed to pll mux clocks\n");
 900		return ret;
 901	}
 902
 903	ret = cdns_sierra_derived_refclk_register(sp);
 904	if (ret) {
 905		dev_err(dev, "Failed to register derived refclk\n");
 906		return ret;
 907	}
 908
 909	sp->clk_data.clks = sp->output_clks;
 910	sp->clk_data.clk_num = CDNS_SIERRA_OUTPUT_CLOCKS;
 911	ret = of_clk_add_provider(node, of_clk_src_onecell_get, &sp->clk_data);
 912	if (ret)
 913		dev_err(dev, "Failed to add clock provider: %s\n", node->name);
 914
 915	return ret;
 916}
 917
 918static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
 919				    struct device_node *child)
 920{
 921	u32 phy_type;
 922
 923	if (of_property_read_u32(child, "reg", &inst->mlane))
 924		return -EINVAL;
 925
 926	if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
 927		return -EINVAL;
 928
 929	if (of_property_read_u32(child, "cdns,phy-type", &phy_type))
 930		return -EINVAL;
 931
 932	switch (phy_type) {
 933	case PHY_TYPE_PCIE:
 934		inst->phy_type = TYPE_PCIE;
 935		break;
 936	case PHY_TYPE_USB3:
 937		inst->phy_type = TYPE_USB;
 938		break;
 939	case PHY_TYPE_QSGMII:
 940		inst->phy_type = TYPE_QSGMII;
 941		break;
 942	default:
 943		return -EINVAL;
 944	}
 945
 946	inst->ssc_mode = EXTERNAL_SSC;
 947	of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
 948
 949	return 0;
 950}
 951
 
 
 952static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
 953				       u32 block_offset, u8 reg_offset_shift,
 954				       const struct regmap_config *config)
 955{
 956	struct cdns_regmap_cdb_context *ctx;
 957
 958	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 959	if (!ctx)
 960		return ERR_PTR(-ENOMEM);
 961
 962	ctx->dev = dev;
 963	ctx->base = base + block_offset;
 964	ctx->reg_offset_shift = reg_offset_shift;
 965
 966	return devm_regmap_init(dev, NULL, ctx, config);
 967}
 968
 969static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 970{
 971	struct device *dev = sp->dev;
 972	struct regmap_field *field;
 973	struct reg_field reg_field;
 974	struct regmap *regmap;
 975	int i;
 976
 977	regmap = sp->regmap_common_cdb;
 978	field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
 979	if (IS_ERR(field)) {
 980		dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
 981		return PTR_ERR(field);
 982	}
 983	sp->macro_id_type = field;
 984
 985	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
 986		reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
 987		field = devm_regmap_field_alloc(dev, regmap, reg_field);
 988		if (IS_ERR(field)) {
 989			dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
 990			return PTR_ERR(field);
 991		}
 992		sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
 993
 994		reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
 995		field = devm_regmap_field_alloc(dev, regmap, reg_field);
 996		if (IS_ERR(field)) {
 997			dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
 998			return PTR_ERR(field);
 999		}
1000		sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
1001
1002		reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
1003		field = devm_regmap_field_alloc(dev, regmap, reg_field);
1004		if (IS_ERR(field)) {
1005			dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
1006			return PTR_ERR(field);
1007		}
1008		sp->cmn_refrcv_refclk_termen_preg[i] = field;
1009	}
1010
1011	regmap = sp->regmap_phy_pcs_common_cdb;
1012	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
1013	if (IS_ERR(field)) {
1014		dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
1015		return PTR_ERR(field);
1016	}
1017	sp->phy_pll_cfg_1 = field;
1018
1019	regmap = sp->regmap_phy_pma_common_cdb;
1020	field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
1021	if (IS_ERR(field)) {
1022		dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
1023		return PTR_ERR(field);
1024	}
1025	sp->pma_cmn_ready = field;
1026
1027	for (i = 0; i < SIERRA_MAX_LANES; i++) {
1028		regmap = sp->regmap_lane_cdb[i];
1029		field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
1030		if (IS_ERR(field)) {
1031			dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
1032			return PTR_ERR(field);
1033		}
1034		sp->pllctrl_lock[i] = field;
1035	}
1036
1037	for (i = 0; i < SIERRA_MAX_LANES; i++) {
1038		regmap = sp->regmap_phy_pcs_lane_cdb[i];
1039		field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);
1040		if (IS_ERR(field)) {
1041			dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
1042			return PTR_ERR(field);
1043		}
1044		sp->phy_iso_link_ctrl_1[i] = field;
1045	}
1046
1047	return 0;
1048}
1049
1050static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
1051				   void __iomem *base, u8 block_offset_shift,
1052				   u8 reg_offset_shift)
1053{
1054	struct device *dev = sp->dev;
1055	struct regmap *regmap;
1056	u32 block_offset;
1057	int i;
1058
1059	for (i = 0; i < SIERRA_MAX_LANES; i++) {
1060		block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
1061						      reg_offset_shift);
1062		regmap = cdns_regmap_init(dev, base, block_offset,
1063					  reg_offset_shift,
1064					  &cdns_sierra_lane_cdb_config[i]);
1065		if (IS_ERR(regmap)) {
1066			dev_err(dev, "Failed to init lane CDB regmap\n");
1067			return PTR_ERR(regmap);
1068		}
1069		sp->regmap_lane_cdb[i] = regmap;
1070	}
1071
1072	regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
1073				  reg_offset_shift,
1074				  &cdns_sierra_common_cdb_config);
1075	if (IS_ERR(regmap)) {
1076		dev_err(dev, "Failed to init common CDB regmap\n");
1077		return PTR_ERR(regmap);
1078	}
1079	sp->regmap_common_cdb = regmap;
1080
1081	block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift);
1082	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
1083				  &cdns_sierra_phy_pcs_cmn_cdb_config);
1084	if (IS_ERR(regmap)) {
1085		dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1086		return PTR_ERR(regmap);
1087	}
1088	sp->regmap_phy_pcs_common_cdb = regmap;
1089
1090	for (i = 0; i < SIERRA_MAX_LANES; i++) {
1091		block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
1092							      reg_offset_shift);
1093		regmap = cdns_regmap_init(dev, base, block_offset,
1094					  reg_offset_shift,
1095					  &cdns_sierra_phy_pcs_lane_cdb_config[i]);
1096		if (IS_ERR(regmap)) {
1097			dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
1098			return PTR_ERR(regmap);
1099		}
1100		sp->regmap_phy_pcs_lane_cdb[i] = regmap;
1101	}
1102
1103	block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift);
1104	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
1105				  &cdns_sierra_phy_pma_cmn_cdb_config);
1106	if (IS_ERR(regmap)) {
1107		dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1108		return PTR_ERR(regmap);
1109	}
1110	sp->regmap_phy_pma_common_cdb = regmap;
1111
1112	for (i = 0; i < SIERRA_MAX_LANES; i++) {
1113		block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift,
1114							      reg_offset_shift);
1115		regmap = cdns_regmap_init(dev, base, block_offset,
1116					  reg_offset_shift,
1117					  &cdns_sierra_phy_pma_lane_cdb_config[i]);
1118		if (IS_ERR(regmap)) {
1119			dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
1120			return PTR_ERR(regmap);
1121		}
1122		sp->regmap_phy_pma_lane_cdb[i] = regmap;
1123	}
1124
1125	return 0;
1126}
1127
1128static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
1129				      struct device *dev)
1130{
1131	struct clk *clk;
1132	int ret;
1133
 
 
 
 
 
 
 
1134	clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
1135	if (IS_ERR(clk)) {
1136		dev_err(dev, "cmn_refclk_dig_div clock not found\n");
1137		ret = PTR_ERR(clk);
1138		return ret;
1139	}
1140	sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
1141
1142	clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
1143	if (IS_ERR(clk)) {
1144		dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
1145		ret = PTR_ERR(clk);
1146		return ret;
1147	}
1148	sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
1149
1150	clk = devm_clk_get_optional(dev, "pll0_refclk");
1151	if (IS_ERR(clk)) {
1152		dev_err(dev, "pll0_refclk clock not found\n");
1153		ret = PTR_ERR(clk);
1154		return ret;
1155	}
1156	sp->input_clks[PLL0_REFCLK] = clk;
1157
1158	clk = devm_clk_get_optional(dev, "pll1_refclk");
1159	if (IS_ERR(clk)) {
1160		dev_err(dev, "pll1_refclk clock not found\n");
1161		ret = PTR_ERR(clk);
1162		return ret;
1163	}
1164	sp->input_clks[PLL1_REFCLK] = clk;
1165
1166	return 0;
1167}
1168
1169static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)
1170{
1171	struct device *dev = sp->dev;
1172	struct clk *clk;
1173	int ret;
1174
1175	clk = devm_clk_get_optional(dev, "phy_clk");
1176	if (IS_ERR(clk)) {
1177		dev_err(dev, "failed to get clock phy_clk\n");
1178		return PTR_ERR(clk);
1179	}
1180	sp->input_clks[PHY_CLK] = clk;
1181
1182	ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
1183	if (ret)
1184		return ret;
1185
1186	return 0;
1187}
1188
1189static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
1190{
1191	int ret;
1192
1193	ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1194	if (ret)
1195		return ret;
1196
1197	ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
1198	if (ret)
1199		goto err_pll_cmnlc1;
1200
1201	return 0;
1202
1203err_pll_cmnlc1:
1204	clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1205
 
 
 
1206	return ret;
1207}
1208
1209static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
1210{
1211	clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
1212	clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1213	if (!sp->already_configured)
1214		clk_disable_unprepare(sp->input_clks[PHY_CLK]);
1215}
1216
1217static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
1218				      struct device *dev)
1219{
1220	struct reset_control *rst;
1221
1222	rst = devm_reset_control_get_exclusive(dev, "sierra_reset");
1223	if (IS_ERR(rst)) {
1224		dev_err(dev, "failed to get reset\n");
1225		return PTR_ERR(rst);
1226	}
1227	sp->phy_rst = rst;
1228
1229	rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
1230	if (IS_ERR(rst)) {
1231		dev_err(dev, "failed to get apb reset\n");
1232		return PTR_ERR(rst);
1233	}
1234	sp->apb_rst = rst;
1235
1236	return 0;
1237}
1238
1239static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
1240{
1241	const struct cdns_sierra_data *init_data = sp->init_data;
1242	struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
1243	enum cdns_sierra_phy_type phy_t1, phy_t2;
1244	struct cdns_sierra_vals *phy_pma_ln_vals;
1245	const struct cdns_reg_pairs *reg_pairs;
1246	struct cdns_sierra_vals *pcs_cmn_vals;
1247	int i, j, node, mlane, num_lanes, ret;
1248	enum cdns_sierra_ssc_mode ssc;
1249	struct regmap *regmap;
1250	u32 num_regs;
1251
1252	/* Maximum 2 links (subnodes) are supported */
1253	if (sp->nsubnodes != 2)
1254		return -EINVAL;
1255
1256	clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
1257	clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
1258
1259	/* PHY configured to use both PLL LC and LC1 */
1260	regmap_field_write(sp->phy_pll_cfg_1, 0x1);
1261
1262	phy_t1 = sp->phys[0].phy_type;
1263	phy_t2 = sp->phys[1].phy_type;
1264
1265	/*
1266	 * PHY configuration for multi-link operation is done in two steps.
1267	 * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes.
1268	 * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe
1269	 * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below.
1270	 *
1271	 * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII
1272	 *     So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc].
1273	 *     This will configure PHY registers associated for PCIe (i.e. first protocol)
1274	 *     involving PLLLC registers and registers for first 2 lanes of PHY.
1275	 * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now,
1276	 *     phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as
1277	 *     [TYPE_QSGMII][TYPE_PCIE][ssc].
1278	 *     This will configure PHY registers associated for QSGMII (i.e. second protocol)
1279	 *     involving PLLLC1 registers and registers for other 2 lanes of PHY.
1280	 *
1281	 * This completes the PHY configuration for multilink operation. This approach enables
1282	 * dividing the large number of PHY register configurations into protocol specific
1283	 * smaller groups.
1284	 */
1285	for (node = 0; node < sp->nsubnodes; node++) {
1286		if (node == 1) {
1287			/*
1288			 * If first link with phy_t1 is configured, then configure the PHY for
1289			 * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc].
1290			 */
1291			swap(phy_t1, phy_t2);
1292		}
1293
1294		mlane = sp->phys[node].mlane;
1295		ssc = sp->phys[node].ssc_mode;
1296		num_lanes = sp->phys[node].num_lanes;
1297
1298		/* PHY PCS common registers configurations */
1299		pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
1300		if (pcs_cmn_vals) {
1301			reg_pairs = pcs_cmn_vals->reg_pairs;
1302			num_regs = pcs_cmn_vals->num_regs;
1303			regmap = sp->regmap_phy_pcs_common_cdb;
1304			for (i = 0; i < num_regs; i++)
1305				regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
1306		}
1307
1308		/* PHY PMA lane registers configurations */
1309		phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];
1310		if (phy_pma_ln_vals) {
1311			reg_pairs = phy_pma_ln_vals->reg_pairs;
1312			num_regs = phy_pma_ln_vals->num_regs;
1313			for (i = 0; i < num_lanes; i++) {
1314				regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];
1315				for (j = 0; j < num_regs; j++)
1316					regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
1317			}
1318		}
1319
1320		/* PMA common registers configurations */
1321		pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];
1322		if (pma_cmn_vals) {
1323			reg_pairs = pma_cmn_vals->reg_pairs;
1324			num_regs = pma_cmn_vals->num_regs;
1325			regmap = sp->regmap_common_cdb;
1326			for (i = 0; i < num_regs; i++)
1327				regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
1328		}
1329
1330		/* PMA lane registers configurations */
1331		pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];
1332		if (pma_ln_vals) {
1333			reg_pairs = pma_ln_vals->reg_pairs;
1334			num_regs = pma_ln_vals->num_regs;
1335			for (i = 0; i < num_lanes; i++) {
1336				regmap = sp->regmap_lane_cdb[i + mlane];
1337				for (j = 0; j < num_regs; j++)
1338					regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
1339			}
1340		}
1341
1342		if (phy_t1 == TYPE_QSGMII)
1343			reset_control_deassert(sp->phys[node].lnk_rst);
1344	}
1345
1346	/* Take the PHY out of reset */
1347	ret = reset_control_deassert(sp->phy_rst);
1348	if (ret)
1349		return ret;
1350
1351	return 0;
1352}
1353
1354static int cdns_sierra_phy_probe(struct platform_device *pdev)
1355{
1356	struct cdns_sierra_phy *sp;
1357	struct phy_provider *phy_provider;
1358	struct device *dev = &pdev->dev;
1359	const struct cdns_sierra_data *data;
 
1360	unsigned int id_value;
1361	int ret, node = 0;
1362	void __iomem *base;
1363	struct device_node *dn = dev->of_node, *child;
1364
1365	if (of_get_child_count(dn) == 0)
1366		return -ENODEV;
1367
1368	/* Get init data for this PHY */
1369	data = of_device_get_match_data(dev);
1370	if (!data)
1371		return -EINVAL;
1372
 
 
1373	sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
1374	if (!sp)
1375		return -ENOMEM;
1376	dev_set_drvdata(dev, sp);
1377	sp->dev = dev;
1378	sp->init_data = data;
1379
1380	base = devm_platform_ioremap_resource(pdev, 0);
1381	if (IS_ERR(base)) {
1382		dev_err(dev, "missing \"reg\"\n");
1383		return PTR_ERR(base);
1384	}
1385
1386	ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
1387				      data->reg_offset_shift);
1388	if (ret)
1389		return ret;
1390
1391	ret = cdns_regfield_init(sp);
1392	if (ret)
1393		return ret;
1394
1395	platform_set_drvdata(pdev, sp);
1396
1397	ret = cdns_sierra_phy_get_clocks(sp, dev);
1398	if (ret)
1399		return ret;
1400
1401	ret = cdns_sierra_clk_register(sp);
1402	if (ret)
1403		return ret;
1404
1405	ret = cdns_sierra_phy_enable_clocks(sp);
1406	if (ret)
1407		goto unregister_clk;
1408
1409	regmap_field_read(sp->pma_cmn_ready, &sp->already_configured);
 
 
1410
1411	if (!sp->already_configured) {
1412		ret = cdns_sierra_phy_clk(sp);
1413		if (ret)
1414			goto clk_disable;
1415
1416		ret = cdns_sierra_phy_get_resets(sp, dev);
1417		if (ret)
1418			goto clk_disable;
1419
1420		/* Enable APB */
1421		reset_control_deassert(sp->apb_rst);
1422	}
1423
1424	/* Check that PHY is present */
1425	regmap_field_read(sp->macro_id_type, &id_value);
1426	if  (sp->init_data->id_value != id_value) {
1427		ret = -EINVAL;
1428		goto ctrl_assert;
1429	}
1430
1431	sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");
1432
1433	for_each_available_child_of_node(dn, child) {
1434		struct phy *gphy;
1435
1436		if (!(of_node_name_eq(child, "phy") ||
1437		      of_node_name_eq(child, "link")))
1438			continue;
1439
1440		sp->phys[node].lnk_rst =
1441			of_reset_control_array_get_exclusive(child);
1442
1443		if (IS_ERR(sp->phys[node].lnk_rst)) {
1444			dev_err(dev, "failed to get reset %s\n",
1445				child->full_name);
1446			ret = PTR_ERR(sp->phys[node].lnk_rst);
1447			of_node_put(child);
1448			goto put_control;
1449		}
1450
1451		if (!sp->autoconf) {
1452			ret = cdns_sierra_get_optional(&sp->phys[node], child);
1453			if (ret) {
1454				dev_err(dev, "missing property in node %s\n",
1455					child->name);
1456				of_node_put(child);
1457				reset_control_put(sp->phys[node].lnk_rst);
1458				goto put_control;
1459			}
1460		}
1461
1462		sp->num_lanes += sp->phys[node].num_lanes;
1463
1464		if (!sp->already_configured)
1465			gphy = devm_phy_create(dev, child, &ops);
1466		else
1467			gphy = devm_phy_create(dev, child, &noop_ops);
1468		if (IS_ERR(gphy)) {
1469			ret = PTR_ERR(gphy);
1470			of_node_put(child);
1471			reset_control_put(sp->phys[node].lnk_rst);
1472			goto put_control;
1473		}
1474		sp->phys[node].phy = gphy;
1475		phy_set_drvdata(gphy, &sp->phys[node]);
1476
1477		node++;
1478	}
1479	sp->nsubnodes = node;
1480
1481	if (sp->num_lanes > SIERRA_MAX_LANES) {
1482		ret = -EINVAL;
1483		dev_err(dev, "Invalid lane configuration\n");
1484		goto put_control;
1485	}
1486
1487	/* If more than one subnode, configure the PHY as multilink */
1488	if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) {
1489		ret = cdns_sierra_phy_configure_multilink(sp);
1490		if (ret)
1491			goto put_control;
1492	}
1493
1494	pm_runtime_enable(dev);
1495	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1496	if (IS_ERR(phy_provider)) {
1497		ret = PTR_ERR(phy_provider);
1498		goto put_control;
1499	}
1500
1501	return 0;
1502
1503put_control:
1504	while (--node >= 0)
1505		reset_control_put(sp->phys[node].lnk_rst);
1506ctrl_assert:
1507	if (!sp->already_configured)
1508		reset_control_assert(sp->apb_rst);
1509clk_disable:
1510	cdns_sierra_phy_disable_clocks(sp);
 
1511unregister_clk:
1512	cdns_sierra_clk_unregister(sp);
1513	return ret;
1514}
1515
1516static int cdns_sierra_phy_remove(struct platform_device *pdev)
1517{
1518	struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
1519	int i;
1520
1521	reset_control_assert(phy->phy_rst);
1522	reset_control_assert(phy->apb_rst);
1523	pm_runtime_disable(&pdev->dev);
1524
1525	cdns_sierra_phy_disable_clocks(phy);
1526	/*
1527	 * The device level resets will be put automatically.
1528	 * Need to put the subnode resets here though.
1529	 */
1530	for (i = 0; i < phy->nsubnodes; i++) {
1531		reset_control_assert(phy->phys[i].lnk_rst);
1532		reset_control_put(phy->phys[i].lnk_rst);
1533	}
1534
1535	cdns_sierra_clk_unregister(phy);
1536
1537	return 0;
1538}
1539
1540/* QSGMII PHY PMA lane configuration */
1541static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
1542	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
1543};
1544
1545static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
1546	.reg_pairs = qsgmii_phy_pma_ln_regs,
1547	.num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
1548};
1549
1550/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
1551static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
1552	{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1553	{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1554	{0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1555};
1556
1557static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
1558	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1559	{0x0252, SIERRA_DET_STANDEC_E_PREG},
1560	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1561	{0x0FFE, SIERRA_PSC_RX_A0_PREG},
1562	{0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
1563	{0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
1564	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
1565	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1566	{0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1567	{0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1568	{0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
1569	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1570	{0x8422, SIERRA_CTLELUT_CTRL_PREG},
1571	{0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},
1572	{0x4111, SIERRA_DFE_SMP_RATESEL_PREG},
1573	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1574	{0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},
1575	{0x0186, SIERRA_DEQ_GLUT0},
1576	{0x0186, SIERRA_DEQ_GLUT1},
1577	{0x0186, SIERRA_DEQ_GLUT2},
1578	{0x0186, SIERRA_DEQ_GLUT3},
1579	{0x0186, SIERRA_DEQ_GLUT4},
1580	{0x0861, SIERRA_DEQ_ALUT0},
1581	{0x07E0, SIERRA_DEQ_ALUT1},
1582	{0x079E, SIERRA_DEQ_ALUT2},
1583	{0x071D, SIERRA_DEQ_ALUT3},
1584	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
1585	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1586	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1587	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
1588	{0x0033, SIERRA_DEQ_PICTRL_PREG},
1589	{0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
1590	{0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1591	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
1592	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
1593	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
1594};
1595
1596static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = {
1597	.reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs,
1598	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs),
1599};
1600
1601static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = {
1602	.reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs,
1603	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs),
1604};
1605
1606/* PCIE PHY PCS common configuration */
1607static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
1608	{0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
1609};
1610
1611static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
1612	.reg_pairs = pcie_phy_pcs_cmn_regs,
1613	.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
1614};
1615
1616/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */
1617static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = {
1618	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1619	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1620	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1621	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
1622};
1623
1624/*
1625 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
1626 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1627 */
1628static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = {
1629	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1630	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1631	{0x0004, SIERRA_PSC_LN_A3_PREG},
1632	{0x0004, SIERRA_PSC_LN_A4_PREG},
1633	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1634	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
1635	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1636	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1637	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1638	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1639	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1640	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1641	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
1642	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1643	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1644	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1645	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1646	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1647	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1648	{0x0041, SIERRA_DEQ_GLUT0},
1649	{0x0082, SIERRA_DEQ_GLUT1},
1650	{0x00C3, SIERRA_DEQ_GLUT2},
1651	{0x0145, SIERRA_DEQ_GLUT3},
1652	{0x0186, SIERRA_DEQ_GLUT4},
1653	{0x09E7, SIERRA_DEQ_ALUT0},
1654	{0x09A6, SIERRA_DEQ_ALUT1},
1655	{0x0965, SIERRA_DEQ_ALUT2},
1656	{0x08E3, SIERRA_DEQ_ALUT3},
1657	{0x00FA, SIERRA_DEQ_DFETAP0},
1658	{0x00FA, SIERRA_DEQ_DFETAP1},
1659	{0x00FA, SIERRA_DEQ_DFETAP2},
1660	{0x00FA, SIERRA_DEQ_DFETAP3},
1661	{0x00FA, SIERRA_DEQ_DFETAP4},
1662	{0x000F, SIERRA_DEQ_PRECUR_PREG},
1663	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
1664	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1665	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1666	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1667	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1668	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1669	{0x002B, SIERRA_CPI_TRIM_PREG},
1670	{0x0003, SIERRA_EPI_CTRL_PREG},
1671	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
1672	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1673	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1674	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1675};
1676
1677static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = {
1678	.reg_pairs = pcie_100_no_ssc_plllc_cmn_regs,
1679	.num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs),
1680};
1681
1682static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = {
1683	.reg_pairs = ml_pcie_100_no_ssc_ln_regs,
1684	.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs),
1685};
1686
1687/*
1688 * TI J721E:
1689 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
1690 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1691 */
1692static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = {
1693	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1694	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1695	{0x0004, SIERRA_PSC_LN_A3_PREG},
1696	{0x0004, SIERRA_PSC_LN_A4_PREG},
1697	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1698	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
1699	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1700	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1701	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1702	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1703	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1704	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1705	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
1706	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1707	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1708	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1709	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1710	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1711	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1712	{0x0041, SIERRA_DEQ_GLUT0},
1713	{0x0082, SIERRA_DEQ_GLUT1},
1714	{0x00C3, SIERRA_DEQ_GLUT2},
1715	{0x0145, SIERRA_DEQ_GLUT3},
1716	{0x0186, SIERRA_DEQ_GLUT4},
1717	{0x09E7, SIERRA_DEQ_ALUT0},
1718	{0x09A6, SIERRA_DEQ_ALUT1},
1719	{0x0965, SIERRA_DEQ_ALUT2},
1720	{0x08E3, SIERRA_DEQ_ALUT3},
1721	{0x00FA, SIERRA_DEQ_DFETAP0},
1722	{0x00FA, SIERRA_DEQ_DFETAP1},
1723	{0x00FA, SIERRA_DEQ_DFETAP2},
1724	{0x00FA, SIERRA_DEQ_DFETAP3},
1725	{0x00FA, SIERRA_DEQ_DFETAP4},
1726	{0x000F, SIERRA_DEQ_PRECUR_PREG},
1727	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
1728	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1729	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1730	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1731	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1732	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1733	{0x002B, SIERRA_CPI_TRIM_PREG},
1734	{0x0003, SIERRA_EPI_CTRL_PREG},
1735	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
1736	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1737	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1738	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
1739	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
1740};
1741
1742static struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = {
1743	.reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs,
1744	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs),
1745};
1746
1747/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */
1748static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = {
1749	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
1750	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1751	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1752	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1753	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1754	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
1755	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
1756	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
1757	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
1758	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
1759	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
1760};
1761
1762/*
1763 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
1764 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1765 */
1766static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = {
1767	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1768	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1769	{0x0004, SIERRA_PSC_LN_A3_PREG},
1770	{0x0004, SIERRA_PSC_LN_A4_PREG},
1771	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1772	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
1773	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1774	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1775	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1776	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1777	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1778	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1779	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1780	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
1781	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1782	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1783	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1784	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1785	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1786	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1787	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1788	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1789	{0x0041, SIERRA_DEQ_GLUT0},
1790	{0x0082, SIERRA_DEQ_GLUT1},
1791	{0x00C3, SIERRA_DEQ_GLUT2},
1792	{0x0145, SIERRA_DEQ_GLUT3},
1793	{0x0186, SIERRA_DEQ_GLUT4},
1794	{0x09E7, SIERRA_DEQ_ALUT0},
1795	{0x09A6, SIERRA_DEQ_ALUT1},
1796	{0x0965, SIERRA_DEQ_ALUT2},
1797	{0x08E3, SIERRA_DEQ_ALUT3},
1798	{0x00FA, SIERRA_DEQ_DFETAP0},
1799	{0x00FA, SIERRA_DEQ_DFETAP1},
1800	{0x00FA, SIERRA_DEQ_DFETAP2},
1801	{0x00FA, SIERRA_DEQ_DFETAP3},
1802	{0x00FA, SIERRA_DEQ_DFETAP4},
1803	{0x000F, SIERRA_DEQ_PRECUR_PREG},
1804	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
1805	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1806	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1807	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1808	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1809	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1810	{0x002B, SIERRA_CPI_TRIM_PREG},
1811	{0x0003, SIERRA_EPI_CTRL_PREG},
1812	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
1813	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1814	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1815	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1816};
1817
1818static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = {
1819	.reg_pairs = pcie_100_int_ssc_plllc_cmn_regs,
1820	.num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs),
1821};
1822
1823static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = {
1824	.reg_pairs = ml_pcie_100_int_ssc_ln_regs,
1825	.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs),
1826};
1827
1828/*
1829 * TI J721E:
1830 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
1831 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1832 */
1833static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = {
1834	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1835	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1836	{0x0004, SIERRA_PSC_LN_A3_PREG},
1837	{0x0004, SIERRA_PSC_LN_A4_PREG},
1838	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1839	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
1840	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1841	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1842	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1843	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1844	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1845	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1846	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1847	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
1848	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1849	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1850	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1851	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1852	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1853	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1854	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1855	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1856	{0x0041, SIERRA_DEQ_GLUT0},
1857	{0x0082, SIERRA_DEQ_GLUT1},
1858	{0x00C3, SIERRA_DEQ_GLUT2},
1859	{0x0145, SIERRA_DEQ_GLUT3},
1860	{0x0186, SIERRA_DEQ_GLUT4},
1861	{0x09E7, SIERRA_DEQ_ALUT0},
1862	{0x09A6, SIERRA_DEQ_ALUT1},
1863	{0x0965, SIERRA_DEQ_ALUT2},
1864	{0x08E3, SIERRA_DEQ_ALUT3},
1865	{0x00FA, SIERRA_DEQ_DFETAP0},
1866	{0x00FA, SIERRA_DEQ_DFETAP1},
1867	{0x00FA, SIERRA_DEQ_DFETAP2},
1868	{0x00FA, SIERRA_DEQ_DFETAP3},
1869	{0x00FA, SIERRA_DEQ_DFETAP4},
1870	{0x000F, SIERRA_DEQ_PRECUR_PREG},
1871	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
1872	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1873	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1874	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1875	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1876	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1877	{0x002B, SIERRA_CPI_TRIM_PREG},
1878	{0x0003, SIERRA_EPI_CTRL_PREG},
1879	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
1880	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1881	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1882	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
1883	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
1884};
1885
1886static struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = {
1887	.reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs,
1888	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs),
1889};
1890
1891/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */
1892static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = {
1893	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1894	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1895	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1896	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1897	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
1898};
1899
1900/*
1901 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
1902 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1903 */
1904static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = {
1905	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1906	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1907	{0x0004, SIERRA_PSC_LN_A3_PREG},
1908	{0x0004, SIERRA_PSC_LN_A4_PREG},
1909	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1910	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
1911	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1912	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1913	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1914	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1915	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1916	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1917	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1918	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
1919	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1920	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1921	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1922	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1923	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1924	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1925	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1926	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1927	{0x0041, SIERRA_DEQ_GLUT0},
1928	{0x0082, SIERRA_DEQ_GLUT1},
1929	{0x00C3, SIERRA_DEQ_GLUT2},
1930	{0x0145, SIERRA_DEQ_GLUT3},
1931	{0x0186, SIERRA_DEQ_GLUT4},
1932	{0x09E7, SIERRA_DEQ_ALUT0},
1933	{0x09A6, SIERRA_DEQ_ALUT1},
1934	{0x0965, SIERRA_DEQ_ALUT2},
1935	{0x08E3, SIERRA_DEQ_ALUT3},
1936	{0x00FA, SIERRA_DEQ_DFETAP0},
1937	{0x00FA, SIERRA_DEQ_DFETAP1},
1938	{0x00FA, SIERRA_DEQ_DFETAP2},
1939	{0x00FA, SIERRA_DEQ_DFETAP3},
1940	{0x00FA, SIERRA_DEQ_DFETAP4},
1941	{0x000F, SIERRA_DEQ_PRECUR_PREG},
1942	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
1943	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1944	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1945	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1946	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1947	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1948	{0x002B, SIERRA_CPI_TRIM_PREG},
1949	{0x0003, SIERRA_EPI_CTRL_PREG},
1950	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
1951	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1952	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1953	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1954};
1955
1956static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = {
1957	.reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs,
1958	.num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs),
1959};
1960
1961static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = {
1962	.reg_pairs = ml_pcie_100_ext_ssc_ln_regs,
1963	.num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs),
1964};
1965
1966/*
1967 * TI J721E:
1968 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
1969 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1970 */
1971static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = {
1972	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
1973	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1974	{0x0004, SIERRA_PSC_LN_A3_PREG},
1975	{0x0004, SIERRA_PSC_LN_A4_PREG},
1976	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1977	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
1978	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1979	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1980	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1981	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1982	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1983	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1984	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1985	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
1986	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1987	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1988	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1989	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1990	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1991	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1992	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1993	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1994	{0x0041, SIERRA_DEQ_GLUT0},
1995	{0x0082, SIERRA_DEQ_GLUT1},
1996	{0x00C3, SIERRA_DEQ_GLUT2},
1997	{0x0145, SIERRA_DEQ_GLUT3},
1998	{0x0186, SIERRA_DEQ_GLUT4},
1999	{0x09E7, SIERRA_DEQ_ALUT0},
2000	{0x09A6, SIERRA_DEQ_ALUT1},
2001	{0x0965, SIERRA_DEQ_ALUT2},
2002	{0x08E3, SIERRA_DEQ_ALUT3},
2003	{0x00FA, SIERRA_DEQ_DFETAP0},
2004	{0x00FA, SIERRA_DEQ_DFETAP1},
2005	{0x00FA, SIERRA_DEQ_DFETAP2},
2006	{0x00FA, SIERRA_DEQ_DFETAP3},
2007	{0x00FA, SIERRA_DEQ_DFETAP4},
2008	{0x000F, SIERRA_DEQ_PRECUR_PREG},
2009	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
2010	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2011	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2012	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2013	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2014	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2015	{0x002B, SIERRA_CPI_TRIM_PREG},
2016	{0x0003, SIERRA_EPI_CTRL_PREG},
2017	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
2018	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2019	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2020	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
2021	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
2022};
2023
2024static struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = {
2025	.reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs,
2026	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs),
2027};
2028
2029/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
2030static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
2031	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2032	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2033	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
2034	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
2035};
2036
2037/* refclk100MHz_32b_PCIe_ln_no_ssc */
2038static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {
2039	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
2040	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2041	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
2042	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2043	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2044	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2045	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2046	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2047	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2048	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
2049	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2050	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2051	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2052	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2053	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2054	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2055	{0x0041, SIERRA_DEQ_GLUT0},
2056	{0x0082, SIERRA_DEQ_GLUT1},
2057	{0x00C3, SIERRA_DEQ_GLUT2},
2058	{0x0145, SIERRA_DEQ_GLUT3},
2059	{0x0186, SIERRA_DEQ_GLUT4},
2060	{0x09E7, SIERRA_DEQ_ALUT0},
2061	{0x09A6, SIERRA_DEQ_ALUT1},
2062	{0x0965, SIERRA_DEQ_ALUT2},
2063	{0x08E3, SIERRA_DEQ_ALUT3},
2064	{0x00FA, SIERRA_DEQ_DFETAP0},
2065	{0x00FA, SIERRA_DEQ_DFETAP1},
2066	{0x00FA, SIERRA_DEQ_DFETAP2},
2067	{0x00FA, SIERRA_DEQ_DFETAP3},
2068	{0x00FA, SIERRA_DEQ_DFETAP4},
2069	{0x000F, SIERRA_DEQ_PRECUR_PREG},
2070	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
2071	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2072	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2073	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2074	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2075	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2076	{0x002B, SIERRA_CPI_TRIM_PREG},
2077	{0x0003, SIERRA_EPI_CTRL_PREG},
2078	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
2079	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2080	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2081	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2082};
2083
2084static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {
2085	.reg_pairs = cdns_pcie_cmn_regs_no_ssc,
2086	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),
2087};
2088
2089static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {
2090	.reg_pairs = cdns_pcie_ln_regs_no_ssc,
2091	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),
2092};
2093
2094/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */
2095static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {
2096	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
2097	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2098	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2099	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
2100	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2101	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
2102	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
2103	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
2104	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
2105	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
2106	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
2107};
2108
2109/* refclk100MHz_32b_PCIe_ln_int_ssc */
2110static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {
2111	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
2112	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2113	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
2114	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2115	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
2116	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2117	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2118	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2119	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2120	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2121	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
2122	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2123	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2124	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2125	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2126	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2127	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2128	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2129	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2130	{0x0041, SIERRA_DEQ_GLUT0},
2131	{0x0082, SIERRA_DEQ_GLUT1},
2132	{0x00C3, SIERRA_DEQ_GLUT2},
2133	{0x0145, SIERRA_DEQ_GLUT3},
2134	{0x0186, SIERRA_DEQ_GLUT4},
2135	{0x09E7, SIERRA_DEQ_ALUT0},
2136	{0x09A6, SIERRA_DEQ_ALUT1},
2137	{0x0965, SIERRA_DEQ_ALUT2},
2138	{0x08E3, SIERRA_DEQ_ALUT3},
2139	{0x00FA, SIERRA_DEQ_DFETAP0},
2140	{0x00FA, SIERRA_DEQ_DFETAP1},
2141	{0x00FA, SIERRA_DEQ_DFETAP2},
2142	{0x00FA, SIERRA_DEQ_DFETAP3},
2143	{0x00FA, SIERRA_DEQ_DFETAP4},
2144	{0x000F, SIERRA_DEQ_PRECUR_PREG},
2145	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
2146	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2147	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2148	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2149	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2150	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2151	{0x002B, SIERRA_CPI_TRIM_PREG},
2152	{0x0003, SIERRA_EPI_CTRL_PREG},
2153	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
2154	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2155	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2156	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2157};
2158
2159static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {
2160	.reg_pairs = cdns_pcie_cmn_regs_int_ssc,
2161	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),
2162};
2163
2164static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {
2165	.reg_pairs = cdns_pcie_ln_regs_int_ssc,
2166	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),
2167};
2168
2169/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
2170static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
2171	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2172	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2173	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
2174	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2175	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
2176};
2177
2178/* refclk100MHz_32b_PCIe_ln_ext_ssc */
2179static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
2180	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
2181	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2182	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
2183	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2184	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
2185	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2186	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2187	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2188	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2189	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2190	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
2191	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2192	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2193	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2194	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2195	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2196	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2197	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2198	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2199	{0x0041, SIERRA_DEQ_GLUT0},
2200	{0x0082, SIERRA_DEQ_GLUT1},
2201	{0x00C3, SIERRA_DEQ_GLUT2},
2202	{0x0145, SIERRA_DEQ_GLUT3},
2203	{0x0186, SIERRA_DEQ_GLUT4},
2204	{0x09E7, SIERRA_DEQ_ALUT0},
2205	{0x09A6, SIERRA_DEQ_ALUT1},
2206	{0x0965, SIERRA_DEQ_ALUT2},
2207	{0x08E3, SIERRA_DEQ_ALUT3},
2208	{0x00FA, SIERRA_DEQ_DFETAP0},
2209	{0x00FA, SIERRA_DEQ_DFETAP1},
2210	{0x00FA, SIERRA_DEQ_DFETAP2},
2211	{0x00FA, SIERRA_DEQ_DFETAP3},
2212	{0x00FA, SIERRA_DEQ_DFETAP4},
2213	{0x000F, SIERRA_DEQ_PRECUR_PREG},
2214	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
2215	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2216	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2217	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2218	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2219	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2220	{0x002B, SIERRA_CPI_TRIM_PREG},
2221	{0x0003, SIERRA_EPI_CTRL_PREG},
2222	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
2223	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2224	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2225	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2226};
2227
2228static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
2229	.reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
2230	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
2231};
2232
2233static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
2234	.reg_pairs = cdns_pcie_ln_regs_ext_ssc,
2235	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
2236};
2237
2238/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
2239static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
2240	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2241	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2242	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2243	{0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
2244};
2245
2246/* refclk100MHz_20b_USB_ln_ext_ssc */
2247static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
2248	{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
2249	{0x000F, SIERRA_DET_STANDEC_B_PREG},
2250	{0x55A5, SIERRA_DET_STANDEC_C_PREG},
2251	{0x69ad, SIERRA_DET_STANDEC_D_PREG},
2252	{0x0241, SIERRA_DET_STANDEC_E_PREG},
2253	{0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
2254	{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
2255	{0xCF00, SIERRA_PSM_DIAG_PREG},
2256	{0x001F, SIERRA_PSC_TX_A0_PREG},
2257	{0x0007, SIERRA_PSC_TX_A1_PREG},
2258	{0x0003, SIERRA_PSC_TX_A2_PREG},
2259	{0x0003, SIERRA_PSC_TX_A3_PREG},
2260	{0x0FFF, SIERRA_PSC_RX_A0_PREG},
2261	{0x0003, SIERRA_PSC_RX_A1_PREG},
2262	{0x0003, SIERRA_PSC_RX_A2_PREG},
2263	{0x0001, SIERRA_PSC_RX_A3_PREG},
2264	{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
2265	{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
2266	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
2267	{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
2268	{0x2512, SIERRA_DFE_BIASTRIM_PREG},
2269	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
2270	{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
2271	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2272	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2273	{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
2274	{0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2275	{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
2276	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
2277	{0x0000, SIERRA_CREQ_SPARE_PREG},
2278	{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2279	{0x8452, SIERRA_CTLELUT_CTRL_PREG},
2280	{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
2281	{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
2282	{0x0003, SIERRA_DEQ_PHALIGN_CTRL},
2283	{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
2284	{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2285	{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2286	{0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2287	{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2288	{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
2289	{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
2290	{0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
2291	{0x0014, SIERRA_DEQ_GLUT0},
2292	{0x0014, SIERRA_DEQ_GLUT1},
2293	{0x0014, SIERRA_DEQ_GLUT2},
2294	{0x0014, SIERRA_DEQ_GLUT3},
2295	{0x0014, SIERRA_DEQ_GLUT4},
2296	{0x0014, SIERRA_DEQ_GLUT5},
2297	{0x0014, SIERRA_DEQ_GLUT6},
2298	{0x0014, SIERRA_DEQ_GLUT7},
2299	{0x0014, SIERRA_DEQ_GLUT8},
2300	{0x0014, SIERRA_DEQ_GLUT9},
2301	{0x0014, SIERRA_DEQ_GLUT10},
2302	{0x0014, SIERRA_DEQ_GLUT11},
2303	{0x0014, SIERRA_DEQ_GLUT12},
2304	{0x0014, SIERRA_DEQ_GLUT13},
2305	{0x0014, SIERRA_DEQ_GLUT14},
2306	{0x0014, SIERRA_DEQ_GLUT15},
2307	{0x0014, SIERRA_DEQ_GLUT16},
2308	{0x0BAE, SIERRA_DEQ_ALUT0},
2309	{0x0AEB, SIERRA_DEQ_ALUT1},
2310	{0x0A28, SIERRA_DEQ_ALUT2},
2311	{0x0965, SIERRA_DEQ_ALUT3},
2312	{0x08A2, SIERRA_DEQ_ALUT4},
2313	{0x07DF, SIERRA_DEQ_ALUT5},
2314	{0x071C, SIERRA_DEQ_ALUT6},
2315	{0x0659, SIERRA_DEQ_ALUT7},
2316	{0x0596, SIERRA_DEQ_ALUT8},
2317	{0x0514, SIERRA_DEQ_ALUT9},
2318	{0x0492, SIERRA_DEQ_ALUT10},
2319	{0x0410, SIERRA_DEQ_ALUT11},
2320	{0x038E, SIERRA_DEQ_ALUT12},
2321	{0x030C, SIERRA_DEQ_ALUT13},
2322	{0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
2323	{0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
2324	{0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
2325	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2326	{0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
2327	{0x0033, SIERRA_DEQ_PICTRL_PREG},
2328	{0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
2329	{0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
2330	{0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
2331	{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
2332	{0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
2333	{0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
2334	{0x000F, SIERRA_LFPSFILT_NS_PREG},
2335	{0x0009, SIERRA_LFPSFILT_RD_PREG},
2336	{0x0001, SIERRA_LFPSFILT_MP_PREG},
2337	{0x6013, SIERRA_SIGDET_SUPPORT_PREG},
2338	{0x8013, SIERRA_SDFILT_H2L_A_PREG},
2339	{0x8009, SIERRA_SDFILT_L2H_PREG},
2340	{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
2341	{0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2342	{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
2343};
2344
2345static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
2346	.reg_pairs = cdns_usb_cmn_regs_ext_ssc,
2347	.num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
2348};
2349
2350static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
2351	.reg_pairs = cdns_usb_ln_regs_ext_ssc,
2352	.num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
2353};
2354
2355static const struct cdns_sierra_data cdns_map_sierra = {
2356	.id_value = SIERRA_MACRO_ID,
2357	.block_offset_shift = 0x2,
2358	.reg_offset_shift = 0x2,
2359	.pcs_cmn_vals = {
2360		[TYPE_PCIE] = {
2361			[TYPE_NONE] = {
2362				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2363				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2364				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2365			},
2366			[TYPE_QSGMII] = {
2367				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2368				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2369				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2370			},
2371		},
2372	},
2373	.pma_cmn_vals = {
2374		[TYPE_PCIE] = {
2375			[TYPE_NONE] = {
2376				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2377				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
2378				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2379			},
2380			[TYPE_QSGMII] = {
2381				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2382				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2383				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2384			},
2385		},
2386		[TYPE_USB] = {
2387			[TYPE_NONE] = {
2388				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2389			},
2390		},
2391		[TYPE_QSGMII] = {
2392			[TYPE_PCIE] = {
2393				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2394				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2395				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2396			},
2397		},
2398	},
2399	.pma_ln_vals = {
2400		[TYPE_PCIE] = {
2401			[TYPE_NONE] = {
2402				[NO_SSC] = &pcie_100_no_ssc_ln_vals,
2403				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
2404				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
2405			},
2406			[TYPE_QSGMII] = {
2407				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2408				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2409				[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2410			},
2411		},
2412		[TYPE_USB] = {
2413			[TYPE_NONE] = {
2414				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2415			},
2416		},
2417		[TYPE_QSGMII] = {
2418			[TYPE_PCIE] = {
2419				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2420				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2421				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2422			},
2423		},
2424	},
2425};
2426
2427static const struct cdns_sierra_data cdns_ti_map_sierra = {
2428	.id_value = SIERRA_MACRO_ID,
2429	.block_offset_shift = 0x0,
2430	.reg_offset_shift = 0x1,
2431	.pcs_cmn_vals = {
2432		[TYPE_PCIE] = {
2433			[TYPE_NONE] = {
2434				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2435				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2436				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2437			},
2438			[TYPE_QSGMII] = {
2439				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2440				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2441				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2442			},
2443		},
2444	},
2445	.phy_pma_ln_vals = {
2446		[TYPE_QSGMII] = {
2447			[TYPE_PCIE] = {
2448				[NO_SSC] = &qsgmii_phy_pma_ln_vals,
2449				[EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
2450				[INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
2451			},
2452		},
2453	},
2454	.pma_cmn_vals = {
2455		[TYPE_PCIE] = {
2456			[TYPE_NONE] = {
2457				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2458				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
2459				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2460			},
2461			[TYPE_QSGMII] = {
2462				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2463				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2464				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2465			},
2466		},
2467		[TYPE_USB] = {
2468			[TYPE_NONE] = {
2469				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2470			},
2471		},
2472		[TYPE_QSGMII] = {
2473			[TYPE_PCIE] = {
2474				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2475				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2476				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2477			},
2478		},
2479	},
2480	.pma_ln_vals = {
2481		[TYPE_PCIE] = {
2482			[TYPE_NONE] = {
2483				[NO_SSC] = &pcie_100_no_ssc_ln_vals,
2484				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
2485				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
2486			},
2487			[TYPE_QSGMII] = {
2488				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
2489				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
2490				[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
2491			},
2492		},
2493		[TYPE_USB] = {
2494			[TYPE_NONE] = {
2495				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2496			},
2497		},
2498		[TYPE_QSGMII] = {
2499			[TYPE_PCIE] = {
2500				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2501				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2502				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2503			},
2504		},
2505	},
2506};
2507
2508static const struct of_device_id cdns_sierra_id_table[] = {
2509	{
2510		.compatible = "cdns,sierra-phy-t0",
2511		.data = &cdns_map_sierra,
2512	},
2513	{
2514		.compatible = "ti,sierra-phy-t0",
2515		.data = &cdns_ti_map_sierra,
2516	},
2517	{}
2518};
2519MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);
2520
2521static struct platform_driver cdns_sierra_driver = {
2522	.probe		= cdns_sierra_phy_probe,
2523	.remove		= cdns_sierra_phy_remove,
2524	.driver		= {
2525		.name	= "cdns-sierra-phy",
2526		.of_match_table = cdns_sierra_id_table,
2527	},
2528};
2529module_platform_driver(cdns_sierra_driver);
2530
2531MODULE_ALIAS("platform:cdns_sierra");
2532MODULE_AUTHOR("Cadence Design Systems");
2533MODULE_DESCRIPTION("CDNS sierra phy driver");
2534MODULE_LICENSE("GPL v2");

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Cadence Sierra PHY Driver
   4 *
   5 * Copyright (c) 2018 Cadence Design Systems
   6 * Author: Alan Douglas <adouglas@cadence.com>
   7 *
   8 */
   9#include <linux/clk.h>
  10#include <linux/clk-provider.h>
  11#include <linux/delay.h>
  12#include <linux/err.h>
  13#include <linux/io.h>
  14#include <linux/module.h>
  15#include <linux/phy/phy.h>
  16#include <linux/platform_device.h>
  17#include <linux/pm_runtime.h>
  18#include <linux/regmap.h>
  19#include <linux/reset.h>
  20#include <linux/slab.h>
  21#include <linux/of.h>
  22#include <linux/of_platform.h>
  23#include <dt-bindings/phy/phy.h>
  24#include <dt-bindings/phy/phy-cadence.h>
  25
 
 
 
  26/* PHY register offsets */
  27#define SIERRA_COMMON_CDB_OFFSET			0x0
  28#define SIERRA_MACRO_ID_REG				0x0
  29#define SIERRA_CMN_PLLLC_GEN_PREG			0x42
  30#define SIERRA_CMN_PLLLC_MODE_PREG			0x48
  31#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG		0x49
  32#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG		0x4A
  33#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG		0x4B
 
  34#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG		0x4F
  35#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG		0x50
 
 
 
 
  36#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG	0x62
 
  37#define SIERRA_CMN_REFRCV_PREG				0x98
  38#define SIERRA_CMN_REFRCV1_PREG				0xB8
  39#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC2
 
 
 
  40
  41#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
  42				((0x4000 << (block_offset)) + \
  43				 (((ln) << 9) << (reg_offset)))
  44
  45#define SIERRA_DET_STANDEC_A_PREG			0x000
  46#define SIERRA_DET_STANDEC_B_PREG			0x001
  47#define SIERRA_DET_STANDEC_C_PREG			0x002
  48#define SIERRA_DET_STANDEC_D_PREG			0x003
  49#define SIERRA_DET_STANDEC_E_PREG			0x004
  50#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG		0x008
  51#define SIERRA_PSM_A0IN_TMR_PREG			0x009
 
  52#define SIERRA_PSM_DIAG_PREG				0x015
 
 
 
  53#define SIERRA_PSC_TX_A0_PREG				0x028
  54#define SIERRA_PSC_TX_A1_PREG				0x029
  55#define SIERRA_PSC_TX_A2_PREG				0x02A
  56#define SIERRA_PSC_TX_A3_PREG				0x02B
  57#define SIERRA_PSC_RX_A0_PREG				0x030
  58#define SIERRA_PSC_RX_A1_PREG				0x031
  59#define SIERRA_PSC_RX_A2_PREG				0x032
  60#define SIERRA_PSC_RX_A3_PREG				0x033
  61#define SIERRA_PLLCTRL_SUBRATE_PREG			0x03A
 
  62#define SIERRA_PLLCTRL_GEN_D_PREG			0x03E
  63#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG			0x03F
  64#define SIERRA_PLLCTRL_STATUS_PREG			0x044
  65#define SIERRA_CLKPATH_BIASTRIM_PREG			0x04B
  66#define SIERRA_DFE_BIASTRIM_PREG			0x04C
  67#define SIERRA_DRVCTRL_ATTEN_PREG			0x06A
 
 
  68#define SIERRA_CLKPATHCTRL_TMR_PREG			0x081
  69#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG		0x085
  70#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG		0x086
  71#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG		0x087
  72#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG		0x088
 
  73#define SIERRA_CREQ_CCLKDET_MODE01_PREG			0x08E
 
  74#define SIERRA_RX_CTLE_MAINTENANCE_PREG			0x091
  75#define SIERRA_CREQ_FSMCLK_SEL_PREG			0x092
  76#define SIERRA_CREQ_EQ_CTRL_PREG			0x093
  77#define SIERRA_CREQ_SPARE_PREG				0x096
  78#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG		0x097
  79#define SIERRA_CTLELUT_CTRL_PREG			0x098
  80#define SIERRA_DFE_ECMP_RATESEL_PREG			0x0C0
  81#define SIERRA_DFE_SMP_RATESEL_PREG			0x0C1
  82#define SIERRA_DEQ_PHALIGN_CTRL				0x0C4
  83#define SIERRA_DEQ_CONCUR_CTRL1_PREG			0x0C8
  84#define SIERRA_DEQ_CONCUR_CTRL2_PREG			0x0C9
  85#define SIERRA_DEQ_EPIPWR_CTRL2_PREG			0x0CD
  86#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG		0x0CE
  87#define SIERRA_DEQ_ERRCMP_CTRL_PREG			0x0D0
  88#define SIERRA_DEQ_OFFSET_CTRL_PREG			0x0D8
  89#define SIERRA_DEQ_GAIN_CTRL_PREG			0x0E0
  90#define SIERRA_DEQ_VGATUNE_CTRL_PREG			0x0E1
  91#define SIERRA_DEQ_GLUT0				0x0E8
  92#define SIERRA_DEQ_GLUT1				0x0E9
  93#define SIERRA_DEQ_GLUT2				0x0EA
  94#define SIERRA_DEQ_GLUT3				0x0EB
  95#define SIERRA_DEQ_GLUT4				0x0EC
  96#define SIERRA_DEQ_GLUT5				0x0ED
  97#define SIERRA_DEQ_GLUT6				0x0EE
  98#define SIERRA_DEQ_GLUT7				0x0EF
  99#define SIERRA_DEQ_GLUT8				0x0F0
 100#define SIERRA_DEQ_GLUT9				0x0F1
 101#define SIERRA_DEQ_GLUT10				0x0F2
 102#define SIERRA_DEQ_GLUT11				0x0F3
 103#define SIERRA_DEQ_GLUT12				0x0F4
 104#define SIERRA_DEQ_GLUT13				0x0F5
 105#define SIERRA_DEQ_GLUT14				0x0F6
 106#define SIERRA_DEQ_GLUT15				0x0F7
 107#define SIERRA_DEQ_GLUT16				0x0F8
 108#define SIERRA_DEQ_ALUT0				0x108
 109#define SIERRA_DEQ_ALUT1				0x109
 110#define SIERRA_DEQ_ALUT2				0x10A
 111#define SIERRA_DEQ_ALUT3				0x10B
 112#define SIERRA_DEQ_ALUT4				0x10C
 113#define SIERRA_DEQ_ALUT5				0x10D
 114#define SIERRA_DEQ_ALUT6				0x10E
 115#define SIERRA_DEQ_ALUT7				0x10F
 116#define SIERRA_DEQ_ALUT8				0x110
 117#define SIERRA_DEQ_ALUT9				0x111
 118#define SIERRA_DEQ_ALUT10				0x112
 119#define SIERRA_DEQ_ALUT11				0x113
 120#define SIERRA_DEQ_ALUT12				0x114
 121#define SIERRA_DEQ_ALUT13				0x115
 122#define SIERRA_DEQ_DFETAP_CTRL_PREG			0x128
 
 
 
 
 
 123#define SIERRA_DFE_EN_1010_IGNORE_PREG			0x134
 
 
 
 124#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150
 125#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151
 
 
 126#define SIERRA_DEQ_PICTRL_PREG				0x161
 127#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170
 128#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171
 129#define SIERRA_CPICAL_PICNT_MODE1_PREG			0x174
 130#define SIERRA_CPI_OUTBUF_RATESEL_PREG			0x17C
 
 
 131#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG		0x183
 
 132#define SIERRA_LFPSDET_SUPPORT_PREG			0x188
 133#define SIERRA_LFPSFILT_NS_PREG				0x18A
 134#define SIERRA_LFPSFILT_RD_PREG				0x18B
 135#define SIERRA_LFPSFILT_MP_PREG				0x18C
 136#define SIERRA_SIGDET_SUPPORT_PREG			0x190
 137#define SIERRA_SDFILT_H2L_A_PREG			0x191
 138#define SIERRA_SDFILT_L2H_PREG				0x193
 139#define SIERRA_RXBUFFER_CTLECTRL_PREG			0x19E
 140#define SIERRA_RXBUFFER_RCDFECTRL_PREG			0x19F
 141#define SIERRA_RXBUFFER_DFECTRL_PREG			0x1A0
 142#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG		0x14F
 143#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150
 144
 145#define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset)	\
 146				      (0xc000 << (block_offset))
 
 
 147#define SIERRA_PHY_PLL_CFG				0xe
 148
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 149#define SIERRA_MACRO_ID					0x00007364
 150#define SIERRA_MAX_LANES				16
 151#define PLL_LOCK_TIME					100000
 152
 153#define CDNS_SIERRA_OUTPUT_CLOCKS			2
 154#define CDNS_SIERRA_INPUT_CLOCKS			5
 155enum cdns_sierra_clock_input {
 156	PHY_CLK,
 157	CMN_REFCLK_DIG_DIV,
 158	CMN_REFCLK1_DIG_DIV,
 159	PLL0_REFCLK,
 160	PLL1_REFCLK,
 161};
 162
 163#define SIERRA_NUM_CMN_PLLC				2
 164#define SIERRA_NUM_CMN_PLLC_PARENTS			2
 165
 166static const struct reg_field macro_id_type =
 167				REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 168static const struct reg_field phy_pll_cfg_1 =
 169				REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 
 
 170static const struct reg_field pllctrl_lock =
 171				REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
 
 
 
 
 
 
 172
 173static const char * const clk_names[] = {
 174	[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
 175	[CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
 
 176};
 177
 178enum cdns_sierra_cmn_plllc {
 179	CMN_PLLLC,
 180	CMN_PLLLC1,
 181};
 182
 183struct cdns_sierra_pll_mux_reg_fields {
 184	struct reg_field	pfdclk_sel_preg;
 185	struct reg_field	plllc1en_field;
 186	struct reg_field	termen_field;
 187};
 188
 189static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
 190	[CMN_PLLLC] = {
 191		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
 192		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
 193		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
 194	},
 195	[CMN_PLLLC1] = {
 196		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
 197		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
 198		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
 199	},
 200};
 201
 202struct cdns_sierra_pll_mux {
 203	struct clk_hw		hw;
 204	struct regmap_field	*pfdclk_sel_preg;
 205	struct regmap_field	*plllc1en_field;
 206	struct regmap_field	*termen_field;
 207	struct clk_init_data	clk_data;
 208};
 209
 210#define to_cdns_sierra_pll_mux(_hw)	\
 211			container_of(_hw, struct cdns_sierra_pll_mux, hw)
 212
 213static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
 214	[CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK },
 215	[CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },
 216};
 217
 218static u32 cdns_sierra_pll_mux_table[] = { 0, 1 };
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 219
 220struct cdns_sierra_inst {
 221	struct phy *phy;
 222	u32 phy_type;
 223	u32 num_lanes;
 224	u32 mlane;
 225	struct reset_control *lnk_rst;
 
 226};
 227
 228struct cdns_reg_pairs {
 229	u16 val;
 230	u32 off;
 231};
 232
 
 
 
 
 
 233struct cdns_sierra_data {
 234		u32 id_value;
 235		u8 block_offset_shift;
 236		u8 reg_offset_shift;
 237		u32 pcie_cmn_regs;
 238		u32 pcie_ln_regs;
 239		u32 usb_cmn_regs;
 240		u32 usb_ln_regs;
 241		const struct cdns_reg_pairs *pcie_cmn_vals;
 242		const struct cdns_reg_pairs *pcie_ln_vals;
 243		const struct cdns_reg_pairs *usb_cmn_vals;
 244		const struct cdns_reg_pairs *usb_ln_vals;
 245};
 246
 247struct cdns_regmap_cdb_context {
 248	struct device *dev;
 249	void __iomem *base;
 250	u8 reg_offset_shift;
 251};
 252
 253struct cdns_sierra_phy {
 254	struct device *dev;
 255	struct regmap *regmap;
 256	struct cdns_sierra_data *init_data;
 257	struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
 258	struct reset_control *phy_rst;
 259	struct reset_control *apb_rst;
 260	struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 261	struct regmap *regmap_phy_config_ctrl;
 
 
 
 262	struct regmap *regmap_common_cdb;
 263	struct regmap_field *macro_id_type;
 264	struct regmap_field *phy_pll_cfg_1;
 
 265	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
 
 266	struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
 267	struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
 268	struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
 269	struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
 270	int nsubnodes;
 271	u32 num_lanes;
 272	bool autoconf;
 
 273	struct clk_onecell_data clk_data;
 274	struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS];
 275};
 276
 277static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
 278{
 279	struct cdns_regmap_cdb_context *ctx = context;
 280	u32 offset = reg << ctx->reg_offset_shift;
 281
 282	writew(val, ctx->base + offset);
 283
 284	return 0;
 285}
 286
 287static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
 288{
 289	struct cdns_regmap_cdb_context *ctx = context;
 290	u32 offset = reg << ctx->reg_offset_shift;
 291
 292	*val = readw(ctx->base + offset);
 293	return 0;
 294}
 295
 296#define SIERRA_LANE_CDB_REGMAP_CONF(n) \
 297{ \
 298	.name = "sierra_lane" n "_cdb", \
 299	.reg_stride = 1, \
 300	.fast_io = true, \
 301	.reg_write = cdns_regmap_write, \
 302	.reg_read = cdns_regmap_read, \
 303}
 304
 305static const struct regmap_config cdns_sierra_lane_cdb_config[] = {
 306	SIERRA_LANE_CDB_REGMAP_CONF("0"),
 307	SIERRA_LANE_CDB_REGMAP_CONF("1"),
 308	SIERRA_LANE_CDB_REGMAP_CONF("2"),
 309	SIERRA_LANE_CDB_REGMAP_CONF("3"),
 310	SIERRA_LANE_CDB_REGMAP_CONF("4"),
 311	SIERRA_LANE_CDB_REGMAP_CONF("5"),
 312	SIERRA_LANE_CDB_REGMAP_CONF("6"),
 313	SIERRA_LANE_CDB_REGMAP_CONF("7"),
 314	SIERRA_LANE_CDB_REGMAP_CONF("8"),
 315	SIERRA_LANE_CDB_REGMAP_CONF("9"),
 316	SIERRA_LANE_CDB_REGMAP_CONF("10"),
 317	SIERRA_LANE_CDB_REGMAP_CONF("11"),
 318	SIERRA_LANE_CDB_REGMAP_CONF("12"),
 319	SIERRA_LANE_CDB_REGMAP_CONF("13"),
 320	SIERRA_LANE_CDB_REGMAP_CONF("14"),
 321	SIERRA_LANE_CDB_REGMAP_CONF("15"),
 322};
 323
 324static const struct regmap_config cdns_sierra_common_cdb_config = {
 325	.name = "sierra_common_cdb",
 326	.reg_stride = 1,
 327	.fast_io = true,
 328	.reg_write = cdns_regmap_write,
 329	.reg_read = cdns_regmap_read,
 330};
 331
 332static const struct regmap_config cdns_sierra_phy_config_ctrl_config = {
 333	.name = "sierra_phy_config_ctrl",
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 334	.reg_stride = 1,
 335	.fast_io = true,
 336	.reg_write = cdns_regmap_write,
 337	.reg_read = cdns_regmap_read,
 338};
 339
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 340static int cdns_sierra_phy_init(struct phy *gphy)
 341{
 342	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 343	struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
 
 
 
 
 
 
 
 344	struct regmap *regmap;
 
 345	int i, j;
 346	const struct cdns_reg_pairs *cmn_vals, *ln_vals;
 347	u32 num_cmn_regs, num_ln_regs;
 348
 349	/* Initialise the PHY registers, unless auto configured */
 350	if (phy->autoconf)
 351		return 0;
 352
 353	clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
 354	clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
 355	if (ins->phy_type == PHY_TYPE_PCIE) {
 356		num_cmn_regs = phy->init_data->pcie_cmn_regs;
 357		num_ln_regs = phy->init_data->pcie_ln_regs;
 358		cmn_vals = phy->init_data->pcie_cmn_vals;
 359		ln_vals = phy->init_data->pcie_ln_vals;
 360	} else if (ins->phy_type == PHY_TYPE_USB3) {
 361		num_cmn_regs = phy->init_data->usb_cmn_regs;
 362		num_ln_regs = phy->init_data->usb_ln_regs;
 363		cmn_vals = phy->init_data->usb_cmn_vals;
 364		ln_vals = phy->init_data->usb_ln_vals;
 365	} else {
 366		return -EINVAL;
 
 
 
 
 
 
 
 
 
 367	}
 368
 369	regmap = phy->regmap_common_cdb;
 370	for (j = 0; j < num_cmn_regs ; j++)
 371		regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
 372
 373	for (i = 0; i < ins->num_lanes; i++) {
 374		for (j = 0; j < num_ln_regs ; j++) {
 
 
 
 
 
 
 
 
 
 
 375			regmap = phy->regmap_lane_cdb[i + ins->mlane];
 376			regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
 
 377		}
 378	}
 379
 380	return 0;
 381}
 382
 383static int cdns_sierra_phy_on(struct phy *gphy)
 384{
 385	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
 386	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 387	struct device *dev = sp->dev;
 388	u32 val;
 389	int ret;
 390
 391	ret = reset_control_deassert(sp->phy_rst);
 392	if (ret) {
 393		dev_err(dev, "Failed to take the PHY out of reset\n");
 394		return ret;
 
 
 
 395	}
 396
 397	/* Take the PHY lane group out of reset */
 398	ret = reset_control_deassert(ins->lnk_rst);
 399	if (ret) {
 400		dev_err(dev, "Failed to take the PHY lane out of reset\n");
 401		return ret;
 402	}
 403
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 404	ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
 405					     val, val, 1000, PLL_LOCK_TIME);
 406	if (ret < 0)
 407		dev_err(dev, "PLL lock of lane failed\n");
 408
 409	return ret;
 410}
 411
 412static int cdns_sierra_phy_off(struct phy *gphy)
 413{
 414	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 415
 416	return reset_control_assert(ins->lnk_rst);
 417}
 418
 419static int cdns_sierra_phy_reset(struct phy *gphy)
 420{
 421	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
 422
 423	reset_control_assert(sp->phy_rst);
 424	reset_control_deassert(sp->phy_rst);
 425	return 0;
 426};
 427
 428static const struct phy_ops ops = {
 429	.init		= cdns_sierra_phy_init,
 430	.power_on	= cdns_sierra_phy_on,
 431	.power_off	= cdns_sierra_phy_off,
 432	.reset		= cdns_sierra_phy_reset,
 433	.owner		= THIS_MODULE,
 434};
 435
 
 
 
 
 
 
 
 
 
 
 
 
 436static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
 437{
 438	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
 
 
 439	struct regmap_field *field = mux->pfdclk_sel_preg;
 440	unsigned int val;
 
 441
 442	regmap_field_read(field, &val);
 443	return clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table, 0, val);
 
 
 
 
 
 
 
 
 
 
 
 444}
 445
 446static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
 447{
 448	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
 449	struct regmap_field *plllc1en_field = mux->plllc1en_field;
 450	struct regmap_field *termen_field = mux->termen_field;
 451	struct regmap_field *field = mux->pfdclk_sel_preg;
 452	int val, ret;
 453
 454	ret = regmap_field_write(plllc1en_field, 0);
 455	ret |= regmap_field_write(termen_field, 0);
 456	if (index == 1) {
 457		ret |= regmap_field_write(plllc1en_field, 1);
 458		ret |= regmap_field_write(termen_field, 1);
 459	}
 460
 461	val = cdns_sierra_pll_mux_table[index];
 
 
 
 
 462	ret |= regmap_field_write(field, val);
 463
 464	return ret;
 465}
 466
 467static const struct clk_ops cdns_sierra_pll_mux_ops = {
 468	.set_parent = cdns_sierra_pll_mux_set_parent,
 469	.get_parent = cdns_sierra_pll_mux_get_parent,
 470};
 471
 472static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,
 473					struct regmap_field *pfdclk1_sel_field,
 474					struct regmap_field *plllc1en_field,
 475					struct regmap_field *termen_field,
 476					int clk_index)
 477{
 478	struct cdns_sierra_pll_mux *mux;
 479	struct device *dev = sp->dev;
 480	struct clk_init_data *init;
 481	const char **parent_names;
 482	unsigned int num_parents;
 483	char clk_name[100];
 484	struct clk *clk;
 485	int i;
 486
 487	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 488	if (!mux)
 489		return -ENOMEM;
 490
 491	num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
 492	parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
 493	if (!parent_names)
 494		return -ENOMEM;
 495
 496	for (i = 0; i < num_parents; i++) {
 497		clk = sp->input_clks[pll_mux_parent_index[clk_index][i]];
 498		if (IS_ERR_OR_NULL(clk)) {
 499			dev_err(dev, "No parent clock for derived_refclk\n");
 500			return PTR_ERR(clk);
 501		}
 502		parent_names[i] = __clk_get_name(clk);
 503	}
 504
 505	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);
 506
 507	init = &mux->clk_data;
 508
 509	init->ops = &cdns_sierra_pll_mux_ops;
 510	init->flags = CLK_SET_RATE_NO_REPARENT;
 511	init->parent_names = parent_names;
 512	init->num_parents = num_parents;
 513	init->name = clk_name;
 514
 515	mux->pfdclk_sel_preg = pfdclk1_sel_field;
 516	mux->plllc1en_field = plllc1en_field;
 517	mux->termen_field = termen_field;
 518	mux->hw.init = init;
 519
 520	clk = devm_clk_register(dev, &mux->hw);
 521	if (IS_ERR(clk))
 522		return PTR_ERR(clk);
 523
 524	sp->output_clks[clk_index] = clk;
 525
 526	return 0;
 527}
 528
 529static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp)
 530{
 531	struct regmap_field *pfdclk1_sel_field;
 532	struct regmap_field *plllc1en_field;
 533	struct regmap_field *termen_field;
 534	struct device *dev = sp->dev;
 535	int ret = 0, i, clk_index;
 536
 537	clk_index = CDNS_SIERRA_PLL_CMNLC;
 538	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) {
 539		pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i];
 540		plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i];
 541		termen_field = sp->cmn_refrcv_refclk_termen_preg[i];
 542
 543		ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field,
 544						   termen_field, clk_index);
 545		if (ret) {
 546			dev_err(dev, "Fail to register cmn plllc mux\n");
 547			return ret;
 548		}
 549	}
 550
 551	return 0;
 552}
 553
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 554static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp)
 555{
 556	struct device *dev = sp->dev;
 557	struct device_node *node = dev->of_node;
 558
 559	of_clk_del_provider(node);
 560}
 561
 562static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp)
 563{
 564	struct device *dev = sp->dev;
 565	struct device_node *node = dev->of_node;
 566	int ret;
 567
 568	ret = cdns_sierra_phy_register_pll_mux(sp);
 569	if (ret) {
 570		dev_err(dev, "Failed to pll mux clocks\n");
 571		return ret;
 572	}
 573
 
 
 
 
 
 
 574	sp->clk_data.clks = sp->output_clks;
 575	sp->clk_data.clk_num = CDNS_SIERRA_OUTPUT_CLOCKS;
 576	ret = of_clk_add_provider(node, of_clk_src_onecell_get, &sp->clk_data);
 577	if (ret)
 578		dev_err(dev, "Failed to add clock provider: %s\n", node->name);
 579
 580	return ret;
 581}
 582
 583static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
 584				    struct device_node *child)
 585{
 
 
 586	if (of_property_read_u32(child, "reg", &inst->mlane))
 587		return -EINVAL;
 588
 589	if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
 590		return -EINVAL;
 591
 592	if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type))
 593		return -EINVAL;
 594
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 595	return 0;
 596}
 597
 598static const struct of_device_id cdns_sierra_id_table[];
 599
 600static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
 601				       u32 block_offset, u8 reg_offset_shift,
 602				       const struct regmap_config *config)
 603{
 604	struct cdns_regmap_cdb_context *ctx;
 605
 606	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 607	if (!ctx)
 608		return ERR_PTR(-ENOMEM);
 609
 610	ctx->dev = dev;
 611	ctx->base = base + block_offset;
 612	ctx->reg_offset_shift = reg_offset_shift;
 613
 614	return devm_regmap_init(dev, NULL, ctx, config);
 615}
 616
 617static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 618{
 619	struct device *dev = sp->dev;
 620	struct regmap_field *field;
 621	struct reg_field reg_field;
 622	struct regmap *regmap;
 623	int i;
 624
 625	regmap = sp->regmap_common_cdb;
 626	field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
 627	if (IS_ERR(field)) {
 628		dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
 629		return PTR_ERR(field);
 630	}
 631	sp->macro_id_type = field;
 632
 633	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
 634		reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
 635		field = devm_regmap_field_alloc(dev, regmap, reg_field);
 636		if (IS_ERR(field)) {
 637			dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
 638			return PTR_ERR(field);
 639		}
 640		sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
 641
 642		reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
 643		field = devm_regmap_field_alloc(dev, regmap, reg_field);
 644		if (IS_ERR(field)) {
 645			dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
 646			return PTR_ERR(field);
 647		}
 648		sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
 649
 650		reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
 651		field = devm_regmap_field_alloc(dev, regmap, reg_field);
 652		if (IS_ERR(field)) {
 653			dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
 654			return PTR_ERR(field);
 655		}
 656		sp->cmn_refrcv_refclk_termen_preg[i] = field;
 657	}
 658
 659	regmap = sp->regmap_phy_config_ctrl;
 660	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
 661	if (IS_ERR(field)) {
 662		dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
 663		return PTR_ERR(field);
 664	}
 665	sp->phy_pll_cfg_1 = field;
 666
 
 
 
 
 
 
 
 
 667	for (i = 0; i < SIERRA_MAX_LANES; i++) {
 668		regmap = sp->regmap_lane_cdb[i];
 669		field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
 670		if (IS_ERR(field)) {
 671			dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 672			return PTR_ERR(field);
 673		}
 674		sp->pllctrl_lock[i] =  field;
 
 
 
 
 
 
 
 
 
 
 675	}
 676
 677	return 0;
 678}
 679
 680static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
 681				   void __iomem *base, u8 block_offset_shift,
 682				   u8 reg_offset_shift)
 683{
 684	struct device *dev = sp->dev;
 685	struct regmap *regmap;
 686	u32 block_offset;
 687	int i;
 688
 689	for (i = 0; i < SIERRA_MAX_LANES; i++) {
 690		block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
 691						      reg_offset_shift);
 692		regmap = cdns_regmap_init(dev, base, block_offset,
 693					  reg_offset_shift,
 694					  &cdns_sierra_lane_cdb_config[i]);
 695		if (IS_ERR(regmap)) {
 696			dev_err(dev, "Failed to init lane CDB regmap\n");
 697			return PTR_ERR(regmap);
 698		}
 699		sp->regmap_lane_cdb[i] = regmap;
 700	}
 701
 702	regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
 703				  reg_offset_shift,
 704				  &cdns_sierra_common_cdb_config);
 705	if (IS_ERR(regmap)) {
 706		dev_err(dev, "Failed to init common CDB regmap\n");
 707		return PTR_ERR(regmap);
 708	}
 709	sp->regmap_common_cdb = regmap;
 710
 711	block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift);
 712	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
 713				  &cdns_sierra_phy_config_ctrl_config);
 714	if (IS_ERR(regmap)) {
 715		dev_err(dev, "Failed to init PHY config and control regmap\n");
 716		return PTR_ERR(regmap);
 717	}
 718	sp->regmap_phy_config_ctrl = regmap;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 719
 720	return 0;
 721}
 722
 723static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
 724				      struct device *dev)
 725{
 726	struct clk *clk;
 727	int ret;
 728
 729	clk = devm_clk_get_optional(dev, "phy_clk");
 730	if (IS_ERR(clk)) {
 731		dev_err(dev, "failed to get clock phy_clk\n");
 732		return PTR_ERR(clk);
 733	}
 734	sp->input_clks[PHY_CLK] = clk;
 735
 736	clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
 737	if (IS_ERR(clk)) {
 738		dev_err(dev, "cmn_refclk_dig_div clock not found\n");
 739		ret = PTR_ERR(clk);
 740		return ret;
 741	}
 742	sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
 743
 744	clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
 745	if (IS_ERR(clk)) {
 746		dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
 747		ret = PTR_ERR(clk);
 748		return ret;
 749	}
 750	sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
 751
 752	clk = devm_clk_get_optional(dev, "pll0_refclk");
 753	if (IS_ERR(clk)) {
 754		dev_err(dev, "pll0_refclk clock not found\n");
 755		ret = PTR_ERR(clk);
 756		return ret;
 757	}
 758	sp->input_clks[PLL0_REFCLK] = clk;
 759
 760	clk = devm_clk_get_optional(dev, "pll1_refclk");
 761	if (IS_ERR(clk)) {
 762		dev_err(dev, "pll1_refclk clock not found\n");
 763		ret = PTR_ERR(clk);
 764		return ret;
 765	}
 766	sp->input_clks[PLL1_REFCLK] = clk;
 767
 768	return 0;
 769}
 770
 771static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
 772{
 
 
 773	int ret;
 774
 
 
 
 
 
 
 
 775	ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
 776	if (ret)
 777		return ret;
 778
 
 
 
 
 
 
 
 779	ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
 780	if (ret)
 781		goto err_pll_cmnlc;
 782
 783	ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
 784	if (ret)
 785		goto err_pll_cmnlc1;
 786
 787	return 0;
 788
 789err_pll_cmnlc1:
 790	clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
 791
 792err_pll_cmnlc:
 793	clk_disable_unprepare(sp->input_clks[PHY_CLK]);
 794
 795	return ret;
 796}
 797
 798static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
 799{
 800	clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
 801	clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
 802	clk_disable_unprepare(sp->input_clks[PHY_CLK]);
 
 803}
 804
 805static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
 806				      struct device *dev)
 807{
 808	struct reset_control *rst;
 809
 810	rst = devm_reset_control_get_exclusive(dev, "sierra_reset");
 811	if (IS_ERR(rst)) {
 812		dev_err(dev, "failed to get reset\n");
 813		return PTR_ERR(rst);
 814	}
 815	sp->phy_rst = rst;
 816
 817	rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
 818	if (IS_ERR(rst)) {
 819		dev_err(dev, "failed to get apb reset\n");
 820		return PTR_ERR(rst);
 821	}
 822	sp->apb_rst = rst;
 823
 824	return 0;
 825}
 826
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 827static int cdns_sierra_phy_probe(struct platform_device *pdev)
 828{
 829	struct cdns_sierra_phy *sp;
 830	struct phy_provider *phy_provider;
 831	struct device *dev = &pdev->dev;
 832	const struct of_device_id *match;
 833	struct cdns_sierra_data *data;
 834	unsigned int id_value;
 835	int i, ret, node = 0;
 836	void __iomem *base;
 837	struct device_node *dn = dev->of_node, *child;
 838
 839	if (of_get_child_count(dn) == 0)
 840		return -ENODEV;
 841
 842	/* Get init data for this PHY */
 843	match = of_match_device(cdns_sierra_id_table, dev);
 844	if (!match)
 845		return -EINVAL;
 846
 847	data = (struct cdns_sierra_data *)match->data;
 848
 849	sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
 850	if (!sp)
 851		return -ENOMEM;
 852	dev_set_drvdata(dev, sp);
 853	sp->dev = dev;
 854	sp->init_data = data;
 855
 856	base = devm_platform_ioremap_resource(pdev, 0);
 857	if (IS_ERR(base)) {
 858		dev_err(dev, "missing \"reg\"\n");
 859		return PTR_ERR(base);
 860	}
 861
 862	ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
 863				      data->reg_offset_shift);
 864	if (ret)
 865		return ret;
 866
 867	ret = cdns_regfield_init(sp);
 868	if (ret)
 869		return ret;
 870
 871	platform_set_drvdata(pdev, sp);
 872
 873	ret = cdns_sierra_phy_get_clocks(sp, dev);
 874	if (ret)
 875		return ret;
 876
 877	ret = cdns_sierra_clk_register(sp);
 878	if (ret)
 879		return ret;
 880
 881	ret = cdns_sierra_phy_get_resets(sp, dev);
 882	if (ret)
 883		goto unregister_clk;
 884
 885	ret = cdns_sierra_phy_enable_clocks(sp);
 886	if (ret)
 887		goto unregister_clk;
 888
 889	/* Enable APB */
 890	reset_control_deassert(sp->apb_rst);
 
 
 
 
 
 
 
 
 
 
 891
 892	/* Check that PHY is present */
 893	regmap_field_read(sp->macro_id_type, &id_value);
 894	if  (sp->init_data->id_value != id_value) {
 895		ret = -EINVAL;
 896		goto clk_disable;
 897	}
 898
 899	sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");
 900
 901	for_each_available_child_of_node(dn, child) {
 902		struct phy *gphy;
 903
 904		if (!(of_node_name_eq(child, "phy") ||
 905		      of_node_name_eq(child, "link")))
 906			continue;
 907
 908		sp->phys[node].lnk_rst =
 909			of_reset_control_array_get_exclusive(child);
 910
 911		if (IS_ERR(sp->phys[node].lnk_rst)) {
 912			dev_err(dev, "failed to get reset %s\n",
 913				child->full_name);
 914			ret = PTR_ERR(sp->phys[node].lnk_rst);
 915			goto put_child2;
 
 916		}
 917
 918		if (!sp->autoconf) {
 919			ret = cdns_sierra_get_optional(&sp->phys[node], child);
 920			if (ret) {
 921				dev_err(dev, "missing property in node %s\n",
 922					child->name);
 923				goto put_child;
 
 
 924			}
 925		}
 926
 927		sp->num_lanes += sp->phys[node].num_lanes;
 928
 929		gphy = devm_phy_create(dev, child, &ops);
 930
 
 
 931		if (IS_ERR(gphy)) {
 932			ret = PTR_ERR(gphy);
 933			goto put_child;
 
 
 934		}
 935		sp->phys[node].phy = gphy;
 936		phy_set_drvdata(gphy, &sp->phys[node]);
 937
 938		node++;
 939	}
 940	sp->nsubnodes = node;
 941
 942	if (sp->num_lanes > SIERRA_MAX_LANES) {
 943		ret = -EINVAL;
 944		dev_err(dev, "Invalid lane configuration\n");
 945		goto put_child2;
 946	}
 947
 948	/* If more than one subnode, configure the PHY as multilink */
 949	if (!sp->autoconf && sp->nsubnodes > 1)
 950		regmap_field_write(sp->phy_pll_cfg_1, 0x1);
 
 
 
 951
 952	pm_runtime_enable(dev);
 953	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 954	return PTR_ERR_OR_ZERO(phy_provider);
 
 
 
 955
 956put_child:
 957	node++;
 958put_child2:
 959	for (i = 0; i < node; i++)
 960		reset_control_put(sp->phys[i].lnk_rst);
 961	of_node_put(child);
 
 
 962clk_disable:
 963	cdns_sierra_phy_disable_clocks(sp);
 964	reset_control_assert(sp->apb_rst);
 965unregister_clk:
 966	cdns_sierra_clk_unregister(sp);
 967	return ret;
 968}
 969
 970static int cdns_sierra_phy_remove(struct platform_device *pdev)
 971{
 972	struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
 973	int i;
 974
 975	reset_control_assert(phy->phy_rst);
 976	reset_control_assert(phy->apb_rst);
 977	pm_runtime_disable(&pdev->dev);
 978
 979	cdns_sierra_phy_disable_clocks(phy);
 980	/*
 981	 * The device level resets will be put automatically.
 982	 * Need to put the subnode resets here though.
 983	 */
 984	for (i = 0; i < phy->nsubnodes; i++) {
 985		reset_control_assert(phy->phys[i].lnk_rst);
 986		reset_control_put(phy->phys[i].lnk_rst);
 987	}
 988
 989	cdns_sierra_clk_unregister(phy);
 990
 991	return 0;
 992}
 993
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 994/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
 995static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
 996	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 997	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 998	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
 999	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1000	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
1001};
1002
1003/* refclk100MHz_32b_PCIe_ln_ext_ssc */
1004static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
 
 
 
 
1005	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1006	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1007	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1008	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1009	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 
 
1010	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1011	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1012};
1013
1014/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
1015static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
1016	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1017	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1018	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1019	{0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
1020};
1021
1022/* refclk100MHz_20b_USB_ln_ext_ssc */
1023static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
1024	{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
1025	{0x000F, SIERRA_DET_STANDEC_B_PREG},
1026	{0x55A5, SIERRA_DET_STANDEC_C_PREG},
1027	{0x69ad, SIERRA_DET_STANDEC_D_PREG},
1028	{0x0241, SIERRA_DET_STANDEC_E_PREG},
1029	{0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
1030	{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
1031	{0xCF00, SIERRA_PSM_DIAG_PREG},
1032	{0x001F, SIERRA_PSC_TX_A0_PREG},
1033	{0x0007, SIERRA_PSC_TX_A1_PREG},
1034	{0x0003, SIERRA_PSC_TX_A2_PREG},
1035	{0x0003, SIERRA_PSC_TX_A3_PREG},
1036	{0x0FFF, SIERRA_PSC_RX_A0_PREG},
1037	{0x0003, SIERRA_PSC_RX_A1_PREG},
1038	{0x0003, SIERRA_PSC_RX_A2_PREG},
1039	{0x0001, SIERRA_PSC_RX_A3_PREG},
1040	{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
1041	{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
1042	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
1043	{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
1044	{0x2512, SIERRA_DFE_BIASTRIM_PREG},
1045	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1046	{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
1047	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1048	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1049	{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1050	{0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1051	{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
1052	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1053	{0x0000, SIERRA_CREQ_SPARE_PREG},
1054	{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1055	{0x8452, SIERRA_CTLELUT_CTRL_PREG},
1056	{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
1057	{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
1058	{0x0003, SIERRA_DEQ_PHALIGN_CTRL},
1059	{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
1060	{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1061	{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1062	{0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1063	{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1064	{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
1065	{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
1066	{0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
1067	{0x0014, SIERRA_DEQ_GLUT0},
1068	{0x0014, SIERRA_DEQ_GLUT1},
1069	{0x0014, SIERRA_DEQ_GLUT2},
1070	{0x0014, SIERRA_DEQ_GLUT3},
1071	{0x0014, SIERRA_DEQ_GLUT4},
1072	{0x0014, SIERRA_DEQ_GLUT5},
1073	{0x0014, SIERRA_DEQ_GLUT6},
1074	{0x0014, SIERRA_DEQ_GLUT7},
1075	{0x0014, SIERRA_DEQ_GLUT8},
1076	{0x0014, SIERRA_DEQ_GLUT9},
1077	{0x0014, SIERRA_DEQ_GLUT10},
1078	{0x0014, SIERRA_DEQ_GLUT11},
1079	{0x0014, SIERRA_DEQ_GLUT12},
1080	{0x0014, SIERRA_DEQ_GLUT13},
1081	{0x0014, SIERRA_DEQ_GLUT14},
1082	{0x0014, SIERRA_DEQ_GLUT15},
1083	{0x0014, SIERRA_DEQ_GLUT16},
1084	{0x0BAE, SIERRA_DEQ_ALUT0},
1085	{0x0AEB, SIERRA_DEQ_ALUT1},
1086	{0x0A28, SIERRA_DEQ_ALUT2},
1087	{0x0965, SIERRA_DEQ_ALUT3},
1088	{0x08A2, SIERRA_DEQ_ALUT4},
1089	{0x07DF, SIERRA_DEQ_ALUT5},
1090	{0x071C, SIERRA_DEQ_ALUT6},
1091	{0x0659, SIERRA_DEQ_ALUT7},
1092	{0x0596, SIERRA_DEQ_ALUT8},
1093	{0x0514, SIERRA_DEQ_ALUT9},
1094	{0x0492, SIERRA_DEQ_ALUT10},
1095	{0x0410, SIERRA_DEQ_ALUT11},
1096	{0x038E, SIERRA_DEQ_ALUT12},
1097	{0x030C, SIERRA_DEQ_ALUT13},
1098	{0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
1099	{0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
1100	{0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1101	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1102	{0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
1103	{0x0033, SIERRA_DEQ_PICTRL_PREG},
1104	{0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
1105	{0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
1106	{0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
1107	{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1108	{0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
1109	{0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
1110	{0x000F, SIERRA_LFPSFILT_NS_PREG},
1111	{0x0009, SIERRA_LFPSFILT_RD_PREG},
1112	{0x0001, SIERRA_LFPSFILT_MP_PREG},
1113	{0x6013, SIERRA_SIGDET_SUPPORT_PREG},
1114	{0x8013, SIERRA_SDFILT_H2L_A_PREG},
1115	{0x8009, SIERRA_SDFILT_L2H_PREG},
1116	{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
1117	{0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1118	{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
1119};
1120
 
 
 
 
 
 
 
 
 
 
1121static const struct cdns_sierra_data cdns_map_sierra = {
1122	SIERRA_MACRO_ID,
1123	0x2,
1124	0x2,
1125	ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
1126	ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
1127	ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
1128	ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
1129	cdns_pcie_cmn_regs_ext_ssc,
1130	cdns_pcie_ln_regs_ext_ssc,
1131	cdns_usb_cmn_regs_ext_ssc,
1132	cdns_usb_ln_regs_ext_ssc,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1133};
1134
1135static const struct cdns_sierra_data cdns_ti_map_sierra = {
1136	SIERRA_MACRO_ID,
1137	0x0,
1138	0x1,
1139	ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
1140	ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
1141	ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
1142	ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
1143	cdns_pcie_cmn_regs_ext_ssc,
1144	cdns_pcie_ln_regs_ext_ssc,
1145	cdns_usb_cmn_regs_ext_ssc,
1146	cdns_usb_ln_regs_ext_ssc,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1147};
1148
1149static const struct of_device_id cdns_sierra_id_table[] = {
1150	{
1151		.compatible = "cdns,sierra-phy-t0",
1152		.data = &cdns_map_sierra,
1153	},
1154	{
1155		.compatible = "ti,sierra-phy-t0",
1156		.data = &cdns_ti_map_sierra,
1157	},
1158	{}
1159};
1160MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);
1161
1162static struct platform_driver cdns_sierra_driver = {
1163	.probe		= cdns_sierra_phy_probe,
1164	.remove		= cdns_sierra_phy_remove,
1165	.driver		= {
1166		.name	= "cdns-sierra-phy",
1167		.of_match_table = cdns_sierra_id_table,
1168	},
1169};
1170module_platform_driver(cdns_sierra_driver);
1171
1172MODULE_ALIAS("platform:cdns_sierra");
1173MODULE_AUTHOR("Cadence Design Systems");
1174MODULE_DESCRIPTION("CDNS sierra phy driver");
1175MODULE_LICENSE("GPL v2");