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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
24 */
25
26#include "amdgpu.h"
27#include "amdgpu_drv.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_dpm.h"
30#include "atom.h"
31#include <linux/pci.h>
32#include <linux/hwmon.h>
33#include <linux/hwmon-sysfs.h>
34#include <linux/nospec.h>
35#include <linux/pm_runtime.h>
36#include <asm/processor.h>
37
38static const struct cg_flag_name clocks[] = {
39 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
40 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
41 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
42 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
43 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
44 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
45 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
48 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
49 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
50 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
51 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
52 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
53 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
54 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
56 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
57 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
59 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
62 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
63 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
64 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
65 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
66 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
67 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
68 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
69 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
70 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
71 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
72 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
73 {0, NULL},
74};
75
76static const struct hwmon_temp_label {
77 enum PP_HWMON_TEMP channel;
78 const char *label;
79} temp_label[] = {
80 {PP_TEMP_EDGE, "edge"},
81 {PP_TEMP_JUNCTION, "junction"},
82 {PP_TEMP_MEM, "mem"},
83};
84
85const char * const amdgpu_pp_profile_name[] = {
86 "BOOTUP_DEFAULT",
87 "3D_FULL_SCREEN",
88 "POWER_SAVING",
89 "VIDEO",
90 "VR",
91 "COMPUTE",
92 "CUSTOM",
93 "WINDOW_3D",
94};
95
96/**
97 * DOC: power_dpm_state
98 *
99 * The power_dpm_state file is a legacy interface and is only provided for
100 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
101 * certain power related parameters. The file power_dpm_state is used for this.
102 * It accepts the following arguments:
103 *
104 * - battery
105 *
106 * - balanced
107 *
108 * - performance
109 *
110 * battery
111 *
112 * On older GPUs, the vbios provided a special power state for battery
113 * operation. Selecting battery switched to this state. This is no
114 * longer provided on newer GPUs so the option does nothing in that case.
115 *
116 * balanced
117 *
118 * On older GPUs, the vbios provided a special power state for balanced
119 * operation. Selecting balanced switched to this state. This is no
120 * longer provided on newer GPUs so the option does nothing in that case.
121 *
122 * performance
123 *
124 * On older GPUs, the vbios provided a special power state for performance
125 * operation. Selecting performance switched to this state. This is no
126 * longer provided on newer GPUs so the option does nothing in that case.
127 *
128 */
129
130static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
131 struct device_attribute *attr,
132 char *buf)
133{
134 struct drm_device *ddev = dev_get_drvdata(dev);
135 struct amdgpu_device *adev = drm_to_adev(ddev);
136 enum amd_pm_state_type pm;
137 int ret;
138
139 if (amdgpu_in_reset(adev))
140 return -EPERM;
141 if (adev->in_suspend && !adev->in_runpm)
142 return -EPERM;
143
144 ret = pm_runtime_get_sync(ddev->dev);
145 if (ret < 0) {
146 pm_runtime_put_autosuspend(ddev->dev);
147 return ret;
148 }
149
150 amdgpu_dpm_get_current_power_state(adev, &pm);
151
152 pm_runtime_mark_last_busy(ddev->dev);
153 pm_runtime_put_autosuspend(ddev->dev);
154
155 return sysfs_emit(buf, "%s\n",
156 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
157 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
158}
159
160static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
161 struct device_attribute *attr,
162 const char *buf,
163 size_t count)
164{
165 struct drm_device *ddev = dev_get_drvdata(dev);
166 struct amdgpu_device *adev = drm_to_adev(ddev);
167 enum amd_pm_state_type state;
168 int ret;
169
170 if (amdgpu_in_reset(adev))
171 return -EPERM;
172 if (adev->in_suspend && !adev->in_runpm)
173 return -EPERM;
174
175 if (strncmp("battery", buf, strlen("battery")) == 0)
176 state = POWER_STATE_TYPE_BATTERY;
177 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
178 state = POWER_STATE_TYPE_BALANCED;
179 else if (strncmp("performance", buf, strlen("performance")) == 0)
180 state = POWER_STATE_TYPE_PERFORMANCE;
181 else
182 return -EINVAL;
183
184 ret = pm_runtime_get_sync(ddev->dev);
185 if (ret < 0) {
186 pm_runtime_put_autosuspend(ddev->dev);
187 return ret;
188 }
189
190 amdgpu_dpm_set_power_state(adev, state);
191
192 pm_runtime_mark_last_busy(ddev->dev);
193 pm_runtime_put_autosuspend(ddev->dev);
194
195 return count;
196}
197
198
199/**
200 * DOC: power_dpm_force_performance_level
201 *
202 * The amdgpu driver provides a sysfs API for adjusting certain power
203 * related parameters. The file power_dpm_force_performance_level is
204 * used for this. It accepts the following arguments:
205 *
206 * - auto
207 *
208 * - low
209 *
210 * - high
211 *
212 * - manual
213 *
214 * - profile_standard
215 *
216 * - profile_min_sclk
217 *
218 * - profile_min_mclk
219 *
220 * - profile_peak
221 *
222 * auto
223 *
224 * When auto is selected, the driver will attempt to dynamically select
225 * the optimal power profile for current conditions in the driver.
226 *
227 * low
228 *
229 * When low is selected, the clocks are forced to the lowest power state.
230 *
231 * high
232 *
233 * When high is selected, the clocks are forced to the highest power state.
234 *
235 * manual
236 *
237 * When manual is selected, the user can manually adjust which power states
238 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
239 * and pp_dpm_pcie files and adjust the power state transition heuristics
240 * via the pp_power_profile_mode sysfs file.
241 *
242 * profile_standard
243 * profile_min_sclk
244 * profile_min_mclk
245 * profile_peak
246 *
247 * When the profiling modes are selected, clock and power gating are
248 * disabled and the clocks are set for different profiling cases. This
249 * mode is recommended for profiling specific work loads where you do
250 * not want clock or power gating for clock fluctuation to interfere
251 * with your results. profile_standard sets the clocks to a fixed clock
252 * level which varies from asic to asic. profile_min_sclk forces the sclk
253 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
254 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
255 *
256 */
257
258static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
259 struct device_attribute *attr,
260 char *buf)
261{
262 struct drm_device *ddev = dev_get_drvdata(dev);
263 struct amdgpu_device *adev = drm_to_adev(ddev);
264 enum amd_dpm_forced_level level = 0xff;
265 int ret;
266
267 if (amdgpu_in_reset(adev))
268 return -EPERM;
269 if (adev->in_suspend && !adev->in_runpm)
270 return -EPERM;
271
272 ret = pm_runtime_get_sync(ddev->dev);
273 if (ret < 0) {
274 pm_runtime_put_autosuspend(ddev->dev);
275 return ret;
276 }
277
278 level = amdgpu_dpm_get_performance_level(adev);
279
280 pm_runtime_mark_last_busy(ddev->dev);
281 pm_runtime_put_autosuspend(ddev->dev);
282
283 return sysfs_emit(buf, "%s\n",
284 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
285 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
286 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
287 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
288 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
289 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
290 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
291 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
292 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
293 "unknown");
294}
295
296static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
297 struct device_attribute *attr,
298 const char *buf,
299 size_t count)
300{
301 struct drm_device *ddev = dev_get_drvdata(dev);
302 struct amdgpu_device *adev = drm_to_adev(ddev);
303 enum amd_dpm_forced_level level;
304 int ret = 0;
305
306 if (amdgpu_in_reset(adev))
307 return -EPERM;
308 if (adev->in_suspend && !adev->in_runpm)
309 return -EPERM;
310
311 if (strncmp("low", buf, strlen("low")) == 0) {
312 level = AMD_DPM_FORCED_LEVEL_LOW;
313 } else if (strncmp("high", buf, strlen("high")) == 0) {
314 level = AMD_DPM_FORCED_LEVEL_HIGH;
315 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
316 level = AMD_DPM_FORCED_LEVEL_AUTO;
317 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
318 level = AMD_DPM_FORCED_LEVEL_MANUAL;
319 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
320 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
321 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
322 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
323 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
324 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
325 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
326 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
327 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
328 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
329 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
330 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
331 } else {
332 return -EINVAL;
333 }
334
335 ret = pm_runtime_get_sync(ddev->dev);
336 if (ret < 0) {
337 pm_runtime_put_autosuspend(ddev->dev);
338 return ret;
339 }
340
341 mutex_lock(&adev->pm.stable_pstate_ctx_lock);
342 if (amdgpu_dpm_force_performance_level(adev, level)) {
343 pm_runtime_mark_last_busy(ddev->dev);
344 pm_runtime_put_autosuspend(ddev->dev);
345 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
346 return -EINVAL;
347 }
348 /* override whatever a user ctx may have set */
349 adev->pm.stable_pstate_ctx = NULL;
350 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
351
352 pm_runtime_mark_last_busy(ddev->dev);
353 pm_runtime_put_autosuspend(ddev->dev);
354
355 return count;
356}
357
358static ssize_t amdgpu_get_pp_num_states(struct device *dev,
359 struct device_attribute *attr,
360 char *buf)
361{
362 struct drm_device *ddev = dev_get_drvdata(dev);
363 struct amdgpu_device *adev = drm_to_adev(ddev);
364 struct pp_states_info data;
365 uint32_t i;
366 int buf_len, ret;
367
368 if (amdgpu_in_reset(adev))
369 return -EPERM;
370 if (adev->in_suspend && !adev->in_runpm)
371 return -EPERM;
372
373 ret = pm_runtime_get_sync(ddev->dev);
374 if (ret < 0) {
375 pm_runtime_put_autosuspend(ddev->dev);
376 return ret;
377 }
378
379 if (amdgpu_dpm_get_pp_num_states(adev, &data))
380 memset(&data, 0, sizeof(data));
381
382 pm_runtime_mark_last_busy(ddev->dev);
383 pm_runtime_put_autosuspend(ddev->dev);
384
385 buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
386 for (i = 0; i < data.nums; i++)
387 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
388 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
389 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
390 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
391 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
392
393 return buf_len;
394}
395
396static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
397 struct device_attribute *attr,
398 char *buf)
399{
400 struct drm_device *ddev = dev_get_drvdata(dev);
401 struct amdgpu_device *adev = drm_to_adev(ddev);
402 struct pp_states_info data = {0};
403 enum amd_pm_state_type pm = 0;
404 int i = 0, ret = 0;
405
406 if (amdgpu_in_reset(adev))
407 return -EPERM;
408 if (adev->in_suspend && !adev->in_runpm)
409 return -EPERM;
410
411 ret = pm_runtime_get_sync(ddev->dev);
412 if (ret < 0) {
413 pm_runtime_put_autosuspend(ddev->dev);
414 return ret;
415 }
416
417 amdgpu_dpm_get_current_power_state(adev, &pm);
418
419 ret = amdgpu_dpm_get_pp_num_states(adev, &data);
420
421 pm_runtime_mark_last_busy(ddev->dev);
422 pm_runtime_put_autosuspend(ddev->dev);
423
424 if (ret)
425 return ret;
426
427 for (i = 0; i < data.nums; i++) {
428 if (pm == data.states[i])
429 break;
430 }
431
432 if (i == data.nums)
433 i = -EINVAL;
434
435 return sysfs_emit(buf, "%d\n", i);
436}
437
438static ssize_t amdgpu_get_pp_force_state(struct device *dev,
439 struct device_attribute *attr,
440 char *buf)
441{
442 struct drm_device *ddev = dev_get_drvdata(dev);
443 struct amdgpu_device *adev = drm_to_adev(ddev);
444
445 if (amdgpu_in_reset(adev))
446 return -EPERM;
447 if (adev->in_suspend && !adev->in_runpm)
448 return -EPERM;
449
450 if (adev->pm.pp_force_state_enabled)
451 return amdgpu_get_pp_cur_state(dev, attr, buf);
452 else
453 return sysfs_emit(buf, "\n");
454}
455
456static ssize_t amdgpu_set_pp_force_state(struct device *dev,
457 struct device_attribute *attr,
458 const char *buf,
459 size_t count)
460{
461 struct drm_device *ddev = dev_get_drvdata(dev);
462 struct amdgpu_device *adev = drm_to_adev(ddev);
463 enum amd_pm_state_type state = 0;
464 struct pp_states_info data;
465 unsigned long idx;
466 int ret;
467
468 if (amdgpu_in_reset(adev))
469 return -EPERM;
470 if (adev->in_suspend && !adev->in_runpm)
471 return -EPERM;
472
473 adev->pm.pp_force_state_enabled = false;
474
475 if (strlen(buf) == 1)
476 return count;
477
478 ret = kstrtoul(buf, 0, &idx);
479 if (ret || idx >= ARRAY_SIZE(data.states))
480 return -EINVAL;
481
482 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
483
484 ret = pm_runtime_get_sync(ddev->dev);
485 if (ret < 0) {
486 pm_runtime_put_autosuspend(ddev->dev);
487 return ret;
488 }
489
490 ret = amdgpu_dpm_get_pp_num_states(adev, &data);
491 if (ret)
492 goto err_out;
493
494 state = data.states[idx];
495
496 /* only set user selected power states */
497 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
498 state != POWER_STATE_TYPE_DEFAULT) {
499 ret = amdgpu_dpm_dispatch_task(adev,
500 AMD_PP_TASK_ENABLE_USER_STATE, &state);
501 if (ret)
502 goto err_out;
503
504 adev->pm.pp_force_state_enabled = true;
505 }
506
507 pm_runtime_mark_last_busy(ddev->dev);
508 pm_runtime_put_autosuspend(ddev->dev);
509
510 return count;
511
512err_out:
513 pm_runtime_mark_last_busy(ddev->dev);
514 pm_runtime_put_autosuspend(ddev->dev);
515 return ret;
516}
517
518/**
519 * DOC: pp_table
520 *
521 * The amdgpu driver provides a sysfs API for uploading new powerplay
522 * tables. The file pp_table is used for this. Reading the file
523 * will dump the current power play table. Writing to the file
524 * will attempt to upload a new powerplay table and re-initialize
525 * powerplay using that new table.
526 *
527 */
528
529static ssize_t amdgpu_get_pp_table(struct device *dev,
530 struct device_attribute *attr,
531 char *buf)
532{
533 struct drm_device *ddev = dev_get_drvdata(dev);
534 struct amdgpu_device *adev = drm_to_adev(ddev);
535 char *table = NULL;
536 int size, ret;
537
538 if (amdgpu_in_reset(adev))
539 return -EPERM;
540 if (adev->in_suspend && !adev->in_runpm)
541 return -EPERM;
542
543 ret = pm_runtime_get_sync(ddev->dev);
544 if (ret < 0) {
545 pm_runtime_put_autosuspend(ddev->dev);
546 return ret;
547 }
548
549 size = amdgpu_dpm_get_pp_table(adev, &table);
550
551 pm_runtime_mark_last_busy(ddev->dev);
552 pm_runtime_put_autosuspend(ddev->dev);
553
554 if (size <= 0)
555 return size;
556
557 if (size >= PAGE_SIZE)
558 size = PAGE_SIZE - 1;
559
560 memcpy(buf, table, size);
561
562 return size;
563}
564
565static ssize_t amdgpu_set_pp_table(struct device *dev,
566 struct device_attribute *attr,
567 const char *buf,
568 size_t count)
569{
570 struct drm_device *ddev = dev_get_drvdata(dev);
571 struct amdgpu_device *adev = drm_to_adev(ddev);
572 int ret = 0;
573
574 if (amdgpu_in_reset(adev))
575 return -EPERM;
576 if (adev->in_suspend && !adev->in_runpm)
577 return -EPERM;
578
579 ret = pm_runtime_get_sync(ddev->dev);
580 if (ret < 0) {
581 pm_runtime_put_autosuspend(ddev->dev);
582 return ret;
583 }
584
585 ret = amdgpu_dpm_set_pp_table(adev, buf, count);
586
587 pm_runtime_mark_last_busy(ddev->dev);
588 pm_runtime_put_autosuspend(ddev->dev);
589
590 if (ret)
591 return ret;
592
593 return count;
594}
595
596/**
597 * DOC: pp_od_clk_voltage
598 *
599 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
600 * in each power level within a power state. The pp_od_clk_voltage is used for
601 * this.
602 *
603 * Note that the actual memory controller clock rate are exposed, not
604 * the effective memory clock of the DRAMs. To translate it, use the
605 * following formula:
606 *
607 * Clock conversion (Mhz):
608 *
609 * HBM: effective_memory_clock = memory_controller_clock * 1
610 *
611 * G5: effective_memory_clock = memory_controller_clock * 1
612 *
613 * G6: effective_memory_clock = memory_controller_clock * 2
614 *
615 * DRAM data rate (MT/s):
616 *
617 * HBM: effective_memory_clock * 2 = data_rate
618 *
619 * G5: effective_memory_clock * 4 = data_rate
620 *
621 * G6: effective_memory_clock * 8 = data_rate
622 *
623 * Bandwidth (MB/s):
624 *
625 * data_rate * vram_bit_width / 8 = memory_bandwidth
626 *
627 * Some examples:
628 *
629 * G5 on RX460:
630 *
631 * memory_controller_clock = 1750 Mhz
632 *
633 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
634 *
635 * data rate = 1750 * 4 = 7000 MT/s
636 *
637 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
638 *
639 * G6 on RX5700:
640 *
641 * memory_controller_clock = 875 Mhz
642 *
643 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
644 *
645 * data rate = 1750 * 8 = 14000 MT/s
646 *
647 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
648 *
649 * < For Vega10 and previous ASICs >
650 *
651 * Reading the file will display:
652 *
653 * - a list of engine clock levels and voltages labeled OD_SCLK
654 *
655 * - a list of memory clock levels and voltages labeled OD_MCLK
656 *
657 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
658 *
659 * To manually adjust these settings, first select manual using
660 * power_dpm_force_performance_level. Enter a new value for each
661 * level by writing a string that contains "s/m level clock voltage" to
662 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
663 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
664 * 810 mV. When you have edited all of the states as needed, write
665 * "c" (commit) to the file to commit your changes. If you want to reset to the
666 * default power levels, write "r" (reset) to the file to reset them.
667 *
668 *
669 * < For Vega20 and newer ASICs >
670 *
671 * Reading the file will display:
672 *
673 * - minimum and maximum engine clock labeled OD_SCLK
674 *
675 * - minimum(not available for Vega20 and Navi1x) and maximum memory
676 * clock labeled OD_MCLK
677 *
678 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
679 * They can be used to calibrate the sclk voltage curve.
680 *
681 * - voltage offset(in mV) applied on target voltage calculation.
682 * This is available for Sienna Cichlid, Navy Flounder and Dimgrey
683 * Cavefish. For these ASICs, the target voltage calculation can be
684 * illustrated by "voltage = voltage calculated from v/f curve +
685 * overdrive vddgfx offset"
686 *
687 * - a list of valid ranges for sclk, mclk, and voltage curve points
688 * labeled OD_RANGE
689 *
690 * < For APUs >
691 *
692 * Reading the file will display:
693 *
694 * - minimum and maximum engine clock labeled OD_SCLK
695 *
696 * - a list of valid ranges for sclk labeled OD_RANGE
697 *
698 * < For VanGogh >
699 *
700 * Reading the file will display:
701 *
702 * - minimum and maximum engine clock labeled OD_SCLK
703 * - minimum and maximum core clocks labeled OD_CCLK
704 *
705 * - a list of valid ranges for sclk and cclk labeled OD_RANGE
706 *
707 * To manually adjust these settings:
708 *
709 * - First select manual using power_dpm_force_performance_level
710 *
711 * - For clock frequency setting, enter a new value by writing a
712 * string that contains "s/m index clock" to the file. The index
713 * should be 0 if to set minimum clock. And 1 if to set maximum
714 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
715 * "m 1 800" will update maximum mclk to be 800Mhz. For core
716 * clocks on VanGogh, the string contains "p core index clock".
717 * E.g., "p 2 0 800" would set the minimum core clock on core
718 * 2 to 800Mhz.
719 *
720 * For sclk voltage curve, enter the new values by writing a
721 * string that contains "vc point clock voltage" to the file. The
722 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
723 * update point1 with clock set as 300Mhz and voltage as
724 * 600mV. "vc 2 1000 1000" will update point3 with clock set
725 * as 1000Mhz and voltage 1000mV.
726 *
727 * To update the voltage offset applied for gfxclk/voltage calculation,
728 * enter the new value by writing a string that contains "vo offset".
729 * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
730 * And the offset can be a positive or negative value.
731 *
732 * - When you have edited all of the states as needed, write "c" (commit)
733 * to the file to commit your changes
734 *
735 * - If you want to reset to the default power levels, write "r" (reset)
736 * to the file to reset them
737 *
738 */
739
740static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
741 struct device_attribute *attr,
742 const char *buf,
743 size_t count)
744{
745 struct drm_device *ddev = dev_get_drvdata(dev);
746 struct amdgpu_device *adev = drm_to_adev(ddev);
747 int ret;
748 uint32_t parameter_size = 0;
749 long parameter[64];
750 char buf_cpy[128];
751 char *tmp_str;
752 char *sub_str;
753 const char delimiter[3] = {' ', '\n', '\0'};
754 uint32_t type;
755
756 if (amdgpu_in_reset(adev))
757 return -EPERM;
758 if (adev->in_suspend && !adev->in_runpm)
759 return -EPERM;
760
761 if (count > 127)
762 return -EINVAL;
763
764 if (*buf == 's')
765 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
766 else if (*buf == 'p')
767 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
768 else if (*buf == 'm')
769 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
770 else if(*buf == 'r')
771 type = PP_OD_RESTORE_DEFAULT_TABLE;
772 else if (*buf == 'c')
773 type = PP_OD_COMMIT_DPM_TABLE;
774 else if (!strncmp(buf, "vc", 2))
775 type = PP_OD_EDIT_VDDC_CURVE;
776 else if (!strncmp(buf, "vo", 2))
777 type = PP_OD_EDIT_VDDGFX_OFFSET;
778 else
779 return -EINVAL;
780
781 memcpy(buf_cpy, buf, count+1);
782
783 tmp_str = buf_cpy;
784
785 if ((type == PP_OD_EDIT_VDDC_CURVE) ||
786 (type == PP_OD_EDIT_VDDGFX_OFFSET))
787 tmp_str++;
788 while (isspace(*++tmp_str));
789
790 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
791 if (strlen(sub_str) == 0)
792 continue;
793 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
794 if (ret)
795 return -EINVAL;
796 parameter_size++;
797
798 while (isspace(*tmp_str))
799 tmp_str++;
800 }
801
802 ret = pm_runtime_get_sync(ddev->dev);
803 if (ret < 0) {
804 pm_runtime_put_autosuspend(ddev->dev);
805 return ret;
806 }
807
808 if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
809 type,
810 parameter,
811 parameter_size))
812 goto err_out;
813
814 if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
815 parameter, parameter_size))
816 goto err_out;
817
818 if (type == PP_OD_COMMIT_DPM_TABLE) {
819 if (amdgpu_dpm_dispatch_task(adev,
820 AMD_PP_TASK_READJUST_POWER_STATE,
821 NULL))
822 goto err_out;
823 }
824
825 pm_runtime_mark_last_busy(ddev->dev);
826 pm_runtime_put_autosuspend(ddev->dev);
827
828 return count;
829
830err_out:
831 pm_runtime_mark_last_busy(ddev->dev);
832 pm_runtime_put_autosuspend(ddev->dev);
833 return -EINVAL;
834}
835
836static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
837 struct device_attribute *attr,
838 char *buf)
839{
840 struct drm_device *ddev = dev_get_drvdata(dev);
841 struct amdgpu_device *adev = drm_to_adev(ddev);
842 int size = 0;
843 int ret;
844 enum pp_clock_type od_clocks[6] = {
845 OD_SCLK,
846 OD_MCLK,
847 OD_VDDC_CURVE,
848 OD_RANGE,
849 OD_VDDGFX_OFFSET,
850 OD_CCLK,
851 };
852 uint clk_index;
853
854 if (amdgpu_in_reset(adev))
855 return -EPERM;
856 if (adev->in_suspend && !adev->in_runpm)
857 return -EPERM;
858
859 ret = pm_runtime_get_sync(ddev->dev);
860 if (ret < 0) {
861 pm_runtime_put_autosuspend(ddev->dev);
862 return ret;
863 }
864
865 for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
866 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
867 if (ret)
868 break;
869 }
870 if (ret == -ENOENT) {
871 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
872 if (size > 0) {
873 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
874 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
875 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
876 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
877 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
878 }
879 }
880
881 if (size == 0)
882 size = sysfs_emit(buf, "\n");
883
884 pm_runtime_mark_last_busy(ddev->dev);
885 pm_runtime_put_autosuspend(ddev->dev);
886
887 return size;
888}
889
890/**
891 * DOC: pp_features
892 *
893 * The amdgpu driver provides a sysfs API for adjusting what powerplay
894 * features to be enabled. The file pp_features is used for this. And
895 * this is only available for Vega10 and later dGPUs.
896 *
897 * Reading back the file will show you the followings:
898 * - Current ppfeature masks
899 * - List of the all supported powerplay features with their naming,
900 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
901 *
902 * To manually enable or disable a specific feature, just set or clear
903 * the corresponding bit from original ppfeature masks and input the
904 * new ppfeature masks.
905 */
906static ssize_t amdgpu_set_pp_features(struct device *dev,
907 struct device_attribute *attr,
908 const char *buf,
909 size_t count)
910{
911 struct drm_device *ddev = dev_get_drvdata(dev);
912 struct amdgpu_device *adev = drm_to_adev(ddev);
913 uint64_t featuremask;
914 int ret;
915
916 if (amdgpu_in_reset(adev))
917 return -EPERM;
918 if (adev->in_suspend && !adev->in_runpm)
919 return -EPERM;
920
921 ret = kstrtou64(buf, 0, &featuremask);
922 if (ret)
923 return -EINVAL;
924
925 ret = pm_runtime_get_sync(ddev->dev);
926 if (ret < 0) {
927 pm_runtime_put_autosuspend(ddev->dev);
928 return ret;
929 }
930
931 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
932
933 pm_runtime_mark_last_busy(ddev->dev);
934 pm_runtime_put_autosuspend(ddev->dev);
935
936 if (ret)
937 return -EINVAL;
938
939 return count;
940}
941
942static ssize_t amdgpu_get_pp_features(struct device *dev,
943 struct device_attribute *attr,
944 char *buf)
945{
946 struct drm_device *ddev = dev_get_drvdata(dev);
947 struct amdgpu_device *adev = drm_to_adev(ddev);
948 ssize_t size;
949 int ret;
950
951 if (amdgpu_in_reset(adev))
952 return -EPERM;
953 if (adev->in_suspend && !adev->in_runpm)
954 return -EPERM;
955
956 ret = pm_runtime_get_sync(ddev->dev);
957 if (ret < 0) {
958 pm_runtime_put_autosuspend(ddev->dev);
959 return ret;
960 }
961
962 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
963 if (size <= 0)
964 size = sysfs_emit(buf, "\n");
965
966 pm_runtime_mark_last_busy(ddev->dev);
967 pm_runtime_put_autosuspend(ddev->dev);
968
969 return size;
970}
971
972/**
973 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
974 *
975 * The amdgpu driver provides a sysfs API for adjusting what power levels
976 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
977 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
978 * this.
979 *
980 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
981 * Vega10 and later ASICs.
982 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
983 *
984 * Reading back the files will show you the available power levels within
985 * the power state and the clock information for those levels.
986 *
987 * To manually adjust these states, first select manual using
988 * power_dpm_force_performance_level.
989 * Secondly, enter a new value for each level by inputing a string that
990 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
991 * E.g.,
992 *
993 * .. code-block:: bash
994 *
995 * echo "4 5 6" > pp_dpm_sclk
996 *
997 * will enable sclk levels 4, 5, and 6.
998 *
999 * NOTE: change to the dcefclk max dpm level is not supported now
1000 */
1001
1002static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1003 enum pp_clock_type type,
1004 char *buf)
1005{
1006 struct drm_device *ddev = dev_get_drvdata(dev);
1007 struct amdgpu_device *adev = drm_to_adev(ddev);
1008 int size = 0;
1009 int ret = 0;
1010
1011 if (amdgpu_in_reset(adev))
1012 return -EPERM;
1013 if (adev->in_suspend && !adev->in_runpm)
1014 return -EPERM;
1015
1016 ret = pm_runtime_get_sync(ddev->dev);
1017 if (ret < 0) {
1018 pm_runtime_put_autosuspend(ddev->dev);
1019 return ret;
1020 }
1021
1022 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1023 if (ret == -ENOENT)
1024 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1025
1026 if (size == 0)
1027 size = sysfs_emit(buf, "\n");
1028
1029 pm_runtime_mark_last_busy(ddev->dev);
1030 pm_runtime_put_autosuspend(ddev->dev);
1031
1032 return size;
1033}
1034
1035/*
1036 * Worst case: 32 bits individually specified, in octal at 12 characters
1037 * per line (+1 for \n).
1038 */
1039#define AMDGPU_MASK_BUF_MAX (32 * 13)
1040
1041static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1042{
1043 int ret;
1044 unsigned long level;
1045 char *sub_str = NULL;
1046 char *tmp;
1047 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1048 const char delimiter[3] = {' ', '\n', '\0'};
1049 size_t bytes;
1050
1051 *mask = 0;
1052
1053 bytes = min(count, sizeof(buf_cpy) - 1);
1054 memcpy(buf_cpy, buf, bytes);
1055 buf_cpy[bytes] = '\0';
1056 tmp = buf_cpy;
1057 while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1058 if (strlen(sub_str)) {
1059 ret = kstrtoul(sub_str, 0, &level);
1060 if (ret || level > 31)
1061 return -EINVAL;
1062 *mask |= 1 << level;
1063 } else
1064 break;
1065 }
1066
1067 return 0;
1068}
1069
1070static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1071 enum pp_clock_type type,
1072 const char *buf,
1073 size_t count)
1074{
1075 struct drm_device *ddev = dev_get_drvdata(dev);
1076 struct amdgpu_device *adev = drm_to_adev(ddev);
1077 int ret;
1078 uint32_t mask = 0;
1079
1080 if (amdgpu_in_reset(adev))
1081 return -EPERM;
1082 if (adev->in_suspend && !adev->in_runpm)
1083 return -EPERM;
1084
1085 ret = amdgpu_read_mask(buf, count, &mask);
1086 if (ret)
1087 return ret;
1088
1089 ret = pm_runtime_get_sync(ddev->dev);
1090 if (ret < 0) {
1091 pm_runtime_put_autosuspend(ddev->dev);
1092 return ret;
1093 }
1094
1095 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1096
1097 pm_runtime_mark_last_busy(ddev->dev);
1098 pm_runtime_put_autosuspend(ddev->dev);
1099
1100 if (ret)
1101 return -EINVAL;
1102
1103 return count;
1104}
1105
1106static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1107 struct device_attribute *attr,
1108 char *buf)
1109{
1110 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1111}
1112
1113static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1114 struct device_attribute *attr,
1115 const char *buf,
1116 size_t count)
1117{
1118 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1119}
1120
1121static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1122 struct device_attribute *attr,
1123 char *buf)
1124{
1125 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1126}
1127
1128static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1129 struct device_attribute *attr,
1130 const char *buf,
1131 size_t count)
1132{
1133 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1134}
1135
1136static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1137 struct device_attribute *attr,
1138 char *buf)
1139{
1140 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1141}
1142
1143static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1144 struct device_attribute *attr,
1145 const char *buf,
1146 size_t count)
1147{
1148 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1149}
1150
1151static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1152 struct device_attribute *attr,
1153 char *buf)
1154{
1155 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1156}
1157
1158static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1159 struct device_attribute *attr,
1160 const char *buf,
1161 size_t count)
1162{
1163 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1164}
1165
1166static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1167 struct device_attribute *attr,
1168 char *buf)
1169{
1170 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1171}
1172
1173static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1174 struct device_attribute *attr,
1175 const char *buf,
1176 size_t count)
1177{
1178 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1179}
1180
1181static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1182 struct device_attribute *attr,
1183 char *buf)
1184{
1185 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1186}
1187
1188static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1189 struct device_attribute *attr,
1190 const char *buf,
1191 size_t count)
1192{
1193 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1194}
1195
1196static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1197 struct device_attribute *attr,
1198 char *buf)
1199{
1200 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1201}
1202
1203static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1204 struct device_attribute *attr,
1205 const char *buf,
1206 size_t count)
1207{
1208 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1209}
1210
1211static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1212 struct device_attribute *attr,
1213 char *buf)
1214{
1215 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1216}
1217
1218static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1219 struct device_attribute *attr,
1220 const char *buf,
1221 size_t count)
1222{
1223 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1224}
1225
1226static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1227 struct device_attribute *attr,
1228 char *buf)
1229{
1230 struct drm_device *ddev = dev_get_drvdata(dev);
1231 struct amdgpu_device *adev = drm_to_adev(ddev);
1232 uint32_t value = 0;
1233 int ret;
1234
1235 if (amdgpu_in_reset(adev))
1236 return -EPERM;
1237 if (adev->in_suspend && !adev->in_runpm)
1238 return -EPERM;
1239
1240 ret = pm_runtime_get_sync(ddev->dev);
1241 if (ret < 0) {
1242 pm_runtime_put_autosuspend(ddev->dev);
1243 return ret;
1244 }
1245
1246 value = amdgpu_dpm_get_sclk_od(adev);
1247
1248 pm_runtime_mark_last_busy(ddev->dev);
1249 pm_runtime_put_autosuspend(ddev->dev);
1250
1251 return sysfs_emit(buf, "%d\n", value);
1252}
1253
1254static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1255 struct device_attribute *attr,
1256 const char *buf,
1257 size_t count)
1258{
1259 struct drm_device *ddev = dev_get_drvdata(dev);
1260 struct amdgpu_device *adev = drm_to_adev(ddev);
1261 int ret;
1262 long int value;
1263
1264 if (amdgpu_in_reset(adev))
1265 return -EPERM;
1266 if (adev->in_suspend && !adev->in_runpm)
1267 return -EPERM;
1268
1269 ret = kstrtol(buf, 0, &value);
1270
1271 if (ret)
1272 return -EINVAL;
1273
1274 ret = pm_runtime_get_sync(ddev->dev);
1275 if (ret < 0) {
1276 pm_runtime_put_autosuspend(ddev->dev);
1277 return ret;
1278 }
1279
1280 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1281
1282 pm_runtime_mark_last_busy(ddev->dev);
1283 pm_runtime_put_autosuspend(ddev->dev);
1284
1285 return count;
1286}
1287
1288static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1289 struct device_attribute *attr,
1290 char *buf)
1291{
1292 struct drm_device *ddev = dev_get_drvdata(dev);
1293 struct amdgpu_device *adev = drm_to_adev(ddev);
1294 uint32_t value = 0;
1295 int ret;
1296
1297 if (amdgpu_in_reset(adev))
1298 return -EPERM;
1299 if (adev->in_suspend && !adev->in_runpm)
1300 return -EPERM;
1301
1302 ret = pm_runtime_get_sync(ddev->dev);
1303 if (ret < 0) {
1304 pm_runtime_put_autosuspend(ddev->dev);
1305 return ret;
1306 }
1307
1308 value = amdgpu_dpm_get_mclk_od(adev);
1309
1310 pm_runtime_mark_last_busy(ddev->dev);
1311 pm_runtime_put_autosuspend(ddev->dev);
1312
1313 return sysfs_emit(buf, "%d\n", value);
1314}
1315
1316static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1317 struct device_attribute *attr,
1318 const char *buf,
1319 size_t count)
1320{
1321 struct drm_device *ddev = dev_get_drvdata(dev);
1322 struct amdgpu_device *adev = drm_to_adev(ddev);
1323 int ret;
1324 long int value;
1325
1326 if (amdgpu_in_reset(adev))
1327 return -EPERM;
1328 if (adev->in_suspend && !adev->in_runpm)
1329 return -EPERM;
1330
1331 ret = kstrtol(buf, 0, &value);
1332
1333 if (ret)
1334 return -EINVAL;
1335
1336 ret = pm_runtime_get_sync(ddev->dev);
1337 if (ret < 0) {
1338 pm_runtime_put_autosuspend(ddev->dev);
1339 return ret;
1340 }
1341
1342 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1343
1344 pm_runtime_mark_last_busy(ddev->dev);
1345 pm_runtime_put_autosuspend(ddev->dev);
1346
1347 return count;
1348}
1349
1350/**
1351 * DOC: pp_power_profile_mode
1352 *
1353 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1354 * related to switching between power levels in a power state. The file
1355 * pp_power_profile_mode is used for this.
1356 *
1357 * Reading this file outputs a list of all of the predefined power profiles
1358 * and the relevant heuristics settings for that profile.
1359 *
1360 * To select a profile or create a custom profile, first select manual using
1361 * power_dpm_force_performance_level. Writing the number of a predefined
1362 * profile to pp_power_profile_mode will enable those heuristics. To
1363 * create a custom set of heuristics, write a string of numbers to the file
1364 * starting with the number of the custom profile along with a setting
1365 * for each heuristic parameter. Due to differences across asic families
1366 * the heuristic parameters vary from family to family.
1367 *
1368 */
1369
1370static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1371 struct device_attribute *attr,
1372 char *buf)
1373{
1374 struct drm_device *ddev = dev_get_drvdata(dev);
1375 struct amdgpu_device *adev = drm_to_adev(ddev);
1376 ssize_t size;
1377 int ret;
1378
1379 if (amdgpu_in_reset(adev))
1380 return -EPERM;
1381 if (adev->in_suspend && !adev->in_runpm)
1382 return -EPERM;
1383
1384 ret = pm_runtime_get_sync(ddev->dev);
1385 if (ret < 0) {
1386 pm_runtime_put_autosuspend(ddev->dev);
1387 return ret;
1388 }
1389
1390 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1391 if (size <= 0)
1392 size = sysfs_emit(buf, "\n");
1393
1394 pm_runtime_mark_last_busy(ddev->dev);
1395 pm_runtime_put_autosuspend(ddev->dev);
1396
1397 return size;
1398}
1399
1400
1401static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1402 struct device_attribute *attr,
1403 const char *buf,
1404 size_t count)
1405{
1406 int ret;
1407 struct drm_device *ddev = dev_get_drvdata(dev);
1408 struct amdgpu_device *adev = drm_to_adev(ddev);
1409 uint32_t parameter_size = 0;
1410 long parameter[64];
1411 char *sub_str, buf_cpy[128];
1412 char *tmp_str;
1413 uint32_t i = 0;
1414 char tmp[2];
1415 long int profile_mode = 0;
1416 const char delimiter[3] = {' ', '\n', '\0'};
1417
1418 if (amdgpu_in_reset(adev))
1419 return -EPERM;
1420 if (adev->in_suspend && !adev->in_runpm)
1421 return -EPERM;
1422
1423 tmp[0] = *(buf);
1424 tmp[1] = '\0';
1425 ret = kstrtol(tmp, 0, &profile_mode);
1426 if (ret)
1427 return -EINVAL;
1428
1429 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1430 if (count < 2 || count > 127)
1431 return -EINVAL;
1432 while (isspace(*++buf))
1433 i++;
1434 memcpy(buf_cpy, buf, count-i);
1435 tmp_str = buf_cpy;
1436 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1437 if (strlen(sub_str) == 0)
1438 continue;
1439 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
1440 if (ret)
1441 return -EINVAL;
1442 parameter_size++;
1443 while (isspace(*tmp_str))
1444 tmp_str++;
1445 }
1446 }
1447 parameter[parameter_size] = profile_mode;
1448
1449 ret = pm_runtime_get_sync(ddev->dev);
1450 if (ret < 0) {
1451 pm_runtime_put_autosuspend(ddev->dev);
1452 return ret;
1453 }
1454
1455 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1456
1457 pm_runtime_mark_last_busy(ddev->dev);
1458 pm_runtime_put_autosuspend(ddev->dev);
1459
1460 if (!ret)
1461 return count;
1462
1463 return -EINVAL;
1464}
1465
1466/**
1467 * DOC: gpu_busy_percent
1468 *
1469 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1470 * is as a percentage. The file gpu_busy_percent is used for this.
1471 * The SMU firmware computes a percentage of load based on the
1472 * aggregate activity level in the IP cores.
1473 */
1474static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1475 struct device_attribute *attr,
1476 char *buf)
1477{
1478 struct drm_device *ddev = dev_get_drvdata(dev);
1479 struct amdgpu_device *adev = drm_to_adev(ddev);
1480 int r, value, size = sizeof(value);
1481
1482 if (amdgpu_in_reset(adev))
1483 return -EPERM;
1484 if (adev->in_suspend && !adev->in_runpm)
1485 return -EPERM;
1486
1487 r = pm_runtime_get_sync(ddev->dev);
1488 if (r < 0) {
1489 pm_runtime_put_autosuspend(ddev->dev);
1490 return r;
1491 }
1492
1493 /* read the IP busy sensor */
1494 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1495 (void *)&value, &size);
1496
1497 pm_runtime_mark_last_busy(ddev->dev);
1498 pm_runtime_put_autosuspend(ddev->dev);
1499
1500 if (r)
1501 return r;
1502
1503 return sysfs_emit(buf, "%d\n", value);
1504}
1505
1506/**
1507 * DOC: mem_busy_percent
1508 *
1509 * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1510 * is as a percentage. The file mem_busy_percent is used for this.
1511 * The SMU firmware computes a percentage of load based on the
1512 * aggregate activity level in the IP cores.
1513 */
1514static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1515 struct device_attribute *attr,
1516 char *buf)
1517{
1518 struct drm_device *ddev = dev_get_drvdata(dev);
1519 struct amdgpu_device *adev = drm_to_adev(ddev);
1520 int r, value, size = sizeof(value);
1521
1522 if (amdgpu_in_reset(adev))
1523 return -EPERM;
1524 if (adev->in_suspend && !adev->in_runpm)
1525 return -EPERM;
1526
1527 r = pm_runtime_get_sync(ddev->dev);
1528 if (r < 0) {
1529 pm_runtime_put_autosuspend(ddev->dev);
1530 return r;
1531 }
1532
1533 /* read the IP busy sensor */
1534 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1535 (void *)&value, &size);
1536
1537 pm_runtime_mark_last_busy(ddev->dev);
1538 pm_runtime_put_autosuspend(ddev->dev);
1539
1540 if (r)
1541 return r;
1542
1543 return sysfs_emit(buf, "%d\n", value);
1544}
1545
1546/**
1547 * DOC: pcie_bw
1548 *
1549 * The amdgpu driver provides a sysfs API for estimating how much data
1550 * has been received and sent by the GPU in the last second through PCIe.
1551 * The file pcie_bw is used for this.
1552 * The Perf counters count the number of received and sent messages and return
1553 * those values, as well as the maximum payload size of a PCIe packet (mps).
1554 * Note that it is not possible to easily and quickly obtain the size of each
1555 * packet transmitted, so we output the max payload size (mps) to allow for
1556 * quick estimation of the PCIe bandwidth usage
1557 */
1558static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1559 struct device_attribute *attr,
1560 char *buf)
1561{
1562 struct drm_device *ddev = dev_get_drvdata(dev);
1563 struct amdgpu_device *adev = drm_to_adev(ddev);
1564 uint64_t count0 = 0, count1 = 0;
1565 int ret;
1566
1567 if (amdgpu_in_reset(adev))
1568 return -EPERM;
1569 if (adev->in_suspend && !adev->in_runpm)
1570 return -EPERM;
1571
1572 if (adev->flags & AMD_IS_APU)
1573 return -ENODATA;
1574
1575 if (!adev->asic_funcs->get_pcie_usage)
1576 return -ENODATA;
1577
1578 ret = pm_runtime_get_sync(ddev->dev);
1579 if (ret < 0) {
1580 pm_runtime_put_autosuspend(ddev->dev);
1581 return ret;
1582 }
1583
1584 amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1585
1586 pm_runtime_mark_last_busy(ddev->dev);
1587 pm_runtime_put_autosuspend(ddev->dev);
1588
1589 return sysfs_emit(buf, "%llu %llu %i\n",
1590 count0, count1, pcie_get_mps(adev->pdev));
1591}
1592
1593/**
1594 * DOC: unique_id
1595 *
1596 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1597 * The file unique_id is used for this.
1598 * This will provide a Unique ID that will persist from machine to machine
1599 *
1600 * NOTE: This will only work for GFX9 and newer. This file will be absent
1601 * on unsupported ASICs (GFX8 and older)
1602 */
1603static ssize_t amdgpu_get_unique_id(struct device *dev,
1604 struct device_attribute *attr,
1605 char *buf)
1606{
1607 struct drm_device *ddev = dev_get_drvdata(dev);
1608 struct amdgpu_device *adev = drm_to_adev(ddev);
1609
1610 if (amdgpu_in_reset(adev))
1611 return -EPERM;
1612 if (adev->in_suspend && !adev->in_runpm)
1613 return -EPERM;
1614
1615 if (adev->unique_id)
1616 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1617
1618 return 0;
1619}
1620
1621/**
1622 * DOC: thermal_throttling_logging
1623 *
1624 * Thermal throttling pulls down the clock frequency and thus the performance.
1625 * It's an useful mechanism to protect the chip from overheating. Since it
1626 * impacts performance, the user controls whether it is enabled and if so,
1627 * the log frequency.
1628 *
1629 * Reading back the file shows you the status(enabled or disabled) and
1630 * the interval(in seconds) between each thermal logging.
1631 *
1632 * Writing an integer to the file, sets a new logging interval, in seconds.
1633 * The value should be between 1 and 3600. If the value is less than 1,
1634 * thermal logging is disabled. Values greater than 3600 are ignored.
1635 */
1636static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1637 struct device_attribute *attr,
1638 char *buf)
1639{
1640 struct drm_device *ddev = dev_get_drvdata(dev);
1641 struct amdgpu_device *adev = drm_to_adev(ddev);
1642
1643 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1644 adev_to_drm(adev)->unique,
1645 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1646 adev->throttling_logging_rs.interval / HZ + 1);
1647}
1648
1649static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1650 struct device_attribute *attr,
1651 const char *buf,
1652 size_t count)
1653{
1654 struct drm_device *ddev = dev_get_drvdata(dev);
1655 struct amdgpu_device *adev = drm_to_adev(ddev);
1656 long throttling_logging_interval;
1657 unsigned long flags;
1658 int ret = 0;
1659
1660 ret = kstrtol(buf, 0, &throttling_logging_interval);
1661 if (ret)
1662 return ret;
1663
1664 if (throttling_logging_interval > 3600)
1665 return -EINVAL;
1666
1667 if (throttling_logging_interval > 0) {
1668 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1669 /*
1670 * Reset the ratelimit timer internals.
1671 * This can effectively restart the timer.
1672 */
1673 adev->throttling_logging_rs.interval =
1674 (throttling_logging_interval - 1) * HZ;
1675 adev->throttling_logging_rs.begin = 0;
1676 adev->throttling_logging_rs.printed = 0;
1677 adev->throttling_logging_rs.missed = 0;
1678 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1679
1680 atomic_set(&adev->throttling_logging_enabled, 1);
1681 } else {
1682 atomic_set(&adev->throttling_logging_enabled, 0);
1683 }
1684
1685 return count;
1686}
1687
1688/**
1689 * DOC: gpu_metrics
1690 *
1691 * The amdgpu driver provides a sysfs API for retrieving current gpu
1692 * metrics data. The file gpu_metrics is used for this. Reading the
1693 * file will dump all the current gpu metrics data.
1694 *
1695 * These data include temperature, frequency, engines utilization,
1696 * power consume, throttler status, fan speed and cpu core statistics(
1697 * available for APU only). That's it will give a snapshot of all sensors
1698 * at the same time.
1699 */
1700static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1701 struct device_attribute *attr,
1702 char *buf)
1703{
1704 struct drm_device *ddev = dev_get_drvdata(dev);
1705 struct amdgpu_device *adev = drm_to_adev(ddev);
1706 void *gpu_metrics;
1707 ssize_t size = 0;
1708 int ret;
1709
1710 if (amdgpu_in_reset(adev))
1711 return -EPERM;
1712 if (adev->in_suspend && !adev->in_runpm)
1713 return -EPERM;
1714
1715 ret = pm_runtime_get_sync(ddev->dev);
1716 if (ret < 0) {
1717 pm_runtime_put_autosuspend(ddev->dev);
1718 return ret;
1719 }
1720
1721 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1722 if (size <= 0)
1723 goto out;
1724
1725 if (size >= PAGE_SIZE)
1726 size = PAGE_SIZE - 1;
1727
1728 memcpy(buf, gpu_metrics, size);
1729
1730out:
1731 pm_runtime_mark_last_busy(ddev->dev);
1732 pm_runtime_put_autosuspend(ddev->dev);
1733
1734 return size;
1735}
1736
1737static int amdgpu_device_read_powershift(struct amdgpu_device *adev,
1738 uint32_t *ss_power, bool dgpu_share)
1739{
1740 struct drm_device *ddev = adev_to_drm(adev);
1741 uint32_t size;
1742 int r = 0;
1743
1744 if (amdgpu_in_reset(adev))
1745 return -EPERM;
1746 if (adev->in_suspend && !adev->in_runpm)
1747 return -EPERM;
1748
1749 r = pm_runtime_get_sync(ddev->dev);
1750 if (r < 0) {
1751 pm_runtime_put_autosuspend(ddev->dev);
1752 return r;
1753 }
1754
1755 if (dgpu_share)
1756 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1757 (void *)ss_power, &size);
1758 else
1759 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1760 (void *)ss_power, &size);
1761
1762 pm_runtime_mark_last_busy(ddev->dev);
1763 pm_runtime_put_autosuspend(ddev->dev);
1764 return r;
1765}
1766
1767static int amdgpu_show_powershift_percent(struct device *dev,
1768 char *buf, bool dgpu_share)
1769{
1770 struct drm_device *ddev = dev_get_drvdata(dev);
1771 struct amdgpu_device *adev = drm_to_adev(ddev);
1772 uint32_t ss_power;
1773 int r = 0, i;
1774
1775 r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1776 if (r == -EOPNOTSUPP) {
1777 /* sensor not available on dGPU, try to read from APU */
1778 adev = NULL;
1779 mutex_lock(&mgpu_info.mutex);
1780 for (i = 0; i < mgpu_info.num_gpu; i++) {
1781 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1782 adev = mgpu_info.gpu_ins[i].adev;
1783 break;
1784 }
1785 }
1786 mutex_unlock(&mgpu_info.mutex);
1787 if (adev)
1788 r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1789 }
1790
1791 if (!r)
1792 r = sysfs_emit(buf, "%u%%\n", ss_power);
1793
1794 return r;
1795}
1796/**
1797 * DOC: smartshift_apu_power
1798 *
1799 * The amdgpu driver provides a sysfs API for reporting APU power
1800 * shift in percentage if platform supports smartshift. Value 0 means that
1801 * there is no powershift and values between [1-100] means that the power
1802 * is shifted to APU, the percentage of boost is with respect to APU power
1803 * limit on the platform.
1804 */
1805
1806static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1807 char *buf)
1808{
1809 return amdgpu_show_powershift_percent(dev, buf, false);
1810}
1811
1812/**
1813 * DOC: smartshift_dgpu_power
1814 *
1815 * The amdgpu driver provides a sysfs API for reporting dGPU power
1816 * shift in percentage if platform supports smartshift. Value 0 means that
1817 * there is no powershift and values between [1-100] means that the power is
1818 * shifted to dGPU, the percentage of boost is with respect to dGPU power
1819 * limit on the platform.
1820 */
1821
1822static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1823 char *buf)
1824{
1825 return amdgpu_show_powershift_percent(dev, buf, true);
1826}
1827
1828/**
1829 * DOC: smartshift_bias
1830 *
1831 * The amdgpu driver provides a sysfs API for reporting the
1832 * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1833 * and the default is 0. -100 sets maximum preference to APU
1834 * and 100 sets max perference to dGPU.
1835 */
1836
1837static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1838 struct device_attribute *attr,
1839 char *buf)
1840{
1841 int r = 0;
1842
1843 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1844
1845 return r;
1846}
1847
1848static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1849 struct device_attribute *attr,
1850 const char *buf, size_t count)
1851{
1852 struct drm_device *ddev = dev_get_drvdata(dev);
1853 struct amdgpu_device *adev = drm_to_adev(ddev);
1854 int r = 0;
1855 int bias = 0;
1856
1857 if (amdgpu_in_reset(adev))
1858 return -EPERM;
1859 if (adev->in_suspend && !adev->in_runpm)
1860 return -EPERM;
1861
1862 r = pm_runtime_get_sync(ddev->dev);
1863 if (r < 0) {
1864 pm_runtime_put_autosuspend(ddev->dev);
1865 return r;
1866 }
1867
1868 r = kstrtoint(buf, 10, &bias);
1869 if (r)
1870 goto out;
1871
1872 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1873 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1874 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1875 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1876
1877 amdgpu_smartshift_bias = bias;
1878 r = count;
1879
1880 /* TODO: update bias level with SMU message */
1881
1882out:
1883 pm_runtime_mark_last_busy(ddev->dev);
1884 pm_runtime_put_autosuspend(ddev->dev);
1885 return r;
1886}
1887
1888
1889static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1890 uint32_t mask, enum amdgpu_device_attr_states *states)
1891{
1892 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1893 *states = ATTR_STATE_UNSUPPORTED;
1894
1895 return 0;
1896}
1897
1898static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1899 uint32_t mask, enum amdgpu_device_attr_states *states)
1900{
1901 uint32_t ss_power, size;
1902
1903 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1904 *states = ATTR_STATE_UNSUPPORTED;
1905 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1906 (void *)&ss_power, &size))
1907 *states = ATTR_STATE_UNSUPPORTED;
1908 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1909 (void *)&ss_power, &size))
1910 *states = ATTR_STATE_UNSUPPORTED;
1911
1912 return 0;
1913}
1914
1915static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1916 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1917 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1918 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1919 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1920 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1921 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1922 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1923 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1924 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1925 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1926 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1927 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1928 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1929 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1930 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
1931 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC),
1932 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1933 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC),
1934 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1935 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1936 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC),
1937 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1938 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1939 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1940 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1941 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC,
1942 .attr_update = ss_power_attr_update),
1943 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC,
1944 .attr_update = ss_power_attr_update),
1945 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC,
1946 .attr_update = ss_bias_attr_update),
1947};
1948
1949static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1950 uint32_t mask, enum amdgpu_device_attr_states *states)
1951{
1952 struct device_attribute *dev_attr = &attr->dev_attr;
1953 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
1954 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
1955 const char *attr_name = dev_attr->attr.name;
1956
1957 if (!(attr->flags & mask)) {
1958 *states = ATTR_STATE_UNSUPPORTED;
1959 return 0;
1960 }
1961
1962#define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name))
1963
1964 if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1965 if (gc_ver < IP_VERSION(9, 0, 0))
1966 *states = ATTR_STATE_UNSUPPORTED;
1967 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1968 if (gc_ver < IP_VERSION(9, 0, 0) ||
1969 gc_ver == IP_VERSION(9, 4, 1) ||
1970 gc_ver == IP_VERSION(9, 4, 2))
1971 *states = ATTR_STATE_UNSUPPORTED;
1972 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1973 if (mp1_ver < IP_VERSION(10, 0, 0))
1974 *states = ATTR_STATE_UNSUPPORTED;
1975 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1976 *states = ATTR_STATE_UNSUPPORTED;
1977 if (amdgpu_dpm_is_overdrive_supported(adev))
1978 *states = ATTR_STATE_SUPPORTED;
1979 } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
1980 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
1981 *states = ATTR_STATE_UNSUPPORTED;
1982 } else if (DEVICE_ATTR_IS(pcie_bw)) {
1983 /* PCIe Perf counters won't work on APU nodes */
1984 if (adev->flags & AMD_IS_APU)
1985 *states = ATTR_STATE_UNSUPPORTED;
1986 } else if (DEVICE_ATTR_IS(unique_id)) {
1987 switch (gc_ver) {
1988 case IP_VERSION(9, 0, 1):
1989 case IP_VERSION(9, 4, 0):
1990 case IP_VERSION(9, 4, 1):
1991 case IP_VERSION(9, 4, 2):
1992 case IP_VERSION(10, 3, 0):
1993 case IP_VERSION(11, 0, 0):
1994 case IP_VERSION(11, 0, 1):
1995 case IP_VERSION(11, 0, 2):
1996 *states = ATTR_STATE_SUPPORTED;
1997 break;
1998 default:
1999 *states = ATTR_STATE_UNSUPPORTED;
2000 }
2001 } else if (DEVICE_ATTR_IS(pp_features)) {
2002 if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0))
2003 *states = ATTR_STATE_UNSUPPORTED;
2004 } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2005 if (gc_ver < IP_VERSION(9, 1, 0))
2006 *states = ATTR_STATE_UNSUPPORTED;
2007 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2008 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2009 gc_ver == IP_VERSION(10, 3, 0) ||
2010 gc_ver == IP_VERSION(10, 1, 2) ||
2011 gc_ver == IP_VERSION(11, 0, 0) ||
2012 gc_ver == IP_VERSION(11, 0, 2) ||
2013 gc_ver == IP_VERSION(11, 0, 3)))
2014 *states = ATTR_STATE_UNSUPPORTED;
2015 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2016 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2017 gc_ver == IP_VERSION(10, 3, 0) ||
2018 gc_ver == IP_VERSION(10, 1, 2) ||
2019 gc_ver == IP_VERSION(11, 0, 0) ||
2020 gc_ver == IP_VERSION(11, 0, 2) ||
2021 gc_ver == IP_VERSION(11, 0, 3)))
2022 *states = ATTR_STATE_UNSUPPORTED;
2023 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2024 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2025 *states = ATTR_STATE_UNSUPPORTED;
2026 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2027 *states = ATTR_STATE_UNSUPPORTED;
2028 }
2029
2030 switch (gc_ver) {
2031 case IP_VERSION(9, 4, 1):
2032 case IP_VERSION(9, 4, 2):
2033 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2034 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2035 DEVICE_ATTR_IS(pp_dpm_socclk) ||
2036 DEVICE_ATTR_IS(pp_dpm_fclk)) {
2037 dev_attr->attr.mode &= ~S_IWUGO;
2038 dev_attr->store = NULL;
2039 }
2040 break;
2041 case IP_VERSION(10, 3, 0):
2042 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2043 amdgpu_sriov_vf(adev)) {
2044 dev_attr->attr.mode &= ~0222;
2045 dev_attr->store = NULL;
2046 }
2047 break;
2048 default:
2049 break;
2050 }
2051
2052 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2053 /* SMU MP1 does not support dcefclk level setting */
2054 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2055 dev_attr->attr.mode &= ~S_IWUGO;
2056 dev_attr->store = NULL;
2057 }
2058 }
2059
2060 /* setting should not be allowed from VF if not in one VF mode */
2061 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2062 dev_attr->attr.mode &= ~S_IWUGO;
2063 dev_attr->store = NULL;
2064 }
2065
2066#undef DEVICE_ATTR_IS
2067
2068 return 0;
2069}
2070
2071
2072static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2073 struct amdgpu_device_attr *attr,
2074 uint32_t mask, struct list_head *attr_list)
2075{
2076 int ret = 0;
2077 struct device_attribute *dev_attr = &attr->dev_attr;
2078 const char *name = dev_attr->attr.name;
2079 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2080 struct amdgpu_device_attr_entry *attr_entry;
2081
2082 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2083 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2084
2085 BUG_ON(!attr);
2086
2087 attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2088
2089 ret = attr_update(adev, attr, mask, &attr_states);
2090 if (ret) {
2091 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2092 name, ret);
2093 return ret;
2094 }
2095
2096 if (attr_states == ATTR_STATE_UNSUPPORTED)
2097 return 0;
2098
2099 ret = device_create_file(adev->dev, dev_attr);
2100 if (ret) {
2101 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2102 name, ret);
2103 }
2104
2105 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2106 if (!attr_entry)
2107 return -ENOMEM;
2108
2109 attr_entry->attr = attr;
2110 INIT_LIST_HEAD(&attr_entry->entry);
2111
2112 list_add_tail(&attr_entry->entry, attr_list);
2113
2114 return ret;
2115}
2116
2117static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2118{
2119 struct device_attribute *dev_attr = &attr->dev_attr;
2120
2121 device_remove_file(adev->dev, dev_attr);
2122}
2123
2124static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2125 struct list_head *attr_list);
2126
2127static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2128 struct amdgpu_device_attr *attrs,
2129 uint32_t counts,
2130 uint32_t mask,
2131 struct list_head *attr_list)
2132{
2133 int ret = 0;
2134 uint32_t i = 0;
2135
2136 for (i = 0; i < counts; i++) {
2137 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2138 if (ret)
2139 goto failed;
2140 }
2141
2142 return 0;
2143
2144failed:
2145 amdgpu_device_attr_remove_groups(adev, attr_list);
2146
2147 return ret;
2148}
2149
2150static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2151 struct list_head *attr_list)
2152{
2153 struct amdgpu_device_attr_entry *entry, *entry_tmp;
2154
2155 if (list_empty(attr_list))
2156 return ;
2157
2158 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2159 amdgpu_device_attr_remove(adev, entry->attr);
2160 list_del(&entry->entry);
2161 kfree(entry);
2162 }
2163}
2164
2165static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2166 struct device_attribute *attr,
2167 char *buf)
2168{
2169 struct amdgpu_device *adev = dev_get_drvdata(dev);
2170 int channel = to_sensor_dev_attr(attr)->index;
2171 int r, temp = 0, size = sizeof(temp);
2172
2173 if (amdgpu_in_reset(adev))
2174 return -EPERM;
2175 if (adev->in_suspend && !adev->in_runpm)
2176 return -EPERM;
2177
2178 if (channel >= PP_TEMP_MAX)
2179 return -EINVAL;
2180
2181 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2182 if (r < 0) {
2183 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2184 return r;
2185 }
2186
2187 switch (channel) {
2188 case PP_TEMP_JUNCTION:
2189 /* get current junction temperature */
2190 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2191 (void *)&temp, &size);
2192 break;
2193 case PP_TEMP_EDGE:
2194 /* get current edge temperature */
2195 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2196 (void *)&temp, &size);
2197 break;
2198 case PP_TEMP_MEM:
2199 /* get current memory temperature */
2200 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2201 (void *)&temp, &size);
2202 break;
2203 default:
2204 r = -EINVAL;
2205 break;
2206 }
2207
2208 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2209 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2210
2211 if (r)
2212 return r;
2213
2214 return sysfs_emit(buf, "%d\n", temp);
2215}
2216
2217static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2218 struct device_attribute *attr,
2219 char *buf)
2220{
2221 struct amdgpu_device *adev = dev_get_drvdata(dev);
2222 int hyst = to_sensor_dev_attr(attr)->index;
2223 int temp;
2224
2225 if (hyst)
2226 temp = adev->pm.dpm.thermal.min_temp;
2227 else
2228 temp = adev->pm.dpm.thermal.max_temp;
2229
2230 return sysfs_emit(buf, "%d\n", temp);
2231}
2232
2233static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2234 struct device_attribute *attr,
2235 char *buf)
2236{
2237 struct amdgpu_device *adev = dev_get_drvdata(dev);
2238 int hyst = to_sensor_dev_attr(attr)->index;
2239 int temp;
2240
2241 if (hyst)
2242 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2243 else
2244 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2245
2246 return sysfs_emit(buf, "%d\n", temp);
2247}
2248
2249static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2250 struct device_attribute *attr,
2251 char *buf)
2252{
2253 struct amdgpu_device *adev = dev_get_drvdata(dev);
2254 int hyst = to_sensor_dev_attr(attr)->index;
2255 int temp;
2256
2257 if (hyst)
2258 temp = adev->pm.dpm.thermal.min_mem_temp;
2259 else
2260 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2261
2262 return sysfs_emit(buf, "%d\n", temp);
2263}
2264
2265static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2266 struct device_attribute *attr,
2267 char *buf)
2268{
2269 int channel = to_sensor_dev_attr(attr)->index;
2270
2271 if (channel >= PP_TEMP_MAX)
2272 return -EINVAL;
2273
2274 return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2275}
2276
2277static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2278 struct device_attribute *attr,
2279 char *buf)
2280{
2281 struct amdgpu_device *adev = dev_get_drvdata(dev);
2282 int channel = to_sensor_dev_attr(attr)->index;
2283 int temp = 0;
2284
2285 if (channel >= PP_TEMP_MAX)
2286 return -EINVAL;
2287
2288 switch (channel) {
2289 case PP_TEMP_JUNCTION:
2290 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2291 break;
2292 case PP_TEMP_EDGE:
2293 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2294 break;
2295 case PP_TEMP_MEM:
2296 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2297 break;
2298 }
2299
2300 return sysfs_emit(buf, "%d\n", temp);
2301}
2302
2303static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2304 struct device_attribute *attr,
2305 char *buf)
2306{
2307 struct amdgpu_device *adev = dev_get_drvdata(dev);
2308 u32 pwm_mode = 0;
2309 int ret;
2310
2311 if (amdgpu_in_reset(adev))
2312 return -EPERM;
2313 if (adev->in_suspend && !adev->in_runpm)
2314 return -EPERM;
2315
2316 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2317 if (ret < 0) {
2318 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2319 return ret;
2320 }
2321
2322 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2323
2324 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2325 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2326
2327 if (ret)
2328 return -EINVAL;
2329
2330 return sysfs_emit(buf, "%u\n", pwm_mode);
2331}
2332
2333static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2334 struct device_attribute *attr,
2335 const char *buf,
2336 size_t count)
2337{
2338 struct amdgpu_device *adev = dev_get_drvdata(dev);
2339 int err, ret;
2340 int value;
2341
2342 if (amdgpu_in_reset(adev))
2343 return -EPERM;
2344 if (adev->in_suspend && !adev->in_runpm)
2345 return -EPERM;
2346
2347 err = kstrtoint(buf, 10, &value);
2348 if (err)
2349 return err;
2350
2351 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2352 if (ret < 0) {
2353 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2354 return ret;
2355 }
2356
2357 ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2358
2359 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2360 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2361
2362 if (ret)
2363 return -EINVAL;
2364
2365 return count;
2366}
2367
2368static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2369 struct device_attribute *attr,
2370 char *buf)
2371{
2372 return sysfs_emit(buf, "%i\n", 0);
2373}
2374
2375static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2376 struct device_attribute *attr,
2377 char *buf)
2378{
2379 return sysfs_emit(buf, "%i\n", 255);
2380}
2381
2382static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2383 struct device_attribute *attr,
2384 const char *buf, size_t count)
2385{
2386 struct amdgpu_device *adev = dev_get_drvdata(dev);
2387 int err;
2388 u32 value;
2389 u32 pwm_mode;
2390
2391 if (amdgpu_in_reset(adev))
2392 return -EPERM;
2393 if (adev->in_suspend && !adev->in_runpm)
2394 return -EPERM;
2395
2396 err = kstrtou32(buf, 10, &value);
2397 if (err)
2398 return err;
2399
2400 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2401 if (err < 0) {
2402 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2403 return err;
2404 }
2405
2406 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2407 if (err)
2408 goto out;
2409
2410 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2411 pr_info("manual fan speed control should be enabled first\n");
2412 err = -EINVAL;
2413 goto out;
2414 }
2415
2416 err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2417
2418out:
2419 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2420 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2421
2422 if (err)
2423 return err;
2424
2425 return count;
2426}
2427
2428static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2429 struct device_attribute *attr,
2430 char *buf)
2431{
2432 struct amdgpu_device *adev = dev_get_drvdata(dev);
2433 int err;
2434 u32 speed = 0;
2435
2436 if (amdgpu_in_reset(adev))
2437 return -EPERM;
2438 if (adev->in_suspend && !adev->in_runpm)
2439 return -EPERM;
2440
2441 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2442 if (err < 0) {
2443 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2444 return err;
2445 }
2446
2447 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2448
2449 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2450 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2451
2452 if (err)
2453 return err;
2454
2455 return sysfs_emit(buf, "%i\n", speed);
2456}
2457
2458static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2459 struct device_attribute *attr,
2460 char *buf)
2461{
2462 struct amdgpu_device *adev = dev_get_drvdata(dev);
2463 int err;
2464 u32 speed = 0;
2465
2466 if (amdgpu_in_reset(adev))
2467 return -EPERM;
2468 if (adev->in_suspend && !adev->in_runpm)
2469 return -EPERM;
2470
2471 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2472 if (err < 0) {
2473 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2474 return err;
2475 }
2476
2477 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2478
2479 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2480 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2481
2482 if (err)
2483 return err;
2484
2485 return sysfs_emit(buf, "%i\n", speed);
2486}
2487
2488static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2489 struct device_attribute *attr,
2490 char *buf)
2491{
2492 struct amdgpu_device *adev = dev_get_drvdata(dev);
2493 u32 min_rpm = 0;
2494 u32 size = sizeof(min_rpm);
2495 int r;
2496
2497 if (amdgpu_in_reset(adev))
2498 return -EPERM;
2499 if (adev->in_suspend && !adev->in_runpm)
2500 return -EPERM;
2501
2502 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2503 if (r < 0) {
2504 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2505 return r;
2506 }
2507
2508 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2509 (void *)&min_rpm, &size);
2510
2511 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2512 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2513
2514 if (r)
2515 return r;
2516
2517 return sysfs_emit(buf, "%d\n", min_rpm);
2518}
2519
2520static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2521 struct device_attribute *attr,
2522 char *buf)
2523{
2524 struct amdgpu_device *adev = dev_get_drvdata(dev);
2525 u32 max_rpm = 0;
2526 u32 size = sizeof(max_rpm);
2527 int r;
2528
2529 if (amdgpu_in_reset(adev))
2530 return -EPERM;
2531 if (adev->in_suspend && !adev->in_runpm)
2532 return -EPERM;
2533
2534 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2535 if (r < 0) {
2536 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2537 return r;
2538 }
2539
2540 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2541 (void *)&max_rpm, &size);
2542
2543 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2544 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2545
2546 if (r)
2547 return r;
2548
2549 return sysfs_emit(buf, "%d\n", max_rpm);
2550}
2551
2552static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2553 struct device_attribute *attr,
2554 char *buf)
2555{
2556 struct amdgpu_device *adev = dev_get_drvdata(dev);
2557 int err;
2558 u32 rpm = 0;
2559
2560 if (amdgpu_in_reset(adev))
2561 return -EPERM;
2562 if (adev->in_suspend && !adev->in_runpm)
2563 return -EPERM;
2564
2565 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2566 if (err < 0) {
2567 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2568 return err;
2569 }
2570
2571 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2572
2573 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2574 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2575
2576 if (err)
2577 return err;
2578
2579 return sysfs_emit(buf, "%i\n", rpm);
2580}
2581
2582static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2583 struct device_attribute *attr,
2584 const char *buf, size_t count)
2585{
2586 struct amdgpu_device *adev = dev_get_drvdata(dev);
2587 int err;
2588 u32 value;
2589 u32 pwm_mode;
2590
2591 if (amdgpu_in_reset(adev))
2592 return -EPERM;
2593 if (adev->in_suspend && !adev->in_runpm)
2594 return -EPERM;
2595
2596 err = kstrtou32(buf, 10, &value);
2597 if (err)
2598 return err;
2599
2600 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2601 if (err < 0) {
2602 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2603 return err;
2604 }
2605
2606 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2607 if (err)
2608 goto out;
2609
2610 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2611 err = -ENODATA;
2612 goto out;
2613 }
2614
2615 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2616
2617out:
2618 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2619 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2620
2621 if (err)
2622 return err;
2623
2624 return count;
2625}
2626
2627static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2628 struct device_attribute *attr,
2629 char *buf)
2630{
2631 struct amdgpu_device *adev = dev_get_drvdata(dev);
2632 u32 pwm_mode = 0;
2633 int ret;
2634
2635 if (amdgpu_in_reset(adev))
2636 return -EPERM;
2637 if (adev->in_suspend && !adev->in_runpm)
2638 return -EPERM;
2639
2640 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2641 if (ret < 0) {
2642 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2643 return ret;
2644 }
2645
2646 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2647
2648 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2649 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2650
2651 if (ret)
2652 return -EINVAL;
2653
2654 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2655}
2656
2657static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2658 struct device_attribute *attr,
2659 const char *buf,
2660 size_t count)
2661{
2662 struct amdgpu_device *adev = dev_get_drvdata(dev);
2663 int err;
2664 int value;
2665 u32 pwm_mode;
2666
2667 if (amdgpu_in_reset(adev))
2668 return -EPERM;
2669 if (adev->in_suspend && !adev->in_runpm)
2670 return -EPERM;
2671
2672 err = kstrtoint(buf, 10, &value);
2673 if (err)
2674 return err;
2675
2676 if (value == 0)
2677 pwm_mode = AMD_FAN_CTRL_AUTO;
2678 else if (value == 1)
2679 pwm_mode = AMD_FAN_CTRL_MANUAL;
2680 else
2681 return -EINVAL;
2682
2683 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2684 if (err < 0) {
2685 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2686 return err;
2687 }
2688
2689 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2690
2691 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2692 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2693
2694 if (err)
2695 return -EINVAL;
2696
2697 return count;
2698}
2699
2700static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2701 struct device_attribute *attr,
2702 char *buf)
2703{
2704 struct amdgpu_device *adev = dev_get_drvdata(dev);
2705 u32 vddgfx;
2706 int r, size = sizeof(vddgfx);
2707
2708 if (amdgpu_in_reset(adev))
2709 return -EPERM;
2710 if (adev->in_suspend && !adev->in_runpm)
2711 return -EPERM;
2712
2713 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2714 if (r < 0) {
2715 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2716 return r;
2717 }
2718
2719 /* get the voltage */
2720 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2721 (void *)&vddgfx, &size);
2722
2723 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2724 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2725
2726 if (r)
2727 return r;
2728
2729 return sysfs_emit(buf, "%d\n", vddgfx);
2730}
2731
2732static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2733 struct device_attribute *attr,
2734 char *buf)
2735{
2736 return sysfs_emit(buf, "vddgfx\n");
2737}
2738
2739static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2740 struct device_attribute *attr,
2741 char *buf)
2742{
2743 struct amdgpu_device *adev = dev_get_drvdata(dev);
2744 u32 vddnb;
2745 int r, size = sizeof(vddnb);
2746
2747 if (amdgpu_in_reset(adev))
2748 return -EPERM;
2749 if (adev->in_suspend && !adev->in_runpm)
2750 return -EPERM;
2751
2752 /* only APUs have vddnb */
2753 if (!(adev->flags & AMD_IS_APU))
2754 return -EINVAL;
2755
2756 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2757 if (r < 0) {
2758 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2759 return r;
2760 }
2761
2762 /* get the voltage */
2763 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2764 (void *)&vddnb, &size);
2765
2766 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2767 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2768
2769 if (r)
2770 return r;
2771
2772 return sysfs_emit(buf, "%d\n", vddnb);
2773}
2774
2775static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2776 struct device_attribute *attr,
2777 char *buf)
2778{
2779 return sysfs_emit(buf, "vddnb\n");
2780}
2781
2782static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2783 struct device_attribute *attr,
2784 char *buf)
2785{
2786 struct amdgpu_device *adev = dev_get_drvdata(dev);
2787 u32 query = 0;
2788 int r, size = sizeof(u32);
2789 unsigned uw;
2790
2791 if (amdgpu_in_reset(adev))
2792 return -EPERM;
2793 if (adev->in_suspend && !adev->in_runpm)
2794 return -EPERM;
2795
2796 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2797 if (r < 0) {
2798 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2799 return r;
2800 }
2801
2802 /* get the voltage */
2803 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2804 (void *)&query, &size);
2805
2806 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2807 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2808
2809 if (r)
2810 return r;
2811
2812 /* convert to microwatts */
2813 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2814
2815 return sysfs_emit(buf, "%u\n", uw);
2816}
2817
2818static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2819 struct device_attribute *attr,
2820 char *buf)
2821{
2822 return sysfs_emit(buf, "%i\n", 0);
2823}
2824
2825
2826static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2827 struct device_attribute *attr,
2828 char *buf,
2829 enum pp_power_limit_level pp_limit_level)
2830{
2831 struct amdgpu_device *adev = dev_get_drvdata(dev);
2832 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2833 uint32_t limit;
2834 ssize_t size;
2835 int r;
2836
2837 if (amdgpu_in_reset(adev))
2838 return -EPERM;
2839 if (adev->in_suspend && !adev->in_runpm)
2840 return -EPERM;
2841
2842 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2843 if (r < 0) {
2844 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2845 return r;
2846 }
2847
2848 r = amdgpu_dpm_get_power_limit(adev, &limit,
2849 pp_limit_level, power_type);
2850
2851 if (!r)
2852 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2853 else
2854 size = sysfs_emit(buf, "\n");
2855
2856 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2857 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2858
2859 return size;
2860}
2861
2862
2863static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2864 struct device_attribute *attr,
2865 char *buf)
2866{
2867 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2868
2869}
2870
2871static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2872 struct device_attribute *attr,
2873 char *buf)
2874{
2875 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2876
2877}
2878
2879static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2880 struct device_attribute *attr,
2881 char *buf)
2882{
2883 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2884
2885}
2886
2887static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2888 struct device_attribute *attr,
2889 char *buf)
2890{
2891 struct amdgpu_device *adev = dev_get_drvdata(dev);
2892 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2893
2894 if (gc_ver == IP_VERSION(10, 3, 1))
2895 return sysfs_emit(buf, "%s\n",
2896 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
2897 "fastPPT" : "slowPPT");
2898 else
2899 return sysfs_emit(buf, "PPT\n");
2900}
2901
2902static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2903 struct device_attribute *attr,
2904 const char *buf,
2905 size_t count)
2906{
2907 struct amdgpu_device *adev = dev_get_drvdata(dev);
2908 int limit_type = to_sensor_dev_attr(attr)->index;
2909 int err;
2910 u32 value;
2911
2912 if (amdgpu_in_reset(adev))
2913 return -EPERM;
2914 if (adev->in_suspend && !adev->in_runpm)
2915 return -EPERM;
2916
2917 if (amdgpu_sriov_vf(adev))
2918 return -EINVAL;
2919
2920 err = kstrtou32(buf, 10, &value);
2921 if (err)
2922 return err;
2923
2924 value = value / 1000000; /* convert to Watt */
2925 value |= limit_type << 24;
2926
2927 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2928 if (err < 0) {
2929 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2930 return err;
2931 }
2932
2933 err = amdgpu_dpm_set_power_limit(adev, value);
2934
2935 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2936 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2937
2938 if (err)
2939 return err;
2940
2941 return count;
2942}
2943
2944static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2945 struct device_attribute *attr,
2946 char *buf)
2947{
2948 struct amdgpu_device *adev = dev_get_drvdata(dev);
2949 uint32_t sclk;
2950 int r, size = sizeof(sclk);
2951
2952 if (amdgpu_in_reset(adev))
2953 return -EPERM;
2954 if (adev->in_suspend && !adev->in_runpm)
2955 return -EPERM;
2956
2957 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2958 if (r < 0) {
2959 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2960 return r;
2961 }
2962
2963 /* get the sclk */
2964 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2965 (void *)&sclk, &size);
2966
2967 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2968 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2969
2970 if (r)
2971 return r;
2972
2973 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
2974}
2975
2976static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2977 struct device_attribute *attr,
2978 char *buf)
2979{
2980 return sysfs_emit(buf, "sclk\n");
2981}
2982
2983static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2984 struct device_attribute *attr,
2985 char *buf)
2986{
2987 struct amdgpu_device *adev = dev_get_drvdata(dev);
2988 uint32_t mclk;
2989 int r, size = sizeof(mclk);
2990
2991 if (amdgpu_in_reset(adev))
2992 return -EPERM;
2993 if (adev->in_suspend && !adev->in_runpm)
2994 return -EPERM;
2995
2996 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2997 if (r < 0) {
2998 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2999 return r;
3000 }
3001
3002 /* get the sclk */
3003 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3004 (void *)&mclk, &size);
3005
3006 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3007 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3008
3009 if (r)
3010 return r;
3011
3012 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3013}
3014
3015static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3016 struct device_attribute *attr,
3017 char *buf)
3018{
3019 return sysfs_emit(buf, "mclk\n");
3020}
3021
3022/**
3023 * DOC: hwmon
3024 *
3025 * The amdgpu driver exposes the following sensor interfaces:
3026 *
3027 * - GPU temperature (via the on-die sensor)
3028 *
3029 * - GPU voltage
3030 *
3031 * - Northbridge voltage (APUs only)
3032 *
3033 * - GPU power
3034 *
3035 * - GPU fan
3036 *
3037 * - GPU gfx/compute engine clock
3038 *
3039 * - GPU memory clock (dGPU only)
3040 *
3041 * hwmon interfaces for GPU temperature:
3042 *
3043 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3044 * - temp2_input and temp3_input are supported on SOC15 dGPUs only
3045 *
3046 * - temp[1-3]_label: temperature channel label
3047 * - temp2_label and temp3_label are supported on SOC15 dGPUs only
3048 *
3049 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3050 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3051 *
3052 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3053 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3054 *
3055 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3056 * - these are supported on SOC15 dGPUs only
3057 *
3058 * hwmon interfaces for GPU voltage:
3059 *
3060 * - in0_input: the voltage on the GPU in millivolts
3061 *
3062 * - in1_input: the voltage on the Northbridge in millivolts
3063 *
3064 * hwmon interfaces for GPU power:
3065 *
3066 * - power1_average: average power used by the GPU in microWatts
3067 *
3068 * - power1_cap_min: minimum cap supported in microWatts
3069 *
3070 * - power1_cap_max: maximum cap supported in microWatts
3071 *
3072 * - power1_cap: selected power cap in microWatts
3073 *
3074 * hwmon interfaces for GPU fan:
3075 *
3076 * - pwm1: pulse width modulation fan level (0-255)
3077 *
3078 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3079 *
3080 * - pwm1_min: pulse width modulation fan control minimum level (0)
3081 *
3082 * - pwm1_max: pulse width modulation fan control maximum level (255)
3083 *
3084 * - fan1_min: a minimum value Unit: revolution/min (RPM)
3085 *
3086 * - fan1_max: a maximum value Unit: revolution/max (RPM)
3087 *
3088 * - fan1_input: fan speed in RPM
3089 *
3090 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3091 *
3092 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3093 *
3094 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3095 * That will get the former one overridden.
3096 *
3097 * hwmon interfaces for GPU clocks:
3098 *
3099 * - freq1_input: the gfx/compute clock in hertz
3100 *
3101 * - freq2_input: the memory clock in hertz
3102 *
3103 * You can use hwmon tools like sensors to view this information on your system.
3104 *
3105 */
3106
3107static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3108static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3109static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3110static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3111static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3112static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3113static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3114static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3115static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3116static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3117static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3118static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3119static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3120static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3121static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3122static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3123static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3124static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3125static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3126static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3127static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3128static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3129static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3130static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3131static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3132static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3133static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3134static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3135static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3136static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3137static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3138static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3139static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3140static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3141static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3142static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3143static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3144static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3145static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3146static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3147static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3148static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3149static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3150static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3151
3152static struct attribute *hwmon_attributes[] = {
3153 &sensor_dev_attr_temp1_input.dev_attr.attr,
3154 &sensor_dev_attr_temp1_crit.dev_attr.attr,
3155 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3156 &sensor_dev_attr_temp2_input.dev_attr.attr,
3157 &sensor_dev_attr_temp2_crit.dev_attr.attr,
3158 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3159 &sensor_dev_attr_temp3_input.dev_attr.attr,
3160 &sensor_dev_attr_temp3_crit.dev_attr.attr,
3161 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3162 &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3163 &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3164 &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3165 &sensor_dev_attr_temp1_label.dev_attr.attr,
3166 &sensor_dev_attr_temp2_label.dev_attr.attr,
3167 &sensor_dev_attr_temp3_label.dev_attr.attr,
3168 &sensor_dev_attr_pwm1.dev_attr.attr,
3169 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3170 &sensor_dev_attr_pwm1_min.dev_attr.attr,
3171 &sensor_dev_attr_pwm1_max.dev_attr.attr,
3172 &sensor_dev_attr_fan1_input.dev_attr.attr,
3173 &sensor_dev_attr_fan1_min.dev_attr.attr,
3174 &sensor_dev_attr_fan1_max.dev_attr.attr,
3175 &sensor_dev_attr_fan1_target.dev_attr.attr,
3176 &sensor_dev_attr_fan1_enable.dev_attr.attr,
3177 &sensor_dev_attr_in0_input.dev_attr.attr,
3178 &sensor_dev_attr_in0_label.dev_attr.attr,
3179 &sensor_dev_attr_in1_input.dev_attr.attr,
3180 &sensor_dev_attr_in1_label.dev_attr.attr,
3181 &sensor_dev_attr_power1_average.dev_attr.attr,
3182 &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3183 &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3184 &sensor_dev_attr_power1_cap.dev_attr.attr,
3185 &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3186 &sensor_dev_attr_power1_label.dev_attr.attr,
3187 &sensor_dev_attr_power2_average.dev_attr.attr,
3188 &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3189 &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3190 &sensor_dev_attr_power2_cap.dev_attr.attr,
3191 &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3192 &sensor_dev_attr_power2_label.dev_attr.attr,
3193 &sensor_dev_attr_freq1_input.dev_attr.attr,
3194 &sensor_dev_attr_freq1_label.dev_attr.attr,
3195 &sensor_dev_attr_freq2_input.dev_attr.attr,
3196 &sensor_dev_attr_freq2_label.dev_attr.attr,
3197 NULL
3198};
3199
3200static umode_t hwmon_attributes_visible(struct kobject *kobj,
3201 struct attribute *attr, int index)
3202{
3203 struct device *dev = kobj_to_dev(kobj);
3204 struct amdgpu_device *adev = dev_get_drvdata(dev);
3205 umode_t effective_mode = attr->mode;
3206 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3207
3208 /* under multi-vf mode, the hwmon attributes are all not supported */
3209 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3210 return 0;
3211
3212 /* under pp one vf mode manage of hwmon attributes is not supported */
3213 if (amdgpu_sriov_is_pp_one_vf(adev))
3214 effective_mode &= ~S_IWUSR;
3215
3216 /* Skip fan attributes if fan is not present */
3217 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3218 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3219 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3220 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3221 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3222 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3223 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3224 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3225 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3226 return 0;
3227
3228 /* Skip fan attributes on APU */
3229 if ((adev->flags & AMD_IS_APU) &&
3230 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3231 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3232 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3233 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3234 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3235 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3236 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3237 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3238 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3239 return 0;
3240
3241 /* Skip crit temp on APU */
3242 if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3243 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3244 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3245 return 0;
3246
3247 /* Skip limit attributes if DPM is not enabled */
3248 if (!adev->pm.dpm_enabled &&
3249 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3250 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3251 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3252 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3253 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3254 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3255 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3256 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3257 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3258 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3259 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3260 return 0;
3261
3262 /* mask fan attributes if we have no bindings for this asic to expose */
3263 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3264 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3265 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3266 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3267 effective_mode &= ~S_IRUGO;
3268
3269 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3270 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3271 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3272 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3273 effective_mode &= ~S_IWUSR;
3274
3275 /* not implemented yet for GC 10.3.1 APUs */
3276 if (((adev->family == AMDGPU_FAMILY_SI) ||
3277 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) &&
3278 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3279 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3280 attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3281 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3282 return 0;
3283
3284 /* not implemented yet for APUs having <= GC 9.3.0 */
3285 if (((adev->family == AMDGPU_FAMILY_SI) ||
3286 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3287 (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3288 return 0;
3289
3290 /* hide max/min values if we can't both query and manage the fan */
3291 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3292 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3293 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3294 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3295 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3296 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3297 return 0;
3298
3299 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3300 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3301 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3302 attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3303 return 0;
3304
3305 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */
3306 adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */
3307 (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3308 attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3309 return 0;
3310
3311 /* only APUs have vddnb */
3312 if (!(adev->flags & AMD_IS_APU) &&
3313 (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3314 attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3315 return 0;
3316
3317 /* no mclk on APUs */
3318 if ((adev->flags & AMD_IS_APU) &&
3319 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3320 attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3321 return 0;
3322
3323 /* only SOC15 dGPUs support hotspot and mem temperatures */
3324 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3325 (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3326 attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3327 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3328 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3329 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3330 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3331 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3332 attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3333 attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3334 attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3335 attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3336 return 0;
3337
3338 /* only Vangogh has fast PPT limit and power labels */
3339 if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3340 (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3341 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3342 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3343 attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3344 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3345 attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3346 return 0;
3347
3348 return effective_mode;
3349}
3350
3351static const struct attribute_group hwmon_attrgroup = {
3352 .attrs = hwmon_attributes,
3353 .is_visible = hwmon_attributes_visible,
3354};
3355
3356static const struct attribute_group *hwmon_groups[] = {
3357 &hwmon_attrgroup,
3358 NULL
3359};
3360
3361int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3362{
3363 int ret;
3364 uint32_t mask = 0;
3365
3366 if (adev->pm.sysfs_initialized)
3367 return 0;
3368
3369 INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3370
3371 if (adev->pm.dpm_enabled == 0)
3372 return 0;
3373
3374 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3375 DRIVER_NAME, adev,
3376 hwmon_groups);
3377 if (IS_ERR(adev->pm.int_hwmon_dev)) {
3378 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3379 dev_err(adev->dev,
3380 "Unable to register hwmon device: %d\n", ret);
3381 return ret;
3382 }
3383
3384 switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3385 case SRIOV_VF_MODE_ONE_VF:
3386 mask = ATTR_FLAG_ONEVF;
3387 break;
3388 case SRIOV_VF_MODE_MULTI_VF:
3389 mask = 0;
3390 break;
3391 case SRIOV_VF_MODE_BARE_METAL:
3392 default:
3393 mask = ATTR_FLAG_MASK_ALL;
3394 break;
3395 }
3396
3397 ret = amdgpu_device_attr_create_groups(adev,
3398 amdgpu_device_attrs,
3399 ARRAY_SIZE(amdgpu_device_attrs),
3400 mask,
3401 &adev->pm.pm_attr_list);
3402 if (ret)
3403 return ret;
3404
3405 adev->pm.sysfs_initialized = true;
3406
3407 return 0;
3408}
3409
3410void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3411{
3412 if (adev->pm.int_hwmon_dev)
3413 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3414
3415 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3416}
3417
3418/*
3419 * Debugfs info
3420 */
3421#if defined(CONFIG_DEBUG_FS)
3422
3423static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3424 struct amdgpu_device *adev) {
3425 uint16_t *p_val;
3426 uint32_t size;
3427 int i;
3428 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3429
3430 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3431 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3432 GFP_KERNEL);
3433
3434 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3435 (void *)p_val, &size)) {
3436 for (i = 0; i < num_cpu_cores; i++)
3437 seq_printf(m, "\t%u MHz (CPU%d)\n",
3438 *(p_val + i), i);
3439 }
3440
3441 kfree(p_val);
3442 }
3443}
3444
3445static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3446{
3447 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3448 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3449 uint32_t value;
3450 uint64_t value64 = 0;
3451 uint32_t query = 0;
3452 int size;
3453
3454 /* GPU Clocks */
3455 size = sizeof(value);
3456 seq_printf(m, "GFX Clocks and Power:\n");
3457
3458 amdgpu_debugfs_prints_cpu_info(m, adev);
3459
3460 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3461 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3462 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3463 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3464 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3465 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3466 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3467 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3468 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3469 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3470 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3471 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3472 size = sizeof(uint32_t);
3473 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3474 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3475 size = sizeof(value);
3476 seq_printf(m, "\n");
3477
3478 /* GPU Temp */
3479 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3480 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3481
3482 /* GPU Load */
3483 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3484 seq_printf(m, "GPU Load: %u %%\n", value);
3485 /* MEM Load */
3486 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3487 seq_printf(m, "MEM Load: %u %%\n", value);
3488
3489 seq_printf(m, "\n");
3490
3491 /* SMC feature mask */
3492 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3493 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3494
3495 /* ASICs greater than CHIP_VEGA20 supports these sensors */
3496 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3497 /* VCN clocks */
3498 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3499 if (!value) {
3500 seq_printf(m, "VCN: Disabled\n");
3501 } else {
3502 seq_printf(m, "VCN: Enabled\n");
3503 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3504 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3505 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3506 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3507 }
3508 }
3509 seq_printf(m, "\n");
3510 } else {
3511 /* UVD clocks */
3512 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3513 if (!value) {
3514 seq_printf(m, "UVD: Disabled\n");
3515 } else {
3516 seq_printf(m, "UVD: Enabled\n");
3517 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3518 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3519 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3520 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3521 }
3522 }
3523 seq_printf(m, "\n");
3524
3525 /* VCE clocks */
3526 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3527 if (!value) {
3528 seq_printf(m, "VCE: Disabled\n");
3529 } else {
3530 seq_printf(m, "VCE: Enabled\n");
3531 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3532 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3533 }
3534 }
3535 }
3536
3537 return 0;
3538}
3539
3540static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3541{
3542 int i;
3543
3544 for (i = 0; clocks[i].flag; i++)
3545 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3546 (flags & clocks[i].flag) ? "On" : "Off");
3547}
3548
3549static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3550{
3551 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3552 struct drm_device *dev = adev_to_drm(adev);
3553 u64 flags = 0;
3554 int r;
3555
3556 if (amdgpu_in_reset(adev))
3557 return -EPERM;
3558 if (adev->in_suspend && !adev->in_runpm)
3559 return -EPERM;
3560
3561 r = pm_runtime_get_sync(dev->dev);
3562 if (r < 0) {
3563 pm_runtime_put_autosuspend(dev->dev);
3564 return r;
3565 }
3566
3567 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3568 r = amdgpu_debugfs_pm_info_pp(m, adev);
3569 if (r)
3570 goto out;
3571 }
3572
3573 amdgpu_device_ip_get_clockgating_state(adev, &flags);
3574
3575 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3576 amdgpu_parse_cg_state(m, flags);
3577 seq_printf(m, "\n");
3578
3579out:
3580 pm_runtime_mark_last_busy(dev->dev);
3581 pm_runtime_put_autosuspend(dev->dev);
3582
3583 return r;
3584}
3585
3586DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3587
3588/*
3589 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3590 *
3591 * Reads debug memory region allocated to PMFW
3592 */
3593static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3594 size_t size, loff_t *pos)
3595{
3596 struct amdgpu_device *adev = file_inode(f)->i_private;
3597 size_t smu_prv_buf_size;
3598 void *smu_prv_buf;
3599 int ret = 0;
3600
3601 if (amdgpu_in_reset(adev))
3602 return -EPERM;
3603 if (adev->in_suspend && !adev->in_runpm)
3604 return -EPERM;
3605
3606 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3607 if (ret)
3608 return ret;
3609
3610 if (!smu_prv_buf || !smu_prv_buf_size)
3611 return -EINVAL;
3612
3613 return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3614 smu_prv_buf_size);
3615}
3616
3617static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3618 .owner = THIS_MODULE,
3619 .open = simple_open,
3620 .read = amdgpu_pm_prv_buffer_read,
3621 .llseek = default_llseek,
3622};
3623
3624#endif
3625
3626void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3627{
3628#if defined(CONFIG_DEBUG_FS)
3629 struct drm_minor *minor = adev_to_drm(adev)->primary;
3630 struct dentry *root = minor->debugfs_root;
3631
3632 if (!adev->pm.dpm_enabled)
3633 return;
3634
3635 debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3636 &amdgpu_debugfs_pm_info_fops);
3637
3638 if (adev->pm.smu_prv_buffer_size > 0)
3639 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3640 adev,
3641 &amdgpu_debugfs_pm_prv_buffer_fops,
3642 adev->pm.smu_prv_buffer_size);
3643
3644 amdgpu_dpm_stb_debug_fs_init(adev);
3645#endif
3646}
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
24 */
25
26#include "amdgpu.h"
27#include "amdgpu_drv.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_dpm.h"
30#include "atom.h"
31#include <linux/pci.h>
32#include <linux/hwmon.h>
33#include <linux/hwmon-sysfs.h>
34#include <linux/nospec.h>
35#include <linux/pm_runtime.h>
36#include <asm/processor.h>
37#include "hwmgr.h"
38
39static const struct cg_flag_name clocks[] = {
40 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
41 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
42 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
43 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
44 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
45 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
46 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
48 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
49 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
50 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
51 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
52 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
53 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
54 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
56 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
57 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
59 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
60 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
62 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
63 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
64 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
65 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
66 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
67 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
68 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
69 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
70
71 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
72 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
73 {0, NULL},
74};
75
76static const struct hwmon_temp_label {
77 enum PP_HWMON_TEMP channel;
78 const char *label;
79} temp_label[] = {
80 {PP_TEMP_EDGE, "edge"},
81 {PP_TEMP_JUNCTION, "junction"},
82 {PP_TEMP_MEM, "mem"},
83};
84
85/**
86 * DOC: power_dpm_state
87 *
88 * The power_dpm_state file is a legacy interface and is only provided for
89 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
90 * certain power related parameters. The file power_dpm_state is used for this.
91 * It accepts the following arguments:
92 *
93 * - battery
94 *
95 * - balanced
96 *
97 * - performance
98 *
99 * battery
100 *
101 * On older GPUs, the vbios provided a special power state for battery
102 * operation. Selecting battery switched to this state. This is no
103 * longer provided on newer GPUs so the option does nothing in that case.
104 *
105 * balanced
106 *
107 * On older GPUs, the vbios provided a special power state for balanced
108 * operation. Selecting balanced switched to this state. This is no
109 * longer provided on newer GPUs so the option does nothing in that case.
110 *
111 * performance
112 *
113 * On older GPUs, the vbios provided a special power state for performance
114 * operation. Selecting performance switched to this state. This is no
115 * longer provided on newer GPUs so the option does nothing in that case.
116 *
117 */
118
119static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
120 struct device_attribute *attr,
121 char *buf)
122{
123 struct drm_device *ddev = dev_get_drvdata(dev);
124 struct amdgpu_device *adev = drm_to_adev(ddev);
125 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
126 enum amd_pm_state_type pm;
127 int ret;
128
129 if (amdgpu_in_reset(adev))
130 return -EPERM;
131 if (adev->in_suspend && !adev->in_runpm)
132 return -EPERM;
133
134 ret = pm_runtime_get_sync(ddev->dev);
135 if (ret < 0) {
136 pm_runtime_put_autosuspend(ddev->dev);
137 return ret;
138 }
139
140 if (pp_funcs->get_current_power_state) {
141 pm = amdgpu_dpm_get_current_power_state(adev);
142 } else {
143 pm = adev->pm.dpm.user_state;
144 }
145
146 pm_runtime_mark_last_busy(ddev->dev);
147 pm_runtime_put_autosuspend(ddev->dev);
148
149 return sysfs_emit(buf, "%s\n",
150 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
151 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
152}
153
154static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
155 struct device_attribute *attr,
156 const char *buf,
157 size_t count)
158{
159 struct drm_device *ddev = dev_get_drvdata(dev);
160 struct amdgpu_device *adev = drm_to_adev(ddev);
161 enum amd_pm_state_type state;
162 int ret;
163
164 if (amdgpu_in_reset(adev))
165 return -EPERM;
166 if (adev->in_suspend && !adev->in_runpm)
167 return -EPERM;
168
169 if (strncmp("battery", buf, strlen("battery")) == 0)
170 state = POWER_STATE_TYPE_BATTERY;
171 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
172 state = POWER_STATE_TYPE_BALANCED;
173 else if (strncmp("performance", buf, strlen("performance")) == 0)
174 state = POWER_STATE_TYPE_PERFORMANCE;
175 else
176 return -EINVAL;
177
178 ret = pm_runtime_get_sync(ddev->dev);
179 if (ret < 0) {
180 pm_runtime_put_autosuspend(ddev->dev);
181 return ret;
182 }
183
184 if (is_support_sw_smu(adev)) {
185 mutex_lock(&adev->pm.mutex);
186 adev->pm.dpm.user_state = state;
187 mutex_unlock(&adev->pm.mutex);
188 } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
189 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
190 } else {
191 mutex_lock(&adev->pm.mutex);
192 adev->pm.dpm.user_state = state;
193 mutex_unlock(&adev->pm.mutex);
194
195 amdgpu_pm_compute_clocks(adev);
196 }
197 pm_runtime_mark_last_busy(ddev->dev);
198 pm_runtime_put_autosuspend(ddev->dev);
199
200 return count;
201}
202
203
204/**
205 * DOC: power_dpm_force_performance_level
206 *
207 * The amdgpu driver provides a sysfs API for adjusting certain power
208 * related parameters. The file power_dpm_force_performance_level is
209 * used for this. It accepts the following arguments:
210 *
211 * - auto
212 *
213 * - low
214 *
215 * - high
216 *
217 * - manual
218 *
219 * - profile_standard
220 *
221 * - profile_min_sclk
222 *
223 * - profile_min_mclk
224 *
225 * - profile_peak
226 *
227 * auto
228 *
229 * When auto is selected, the driver will attempt to dynamically select
230 * the optimal power profile for current conditions in the driver.
231 *
232 * low
233 *
234 * When low is selected, the clocks are forced to the lowest power state.
235 *
236 * high
237 *
238 * When high is selected, the clocks are forced to the highest power state.
239 *
240 * manual
241 *
242 * When manual is selected, the user can manually adjust which power states
243 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
244 * and pp_dpm_pcie files and adjust the power state transition heuristics
245 * via the pp_power_profile_mode sysfs file.
246 *
247 * profile_standard
248 * profile_min_sclk
249 * profile_min_mclk
250 * profile_peak
251 *
252 * When the profiling modes are selected, clock and power gating are
253 * disabled and the clocks are set for different profiling cases. This
254 * mode is recommended for profiling specific work loads where you do
255 * not want clock or power gating for clock fluctuation to interfere
256 * with your results. profile_standard sets the clocks to a fixed clock
257 * level which varies from asic to asic. profile_min_sclk forces the sclk
258 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
259 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
260 *
261 */
262
263static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
264 struct device_attribute *attr,
265 char *buf)
266{
267 struct drm_device *ddev = dev_get_drvdata(dev);
268 struct amdgpu_device *adev = drm_to_adev(ddev);
269 enum amd_dpm_forced_level level = 0xff;
270 int ret;
271
272 if (amdgpu_in_reset(adev))
273 return -EPERM;
274 if (adev->in_suspend && !adev->in_runpm)
275 return -EPERM;
276
277 ret = pm_runtime_get_sync(ddev->dev);
278 if (ret < 0) {
279 pm_runtime_put_autosuspend(ddev->dev);
280 return ret;
281 }
282
283 if (adev->powerplay.pp_funcs->get_performance_level)
284 level = amdgpu_dpm_get_performance_level(adev);
285 else
286 level = adev->pm.dpm.forced_level;
287
288 pm_runtime_mark_last_busy(ddev->dev);
289 pm_runtime_put_autosuspend(ddev->dev);
290
291 return sysfs_emit(buf, "%s\n",
292 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
293 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
294 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
295 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
296 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
297 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
298 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
299 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
300 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
301 "unknown");
302}
303
304static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
305 struct device_attribute *attr,
306 const char *buf,
307 size_t count)
308{
309 struct drm_device *ddev = dev_get_drvdata(dev);
310 struct amdgpu_device *adev = drm_to_adev(ddev);
311 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
312 enum amd_dpm_forced_level level;
313 enum amd_dpm_forced_level current_level = 0xff;
314 int ret = 0;
315
316 if (amdgpu_in_reset(adev))
317 return -EPERM;
318 if (adev->in_suspend && !adev->in_runpm)
319 return -EPERM;
320
321 if (strncmp("low", buf, strlen("low")) == 0) {
322 level = AMD_DPM_FORCED_LEVEL_LOW;
323 } else if (strncmp("high", buf, strlen("high")) == 0) {
324 level = AMD_DPM_FORCED_LEVEL_HIGH;
325 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
326 level = AMD_DPM_FORCED_LEVEL_AUTO;
327 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
328 level = AMD_DPM_FORCED_LEVEL_MANUAL;
329 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
330 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
331 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
332 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
333 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
334 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
335 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
336 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
337 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
338 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
339 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
340 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
341 } else {
342 return -EINVAL;
343 }
344
345 ret = pm_runtime_get_sync(ddev->dev);
346 if (ret < 0) {
347 pm_runtime_put_autosuspend(ddev->dev);
348 return ret;
349 }
350
351 if (pp_funcs->get_performance_level)
352 current_level = amdgpu_dpm_get_performance_level(adev);
353
354 if (current_level == level) {
355 pm_runtime_mark_last_busy(ddev->dev);
356 pm_runtime_put_autosuspend(ddev->dev);
357 return count;
358 }
359
360 if (adev->asic_type == CHIP_RAVEN) {
361 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
362 if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
363 amdgpu_gfx_off_ctrl(adev, false);
364 else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
365 amdgpu_gfx_off_ctrl(adev, true);
366 }
367 }
368
369 /* profile_exit setting is valid only when current mode is in profile mode */
370 if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
371 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
372 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
373 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
374 (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
375 pr_err("Currently not in any profile mode!\n");
376 pm_runtime_mark_last_busy(ddev->dev);
377 pm_runtime_put_autosuspend(ddev->dev);
378 return -EINVAL;
379 }
380
381 if (pp_funcs->force_performance_level) {
382 mutex_lock(&adev->pm.mutex);
383 if (adev->pm.dpm.thermal_active) {
384 mutex_unlock(&adev->pm.mutex);
385 pm_runtime_mark_last_busy(ddev->dev);
386 pm_runtime_put_autosuspend(ddev->dev);
387 return -EINVAL;
388 }
389 ret = amdgpu_dpm_force_performance_level(adev, level);
390 if (ret) {
391 mutex_unlock(&adev->pm.mutex);
392 pm_runtime_mark_last_busy(ddev->dev);
393 pm_runtime_put_autosuspend(ddev->dev);
394 return -EINVAL;
395 } else {
396 adev->pm.dpm.forced_level = level;
397 }
398 mutex_unlock(&adev->pm.mutex);
399 }
400 pm_runtime_mark_last_busy(ddev->dev);
401 pm_runtime_put_autosuspend(ddev->dev);
402
403 return count;
404}
405
406static ssize_t amdgpu_get_pp_num_states(struct device *dev,
407 struct device_attribute *attr,
408 char *buf)
409{
410 struct drm_device *ddev = dev_get_drvdata(dev);
411 struct amdgpu_device *adev = drm_to_adev(ddev);
412 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
413 struct pp_states_info data;
414 uint32_t i;
415 int buf_len, ret;
416
417 if (amdgpu_in_reset(adev))
418 return -EPERM;
419 if (adev->in_suspend && !adev->in_runpm)
420 return -EPERM;
421
422 ret = pm_runtime_get_sync(ddev->dev);
423 if (ret < 0) {
424 pm_runtime_put_autosuspend(ddev->dev);
425 return ret;
426 }
427
428 if (pp_funcs->get_pp_num_states) {
429 amdgpu_dpm_get_pp_num_states(adev, &data);
430 } else {
431 memset(&data, 0, sizeof(data));
432 }
433
434 pm_runtime_mark_last_busy(ddev->dev);
435 pm_runtime_put_autosuspend(ddev->dev);
436
437 buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
438 for (i = 0; i < data.nums; i++)
439 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
440 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
441 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
443 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
444
445 return buf_len;
446}
447
448static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
449 struct device_attribute *attr,
450 char *buf)
451{
452 struct drm_device *ddev = dev_get_drvdata(dev);
453 struct amdgpu_device *adev = drm_to_adev(ddev);
454 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
455 struct pp_states_info data = {0};
456 enum amd_pm_state_type pm = 0;
457 int i = 0, ret = 0;
458
459 if (amdgpu_in_reset(adev))
460 return -EPERM;
461 if (adev->in_suspend && !adev->in_runpm)
462 return -EPERM;
463
464 ret = pm_runtime_get_sync(ddev->dev);
465 if (ret < 0) {
466 pm_runtime_put_autosuspend(ddev->dev);
467 return ret;
468 }
469
470 if (pp_funcs->get_current_power_state
471 && pp_funcs->get_pp_num_states) {
472 pm = amdgpu_dpm_get_current_power_state(adev);
473 amdgpu_dpm_get_pp_num_states(adev, &data);
474 }
475
476 pm_runtime_mark_last_busy(ddev->dev);
477 pm_runtime_put_autosuspend(ddev->dev);
478
479 for (i = 0; i < data.nums; i++) {
480 if (pm == data.states[i])
481 break;
482 }
483
484 if (i == data.nums)
485 i = -EINVAL;
486
487 return sysfs_emit(buf, "%d\n", i);
488}
489
490static ssize_t amdgpu_get_pp_force_state(struct device *dev,
491 struct device_attribute *attr,
492 char *buf)
493{
494 struct drm_device *ddev = dev_get_drvdata(dev);
495 struct amdgpu_device *adev = drm_to_adev(ddev);
496
497 if (amdgpu_in_reset(adev))
498 return -EPERM;
499 if (adev->in_suspend && !adev->in_runpm)
500 return -EPERM;
501
502 if (adev->pp_force_state_enabled)
503 return amdgpu_get_pp_cur_state(dev, attr, buf);
504 else
505 return sysfs_emit(buf, "\n");
506}
507
508static ssize_t amdgpu_set_pp_force_state(struct device *dev,
509 struct device_attribute *attr,
510 const char *buf,
511 size_t count)
512{
513 struct drm_device *ddev = dev_get_drvdata(dev);
514 struct amdgpu_device *adev = drm_to_adev(ddev);
515 enum amd_pm_state_type state = 0;
516 unsigned long idx;
517 int ret;
518
519 if (amdgpu_in_reset(adev))
520 return -EPERM;
521 if (adev->in_suspend && !adev->in_runpm)
522 return -EPERM;
523
524 if (strlen(buf) == 1)
525 adev->pp_force_state_enabled = false;
526 else if (is_support_sw_smu(adev))
527 adev->pp_force_state_enabled = false;
528 else if (adev->powerplay.pp_funcs->dispatch_tasks &&
529 adev->powerplay.pp_funcs->get_pp_num_states) {
530 struct pp_states_info data;
531
532 ret = kstrtoul(buf, 0, &idx);
533 if (ret || idx >= ARRAY_SIZE(data.states))
534 return -EINVAL;
535
536 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
537
538 amdgpu_dpm_get_pp_num_states(adev, &data);
539 state = data.states[idx];
540
541 ret = pm_runtime_get_sync(ddev->dev);
542 if (ret < 0) {
543 pm_runtime_put_autosuspend(ddev->dev);
544 return ret;
545 }
546
547 /* only set user selected power states */
548 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
549 state != POWER_STATE_TYPE_DEFAULT) {
550 amdgpu_dpm_dispatch_task(adev,
551 AMD_PP_TASK_ENABLE_USER_STATE, &state);
552 adev->pp_force_state_enabled = true;
553 }
554 pm_runtime_mark_last_busy(ddev->dev);
555 pm_runtime_put_autosuspend(ddev->dev);
556 }
557
558 return count;
559}
560
561/**
562 * DOC: pp_table
563 *
564 * The amdgpu driver provides a sysfs API for uploading new powerplay
565 * tables. The file pp_table is used for this. Reading the file
566 * will dump the current power play table. Writing to the file
567 * will attempt to upload a new powerplay table and re-initialize
568 * powerplay using that new table.
569 *
570 */
571
572static ssize_t amdgpu_get_pp_table(struct device *dev,
573 struct device_attribute *attr,
574 char *buf)
575{
576 struct drm_device *ddev = dev_get_drvdata(dev);
577 struct amdgpu_device *adev = drm_to_adev(ddev);
578 char *table = NULL;
579 int size, ret;
580
581 if (amdgpu_in_reset(adev))
582 return -EPERM;
583 if (adev->in_suspend && !adev->in_runpm)
584 return -EPERM;
585
586 ret = pm_runtime_get_sync(ddev->dev);
587 if (ret < 0) {
588 pm_runtime_put_autosuspend(ddev->dev);
589 return ret;
590 }
591
592 if (adev->powerplay.pp_funcs->get_pp_table) {
593 size = amdgpu_dpm_get_pp_table(adev, &table);
594 pm_runtime_mark_last_busy(ddev->dev);
595 pm_runtime_put_autosuspend(ddev->dev);
596 if (size < 0)
597 return size;
598 } else {
599 pm_runtime_mark_last_busy(ddev->dev);
600 pm_runtime_put_autosuspend(ddev->dev);
601 return 0;
602 }
603
604 if (size >= PAGE_SIZE)
605 size = PAGE_SIZE - 1;
606
607 memcpy(buf, table, size);
608
609 return size;
610}
611
612static ssize_t amdgpu_set_pp_table(struct device *dev,
613 struct device_attribute *attr,
614 const char *buf,
615 size_t count)
616{
617 struct drm_device *ddev = dev_get_drvdata(dev);
618 struct amdgpu_device *adev = drm_to_adev(ddev);
619 int ret = 0;
620
621 if (amdgpu_in_reset(adev))
622 return -EPERM;
623 if (adev->in_suspend && !adev->in_runpm)
624 return -EPERM;
625
626 ret = pm_runtime_get_sync(ddev->dev);
627 if (ret < 0) {
628 pm_runtime_put_autosuspend(ddev->dev);
629 return ret;
630 }
631
632 ret = amdgpu_dpm_set_pp_table(adev, buf, count);
633 if (ret) {
634 pm_runtime_mark_last_busy(ddev->dev);
635 pm_runtime_put_autosuspend(ddev->dev);
636 return ret;
637 }
638
639 pm_runtime_mark_last_busy(ddev->dev);
640 pm_runtime_put_autosuspend(ddev->dev);
641
642 return count;
643}
644
645/**
646 * DOC: pp_od_clk_voltage
647 *
648 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
649 * in each power level within a power state. The pp_od_clk_voltage is used for
650 * this.
651 *
652 * Note that the actual memory controller clock rate are exposed, not
653 * the effective memory clock of the DRAMs. To translate it, use the
654 * following formula:
655 *
656 * Clock conversion (Mhz):
657 *
658 * HBM: effective_memory_clock = memory_controller_clock * 1
659 *
660 * G5: effective_memory_clock = memory_controller_clock * 1
661 *
662 * G6: effective_memory_clock = memory_controller_clock * 2
663 *
664 * DRAM data rate (MT/s):
665 *
666 * HBM: effective_memory_clock * 2 = data_rate
667 *
668 * G5: effective_memory_clock * 4 = data_rate
669 *
670 * G6: effective_memory_clock * 8 = data_rate
671 *
672 * Bandwidth (MB/s):
673 *
674 * data_rate * vram_bit_width / 8 = memory_bandwidth
675 *
676 * Some examples:
677 *
678 * G5 on RX460:
679 *
680 * memory_controller_clock = 1750 Mhz
681 *
682 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
683 *
684 * data rate = 1750 * 4 = 7000 MT/s
685 *
686 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
687 *
688 * G6 on RX5700:
689 *
690 * memory_controller_clock = 875 Mhz
691 *
692 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
693 *
694 * data rate = 1750 * 8 = 14000 MT/s
695 *
696 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
697 *
698 * < For Vega10 and previous ASICs >
699 *
700 * Reading the file will display:
701 *
702 * - a list of engine clock levels and voltages labeled OD_SCLK
703 *
704 * - a list of memory clock levels and voltages labeled OD_MCLK
705 *
706 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
707 *
708 * To manually adjust these settings, first select manual using
709 * power_dpm_force_performance_level. Enter a new value for each
710 * level by writing a string that contains "s/m level clock voltage" to
711 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
712 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
713 * 810 mV. When you have edited all of the states as needed, write
714 * "c" (commit) to the file to commit your changes. If you want to reset to the
715 * default power levels, write "r" (reset) to the file to reset them.
716 *
717 *
718 * < For Vega20 and newer ASICs >
719 *
720 * Reading the file will display:
721 *
722 * - minimum and maximum engine clock labeled OD_SCLK
723 *
724 * - minimum(not available for Vega20 and Navi1x) and maximum memory
725 * clock labeled OD_MCLK
726 *
727 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
728 * They can be used to calibrate the sclk voltage curve.
729 *
730 * - voltage offset(in mV) applied on target voltage calculation.
731 * This is available for Sienna Cichlid, Navy Flounder and Dimgrey
732 * Cavefish. For these ASICs, the target voltage calculation can be
733 * illustrated by "voltage = voltage calculated from v/f curve +
734 * overdrive vddgfx offset"
735 *
736 * - a list of valid ranges for sclk, mclk, and voltage curve points
737 * labeled OD_RANGE
738 *
739 * < For APUs >
740 *
741 * Reading the file will display:
742 *
743 * - minimum and maximum engine clock labeled OD_SCLK
744 *
745 * - a list of valid ranges for sclk labeled OD_RANGE
746 *
747 * < For VanGogh >
748 *
749 * Reading the file will display:
750 *
751 * - minimum and maximum engine clock labeled OD_SCLK
752 * - minimum and maximum core clocks labeled OD_CCLK
753 *
754 * - a list of valid ranges for sclk and cclk labeled OD_RANGE
755 *
756 * To manually adjust these settings:
757 *
758 * - First select manual using power_dpm_force_performance_level
759 *
760 * - For clock frequency setting, enter a new value by writing a
761 * string that contains "s/m index clock" to the file. The index
762 * should be 0 if to set minimum clock. And 1 if to set maximum
763 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
764 * "m 1 800" will update maximum mclk to be 800Mhz. For core
765 * clocks on VanGogh, the string contains "p core index clock".
766 * E.g., "p 2 0 800" would set the minimum core clock on core
767 * 2 to 800Mhz.
768 *
769 * For sclk voltage curve, enter the new values by writing a
770 * string that contains "vc point clock voltage" to the file. The
771 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
772 * update point1 with clock set as 300Mhz and voltage as
773 * 600mV. "vc 2 1000 1000" will update point3 with clock set
774 * as 1000Mhz and voltage 1000mV.
775 *
776 * To update the voltage offset applied for gfxclk/voltage calculation,
777 * enter the new value by writing a string that contains "vo offset".
778 * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
779 * And the offset can be a positive or negative value.
780 *
781 * - When you have edited all of the states as needed, write "c" (commit)
782 * to the file to commit your changes
783 *
784 * - If you want to reset to the default power levels, write "r" (reset)
785 * to the file to reset them
786 *
787 */
788
789static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
790 struct device_attribute *attr,
791 const char *buf,
792 size_t count)
793{
794 struct drm_device *ddev = dev_get_drvdata(dev);
795 struct amdgpu_device *adev = drm_to_adev(ddev);
796 int ret;
797 uint32_t parameter_size = 0;
798 long parameter[64];
799 char buf_cpy[128];
800 char *tmp_str;
801 char *sub_str;
802 const char delimiter[3] = {' ', '\n', '\0'};
803 uint32_t type;
804
805 if (amdgpu_in_reset(adev))
806 return -EPERM;
807 if (adev->in_suspend && !adev->in_runpm)
808 return -EPERM;
809
810 if (count > 127)
811 return -EINVAL;
812
813 if (*buf == 's')
814 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
815 else if (*buf == 'p')
816 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
817 else if (*buf == 'm')
818 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
819 else if(*buf == 'r')
820 type = PP_OD_RESTORE_DEFAULT_TABLE;
821 else if (*buf == 'c')
822 type = PP_OD_COMMIT_DPM_TABLE;
823 else if (!strncmp(buf, "vc", 2))
824 type = PP_OD_EDIT_VDDC_CURVE;
825 else if (!strncmp(buf, "vo", 2))
826 type = PP_OD_EDIT_VDDGFX_OFFSET;
827 else
828 return -EINVAL;
829
830 memcpy(buf_cpy, buf, count+1);
831
832 tmp_str = buf_cpy;
833
834 if ((type == PP_OD_EDIT_VDDC_CURVE) ||
835 (type == PP_OD_EDIT_VDDGFX_OFFSET))
836 tmp_str++;
837 while (isspace(*++tmp_str));
838
839 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
840 if (strlen(sub_str) == 0)
841 continue;
842 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
843 if (ret)
844 return -EINVAL;
845 parameter_size++;
846
847 while (isspace(*tmp_str))
848 tmp_str++;
849 }
850
851 ret = pm_runtime_get_sync(ddev->dev);
852 if (ret < 0) {
853 pm_runtime_put_autosuspend(ddev->dev);
854 return ret;
855 }
856
857 if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
858 ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
859 parameter,
860 parameter_size);
861 if (ret) {
862 pm_runtime_mark_last_busy(ddev->dev);
863 pm_runtime_put_autosuspend(ddev->dev);
864 return -EINVAL;
865 }
866 }
867
868 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
869 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
870 parameter, parameter_size);
871 if (ret) {
872 pm_runtime_mark_last_busy(ddev->dev);
873 pm_runtime_put_autosuspend(ddev->dev);
874 return -EINVAL;
875 }
876 }
877
878 if (type == PP_OD_COMMIT_DPM_TABLE) {
879 if (adev->powerplay.pp_funcs->dispatch_tasks) {
880 amdgpu_dpm_dispatch_task(adev,
881 AMD_PP_TASK_READJUST_POWER_STATE,
882 NULL);
883 pm_runtime_mark_last_busy(ddev->dev);
884 pm_runtime_put_autosuspend(ddev->dev);
885 return count;
886 } else {
887 pm_runtime_mark_last_busy(ddev->dev);
888 pm_runtime_put_autosuspend(ddev->dev);
889 return -EINVAL;
890 }
891 }
892
893 pm_runtime_mark_last_busy(ddev->dev);
894 pm_runtime_put_autosuspend(ddev->dev);
895
896 return count;
897}
898
899static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
900 struct device_attribute *attr,
901 char *buf)
902{
903 struct drm_device *ddev = dev_get_drvdata(dev);
904 struct amdgpu_device *adev = drm_to_adev(ddev);
905 ssize_t size;
906 int ret;
907
908 if (amdgpu_in_reset(adev))
909 return -EPERM;
910 if (adev->in_suspend && !adev->in_runpm)
911 return -EPERM;
912
913 ret = pm_runtime_get_sync(ddev->dev);
914 if (ret < 0) {
915 pm_runtime_put_autosuspend(ddev->dev);
916 return ret;
917 }
918
919 if (adev->powerplay.pp_funcs->print_clock_levels) {
920 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
921 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
922 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
923 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size);
924 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
925 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
926 } else {
927 size = sysfs_emit(buf, "\n");
928 }
929 pm_runtime_mark_last_busy(ddev->dev);
930 pm_runtime_put_autosuspend(ddev->dev);
931
932 return size;
933}
934
935/**
936 * DOC: pp_features
937 *
938 * The amdgpu driver provides a sysfs API for adjusting what powerplay
939 * features to be enabled. The file pp_features is used for this. And
940 * this is only available for Vega10 and later dGPUs.
941 *
942 * Reading back the file will show you the followings:
943 * - Current ppfeature masks
944 * - List of the all supported powerplay features with their naming,
945 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
946 *
947 * To manually enable or disable a specific feature, just set or clear
948 * the corresponding bit from original ppfeature masks and input the
949 * new ppfeature masks.
950 */
951static ssize_t amdgpu_set_pp_features(struct device *dev,
952 struct device_attribute *attr,
953 const char *buf,
954 size_t count)
955{
956 struct drm_device *ddev = dev_get_drvdata(dev);
957 struct amdgpu_device *adev = drm_to_adev(ddev);
958 uint64_t featuremask;
959 int ret;
960
961 if (amdgpu_in_reset(adev))
962 return -EPERM;
963 if (adev->in_suspend && !adev->in_runpm)
964 return -EPERM;
965
966 ret = kstrtou64(buf, 0, &featuremask);
967 if (ret)
968 return -EINVAL;
969
970 ret = pm_runtime_get_sync(ddev->dev);
971 if (ret < 0) {
972 pm_runtime_put_autosuspend(ddev->dev);
973 return ret;
974 }
975
976 if (adev->powerplay.pp_funcs->set_ppfeature_status) {
977 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
978 if (ret) {
979 pm_runtime_mark_last_busy(ddev->dev);
980 pm_runtime_put_autosuspend(ddev->dev);
981 return -EINVAL;
982 }
983 }
984 pm_runtime_mark_last_busy(ddev->dev);
985 pm_runtime_put_autosuspend(ddev->dev);
986
987 return count;
988}
989
990static ssize_t amdgpu_get_pp_features(struct device *dev,
991 struct device_attribute *attr,
992 char *buf)
993{
994 struct drm_device *ddev = dev_get_drvdata(dev);
995 struct amdgpu_device *adev = drm_to_adev(ddev);
996 ssize_t size;
997 int ret;
998
999 if (amdgpu_in_reset(adev))
1000 return -EPERM;
1001 if (adev->in_suspend && !adev->in_runpm)
1002 return -EPERM;
1003
1004 ret = pm_runtime_get_sync(ddev->dev);
1005 if (ret < 0) {
1006 pm_runtime_put_autosuspend(ddev->dev);
1007 return ret;
1008 }
1009
1010 if (adev->powerplay.pp_funcs->get_ppfeature_status)
1011 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
1012 else
1013 size = sysfs_emit(buf, "\n");
1014
1015 pm_runtime_mark_last_busy(ddev->dev);
1016 pm_runtime_put_autosuspend(ddev->dev);
1017
1018 return size;
1019}
1020
1021/**
1022 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1023 *
1024 * The amdgpu driver provides a sysfs API for adjusting what power levels
1025 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
1026 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1027 * this.
1028 *
1029 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1030 * Vega10 and later ASICs.
1031 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1032 *
1033 * Reading back the files will show you the available power levels within
1034 * the power state and the clock information for those levels.
1035 *
1036 * To manually adjust these states, first select manual using
1037 * power_dpm_force_performance_level.
1038 * Secondly, enter a new value for each level by inputing a string that
1039 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1040 * E.g.,
1041 *
1042 * .. code-block:: bash
1043 *
1044 * echo "4 5 6" > pp_dpm_sclk
1045 *
1046 * will enable sclk levels 4, 5, and 6.
1047 *
1048 * NOTE: change to the dcefclk max dpm level is not supported now
1049 */
1050
1051static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1052 enum pp_clock_type type,
1053 char *buf)
1054{
1055 struct drm_device *ddev = dev_get_drvdata(dev);
1056 struct amdgpu_device *adev = drm_to_adev(ddev);
1057 ssize_t size;
1058 int ret;
1059
1060 if (amdgpu_in_reset(adev))
1061 return -EPERM;
1062 if (adev->in_suspend && !adev->in_runpm)
1063 return -EPERM;
1064
1065 ret = pm_runtime_get_sync(ddev->dev);
1066 if (ret < 0) {
1067 pm_runtime_put_autosuspend(ddev->dev);
1068 return ret;
1069 }
1070
1071 if (adev->powerplay.pp_funcs->print_clock_levels)
1072 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1073 else
1074 size = sysfs_emit(buf, "\n");
1075
1076 pm_runtime_mark_last_busy(ddev->dev);
1077 pm_runtime_put_autosuspend(ddev->dev);
1078
1079 return size;
1080}
1081
1082/*
1083 * Worst case: 32 bits individually specified, in octal at 12 characters
1084 * per line (+1 for \n).
1085 */
1086#define AMDGPU_MASK_BUF_MAX (32 * 13)
1087
1088static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1089{
1090 int ret;
1091 unsigned long level;
1092 char *sub_str = NULL;
1093 char *tmp;
1094 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1095 const char delimiter[3] = {' ', '\n', '\0'};
1096 size_t bytes;
1097
1098 *mask = 0;
1099
1100 bytes = min(count, sizeof(buf_cpy) - 1);
1101 memcpy(buf_cpy, buf, bytes);
1102 buf_cpy[bytes] = '\0';
1103 tmp = buf_cpy;
1104 while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1105 if (strlen(sub_str)) {
1106 ret = kstrtoul(sub_str, 0, &level);
1107 if (ret || level > 31)
1108 return -EINVAL;
1109 *mask |= 1 << level;
1110 } else
1111 break;
1112 }
1113
1114 return 0;
1115}
1116
1117static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1118 enum pp_clock_type type,
1119 const char *buf,
1120 size_t count)
1121{
1122 struct drm_device *ddev = dev_get_drvdata(dev);
1123 struct amdgpu_device *adev = drm_to_adev(ddev);
1124 int ret;
1125 uint32_t mask = 0;
1126
1127 if (amdgpu_in_reset(adev))
1128 return -EPERM;
1129 if (adev->in_suspend && !adev->in_runpm)
1130 return -EPERM;
1131
1132 ret = amdgpu_read_mask(buf, count, &mask);
1133 if (ret)
1134 return ret;
1135
1136 ret = pm_runtime_get_sync(ddev->dev);
1137 if (ret < 0) {
1138 pm_runtime_put_autosuspend(ddev->dev);
1139 return ret;
1140 }
1141
1142 if (adev->powerplay.pp_funcs->force_clock_level)
1143 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1144 else
1145 ret = 0;
1146
1147 pm_runtime_mark_last_busy(ddev->dev);
1148 pm_runtime_put_autosuspend(ddev->dev);
1149
1150 if (ret)
1151 return -EINVAL;
1152
1153 return count;
1154}
1155
1156static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1157 struct device_attribute *attr,
1158 char *buf)
1159{
1160 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1161}
1162
1163static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1164 struct device_attribute *attr,
1165 const char *buf,
1166 size_t count)
1167{
1168 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1169}
1170
1171static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1172 struct device_attribute *attr,
1173 char *buf)
1174{
1175 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1176}
1177
1178static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1179 struct device_attribute *attr,
1180 const char *buf,
1181 size_t count)
1182{
1183 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1184}
1185
1186static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1187 struct device_attribute *attr,
1188 char *buf)
1189{
1190 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1191}
1192
1193static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1194 struct device_attribute *attr,
1195 const char *buf,
1196 size_t count)
1197{
1198 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1199}
1200
1201static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1202 struct device_attribute *attr,
1203 char *buf)
1204{
1205 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1206}
1207
1208static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1209 struct device_attribute *attr,
1210 const char *buf,
1211 size_t count)
1212{
1213 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1214}
1215
1216static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1217 struct device_attribute *attr,
1218 char *buf)
1219{
1220 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1221}
1222
1223static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1224 struct device_attribute *attr,
1225 const char *buf,
1226 size_t count)
1227{
1228 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1229}
1230
1231static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1232 struct device_attribute *attr,
1233 char *buf)
1234{
1235 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1236}
1237
1238static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1239 struct device_attribute *attr,
1240 const char *buf,
1241 size_t count)
1242{
1243 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1244}
1245
1246static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1247 struct device_attribute *attr,
1248 char *buf)
1249{
1250 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1251}
1252
1253static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1254 struct device_attribute *attr,
1255 const char *buf,
1256 size_t count)
1257{
1258 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1259}
1260
1261static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1262 struct device_attribute *attr,
1263 char *buf)
1264{
1265 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1266}
1267
1268static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1269 struct device_attribute *attr,
1270 const char *buf,
1271 size_t count)
1272{
1273 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1274}
1275
1276static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1277 struct device_attribute *attr,
1278 char *buf)
1279{
1280 struct drm_device *ddev = dev_get_drvdata(dev);
1281 struct amdgpu_device *adev = drm_to_adev(ddev);
1282 uint32_t value = 0;
1283 int ret;
1284
1285 if (amdgpu_in_reset(adev))
1286 return -EPERM;
1287 if (adev->in_suspend && !adev->in_runpm)
1288 return -EPERM;
1289
1290 ret = pm_runtime_get_sync(ddev->dev);
1291 if (ret < 0) {
1292 pm_runtime_put_autosuspend(ddev->dev);
1293 return ret;
1294 }
1295
1296 if (is_support_sw_smu(adev))
1297 value = 0;
1298 else if (adev->powerplay.pp_funcs->get_sclk_od)
1299 value = amdgpu_dpm_get_sclk_od(adev);
1300
1301 pm_runtime_mark_last_busy(ddev->dev);
1302 pm_runtime_put_autosuspend(ddev->dev);
1303
1304 return sysfs_emit(buf, "%d\n", value);
1305}
1306
1307static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1308 struct device_attribute *attr,
1309 const char *buf,
1310 size_t count)
1311{
1312 struct drm_device *ddev = dev_get_drvdata(dev);
1313 struct amdgpu_device *adev = drm_to_adev(ddev);
1314 int ret;
1315 long int value;
1316
1317 if (amdgpu_in_reset(adev))
1318 return -EPERM;
1319 if (adev->in_suspend && !adev->in_runpm)
1320 return -EPERM;
1321
1322 ret = kstrtol(buf, 0, &value);
1323
1324 if (ret)
1325 return -EINVAL;
1326
1327 ret = pm_runtime_get_sync(ddev->dev);
1328 if (ret < 0) {
1329 pm_runtime_put_autosuspend(ddev->dev);
1330 return ret;
1331 }
1332
1333 if (is_support_sw_smu(adev)) {
1334 value = 0;
1335 } else {
1336 if (adev->powerplay.pp_funcs->set_sclk_od)
1337 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1338
1339 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1340 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1341 } else {
1342 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1343 amdgpu_pm_compute_clocks(adev);
1344 }
1345 }
1346
1347 pm_runtime_mark_last_busy(ddev->dev);
1348 pm_runtime_put_autosuspend(ddev->dev);
1349
1350 return count;
1351}
1352
1353static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1354 struct device_attribute *attr,
1355 char *buf)
1356{
1357 struct drm_device *ddev = dev_get_drvdata(dev);
1358 struct amdgpu_device *adev = drm_to_adev(ddev);
1359 uint32_t value = 0;
1360 int ret;
1361
1362 if (amdgpu_in_reset(adev))
1363 return -EPERM;
1364 if (adev->in_suspend && !adev->in_runpm)
1365 return -EPERM;
1366
1367 ret = pm_runtime_get_sync(ddev->dev);
1368 if (ret < 0) {
1369 pm_runtime_put_autosuspend(ddev->dev);
1370 return ret;
1371 }
1372
1373 if (is_support_sw_smu(adev))
1374 value = 0;
1375 else if (adev->powerplay.pp_funcs->get_mclk_od)
1376 value = amdgpu_dpm_get_mclk_od(adev);
1377
1378 pm_runtime_mark_last_busy(ddev->dev);
1379 pm_runtime_put_autosuspend(ddev->dev);
1380
1381 return sysfs_emit(buf, "%d\n", value);
1382}
1383
1384static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1385 struct device_attribute *attr,
1386 const char *buf,
1387 size_t count)
1388{
1389 struct drm_device *ddev = dev_get_drvdata(dev);
1390 struct amdgpu_device *adev = drm_to_adev(ddev);
1391 int ret;
1392 long int value;
1393
1394 if (amdgpu_in_reset(adev))
1395 return -EPERM;
1396 if (adev->in_suspend && !adev->in_runpm)
1397 return -EPERM;
1398
1399 ret = kstrtol(buf, 0, &value);
1400
1401 if (ret)
1402 return -EINVAL;
1403
1404 ret = pm_runtime_get_sync(ddev->dev);
1405 if (ret < 0) {
1406 pm_runtime_put_autosuspend(ddev->dev);
1407 return ret;
1408 }
1409
1410 if (is_support_sw_smu(adev)) {
1411 value = 0;
1412 } else {
1413 if (adev->powerplay.pp_funcs->set_mclk_od)
1414 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1415
1416 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1417 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1418 } else {
1419 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1420 amdgpu_pm_compute_clocks(adev);
1421 }
1422 }
1423
1424 pm_runtime_mark_last_busy(ddev->dev);
1425 pm_runtime_put_autosuspend(ddev->dev);
1426
1427 return count;
1428}
1429
1430/**
1431 * DOC: pp_power_profile_mode
1432 *
1433 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1434 * related to switching between power levels in a power state. The file
1435 * pp_power_profile_mode is used for this.
1436 *
1437 * Reading this file outputs a list of all of the predefined power profiles
1438 * and the relevant heuristics settings for that profile.
1439 *
1440 * To select a profile or create a custom profile, first select manual using
1441 * power_dpm_force_performance_level. Writing the number of a predefined
1442 * profile to pp_power_profile_mode will enable those heuristics. To
1443 * create a custom set of heuristics, write a string of numbers to the file
1444 * starting with the number of the custom profile along with a setting
1445 * for each heuristic parameter. Due to differences across asic families
1446 * the heuristic parameters vary from family to family.
1447 *
1448 */
1449
1450static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1451 struct device_attribute *attr,
1452 char *buf)
1453{
1454 struct drm_device *ddev = dev_get_drvdata(dev);
1455 struct amdgpu_device *adev = drm_to_adev(ddev);
1456 ssize_t size;
1457 int ret;
1458
1459 if (amdgpu_in_reset(adev))
1460 return -EPERM;
1461 if (adev->in_suspend && !adev->in_runpm)
1462 return -EPERM;
1463
1464 ret = pm_runtime_get_sync(ddev->dev);
1465 if (ret < 0) {
1466 pm_runtime_put_autosuspend(ddev->dev);
1467 return ret;
1468 }
1469
1470 if (adev->powerplay.pp_funcs->get_power_profile_mode)
1471 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1472 else
1473 size = sysfs_emit(buf, "\n");
1474
1475 pm_runtime_mark_last_busy(ddev->dev);
1476 pm_runtime_put_autosuspend(ddev->dev);
1477
1478 return size;
1479}
1480
1481
1482static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1483 struct device_attribute *attr,
1484 const char *buf,
1485 size_t count)
1486{
1487 int ret;
1488 struct drm_device *ddev = dev_get_drvdata(dev);
1489 struct amdgpu_device *adev = drm_to_adev(ddev);
1490 uint32_t parameter_size = 0;
1491 long parameter[64];
1492 char *sub_str, buf_cpy[128];
1493 char *tmp_str;
1494 uint32_t i = 0;
1495 char tmp[2];
1496 long int profile_mode = 0;
1497 const char delimiter[3] = {' ', '\n', '\0'};
1498
1499 if (amdgpu_in_reset(adev))
1500 return -EPERM;
1501 if (adev->in_suspend && !adev->in_runpm)
1502 return -EPERM;
1503
1504 tmp[0] = *(buf);
1505 tmp[1] = '\0';
1506 ret = kstrtol(tmp, 0, &profile_mode);
1507 if (ret)
1508 return -EINVAL;
1509
1510 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1511 if (count < 2 || count > 127)
1512 return -EINVAL;
1513 while (isspace(*++buf))
1514 i++;
1515 memcpy(buf_cpy, buf, count-i);
1516 tmp_str = buf_cpy;
1517 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1518 if (strlen(sub_str) == 0)
1519 continue;
1520 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
1521 if (ret)
1522 return -EINVAL;
1523 parameter_size++;
1524 while (isspace(*tmp_str))
1525 tmp_str++;
1526 }
1527 }
1528 parameter[parameter_size] = profile_mode;
1529
1530 ret = pm_runtime_get_sync(ddev->dev);
1531 if (ret < 0) {
1532 pm_runtime_put_autosuspend(ddev->dev);
1533 return ret;
1534 }
1535
1536 if (adev->powerplay.pp_funcs->set_power_profile_mode)
1537 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1538
1539 pm_runtime_mark_last_busy(ddev->dev);
1540 pm_runtime_put_autosuspend(ddev->dev);
1541
1542 if (!ret)
1543 return count;
1544
1545 return -EINVAL;
1546}
1547
1548/**
1549 * DOC: gpu_busy_percent
1550 *
1551 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1552 * is as a percentage. The file gpu_busy_percent is used for this.
1553 * The SMU firmware computes a percentage of load based on the
1554 * aggregate activity level in the IP cores.
1555 */
1556static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1557 struct device_attribute *attr,
1558 char *buf)
1559{
1560 struct drm_device *ddev = dev_get_drvdata(dev);
1561 struct amdgpu_device *adev = drm_to_adev(ddev);
1562 int r, value, size = sizeof(value);
1563
1564 if (amdgpu_in_reset(adev))
1565 return -EPERM;
1566 if (adev->in_suspend && !adev->in_runpm)
1567 return -EPERM;
1568
1569 r = pm_runtime_get_sync(ddev->dev);
1570 if (r < 0) {
1571 pm_runtime_put_autosuspend(ddev->dev);
1572 return r;
1573 }
1574
1575 /* read the IP busy sensor */
1576 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1577 (void *)&value, &size);
1578
1579 pm_runtime_mark_last_busy(ddev->dev);
1580 pm_runtime_put_autosuspend(ddev->dev);
1581
1582 if (r)
1583 return r;
1584
1585 return sysfs_emit(buf, "%d\n", value);
1586}
1587
1588/**
1589 * DOC: mem_busy_percent
1590 *
1591 * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1592 * is as a percentage. The file mem_busy_percent is used for this.
1593 * The SMU firmware computes a percentage of load based on the
1594 * aggregate activity level in the IP cores.
1595 */
1596static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1597 struct device_attribute *attr,
1598 char *buf)
1599{
1600 struct drm_device *ddev = dev_get_drvdata(dev);
1601 struct amdgpu_device *adev = drm_to_adev(ddev);
1602 int r, value, size = sizeof(value);
1603
1604 if (amdgpu_in_reset(adev))
1605 return -EPERM;
1606 if (adev->in_suspend && !adev->in_runpm)
1607 return -EPERM;
1608
1609 r = pm_runtime_get_sync(ddev->dev);
1610 if (r < 0) {
1611 pm_runtime_put_autosuspend(ddev->dev);
1612 return r;
1613 }
1614
1615 /* read the IP busy sensor */
1616 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1617 (void *)&value, &size);
1618
1619 pm_runtime_mark_last_busy(ddev->dev);
1620 pm_runtime_put_autosuspend(ddev->dev);
1621
1622 if (r)
1623 return r;
1624
1625 return sysfs_emit(buf, "%d\n", value);
1626}
1627
1628/**
1629 * DOC: pcie_bw
1630 *
1631 * The amdgpu driver provides a sysfs API for estimating how much data
1632 * has been received and sent by the GPU in the last second through PCIe.
1633 * The file pcie_bw is used for this.
1634 * The Perf counters count the number of received and sent messages and return
1635 * those values, as well as the maximum payload size of a PCIe packet (mps).
1636 * Note that it is not possible to easily and quickly obtain the size of each
1637 * packet transmitted, so we output the max payload size (mps) to allow for
1638 * quick estimation of the PCIe bandwidth usage
1639 */
1640static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1641 struct device_attribute *attr,
1642 char *buf)
1643{
1644 struct drm_device *ddev = dev_get_drvdata(dev);
1645 struct amdgpu_device *adev = drm_to_adev(ddev);
1646 uint64_t count0 = 0, count1 = 0;
1647 int ret;
1648
1649 if (amdgpu_in_reset(adev))
1650 return -EPERM;
1651 if (adev->in_suspend && !adev->in_runpm)
1652 return -EPERM;
1653
1654 if (adev->flags & AMD_IS_APU)
1655 return -ENODATA;
1656
1657 if (!adev->asic_funcs->get_pcie_usage)
1658 return -ENODATA;
1659
1660 ret = pm_runtime_get_sync(ddev->dev);
1661 if (ret < 0) {
1662 pm_runtime_put_autosuspend(ddev->dev);
1663 return ret;
1664 }
1665
1666 amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1667
1668 pm_runtime_mark_last_busy(ddev->dev);
1669 pm_runtime_put_autosuspend(ddev->dev);
1670
1671 return sysfs_emit(buf, "%llu %llu %i\n",
1672 count0, count1, pcie_get_mps(adev->pdev));
1673}
1674
1675/**
1676 * DOC: unique_id
1677 *
1678 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1679 * The file unique_id is used for this.
1680 * This will provide a Unique ID that will persist from machine to machine
1681 *
1682 * NOTE: This will only work for GFX9 and newer. This file will be absent
1683 * on unsupported ASICs (GFX8 and older)
1684 */
1685static ssize_t amdgpu_get_unique_id(struct device *dev,
1686 struct device_attribute *attr,
1687 char *buf)
1688{
1689 struct drm_device *ddev = dev_get_drvdata(dev);
1690 struct amdgpu_device *adev = drm_to_adev(ddev);
1691
1692 if (amdgpu_in_reset(adev))
1693 return -EPERM;
1694 if (adev->in_suspend && !adev->in_runpm)
1695 return -EPERM;
1696
1697 if (adev->unique_id)
1698 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1699
1700 return 0;
1701}
1702
1703/**
1704 * DOC: thermal_throttling_logging
1705 *
1706 * Thermal throttling pulls down the clock frequency and thus the performance.
1707 * It's an useful mechanism to protect the chip from overheating. Since it
1708 * impacts performance, the user controls whether it is enabled and if so,
1709 * the log frequency.
1710 *
1711 * Reading back the file shows you the status(enabled or disabled) and
1712 * the interval(in seconds) between each thermal logging.
1713 *
1714 * Writing an integer to the file, sets a new logging interval, in seconds.
1715 * The value should be between 1 and 3600. If the value is less than 1,
1716 * thermal logging is disabled. Values greater than 3600 are ignored.
1717 */
1718static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1719 struct device_attribute *attr,
1720 char *buf)
1721{
1722 struct drm_device *ddev = dev_get_drvdata(dev);
1723 struct amdgpu_device *adev = drm_to_adev(ddev);
1724
1725 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1726 adev_to_drm(adev)->unique,
1727 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1728 adev->throttling_logging_rs.interval / HZ + 1);
1729}
1730
1731static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1732 struct device_attribute *attr,
1733 const char *buf,
1734 size_t count)
1735{
1736 struct drm_device *ddev = dev_get_drvdata(dev);
1737 struct amdgpu_device *adev = drm_to_adev(ddev);
1738 long throttling_logging_interval;
1739 unsigned long flags;
1740 int ret = 0;
1741
1742 ret = kstrtol(buf, 0, &throttling_logging_interval);
1743 if (ret)
1744 return ret;
1745
1746 if (throttling_logging_interval > 3600)
1747 return -EINVAL;
1748
1749 if (throttling_logging_interval > 0) {
1750 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1751 /*
1752 * Reset the ratelimit timer internals.
1753 * This can effectively restart the timer.
1754 */
1755 adev->throttling_logging_rs.interval =
1756 (throttling_logging_interval - 1) * HZ;
1757 adev->throttling_logging_rs.begin = 0;
1758 adev->throttling_logging_rs.printed = 0;
1759 adev->throttling_logging_rs.missed = 0;
1760 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1761
1762 atomic_set(&adev->throttling_logging_enabled, 1);
1763 } else {
1764 atomic_set(&adev->throttling_logging_enabled, 0);
1765 }
1766
1767 return count;
1768}
1769
1770/**
1771 * DOC: gpu_metrics
1772 *
1773 * The amdgpu driver provides a sysfs API for retrieving current gpu
1774 * metrics data. The file gpu_metrics is used for this. Reading the
1775 * file will dump all the current gpu metrics data.
1776 *
1777 * These data include temperature, frequency, engines utilization,
1778 * power consume, throttler status, fan speed and cpu core statistics(
1779 * available for APU only). That's it will give a snapshot of all sensors
1780 * at the same time.
1781 */
1782static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1783 struct device_attribute *attr,
1784 char *buf)
1785{
1786 struct drm_device *ddev = dev_get_drvdata(dev);
1787 struct amdgpu_device *adev = drm_to_adev(ddev);
1788 void *gpu_metrics;
1789 ssize_t size = 0;
1790 int ret;
1791
1792 if (amdgpu_in_reset(adev))
1793 return -EPERM;
1794 if (adev->in_suspend && !adev->in_runpm)
1795 return -EPERM;
1796
1797 ret = pm_runtime_get_sync(ddev->dev);
1798 if (ret < 0) {
1799 pm_runtime_put_autosuspend(ddev->dev);
1800 return ret;
1801 }
1802
1803 if (adev->powerplay.pp_funcs->get_gpu_metrics)
1804 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1805
1806 if (size <= 0)
1807 goto out;
1808
1809 if (size >= PAGE_SIZE)
1810 size = PAGE_SIZE - 1;
1811
1812 memcpy(buf, gpu_metrics, size);
1813
1814out:
1815 pm_runtime_mark_last_busy(ddev->dev);
1816 pm_runtime_put_autosuspend(ddev->dev);
1817
1818 return size;
1819}
1820
1821/**
1822 * DOC: smartshift_apu_power
1823 *
1824 * The amdgpu driver provides a sysfs API for reporting APU power
1825 * share if it supports smartshift. The value is expressed as
1826 * the proportion of stapm limit where stapm limit is the total APU
1827 * power limit. The result is in percentage. If APU power is 130% of
1828 * STAPM, then APU is using 30% of the dGPU's headroom.
1829 */
1830
1831static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1832 char *buf)
1833{
1834 struct drm_device *ddev = dev_get_drvdata(dev);
1835 struct amdgpu_device *adev = drm_to_adev(ddev);
1836 uint32_t ss_power, size;
1837 int r = 0;
1838
1839 if (amdgpu_in_reset(adev))
1840 return -EPERM;
1841 if (adev->in_suspend && !adev->in_runpm)
1842 return -EPERM;
1843
1844 r = pm_runtime_get_sync(ddev->dev);
1845 if (r < 0) {
1846 pm_runtime_put_autosuspend(ddev->dev);
1847 return r;
1848 }
1849
1850 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1851 (void *)&ss_power, &size);
1852 if (r)
1853 goto out;
1854
1855 r = sysfs_emit(buf, "%u%%\n", ss_power);
1856
1857out:
1858 pm_runtime_mark_last_busy(ddev->dev);
1859 pm_runtime_put_autosuspend(ddev->dev);
1860 return r;
1861}
1862
1863/**
1864 * DOC: smartshift_dgpu_power
1865 *
1866 * The amdgpu driver provides a sysfs API for reporting the dGPU power
1867 * share if the device is in HG and supports smartshift. The value
1868 * is expressed as the proportion of stapm limit where stapm limit
1869 * is the total APU power limit. The value is in percentage. If dGPU
1870 * power is 20% higher than STAPM power(120%), it's using 20% of the
1871 * APU's power headroom.
1872 */
1873
1874static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1875 char *buf)
1876{
1877 struct drm_device *ddev = dev_get_drvdata(dev);
1878 struct amdgpu_device *adev = drm_to_adev(ddev);
1879 uint32_t ss_power, size;
1880 int r = 0;
1881
1882 if (amdgpu_in_reset(adev))
1883 return -EPERM;
1884 if (adev->in_suspend && !adev->in_runpm)
1885 return -EPERM;
1886
1887 r = pm_runtime_get_sync(ddev->dev);
1888 if (r < 0) {
1889 pm_runtime_put_autosuspend(ddev->dev);
1890 return r;
1891 }
1892
1893 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1894 (void *)&ss_power, &size);
1895
1896 if (r)
1897 goto out;
1898
1899 r = sysfs_emit(buf, "%u%%\n", ss_power);
1900
1901out:
1902 pm_runtime_mark_last_busy(ddev->dev);
1903 pm_runtime_put_autosuspend(ddev->dev);
1904 return r;
1905}
1906
1907/**
1908 * DOC: smartshift_bias
1909 *
1910 * The amdgpu driver provides a sysfs API for reporting the
1911 * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1912 * and the default is 0. -100 sets maximum preference to APU
1913 * and 100 sets max perference to dGPU.
1914 */
1915
1916static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1917 struct device_attribute *attr,
1918 char *buf)
1919{
1920 int r = 0;
1921
1922 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1923
1924 return r;
1925}
1926
1927static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1928 struct device_attribute *attr,
1929 const char *buf, size_t count)
1930{
1931 struct drm_device *ddev = dev_get_drvdata(dev);
1932 struct amdgpu_device *adev = drm_to_adev(ddev);
1933 int r = 0;
1934 int bias = 0;
1935
1936 if (amdgpu_in_reset(adev))
1937 return -EPERM;
1938 if (adev->in_suspend && !adev->in_runpm)
1939 return -EPERM;
1940
1941 r = pm_runtime_get_sync(ddev->dev);
1942 if (r < 0) {
1943 pm_runtime_put_autosuspend(ddev->dev);
1944 return r;
1945 }
1946
1947 r = kstrtoint(buf, 10, &bias);
1948 if (r)
1949 goto out;
1950
1951 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1952 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1953 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1954 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1955
1956 amdgpu_smartshift_bias = bias;
1957 r = count;
1958
1959 /* TODO: upadte bias level with SMU message */
1960
1961out:
1962 pm_runtime_mark_last_busy(ddev->dev);
1963 pm_runtime_put_autosuspend(ddev->dev);
1964 return r;
1965}
1966
1967
1968static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1969 uint32_t mask, enum amdgpu_device_attr_states *states)
1970{
1971 uint32_t ss_power, size;
1972
1973 if (!amdgpu_acpi_is_power_shift_control_supported())
1974 *states = ATTR_STATE_UNSUPPORTED;
1975 else if ((adev->flags & AMD_IS_PX) &&
1976 !amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1977 *states = ATTR_STATE_UNSUPPORTED;
1978 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1979 (void *)&ss_power, &size))
1980 *states = ATTR_STATE_UNSUPPORTED;
1981 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1982 (void *)&ss_power, &size))
1983 *states = ATTR_STATE_UNSUPPORTED;
1984
1985 return 0;
1986}
1987
1988static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1989 uint32_t mask, enum amdgpu_device_attr_states *states)
1990{
1991 uint32_t ss_power, size;
1992
1993 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1994 *states = ATTR_STATE_UNSUPPORTED;
1995 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1996 (void *)&ss_power, &size))
1997 *states = ATTR_STATE_UNSUPPORTED;
1998 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1999 (void *)&ss_power, &size))
2000 *states = ATTR_STATE_UNSUPPORTED;
2001
2002 return 0;
2003}
2004
2005static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2006 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2007 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2008 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC),
2009 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC),
2010 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC),
2011 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC),
2012 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2013 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2014 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2015 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2016 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2017 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2018 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC),
2019 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC),
2020 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
2021 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC),
2022 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC),
2023 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC),
2024 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC),
2025 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC),
2026 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC),
2027 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC),
2028 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC),
2029 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC),
2030 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC),
2031 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC,
2032 .attr_update = ss_power_attr_update),
2033 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC,
2034 .attr_update = ss_power_attr_update),
2035 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC,
2036 .attr_update = ss_bias_attr_update),
2037};
2038
2039static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2040 uint32_t mask, enum amdgpu_device_attr_states *states)
2041{
2042 struct device_attribute *dev_attr = &attr->dev_attr;
2043 const char *attr_name = dev_attr->attr.name;
2044 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2045 enum amd_asic_type asic_type = adev->asic_type;
2046
2047 if (!(attr->flags & mask)) {
2048 *states = ATTR_STATE_UNSUPPORTED;
2049 return 0;
2050 }
2051
2052#define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name))
2053
2054 if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2055 if (asic_type < CHIP_VEGA10)
2056 *states = ATTR_STATE_UNSUPPORTED;
2057 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2058 if (asic_type < CHIP_VEGA10 ||
2059 asic_type == CHIP_ARCTURUS ||
2060 asic_type == CHIP_ALDEBARAN)
2061 *states = ATTR_STATE_UNSUPPORTED;
2062 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2063 if (asic_type < CHIP_VEGA20)
2064 *states = ATTR_STATE_UNSUPPORTED;
2065 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2066 *states = ATTR_STATE_UNSUPPORTED;
2067 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2068 (is_support_sw_smu(adev) && adev->smu.is_apu) ||
2069 (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2070 *states = ATTR_STATE_SUPPORTED;
2071 } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2072 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
2073 *states = ATTR_STATE_UNSUPPORTED;
2074 } else if (DEVICE_ATTR_IS(pcie_bw)) {
2075 /* PCIe Perf counters won't work on APU nodes */
2076 if (adev->flags & AMD_IS_APU)
2077 *states = ATTR_STATE_UNSUPPORTED;
2078 } else if (DEVICE_ATTR_IS(unique_id)) {
2079 if (asic_type != CHIP_VEGA10 &&
2080 asic_type != CHIP_VEGA20 &&
2081 asic_type != CHIP_ARCTURUS)
2082 *states = ATTR_STATE_UNSUPPORTED;
2083 } else if (DEVICE_ATTR_IS(pp_features)) {
2084 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
2085 *states = ATTR_STATE_UNSUPPORTED;
2086 } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2087 if (asic_type < CHIP_VEGA12)
2088 *states = ATTR_STATE_UNSUPPORTED;
2089 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2090 if (!(asic_type == CHIP_VANGOGH))
2091 *states = ATTR_STATE_UNSUPPORTED;
2092 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2093 if (!(asic_type == CHIP_VANGOGH))
2094 *states = ATTR_STATE_UNSUPPORTED;
2095 }
2096
2097 if (asic_type == CHIP_ARCTURUS) {
2098 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
2099 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2100 DEVICE_ATTR_IS(pp_dpm_socclk) ||
2101 DEVICE_ATTR_IS(pp_dpm_fclk)) {
2102 dev_attr->attr.mode &= ~S_IWUGO;
2103 dev_attr->store = NULL;
2104 }
2105 }
2106
2107 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2108 /* SMU MP1 does not support dcefclk level setting */
2109 if (asic_type >= CHIP_NAVI10) {
2110 dev_attr->attr.mode &= ~S_IWUGO;
2111 dev_attr->store = NULL;
2112 }
2113 }
2114
2115#undef DEVICE_ATTR_IS
2116
2117 return 0;
2118}
2119
2120
2121static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2122 struct amdgpu_device_attr *attr,
2123 uint32_t mask, struct list_head *attr_list)
2124{
2125 int ret = 0;
2126 struct device_attribute *dev_attr = &attr->dev_attr;
2127 const char *name = dev_attr->attr.name;
2128 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2129 struct amdgpu_device_attr_entry *attr_entry;
2130
2131 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2132 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2133
2134 BUG_ON(!attr);
2135
2136 attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2137
2138 ret = attr_update(adev, attr, mask, &attr_states);
2139 if (ret) {
2140 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2141 name, ret);
2142 return ret;
2143 }
2144
2145 if (attr_states == ATTR_STATE_UNSUPPORTED)
2146 return 0;
2147
2148 ret = device_create_file(adev->dev, dev_attr);
2149 if (ret) {
2150 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2151 name, ret);
2152 }
2153
2154 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2155 if (!attr_entry)
2156 return -ENOMEM;
2157
2158 attr_entry->attr = attr;
2159 INIT_LIST_HEAD(&attr_entry->entry);
2160
2161 list_add_tail(&attr_entry->entry, attr_list);
2162
2163 return ret;
2164}
2165
2166static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2167{
2168 struct device_attribute *dev_attr = &attr->dev_attr;
2169
2170 device_remove_file(adev->dev, dev_attr);
2171}
2172
2173static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2174 struct list_head *attr_list);
2175
2176static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2177 struct amdgpu_device_attr *attrs,
2178 uint32_t counts,
2179 uint32_t mask,
2180 struct list_head *attr_list)
2181{
2182 int ret = 0;
2183 uint32_t i = 0;
2184
2185 for (i = 0; i < counts; i++) {
2186 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2187 if (ret)
2188 goto failed;
2189 }
2190
2191 return 0;
2192
2193failed:
2194 amdgpu_device_attr_remove_groups(adev, attr_list);
2195
2196 return ret;
2197}
2198
2199static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2200 struct list_head *attr_list)
2201{
2202 struct amdgpu_device_attr_entry *entry, *entry_tmp;
2203
2204 if (list_empty(attr_list))
2205 return ;
2206
2207 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2208 amdgpu_device_attr_remove(adev, entry->attr);
2209 list_del(&entry->entry);
2210 kfree(entry);
2211 }
2212}
2213
2214static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2215 struct device_attribute *attr,
2216 char *buf)
2217{
2218 struct amdgpu_device *adev = dev_get_drvdata(dev);
2219 int channel = to_sensor_dev_attr(attr)->index;
2220 int r, temp = 0, size = sizeof(temp);
2221
2222 if (amdgpu_in_reset(adev))
2223 return -EPERM;
2224 if (adev->in_suspend && !adev->in_runpm)
2225 return -EPERM;
2226
2227 if (channel >= PP_TEMP_MAX)
2228 return -EINVAL;
2229
2230 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2231 if (r < 0) {
2232 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2233 return r;
2234 }
2235
2236 switch (channel) {
2237 case PP_TEMP_JUNCTION:
2238 /* get current junction temperature */
2239 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2240 (void *)&temp, &size);
2241 break;
2242 case PP_TEMP_EDGE:
2243 /* get current edge temperature */
2244 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2245 (void *)&temp, &size);
2246 break;
2247 case PP_TEMP_MEM:
2248 /* get current memory temperature */
2249 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2250 (void *)&temp, &size);
2251 break;
2252 default:
2253 r = -EINVAL;
2254 break;
2255 }
2256
2257 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2258 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2259
2260 if (r)
2261 return r;
2262
2263 return sysfs_emit(buf, "%d\n", temp);
2264}
2265
2266static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2267 struct device_attribute *attr,
2268 char *buf)
2269{
2270 struct amdgpu_device *adev = dev_get_drvdata(dev);
2271 int hyst = to_sensor_dev_attr(attr)->index;
2272 int temp;
2273
2274 if (hyst)
2275 temp = adev->pm.dpm.thermal.min_temp;
2276 else
2277 temp = adev->pm.dpm.thermal.max_temp;
2278
2279 return sysfs_emit(buf, "%d\n", temp);
2280}
2281
2282static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2283 struct device_attribute *attr,
2284 char *buf)
2285{
2286 struct amdgpu_device *adev = dev_get_drvdata(dev);
2287 int hyst = to_sensor_dev_attr(attr)->index;
2288 int temp;
2289
2290 if (hyst)
2291 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2292 else
2293 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2294
2295 return sysfs_emit(buf, "%d\n", temp);
2296}
2297
2298static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2299 struct device_attribute *attr,
2300 char *buf)
2301{
2302 struct amdgpu_device *adev = dev_get_drvdata(dev);
2303 int hyst = to_sensor_dev_attr(attr)->index;
2304 int temp;
2305
2306 if (hyst)
2307 temp = adev->pm.dpm.thermal.min_mem_temp;
2308 else
2309 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2310
2311 return sysfs_emit(buf, "%d\n", temp);
2312}
2313
2314static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2315 struct device_attribute *attr,
2316 char *buf)
2317{
2318 int channel = to_sensor_dev_attr(attr)->index;
2319
2320 if (channel >= PP_TEMP_MAX)
2321 return -EINVAL;
2322
2323 return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2324}
2325
2326static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2327 struct device_attribute *attr,
2328 char *buf)
2329{
2330 struct amdgpu_device *adev = dev_get_drvdata(dev);
2331 int channel = to_sensor_dev_attr(attr)->index;
2332 int temp = 0;
2333
2334 if (channel >= PP_TEMP_MAX)
2335 return -EINVAL;
2336
2337 switch (channel) {
2338 case PP_TEMP_JUNCTION:
2339 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2340 break;
2341 case PP_TEMP_EDGE:
2342 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2343 break;
2344 case PP_TEMP_MEM:
2345 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2346 break;
2347 }
2348
2349 return sysfs_emit(buf, "%d\n", temp);
2350}
2351
2352static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2353 struct device_attribute *attr,
2354 char *buf)
2355{
2356 struct amdgpu_device *adev = dev_get_drvdata(dev);
2357 u32 pwm_mode = 0;
2358 int ret;
2359
2360 if (amdgpu_in_reset(adev))
2361 return -EPERM;
2362 if (adev->in_suspend && !adev->in_runpm)
2363 return -EPERM;
2364
2365 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2366 if (ret < 0) {
2367 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2368 return ret;
2369 }
2370
2371 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2372 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2373 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2374 return -EINVAL;
2375 }
2376
2377 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2378
2379 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2380 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2381
2382 return sprintf(buf, "%u\n", pwm_mode);
2383}
2384
2385static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2386 struct device_attribute *attr,
2387 const char *buf,
2388 size_t count)
2389{
2390 struct amdgpu_device *adev = dev_get_drvdata(dev);
2391 int err, ret;
2392 int value;
2393
2394 if (amdgpu_in_reset(adev))
2395 return -EPERM;
2396 if (adev->in_suspend && !adev->in_runpm)
2397 return -EPERM;
2398
2399 err = kstrtoint(buf, 10, &value);
2400 if (err)
2401 return err;
2402
2403 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2404 if (ret < 0) {
2405 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2406 return ret;
2407 }
2408
2409 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2410 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2411 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2412 return -EINVAL;
2413 }
2414
2415 amdgpu_dpm_set_fan_control_mode(adev, value);
2416
2417 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2418 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2419
2420 return count;
2421}
2422
2423static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2424 struct device_attribute *attr,
2425 char *buf)
2426{
2427 return sprintf(buf, "%i\n", 0);
2428}
2429
2430static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2431 struct device_attribute *attr,
2432 char *buf)
2433{
2434 return sprintf(buf, "%i\n", 255);
2435}
2436
2437static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2438 struct device_attribute *attr,
2439 const char *buf, size_t count)
2440{
2441 struct amdgpu_device *adev = dev_get_drvdata(dev);
2442 int err;
2443 u32 value;
2444 u32 pwm_mode;
2445
2446 if (amdgpu_in_reset(adev))
2447 return -EPERM;
2448 if (adev->in_suspend && !adev->in_runpm)
2449 return -EPERM;
2450
2451 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2452 if (err < 0) {
2453 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2454 return err;
2455 }
2456
2457 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2458 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2459 pr_info("manual fan speed control should be enabled first\n");
2460 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2461 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2462 return -EINVAL;
2463 }
2464
2465 err = kstrtou32(buf, 10, &value);
2466 if (err) {
2467 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2468 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2469 return err;
2470 }
2471
2472 value = (value * 100) / 255;
2473
2474 if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2475 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2476 else
2477 err = -EINVAL;
2478
2479 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2480 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2481
2482 if (err)
2483 return err;
2484
2485 return count;
2486}
2487
2488static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2489 struct device_attribute *attr,
2490 char *buf)
2491{
2492 struct amdgpu_device *adev = dev_get_drvdata(dev);
2493 int err;
2494 u32 speed = 0;
2495
2496 if (amdgpu_in_reset(adev))
2497 return -EPERM;
2498 if (adev->in_suspend && !adev->in_runpm)
2499 return -EPERM;
2500
2501 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2502 if (err < 0) {
2503 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2504 return err;
2505 }
2506
2507 if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2508 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2509 else
2510 err = -EINVAL;
2511
2512 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2513 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2514
2515 if (err)
2516 return err;
2517
2518 speed = (speed * 255) / 100;
2519
2520 return sprintf(buf, "%i\n", speed);
2521}
2522
2523static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2524 struct device_attribute *attr,
2525 char *buf)
2526{
2527 struct amdgpu_device *adev = dev_get_drvdata(dev);
2528 int err;
2529 u32 speed = 0;
2530
2531 if (amdgpu_in_reset(adev))
2532 return -EPERM;
2533 if (adev->in_suspend && !adev->in_runpm)
2534 return -EPERM;
2535
2536 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2537 if (err < 0) {
2538 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2539 return err;
2540 }
2541
2542 if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2543 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2544 else
2545 err = -EINVAL;
2546
2547 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2548 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2549
2550 if (err)
2551 return err;
2552
2553 return sprintf(buf, "%i\n", speed);
2554}
2555
2556static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2557 struct device_attribute *attr,
2558 char *buf)
2559{
2560 struct amdgpu_device *adev = dev_get_drvdata(dev);
2561 u32 min_rpm = 0;
2562 u32 size = sizeof(min_rpm);
2563 int r;
2564
2565 if (amdgpu_in_reset(adev))
2566 return -EPERM;
2567 if (adev->in_suspend && !adev->in_runpm)
2568 return -EPERM;
2569
2570 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2571 if (r < 0) {
2572 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2573 return r;
2574 }
2575
2576 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2577 (void *)&min_rpm, &size);
2578
2579 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2580 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2581
2582 if (r)
2583 return r;
2584
2585 return sysfs_emit(buf, "%d\n", min_rpm);
2586}
2587
2588static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2589 struct device_attribute *attr,
2590 char *buf)
2591{
2592 struct amdgpu_device *adev = dev_get_drvdata(dev);
2593 u32 max_rpm = 0;
2594 u32 size = sizeof(max_rpm);
2595 int r;
2596
2597 if (amdgpu_in_reset(adev))
2598 return -EPERM;
2599 if (adev->in_suspend && !adev->in_runpm)
2600 return -EPERM;
2601
2602 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2603 if (r < 0) {
2604 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2605 return r;
2606 }
2607
2608 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2609 (void *)&max_rpm, &size);
2610
2611 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2612 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2613
2614 if (r)
2615 return r;
2616
2617 return sysfs_emit(buf, "%d\n", max_rpm);
2618}
2619
2620static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2621 struct device_attribute *attr,
2622 char *buf)
2623{
2624 struct amdgpu_device *adev = dev_get_drvdata(dev);
2625 int err;
2626 u32 rpm = 0;
2627
2628 if (amdgpu_in_reset(adev))
2629 return -EPERM;
2630 if (adev->in_suspend && !adev->in_runpm)
2631 return -EPERM;
2632
2633 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2634 if (err < 0) {
2635 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2636 return err;
2637 }
2638
2639 if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2640 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2641 else
2642 err = -EINVAL;
2643
2644 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2645 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2646
2647 if (err)
2648 return err;
2649
2650 return sprintf(buf, "%i\n", rpm);
2651}
2652
2653static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2654 struct device_attribute *attr,
2655 const char *buf, size_t count)
2656{
2657 struct amdgpu_device *adev = dev_get_drvdata(dev);
2658 int err;
2659 u32 value;
2660 u32 pwm_mode;
2661
2662 if (amdgpu_in_reset(adev))
2663 return -EPERM;
2664 if (adev->in_suspend && !adev->in_runpm)
2665 return -EPERM;
2666
2667 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2668 if (err < 0) {
2669 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2670 return err;
2671 }
2672
2673 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2674
2675 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2676 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2677 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2678 return -ENODATA;
2679 }
2680
2681 err = kstrtou32(buf, 10, &value);
2682 if (err) {
2683 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2684 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2685 return err;
2686 }
2687
2688 if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2689 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2690 else
2691 err = -EINVAL;
2692
2693 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2694 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2695
2696 if (err)
2697 return err;
2698
2699 return count;
2700}
2701
2702static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2703 struct device_attribute *attr,
2704 char *buf)
2705{
2706 struct amdgpu_device *adev = dev_get_drvdata(dev);
2707 u32 pwm_mode = 0;
2708 int ret;
2709
2710 if (amdgpu_in_reset(adev))
2711 return -EPERM;
2712 if (adev->in_suspend && !adev->in_runpm)
2713 return -EPERM;
2714
2715 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2716 if (ret < 0) {
2717 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2718 return ret;
2719 }
2720
2721 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2722 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2723 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2724 return -EINVAL;
2725 }
2726
2727 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2728
2729 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2730 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2731
2732 return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2733}
2734
2735static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2736 struct device_attribute *attr,
2737 const char *buf,
2738 size_t count)
2739{
2740 struct amdgpu_device *adev = dev_get_drvdata(dev);
2741 int err;
2742 int value;
2743 u32 pwm_mode;
2744
2745 if (amdgpu_in_reset(adev))
2746 return -EPERM;
2747 if (adev->in_suspend && !adev->in_runpm)
2748 return -EPERM;
2749
2750 err = kstrtoint(buf, 10, &value);
2751 if (err)
2752 return err;
2753
2754 if (value == 0)
2755 pwm_mode = AMD_FAN_CTRL_AUTO;
2756 else if (value == 1)
2757 pwm_mode = AMD_FAN_CTRL_MANUAL;
2758 else
2759 return -EINVAL;
2760
2761 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2762 if (err < 0) {
2763 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2764 return err;
2765 }
2766
2767 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2768 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2769 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2770 return -EINVAL;
2771 }
2772 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2773
2774 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2775 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2776
2777 return count;
2778}
2779
2780static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2781 struct device_attribute *attr,
2782 char *buf)
2783{
2784 struct amdgpu_device *adev = dev_get_drvdata(dev);
2785 u32 vddgfx;
2786 int r, size = sizeof(vddgfx);
2787
2788 if (amdgpu_in_reset(adev))
2789 return -EPERM;
2790 if (adev->in_suspend && !adev->in_runpm)
2791 return -EPERM;
2792
2793 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2794 if (r < 0) {
2795 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2796 return r;
2797 }
2798
2799 /* get the voltage */
2800 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2801 (void *)&vddgfx, &size);
2802
2803 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2804 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2805
2806 if (r)
2807 return r;
2808
2809 return sysfs_emit(buf, "%d\n", vddgfx);
2810}
2811
2812static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2813 struct device_attribute *attr,
2814 char *buf)
2815{
2816 return sysfs_emit(buf, "vddgfx\n");
2817}
2818
2819static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2820 struct device_attribute *attr,
2821 char *buf)
2822{
2823 struct amdgpu_device *adev = dev_get_drvdata(dev);
2824 u32 vddnb;
2825 int r, size = sizeof(vddnb);
2826
2827 if (amdgpu_in_reset(adev))
2828 return -EPERM;
2829 if (adev->in_suspend && !adev->in_runpm)
2830 return -EPERM;
2831
2832 /* only APUs have vddnb */
2833 if (!(adev->flags & AMD_IS_APU))
2834 return -EINVAL;
2835
2836 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2837 if (r < 0) {
2838 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2839 return r;
2840 }
2841
2842 /* get the voltage */
2843 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2844 (void *)&vddnb, &size);
2845
2846 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2847 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2848
2849 if (r)
2850 return r;
2851
2852 return sysfs_emit(buf, "%d\n", vddnb);
2853}
2854
2855static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2856 struct device_attribute *attr,
2857 char *buf)
2858{
2859 return sysfs_emit(buf, "vddnb\n");
2860}
2861
2862static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2863 struct device_attribute *attr,
2864 char *buf)
2865{
2866 struct amdgpu_device *adev = dev_get_drvdata(dev);
2867 u32 query = 0;
2868 int r, size = sizeof(u32);
2869 unsigned uw;
2870
2871 if (amdgpu_in_reset(adev))
2872 return -EPERM;
2873 if (adev->in_suspend && !adev->in_runpm)
2874 return -EPERM;
2875
2876 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2877 if (r < 0) {
2878 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2879 return r;
2880 }
2881
2882 /* get the voltage */
2883 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2884 (void *)&query, &size);
2885
2886 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2887 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2888
2889 if (r)
2890 return r;
2891
2892 /* convert to microwatts */
2893 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2894
2895 return sysfs_emit(buf, "%u\n", uw);
2896}
2897
2898static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2899 struct device_attribute *attr,
2900 char *buf)
2901{
2902 return sprintf(buf, "%i\n", 0);
2903}
2904
2905
2906static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2907 struct device_attribute *attr,
2908 char *buf,
2909 enum pp_power_limit_level pp_limit_level)
2910{
2911 struct amdgpu_device *adev = dev_get_drvdata(dev);
2912 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2913 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2914 uint32_t limit;
2915 ssize_t size;
2916 int r;
2917
2918 if (amdgpu_in_reset(adev))
2919 return -EPERM;
2920 if (adev->in_suspend && !adev->in_runpm)
2921 return -EPERM;
2922
2923 if ( !(pp_funcs && pp_funcs->get_power_limit))
2924 return -ENODATA;
2925
2926 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2927 if (r < 0) {
2928 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2929 return r;
2930 }
2931
2932 r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
2933 pp_limit_level, power_type);
2934
2935 if (!r)
2936 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2937 else
2938 size = sysfs_emit(buf, "\n");
2939
2940 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2941 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2942
2943 return size;
2944}
2945
2946
2947static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2948 struct device_attribute *attr,
2949 char *buf)
2950{
2951 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2952
2953}
2954
2955static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2956 struct device_attribute *attr,
2957 char *buf)
2958{
2959 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2960
2961}
2962
2963static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2964 struct device_attribute *attr,
2965 char *buf)
2966{
2967 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2968
2969}
2970
2971static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2972 struct device_attribute *attr,
2973 char *buf)
2974{
2975 int limit_type = to_sensor_dev_attr(attr)->index;
2976
2977 return sysfs_emit(buf, "%s\n",
2978 limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT");
2979}
2980
2981static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2982 struct device_attribute *attr,
2983 const char *buf,
2984 size_t count)
2985{
2986 struct amdgpu_device *adev = dev_get_drvdata(dev);
2987 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2988 int limit_type = to_sensor_dev_attr(attr)->index;
2989 int err;
2990 u32 value;
2991
2992 if (amdgpu_in_reset(adev))
2993 return -EPERM;
2994 if (adev->in_suspend && !adev->in_runpm)
2995 return -EPERM;
2996
2997 if (amdgpu_sriov_vf(adev))
2998 return -EINVAL;
2999
3000 err = kstrtou32(buf, 10, &value);
3001 if (err)
3002 return err;
3003
3004 value = value / 1000000; /* convert to Watt */
3005 value |= limit_type << 24;
3006
3007 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3008 if (err < 0) {
3009 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3010 return err;
3011 }
3012
3013 if (pp_funcs && pp_funcs->set_power_limit)
3014 err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
3015 else
3016 err = -EINVAL;
3017
3018 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3019 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3020
3021 if (err)
3022 return err;
3023
3024 return count;
3025}
3026
3027static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3028 struct device_attribute *attr,
3029 char *buf)
3030{
3031 struct amdgpu_device *adev = dev_get_drvdata(dev);
3032 uint32_t sclk;
3033 int r, size = sizeof(sclk);
3034
3035 if (amdgpu_in_reset(adev))
3036 return -EPERM;
3037 if (adev->in_suspend && !adev->in_runpm)
3038 return -EPERM;
3039
3040 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3041 if (r < 0) {
3042 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3043 return r;
3044 }
3045
3046 /* get the sclk */
3047 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3048 (void *)&sclk, &size);
3049
3050 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3051 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3052
3053 if (r)
3054 return r;
3055
3056 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3057}
3058
3059static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3060 struct device_attribute *attr,
3061 char *buf)
3062{
3063 return sysfs_emit(buf, "sclk\n");
3064}
3065
3066static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3067 struct device_attribute *attr,
3068 char *buf)
3069{
3070 struct amdgpu_device *adev = dev_get_drvdata(dev);
3071 uint32_t mclk;
3072 int r, size = sizeof(mclk);
3073
3074 if (amdgpu_in_reset(adev))
3075 return -EPERM;
3076 if (adev->in_suspend && !adev->in_runpm)
3077 return -EPERM;
3078
3079 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3080 if (r < 0) {
3081 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3082 return r;
3083 }
3084
3085 /* get the sclk */
3086 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3087 (void *)&mclk, &size);
3088
3089 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3090 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3091
3092 if (r)
3093 return r;
3094
3095 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3096}
3097
3098static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3099 struct device_attribute *attr,
3100 char *buf)
3101{
3102 return sysfs_emit(buf, "mclk\n");
3103}
3104
3105/**
3106 * DOC: hwmon
3107 *
3108 * The amdgpu driver exposes the following sensor interfaces:
3109 *
3110 * - GPU temperature (via the on-die sensor)
3111 *
3112 * - GPU voltage
3113 *
3114 * - Northbridge voltage (APUs only)
3115 *
3116 * - GPU power
3117 *
3118 * - GPU fan
3119 *
3120 * - GPU gfx/compute engine clock
3121 *
3122 * - GPU memory clock (dGPU only)
3123 *
3124 * hwmon interfaces for GPU temperature:
3125 *
3126 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3127 * - temp2_input and temp3_input are supported on SOC15 dGPUs only
3128 *
3129 * - temp[1-3]_label: temperature channel label
3130 * - temp2_label and temp3_label are supported on SOC15 dGPUs only
3131 *
3132 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3133 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3134 *
3135 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3136 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3137 *
3138 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3139 * - these are supported on SOC15 dGPUs only
3140 *
3141 * hwmon interfaces for GPU voltage:
3142 *
3143 * - in0_input: the voltage on the GPU in millivolts
3144 *
3145 * - in1_input: the voltage on the Northbridge in millivolts
3146 *
3147 * hwmon interfaces for GPU power:
3148 *
3149 * - power1_average: average power used by the GPU in microWatts
3150 *
3151 * - power1_cap_min: minimum cap supported in microWatts
3152 *
3153 * - power1_cap_max: maximum cap supported in microWatts
3154 *
3155 * - power1_cap: selected power cap in microWatts
3156 *
3157 * hwmon interfaces for GPU fan:
3158 *
3159 * - pwm1: pulse width modulation fan level (0-255)
3160 *
3161 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3162 *
3163 * - pwm1_min: pulse width modulation fan control minimum level (0)
3164 *
3165 * - pwm1_max: pulse width modulation fan control maximum level (255)
3166 *
3167 * - fan1_min: a minimum value Unit: revolution/min (RPM)
3168 *
3169 * - fan1_max: a maximum value Unit: revolution/max (RPM)
3170 *
3171 * - fan1_input: fan speed in RPM
3172 *
3173 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3174 *
3175 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3176 *
3177 * hwmon interfaces for GPU clocks:
3178 *
3179 * - freq1_input: the gfx/compute clock in hertz
3180 *
3181 * - freq2_input: the memory clock in hertz
3182 *
3183 * You can use hwmon tools like sensors to view this information on your system.
3184 *
3185 */
3186
3187static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3188static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3189static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3190static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3191static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3192static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3193static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3194static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3195static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3196static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3197static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3198static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3199static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3200static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3201static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3202static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3203static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3204static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3205static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3206static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3207static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3208static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3209static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3210static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3211static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3212static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3213static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3214static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3215static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3216static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3217static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3218static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3219static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3220static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3221static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3222static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3223static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3224static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3225static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3226static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3227static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3228static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3229static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3230static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3231
3232static struct attribute *hwmon_attributes[] = {
3233 &sensor_dev_attr_temp1_input.dev_attr.attr,
3234 &sensor_dev_attr_temp1_crit.dev_attr.attr,
3235 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3236 &sensor_dev_attr_temp2_input.dev_attr.attr,
3237 &sensor_dev_attr_temp2_crit.dev_attr.attr,
3238 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3239 &sensor_dev_attr_temp3_input.dev_attr.attr,
3240 &sensor_dev_attr_temp3_crit.dev_attr.attr,
3241 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3242 &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3243 &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3244 &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3245 &sensor_dev_attr_temp1_label.dev_attr.attr,
3246 &sensor_dev_attr_temp2_label.dev_attr.attr,
3247 &sensor_dev_attr_temp3_label.dev_attr.attr,
3248 &sensor_dev_attr_pwm1.dev_attr.attr,
3249 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3250 &sensor_dev_attr_pwm1_min.dev_attr.attr,
3251 &sensor_dev_attr_pwm1_max.dev_attr.attr,
3252 &sensor_dev_attr_fan1_input.dev_attr.attr,
3253 &sensor_dev_attr_fan1_min.dev_attr.attr,
3254 &sensor_dev_attr_fan1_max.dev_attr.attr,
3255 &sensor_dev_attr_fan1_target.dev_attr.attr,
3256 &sensor_dev_attr_fan1_enable.dev_attr.attr,
3257 &sensor_dev_attr_in0_input.dev_attr.attr,
3258 &sensor_dev_attr_in0_label.dev_attr.attr,
3259 &sensor_dev_attr_in1_input.dev_attr.attr,
3260 &sensor_dev_attr_in1_label.dev_attr.attr,
3261 &sensor_dev_attr_power1_average.dev_attr.attr,
3262 &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3263 &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3264 &sensor_dev_attr_power1_cap.dev_attr.attr,
3265 &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3266 &sensor_dev_attr_power1_label.dev_attr.attr,
3267 &sensor_dev_attr_power2_average.dev_attr.attr,
3268 &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3269 &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3270 &sensor_dev_attr_power2_cap.dev_attr.attr,
3271 &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3272 &sensor_dev_attr_power2_label.dev_attr.attr,
3273 &sensor_dev_attr_freq1_input.dev_attr.attr,
3274 &sensor_dev_attr_freq1_label.dev_attr.attr,
3275 &sensor_dev_attr_freq2_input.dev_attr.attr,
3276 &sensor_dev_attr_freq2_label.dev_attr.attr,
3277 NULL
3278};
3279
3280static umode_t hwmon_attributes_visible(struct kobject *kobj,
3281 struct attribute *attr, int index)
3282{
3283 struct device *dev = kobj_to_dev(kobj);
3284 struct amdgpu_device *adev = dev_get_drvdata(dev);
3285 umode_t effective_mode = attr->mode;
3286
3287 /* under multi-vf mode, the hwmon attributes are all not supported */
3288 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3289 return 0;
3290
3291 /* there is no fan under pp one vf mode */
3292 if (amdgpu_sriov_is_pp_one_vf(adev) &&
3293 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3294 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3295 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3296 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3297 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3298 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3299 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3300 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3301 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3302 return 0;
3303
3304 /* Skip fan attributes if fan is not present */
3305 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3306 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3307 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3308 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3309 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3310 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3311 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3312 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3313 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3314 return 0;
3315
3316 /* Skip fan attributes on APU */
3317 if ((adev->flags & AMD_IS_APU) &&
3318 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3319 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3320 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3321 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3322 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3323 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3324 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3325 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3326 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3327 return 0;
3328
3329 /* Skip crit temp on APU */
3330 if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3331 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3332 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3333 return 0;
3334
3335 /* Skip limit attributes if DPM is not enabled */
3336 if (!adev->pm.dpm_enabled &&
3337 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3338 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3339 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3340 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3341 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3342 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3343 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3344 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3345 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3346 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3347 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3348 return 0;
3349
3350 if (!is_support_sw_smu(adev)) {
3351 /* mask fan attributes if we have no bindings for this asic to expose */
3352 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3353 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3354 (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3355 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3356 effective_mode &= ~S_IRUGO;
3357
3358 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3359 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3360 (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3361 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3362 effective_mode &= ~S_IWUSR;
3363 }
3364
3365 if (((adev->family == AMDGPU_FAMILY_SI) ||
3366 ((adev->flags & AMD_IS_APU) &&
3367 (adev->asic_type != CHIP_VANGOGH))) && /* not implemented yet */
3368 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3369 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3370 attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3371 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3372 return 0;
3373
3374 if (((adev->family == AMDGPU_FAMILY_SI) ||
3375 ((adev->flags & AMD_IS_APU) &&
3376 (adev->asic_type < CHIP_RENOIR))) && /* not implemented yet */
3377 (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3378 return 0;
3379
3380 if (!is_support_sw_smu(adev)) {
3381 /* hide max/min values if we can't both query and manage the fan */
3382 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3383 !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3384 (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3385 !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3386 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3387 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3388 return 0;
3389
3390 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3391 !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3392 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3393 attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3394 return 0;
3395 }
3396
3397 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */
3398 adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */
3399 (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3400 attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3401 return 0;
3402
3403 /* only APUs have vddnb */
3404 if (!(adev->flags & AMD_IS_APU) &&
3405 (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3406 attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3407 return 0;
3408
3409 /* no mclk on APUs */
3410 if ((adev->flags & AMD_IS_APU) &&
3411 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3412 attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3413 return 0;
3414
3415 /* only SOC15 dGPUs support hotspot and mem temperatures */
3416 if (((adev->flags & AMD_IS_APU) ||
3417 adev->asic_type < CHIP_VEGA10) &&
3418 (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3419 attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3420 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3421 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3422 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3423 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3424 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3425 attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3426 attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3427 attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3428 attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3429 return 0;
3430
3431 /* only Vangogh has fast PPT limit and power labels */
3432 if (!(adev->asic_type == CHIP_VANGOGH) &&
3433 (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3434 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3435 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3436 attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3437 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3438 attr == &sensor_dev_attr_power2_label.dev_attr.attr ||
3439 attr == &sensor_dev_attr_power1_label.dev_attr.attr))
3440 return 0;
3441
3442 return effective_mode;
3443}
3444
3445static const struct attribute_group hwmon_attrgroup = {
3446 .attrs = hwmon_attributes,
3447 .is_visible = hwmon_attributes_visible,
3448};
3449
3450static const struct attribute_group *hwmon_groups[] = {
3451 &hwmon_attrgroup,
3452 NULL
3453};
3454
3455int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3456{
3457 int ret;
3458 uint32_t mask = 0;
3459
3460 if (adev->pm.sysfs_initialized)
3461 return 0;
3462
3463 if (adev->pm.dpm_enabled == 0)
3464 return 0;
3465
3466 INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3467
3468 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3469 DRIVER_NAME, adev,
3470 hwmon_groups);
3471 if (IS_ERR(adev->pm.int_hwmon_dev)) {
3472 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3473 dev_err(adev->dev,
3474 "Unable to register hwmon device: %d\n", ret);
3475 return ret;
3476 }
3477
3478 switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3479 case SRIOV_VF_MODE_ONE_VF:
3480 mask = ATTR_FLAG_ONEVF;
3481 break;
3482 case SRIOV_VF_MODE_MULTI_VF:
3483 mask = 0;
3484 break;
3485 case SRIOV_VF_MODE_BARE_METAL:
3486 default:
3487 mask = ATTR_FLAG_MASK_ALL;
3488 break;
3489 }
3490
3491 ret = amdgpu_device_attr_create_groups(adev,
3492 amdgpu_device_attrs,
3493 ARRAY_SIZE(amdgpu_device_attrs),
3494 mask,
3495 &adev->pm.pm_attr_list);
3496 if (ret)
3497 return ret;
3498
3499 adev->pm.sysfs_initialized = true;
3500
3501 return 0;
3502}
3503
3504void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3505{
3506 if (adev->pm.dpm_enabled == 0)
3507 return;
3508
3509 if (adev->pm.int_hwmon_dev)
3510 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3511
3512 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3513}
3514
3515/*
3516 * Debugfs info
3517 */
3518#if defined(CONFIG_DEBUG_FS)
3519
3520static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3521 struct amdgpu_device *adev) {
3522 uint16_t *p_val;
3523 uint32_t size;
3524 int i;
3525
3526 if (is_support_cclk_dpm(adev)) {
3527 p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t),
3528 GFP_KERNEL);
3529
3530 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3531 (void *)p_val, &size)) {
3532 for (i = 0; i < adev->smu.cpu_core_num; i++)
3533 seq_printf(m, "\t%u MHz (CPU%d)\n",
3534 *(p_val + i), i);
3535 }
3536
3537 kfree(p_val);
3538 }
3539}
3540
3541static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3542{
3543 uint32_t value;
3544 uint64_t value64 = 0;
3545 uint32_t query = 0;
3546 int size;
3547
3548 /* GPU Clocks */
3549 size = sizeof(value);
3550 seq_printf(m, "GFX Clocks and Power:\n");
3551
3552 amdgpu_debugfs_prints_cpu_info(m, adev);
3553
3554 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3555 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3556 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3557 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3558 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3559 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3560 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3561 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3562 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3563 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3564 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3565 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3566 size = sizeof(uint32_t);
3567 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3568 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3569 size = sizeof(value);
3570 seq_printf(m, "\n");
3571
3572 /* GPU Temp */
3573 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3574 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3575
3576 /* GPU Load */
3577 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3578 seq_printf(m, "GPU Load: %u %%\n", value);
3579 /* MEM Load */
3580 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3581 seq_printf(m, "MEM Load: %u %%\n", value);
3582
3583 seq_printf(m, "\n");
3584
3585 /* SMC feature mask */
3586 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3587 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3588
3589 if (adev->asic_type > CHIP_VEGA20) {
3590 /* VCN clocks */
3591 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3592 if (!value) {
3593 seq_printf(m, "VCN: Disabled\n");
3594 } else {
3595 seq_printf(m, "VCN: Enabled\n");
3596 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3597 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3598 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3599 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3600 }
3601 }
3602 seq_printf(m, "\n");
3603 } else {
3604 /* UVD clocks */
3605 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3606 if (!value) {
3607 seq_printf(m, "UVD: Disabled\n");
3608 } else {
3609 seq_printf(m, "UVD: Enabled\n");
3610 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3611 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3612 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3613 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3614 }
3615 }
3616 seq_printf(m, "\n");
3617
3618 /* VCE clocks */
3619 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3620 if (!value) {
3621 seq_printf(m, "VCE: Disabled\n");
3622 } else {
3623 seq_printf(m, "VCE: Enabled\n");
3624 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3625 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3626 }
3627 }
3628 }
3629
3630 return 0;
3631}
3632
3633static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3634{
3635 int i;
3636
3637 for (i = 0; clocks[i].flag; i++)
3638 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3639 (flags & clocks[i].flag) ? "On" : "Off");
3640}
3641
3642static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3643{
3644 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3645 struct drm_device *dev = adev_to_drm(adev);
3646 u32 flags = 0;
3647 int r;
3648
3649 if (amdgpu_in_reset(adev))
3650 return -EPERM;
3651 if (adev->in_suspend && !adev->in_runpm)
3652 return -EPERM;
3653
3654 r = pm_runtime_get_sync(dev->dev);
3655 if (r < 0) {
3656 pm_runtime_put_autosuspend(dev->dev);
3657 return r;
3658 }
3659
3660 if (!adev->pm.dpm_enabled) {
3661 seq_printf(m, "dpm not enabled\n");
3662 pm_runtime_mark_last_busy(dev->dev);
3663 pm_runtime_put_autosuspend(dev->dev);
3664 return 0;
3665 }
3666
3667 if (!is_support_sw_smu(adev) &&
3668 adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3669 mutex_lock(&adev->pm.mutex);
3670 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3671 adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3672 else
3673 seq_printf(m, "Debugfs support not implemented for this asic\n");
3674 mutex_unlock(&adev->pm.mutex);
3675 r = 0;
3676 } else {
3677 r = amdgpu_debugfs_pm_info_pp(m, adev);
3678 }
3679 if (r)
3680 goto out;
3681
3682 amdgpu_device_ip_get_clockgating_state(adev, &flags);
3683
3684 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3685 amdgpu_parse_cg_state(m, flags);
3686 seq_printf(m, "\n");
3687
3688out:
3689 pm_runtime_mark_last_busy(dev->dev);
3690 pm_runtime_put_autosuspend(dev->dev);
3691
3692 return r;
3693}
3694
3695DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3696
3697/*
3698 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3699 *
3700 * Reads debug memory region allocated to PMFW
3701 */
3702static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3703 size_t size, loff_t *pos)
3704{
3705 struct amdgpu_device *adev = file_inode(f)->i_private;
3706 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
3707 void *pp_handle = adev->powerplay.pp_handle;
3708 size_t smu_prv_buf_size;
3709 void *smu_prv_buf;
3710
3711 if (amdgpu_in_reset(adev))
3712 return -EPERM;
3713 if (adev->in_suspend && !adev->in_runpm)
3714 return -EPERM;
3715
3716 if (pp_funcs && pp_funcs->get_smu_prv_buf_details)
3717 pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf,
3718 &smu_prv_buf_size);
3719 else
3720 return -ENOSYS;
3721
3722 if (!smu_prv_buf || !smu_prv_buf_size)
3723 return -EINVAL;
3724
3725 return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3726 smu_prv_buf_size);
3727}
3728
3729static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3730 .owner = THIS_MODULE,
3731 .open = simple_open,
3732 .read = amdgpu_pm_prv_buffer_read,
3733 .llseek = default_llseek,
3734};
3735
3736#endif
3737
3738void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3739{
3740#if defined(CONFIG_DEBUG_FS)
3741 struct drm_minor *minor = adev_to_drm(adev)->primary;
3742 struct dentry *root = minor->debugfs_root;
3743
3744 debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3745 &amdgpu_debugfs_pm_info_fops);
3746
3747 if (adev->pm.smu_prv_buffer_size > 0)
3748 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3749 adev,
3750 &amdgpu_debugfs_pm_prv_buffer_fops,
3751 adev->pm.smu_prv_buffer_size);
3752#endif
3753}