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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_ucode.h"
33#include "soc15_common.h"
34#include "psp_v3_1.h"
35
36#include "mp/mp_9_0_offset.h"
37#include "mp/mp_9_0_sh_mask.h"
38#include "gc/gc_9_0_offset.h"
39#include "sdma0/sdma0_4_0_offset.h"
40#include "nbio/nbio_6_1_offset.h"
41
42#include "oss/osssys_4_0_offset.h"
43#include "oss/osssys_4_0_sh_mask.h"
44
45MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
46MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
47MODULE_FIRMWARE("amdgpu/vega10_cap.bin");
48MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
49MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
50
51
52#define smnMP1_FIRMWARE_FLAGS 0x3010028
53
54static int psp_v3_1_ring_stop(struct psp_context *psp,
55 enum psp_ring_type ring_type);
56
57static int psp_v3_1_init_microcode(struct psp_context *psp)
58{
59 struct amdgpu_device *adev = psp->adev;
60 const char *chip_name;
61 int err = 0;
62
63 DRM_DEBUG("\n");
64
65 switch (adev->asic_type) {
66 case CHIP_VEGA10:
67 chip_name = "vega10";
68 break;
69 case CHIP_VEGA12:
70 chip_name = "vega12";
71 break;
72 default: BUG();
73 }
74
75 err = psp_init_sos_microcode(psp, chip_name);
76 if (err)
77 return err;
78
79 err = psp_init_asd_microcode(psp, chip_name);
80 if (err)
81 return err;
82
83 return 0;
84}
85
86static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
87{
88 int ret;
89 uint32_t psp_gfxdrv_command_reg = 0;
90 struct amdgpu_device *adev = psp->adev;
91 uint32_t sol_reg;
92
93 /* Check sOS sign of life register to confirm sys driver and sOS
94 * are already been loaded.
95 */
96 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
97 if (sol_reg)
98 return 0;
99
100 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
101 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
102 0x80000000, 0x80000000, false);
103 if (ret)
104 return ret;
105
106 /* Copy PSP System Driver binary to memory */
107 psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
108
109 /* Provide the sys driver to bootloader */
110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
111 (uint32_t)(psp->fw_pri_mc_addr >> 20));
112 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
113 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
114 psp_gfxdrv_command_reg);
115
116 /* there might be handshake issue with hardware which needs delay */
117 mdelay(20);
118
119 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
120 0x80000000, 0x80000000, false);
121
122 return ret;
123}
124
125static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
126{
127 int ret;
128 unsigned int psp_gfxdrv_command_reg = 0;
129 struct amdgpu_device *adev = psp->adev;
130 uint32_t sol_reg;
131
132 /* Check sOS sign of life register to confirm sys driver and sOS
133 * are already been loaded.
134 */
135 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
136 if (sol_reg)
137 return 0;
138
139 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
140 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
141 0x80000000, 0x80000000, false);
142 if (ret)
143 return ret;
144
145 /* Copy Secure OS binary to PSP memory */
146 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
147
148 /* Provide the PSP secure OS to bootloader */
149 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
150 (uint32_t)(psp->fw_pri_mc_addr >> 20));
151 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
152 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
153 psp_gfxdrv_command_reg);
154
155 /* there might be handshake issue with hardware which needs delay */
156 mdelay(20);
157 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
158 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
159 0, true);
160 return ret;
161}
162
163static void psp_v3_1_reroute_ih(struct psp_context *psp)
164{
165 struct amdgpu_device *adev = psp->adev;
166 uint32_t tmp;
167
168 /* Change IH ring for VMC */
169 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
170 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
171 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
172
173 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
174 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
175 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
176
177 mdelay(20);
178 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
179 0x80000000, 0x8000FFFF, false);
180
181 /* Change IH ring for UMC */
182 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
183 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
184
185 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
186 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
188
189 mdelay(20);
190 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
191 0x80000000, 0x8000FFFF, false);
192}
193
194static int psp_v3_1_ring_create(struct psp_context *psp,
195 enum psp_ring_type ring_type)
196{
197 int ret = 0;
198 unsigned int psp_ring_reg = 0;
199 struct psp_ring *ring = &psp->km_ring;
200 struct amdgpu_device *adev = psp->adev;
201
202 psp_v3_1_reroute_ih(psp);
203
204 if (amdgpu_sriov_vf(adev)) {
205 ring->ring_wptr = 0;
206 ret = psp_v3_1_ring_stop(psp, ring_type);
207 if (ret) {
208 DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
209 return ret;
210 }
211
212 /* Write low address of the ring to C2PMSG_102 */
213 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
215 /* Write high address of the ring to C2PMSG_103 */
216 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
217 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
218 /* No size initialization for sriov */
219 /* Write the ring initialization command to C2PMSG_101 */
220 psp_ring_reg = ring_type;
221 psp_ring_reg = psp_ring_reg << 16;
222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
223
224 /* there might be hardware handshake issue which needs delay */
225 mdelay(20);
226
227 /* Wait for response flag (bit 31) in C2PMSG_101 */
228 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
229 mmMP0_SMN_C2PMSG_101), 0x80000000,
230 0x8000FFFF, false);
231 } else {
232
233 /* Write low address of the ring to C2PMSG_69 */
234 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
235 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
236 /* Write high address of the ring to C2PMSG_70 */
237 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
238 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
239 /* Write size of ring to C2PMSG_71 */
240 psp_ring_reg = ring->ring_size;
241 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
242 /* Write the ring initialization command to C2PMSG_64 */
243 psp_ring_reg = ring_type;
244 psp_ring_reg = psp_ring_reg << 16;
245 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
246
247 /* there might be hardware handshake issue which needs delay */
248 mdelay(20);
249
250 /* Wait for response flag (bit 31) in C2PMSG_64 */
251 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
252 mmMP0_SMN_C2PMSG_64), 0x80000000,
253 0x8000FFFF, false);
254
255 }
256 return ret;
257}
258
259static int psp_v3_1_ring_stop(struct psp_context *psp,
260 enum psp_ring_type ring_type)
261{
262 int ret = 0;
263 struct amdgpu_device *adev = psp->adev;
264
265 /* Write the ring destroy command*/
266 if (amdgpu_sriov_vf(adev))
267 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
268 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
269 else
270 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
271 GFX_CTRL_CMD_ID_DESTROY_RINGS);
272
273 /* there might be handshake issue with hardware which needs delay */
274 mdelay(20);
275
276 /* Wait for response flag (bit 31) */
277 if (amdgpu_sriov_vf(adev))
278 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
279 0x80000000, 0x80000000, false);
280 else
281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
282 0x80000000, 0x80000000, false);
283
284 return ret;
285}
286
287static int psp_v3_1_ring_destroy(struct psp_context *psp,
288 enum psp_ring_type ring_type)
289{
290 int ret = 0;
291 struct psp_ring *ring = &psp->km_ring;
292 struct amdgpu_device *adev = psp->adev;
293
294 ret = psp_v3_1_ring_stop(psp, ring_type);
295 if (ret)
296 DRM_ERROR("Fail to stop psp ring\n");
297
298 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
299 &ring->ring_mem_mc_addr,
300 (void **)&ring->ring_mem);
301
302 return ret;
303}
304
305static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
306{
307 struct amdgpu_device *adev = psp->adev;
308 uint32_t reg;
309
310 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
311 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
312}
313
314static int psp_v3_1_mode1_reset(struct psp_context *psp)
315{
316 int ret;
317 uint32_t offset;
318 struct amdgpu_device *adev = psp->adev;
319
320 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
321
322 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
323
324 if (ret) {
325 DRM_INFO("psp is not working correctly before mode1 reset!\n");
326 return -EINVAL;
327 }
328
329 /*send the mode 1 reset command*/
330 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
331
332 msleep(500);
333
334 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
335
336 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
337
338 if (ret) {
339 DRM_INFO("psp mode 1 reset failed!\n");
340 return -EINVAL;
341 }
342
343 DRM_INFO("psp mode1 reset succeed \n");
344
345 return 0;
346}
347
348static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
349{
350 uint32_t data;
351 struct amdgpu_device *adev = psp->adev;
352
353 if (amdgpu_sriov_vf(adev))
354 data = psp->km_ring.ring_wptr;
355 else
356 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
357 return data;
358}
359
360static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
361{
362 struct amdgpu_device *adev = psp->adev;
363
364 if (amdgpu_sriov_vf(adev)) {
365 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
366 /* send interrupt to PSP for SRIOV ring write pointer update */
367 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
368 GFX_CTRL_CMD_ID_CONSUME_CMD);
369 psp->km_ring.ring_wptr = value;
370 } else
371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
372}
373
374static const struct psp_funcs psp_v3_1_funcs = {
375 .init_microcode = psp_v3_1_init_microcode,
376 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
377 .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
378 .ring_create = psp_v3_1_ring_create,
379 .ring_stop = psp_v3_1_ring_stop,
380 .ring_destroy = psp_v3_1_ring_destroy,
381 .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
382 .mode1_reset = psp_v3_1_mode1_reset,
383 .ring_get_wptr = psp_v3_1_ring_get_wptr,
384 .ring_set_wptr = psp_v3_1_ring_set_wptr,
385};
386
387void psp_v3_1_set_psp_funcs(struct psp_context *psp)
388{
389 psp->funcs = &psp_v3_1_funcs;
390}
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_ucode.h"
33#include "soc15_common.h"
34#include "psp_v3_1.h"
35
36#include "mp/mp_9_0_offset.h"
37#include "mp/mp_9_0_sh_mask.h"
38#include "gc/gc_9_0_offset.h"
39#include "sdma0/sdma0_4_0_offset.h"
40#include "nbio/nbio_6_1_offset.h"
41
42#include "oss/osssys_4_0_offset.h"
43#include "oss/osssys_4_0_sh_mask.h"
44
45MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
46MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
47MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
48MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
49
50
51#define smnMP1_FIRMWARE_FLAGS 0x3010028
52
53static int psp_v3_1_ring_stop(struct psp_context *psp,
54 enum psp_ring_type ring_type);
55
56static int psp_v3_1_init_microcode(struct psp_context *psp)
57{
58 struct amdgpu_device *adev = psp->adev;
59 const char *chip_name;
60 int err = 0;
61
62 DRM_DEBUG("\n");
63
64 switch (adev->asic_type) {
65 case CHIP_VEGA10:
66 chip_name = "vega10";
67 break;
68 case CHIP_VEGA12:
69 chip_name = "vega12";
70 break;
71 default: BUG();
72 }
73
74 err = psp_init_sos_microcode(psp, chip_name);
75 if (err)
76 return err;
77
78 err = psp_init_asd_microcode(psp, chip_name);
79 if (err)
80 return err;
81
82 return 0;
83}
84
85static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
86{
87 int ret;
88 uint32_t psp_gfxdrv_command_reg = 0;
89 struct amdgpu_device *adev = psp->adev;
90 uint32_t sol_reg;
91
92 /* Check sOS sign of life register to confirm sys driver and sOS
93 * are already been loaded.
94 */
95 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
96 if (sol_reg)
97 return 0;
98
99 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
100 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
101 0x80000000, 0x80000000, false);
102 if (ret)
103 return ret;
104
105 /* Copy PSP System Driver binary to memory */
106 psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size);
107
108 /* Provide the sys driver to bootloader */
109 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
110 (uint32_t)(psp->fw_pri_mc_addr >> 20));
111 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
112 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
113 psp_gfxdrv_command_reg);
114
115 /* there might be handshake issue with hardware which needs delay */
116 mdelay(20);
117
118 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
119 0x80000000, 0x80000000, false);
120
121 return ret;
122}
123
124static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
125{
126 int ret;
127 unsigned int psp_gfxdrv_command_reg = 0;
128 struct amdgpu_device *adev = psp->adev;
129 uint32_t sol_reg;
130
131 /* Check sOS sign of life register to confirm sys driver and sOS
132 * are already been loaded.
133 */
134 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
135 if (sol_reg)
136 return 0;
137
138 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
139 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
140 0x80000000, 0x80000000, false);
141 if (ret)
142 return ret;
143
144 /* Copy Secure OS binary to PSP memory */
145 psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size);
146
147 /* Provide the PSP secure OS to bootloader */
148 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
149 (uint32_t)(psp->fw_pri_mc_addr >> 20));
150 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
151 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
152 psp_gfxdrv_command_reg);
153
154 /* there might be handshake issue with hardware which needs delay */
155 mdelay(20);
156 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
157 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
158 0, true);
159 return ret;
160}
161
162static int psp_v3_1_ring_init(struct psp_context *psp,
163 enum psp_ring_type ring_type)
164{
165 int ret = 0;
166 struct psp_ring *ring;
167 struct amdgpu_device *adev = psp->adev;
168
169 ring = &psp->km_ring;
170
171 ring->ring_type = ring_type;
172
173 /* allocate 4k Page of Local Frame Buffer memory for ring */
174 ring->ring_size = 0x1000;
175 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
176 AMDGPU_GEM_DOMAIN_VRAM,
177 &adev->firmware.rbuf,
178 &ring->ring_mem_mc_addr,
179 (void **)&ring->ring_mem);
180 if (ret) {
181 ring->ring_size = 0;
182 return ret;
183 }
184
185 return 0;
186}
187
188static void psp_v3_1_reroute_ih(struct psp_context *psp)
189{
190 struct amdgpu_device *adev = psp->adev;
191 uint32_t tmp;
192
193 /* Change IH ring for VMC */
194 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
195 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
196 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
197
198 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
199 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
201
202 mdelay(20);
203 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
204 0x80000000, 0x8000FFFF, false);
205
206 /* Change IH ring for UMC */
207 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
208 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
209
210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
211 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
212 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
213
214 mdelay(20);
215 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
216 0x80000000, 0x8000FFFF, false);
217}
218
219static int psp_v3_1_ring_create(struct psp_context *psp,
220 enum psp_ring_type ring_type)
221{
222 int ret = 0;
223 unsigned int psp_ring_reg = 0;
224 struct psp_ring *ring = &psp->km_ring;
225 struct amdgpu_device *adev = psp->adev;
226
227 psp_v3_1_reroute_ih(psp);
228
229 if (amdgpu_sriov_vf(adev)) {
230 ring->ring_wptr = 0;
231 ret = psp_v3_1_ring_stop(psp, ring_type);
232 if (ret) {
233 DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
234 return ret;
235 }
236
237 /* Write low address of the ring to C2PMSG_102 */
238 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
239 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
240 /* Write high address of the ring to C2PMSG_103 */
241 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
242 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
243 /* No size initialization for sriov */
244 /* Write the ring initialization command to C2PMSG_101 */
245 psp_ring_reg = ring_type;
246 psp_ring_reg = psp_ring_reg << 16;
247 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
248
249 /* there might be hardware handshake issue which needs delay */
250 mdelay(20);
251
252 /* Wait for response flag (bit 31) in C2PMSG_101 */
253 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
254 mmMP0_SMN_C2PMSG_101), 0x80000000,
255 0x8000FFFF, false);
256 } else {
257
258 /* Write low address of the ring to C2PMSG_69 */
259 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
260 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
261 /* Write high address of the ring to C2PMSG_70 */
262 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
263 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
264 /* Write size of ring to C2PMSG_71 */
265 psp_ring_reg = ring->ring_size;
266 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
267 /* Write the ring initialization command to C2PMSG_64 */
268 psp_ring_reg = ring_type;
269 psp_ring_reg = psp_ring_reg << 16;
270 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
271
272 /* there might be hardware handshake issue which needs delay */
273 mdelay(20);
274
275 /* Wait for response flag (bit 31) in C2PMSG_64 */
276 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
277 mmMP0_SMN_C2PMSG_64), 0x80000000,
278 0x8000FFFF, false);
279
280 }
281 return ret;
282}
283
284static int psp_v3_1_ring_stop(struct psp_context *psp,
285 enum psp_ring_type ring_type)
286{
287 int ret = 0;
288 struct amdgpu_device *adev = psp->adev;
289
290 /* Write the ring destroy command*/
291 if (amdgpu_sriov_vf(adev))
292 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
293 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
294 else
295 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
296 GFX_CTRL_CMD_ID_DESTROY_RINGS);
297
298 /* there might be handshake issue with hardware which needs delay */
299 mdelay(20);
300
301 /* Wait for response flag (bit 31) */
302 if (amdgpu_sriov_vf(adev))
303 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
304 0x80000000, 0x80000000, false);
305 else
306 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
307 0x80000000, 0x80000000, false);
308
309 return ret;
310}
311
312static int psp_v3_1_ring_destroy(struct psp_context *psp,
313 enum psp_ring_type ring_type)
314{
315 int ret = 0;
316 struct psp_ring *ring = &psp->km_ring;
317 struct amdgpu_device *adev = psp->adev;
318
319 ret = psp_v3_1_ring_stop(psp, ring_type);
320 if (ret)
321 DRM_ERROR("Fail to stop psp ring\n");
322
323 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
324 &ring->ring_mem_mc_addr,
325 (void **)&ring->ring_mem);
326
327 return ret;
328}
329
330static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
331{
332 struct amdgpu_device *adev = psp->adev;
333 uint32_t reg;
334
335 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
336 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
337}
338
339static int psp_v3_1_mode1_reset(struct psp_context *psp)
340{
341 int ret;
342 uint32_t offset;
343 struct amdgpu_device *adev = psp->adev;
344
345 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
346
347 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
348
349 if (ret) {
350 DRM_INFO("psp is not working correctly before mode1 reset!\n");
351 return -EINVAL;
352 }
353
354 /*send the mode 1 reset command*/
355 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
356
357 msleep(500);
358
359 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
360
361 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
362
363 if (ret) {
364 DRM_INFO("psp mode 1 reset failed!\n");
365 return -EINVAL;
366 }
367
368 DRM_INFO("psp mode1 reset succeed \n");
369
370 return 0;
371}
372
373static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
374{
375 uint32_t data;
376 struct amdgpu_device *adev = psp->adev;
377
378 if (amdgpu_sriov_vf(adev))
379 data = psp->km_ring.ring_wptr;
380 else
381 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
382 return data;
383}
384
385static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
386{
387 struct amdgpu_device *adev = psp->adev;
388
389 if (amdgpu_sriov_vf(adev)) {
390 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
391 /* send interrupt to PSP for SRIOV ring write pointer update */
392 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
393 GFX_CTRL_CMD_ID_CONSUME_CMD);
394 psp->km_ring.ring_wptr = value;
395 } else
396 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
397}
398
399static const struct psp_funcs psp_v3_1_funcs = {
400 .init_microcode = psp_v3_1_init_microcode,
401 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
402 .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
403 .ring_init = psp_v3_1_ring_init,
404 .ring_create = psp_v3_1_ring_create,
405 .ring_stop = psp_v3_1_ring_stop,
406 .ring_destroy = psp_v3_1_ring_destroy,
407 .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
408 .mode1_reset = psp_v3_1_mode1_reset,
409 .ring_get_wptr = psp_v3_1_ring_get_wptr,
410 .ring_set_wptr = psp_v3_1_ring_set_wptr,
411};
412
413void psp_v3_1_set_psp_funcs(struct psp_context *psp)
414{
415 psp->funcs = &psp_v3_1_funcs;
416}