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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#include <linux/kthread.h>
27#include <linux/pci.h>
28#include <linux/uaccess.h>
29#include <linux/pm_runtime.h>
30
31#include "amdgpu.h"
32#include "amdgpu_pm.h"
33#include "amdgpu_dm_debugfs.h"
34#include "amdgpu_ras.h"
35#include "amdgpu_rap.h"
36#include "amdgpu_securedisplay.h"
37#include "amdgpu_fw_attestation.h"
38#include "amdgpu_umr.h"
39
40#include "amdgpu_reset.h"
41#include "amdgpu_psp_ta.h"
42
43#if defined(CONFIG_DEBUG_FS)
44
45/**
46 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
47 *
48 * @read: True if reading
49 * @f: open file handle
50 * @buf: User buffer to write/read to
51 * @size: Number of bytes to write/read
52 * @pos: Offset to seek to
53 *
54 * This debugfs entry has special meaning on the offset being sought.
55 * Various bits have different meanings:
56 *
57 * Bit 62: Indicates a GRBM bank switch is needed
58 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
59 * zero)
60 * Bits 24..33: The SE or ME selector if needed
61 * Bits 34..43: The SH (or SA) or PIPE selector if needed
62 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
63 *
64 * Bit 23: Indicates that the PM power gating lock should be held
65 * This is necessary to read registers that might be
66 * unreliable during a power gating transistion.
67 *
68 * The lower bits are the BYTE offset of the register to read. This
69 * allows reading multiple registers in a single call and having
70 * the returned size reflect that.
71 */
72static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
73 char __user *buf, size_t size, loff_t *pos)
74{
75 struct amdgpu_device *adev = file_inode(f)->i_private;
76 ssize_t result = 0;
77 int r;
78 bool pm_pg_lock, use_bank, use_ring;
79 unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
80
81 pm_pg_lock = use_bank = use_ring = false;
82 instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
83
84 if (size & 0x3 || *pos & 0x3 ||
85 ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
86 return -EINVAL;
87
88 /* are we reading registers for which a PG lock is necessary? */
89 pm_pg_lock = (*pos >> 23) & 1;
90
91 if (*pos & (1ULL << 62)) {
92 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
93 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
94 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
95
96 if (se_bank == 0x3FF)
97 se_bank = 0xFFFFFFFF;
98 if (sh_bank == 0x3FF)
99 sh_bank = 0xFFFFFFFF;
100 if (instance_bank == 0x3FF)
101 instance_bank = 0xFFFFFFFF;
102 use_bank = true;
103 } else if (*pos & (1ULL << 61)) {
104
105 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
106 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
107 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
108 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
109
110 use_ring = true;
111 } else {
112 use_bank = use_ring = false;
113 }
114
115 *pos &= (1UL << 22) - 1;
116
117 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
118 if (r < 0) {
119 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
120 return r;
121 }
122
123 r = amdgpu_virt_enable_access_debugfs(adev);
124 if (r < 0) {
125 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
126 return r;
127 }
128
129 if (use_bank) {
130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
132 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
133 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
134 amdgpu_virt_disable_access_debugfs(adev);
135 return -EINVAL;
136 }
137 mutex_lock(&adev->grbm_idx_mutex);
138 amdgpu_gfx_select_se_sh(adev, se_bank,
139 sh_bank, instance_bank);
140 } else if (use_ring) {
141 mutex_lock(&adev->srbm_mutex);
142 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
143 }
144
145 if (pm_pg_lock)
146 mutex_lock(&adev->pm.mutex);
147
148 while (size) {
149 uint32_t value;
150
151 if (read) {
152 value = RREG32(*pos >> 2);
153 r = put_user(value, (uint32_t *)buf);
154 } else {
155 r = get_user(value, (uint32_t *)buf);
156 if (!r)
157 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
158 }
159 if (r) {
160 result = r;
161 goto end;
162 }
163
164 result += 4;
165 buf += 4;
166 *pos += 4;
167 size -= 4;
168 }
169
170end:
171 if (use_bank) {
172 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
173 mutex_unlock(&adev->grbm_idx_mutex);
174 } else if (use_ring) {
175 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
176 mutex_unlock(&adev->srbm_mutex);
177 }
178
179 if (pm_pg_lock)
180 mutex_unlock(&adev->pm.mutex);
181
182 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
183 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
184
185 amdgpu_virt_disable_access_debugfs(adev);
186 return result;
187}
188
189/*
190 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
191 */
192static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
193 size_t size, loff_t *pos)
194{
195 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
196}
197
198/*
199 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
200 */
201static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
202 size_t size, loff_t *pos)
203{
204 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
205}
206
207static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file)
208{
209 struct amdgpu_debugfs_regs2_data *rd;
210
211 rd = kzalloc(sizeof *rd, GFP_KERNEL);
212 if (!rd)
213 return -ENOMEM;
214 rd->adev = file_inode(file)->i_private;
215 file->private_data = rd;
216 mutex_init(&rd->lock);
217
218 return 0;
219}
220
221static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file)
222{
223 struct amdgpu_debugfs_regs2_data *rd = file->private_data;
224 mutex_destroy(&rd->lock);
225 kfree(file->private_data);
226 return 0;
227}
228
229static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en)
230{
231 struct amdgpu_debugfs_regs2_data *rd = f->private_data;
232 struct amdgpu_device *adev = rd->adev;
233 ssize_t result = 0;
234 int r;
235 uint32_t value;
236
237 if (size & 0x3 || offset & 0x3)
238 return -EINVAL;
239
240 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
241 if (r < 0) {
242 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
243 return r;
244 }
245
246 r = amdgpu_virt_enable_access_debugfs(adev);
247 if (r < 0) {
248 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
249 return r;
250 }
251
252 mutex_lock(&rd->lock);
253
254 if (rd->id.use_grbm) {
255 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||
256 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {
257 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
258 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
259 amdgpu_virt_disable_access_debugfs(adev);
260 mutex_unlock(&rd->lock);
261 return -EINVAL;
262 }
263 mutex_lock(&adev->grbm_idx_mutex);
264 amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
265 rd->id.grbm.sh,
266 rd->id.grbm.instance);
267 }
268
269 if (rd->id.use_srbm) {
270 mutex_lock(&adev->srbm_mutex);
271 amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,
272 rd->id.srbm.queue, rd->id.srbm.vmid);
273 }
274
275 if (rd->id.pg_lock)
276 mutex_lock(&adev->pm.mutex);
277
278 while (size) {
279 if (!write_en) {
280 value = RREG32(offset >> 2);
281 r = put_user(value, (uint32_t *)buf);
282 } else {
283 r = get_user(value, (uint32_t *)buf);
284 if (!r)
285 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value);
286 }
287 if (r) {
288 result = r;
289 goto end;
290 }
291 offset += 4;
292 size -= 4;
293 result += 4;
294 buf += 4;
295 }
296end:
297 if (rd->id.use_grbm) {
298 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
299 mutex_unlock(&adev->grbm_idx_mutex);
300 }
301
302 if (rd->id.use_srbm) {
303 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
304 mutex_unlock(&adev->srbm_mutex);
305 }
306
307 if (rd->id.pg_lock)
308 mutex_unlock(&adev->pm.mutex);
309
310 mutex_unlock(&rd->lock);
311
312 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
313 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
314
315 amdgpu_virt_disable_access_debugfs(adev);
316 return result;
317}
318
319static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data)
320{
321 struct amdgpu_debugfs_regs2_data *rd = f->private_data;
322 int r;
323
324 switch (cmd) {
325 case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:
326 mutex_lock(&rd->lock);
327 r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata *)data, sizeof rd->id);
328 mutex_unlock(&rd->lock);
329 return r ? -EINVAL : 0;
330 default:
331 return -EINVAL;
332 }
333 return 0;
334}
335
336static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
337{
338 return amdgpu_debugfs_regs2_op(f, buf, *pos, size, 0);
339}
340
341static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf, size_t size, loff_t *pos)
342{
343 return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);
344}
345
346
347/**
348 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
349 *
350 * @f: open file handle
351 * @buf: User buffer to store read data in
352 * @size: Number of bytes to read
353 * @pos: Offset to seek to
354 *
355 * The lower bits are the BYTE offset of the register to read. This
356 * allows reading multiple registers in a single call and having
357 * the returned size reflect that.
358 */
359static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
360 size_t size, loff_t *pos)
361{
362 struct amdgpu_device *adev = file_inode(f)->i_private;
363 ssize_t result = 0;
364 int r;
365
366 if (size & 0x3 || *pos & 0x3)
367 return -EINVAL;
368
369 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
370 if (r < 0) {
371 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
372 return r;
373 }
374
375 r = amdgpu_virt_enable_access_debugfs(adev);
376 if (r < 0) {
377 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
378 return r;
379 }
380
381 while (size) {
382 uint32_t value;
383
384 value = RREG32_PCIE(*pos);
385 r = put_user(value, (uint32_t *)buf);
386 if (r)
387 goto out;
388
389 result += 4;
390 buf += 4;
391 *pos += 4;
392 size -= 4;
393 }
394
395 r = result;
396out:
397 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
398 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
399 amdgpu_virt_disable_access_debugfs(adev);
400 return r;
401}
402
403/**
404 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
405 *
406 * @f: open file handle
407 * @buf: User buffer to write data from
408 * @size: Number of bytes to write
409 * @pos: Offset to seek to
410 *
411 * The lower bits are the BYTE offset of the register to write. This
412 * allows writing multiple registers in a single call and having
413 * the returned size reflect that.
414 */
415static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
416 size_t size, loff_t *pos)
417{
418 struct amdgpu_device *adev = file_inode(f)->i_private;
419 ssize_t result = 0;
420 int r;
421
422 if (size & 0x3 || *pos & 0x3)
423 return -EINVAL;
424
425 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
426 if (r < 0) {
427 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
428 return r;
429 }
430
431 r = amdgpu_virt_enable_access_debugfs(adev);
432 if (r < 0) {
433 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
434 return r;
435 }
436
437 while (size) {
438 uint32_t value;
439
440 r = get_user(value, (uint32_t *)buf);
441 if (r)
442 goto out;
443
444 WREG32_PCIE(*pos, value);
445
446 result += 4;
447 buf += 4;
448 *pos += 4;
449 size -= 4;
450 }
451
452 r = result;
453out:
454 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
455 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
456 amdgpu_virt_disable_access_debugfs(adev);
457 return r;
458}
459
460/**
461 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
462 *
463 * @f: open file handle
464 * @buf: User buffer to store read data in
465 * @size: Number of bytes to read
466 * @pos: Offset to seek to
467 *
468 * The lower bits are the BYTE offset of the register to read. This
469 * allows reading multiple registers in a single call and having
470 * the returned size reflect that.
471 */
472static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
473 size_t size, loff_t *pos)
474{
475 struct amdgpu_device *adev = file_inode(f)->i_private;
476 ssize_t result = 0;
477 int r;
478
479 if (size & 0x3 || *pos & 0x3)
480 return -EINVAL;
481
482 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
483 if (r < 0) {
484 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
485 return r;
486 }
487
488 r = amdgpu_virt_enable_access_debugfs(adev);
489 if (r < 0) {
490 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
491 return r;
492 }
493
494 while (size) {
495 uint32_t value;
496
497 value = RREG32_DIDT(*pos >> 2);
498 r = put_user(value, (uint32_t *)buf);
499 if (r)
500 goto out;
501
502 result += 4;
503 buf += 4;
504 *pos += 4;
505 size -= 4;
506 }
507
508 r = result;
509out:
510 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
511 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
512 amdgpu_virt_disable_access_debugfs(adev);
513 return r;
514}
515
516/**
517 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
518 *
519 * @f: open file handle
520 * @buf: User buffer to write data from
521 * @size: Number of bytes to write
522 * @pos: Offset to seek to
523 *
524 * The lower bits are the BYTE offset of the register to write. This
525 * allows writing multiple registers in a single call and having
526 * the returned size reflect that.
527 */
528static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
529 size_t size, loff_t *pos)
530{
531 struct amdgpu_device *adev = file_inode(f)->i_private;
532 ssize_t result = 0;
533 int r;
534
535 if (size & 0x3 || *pos & 0x3)
536 return -EINVAL;
537
538 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
539 if (r < 0) {
540 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
541 return r;
542 }
543
544 r = amdgpu_virt_enable_access_debugfs(adev);
545 if (r < 0) {
546 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
547 return r;
548 }
549
550 while (size) {
551 uint32_t value;
552
553 r = get_user(value, (uint32_t *)buf);
554 if (r)
555 goto out;
556
557 WREG32_DIDT(*pos >> 2, value);
558
559 result += 4;
560 buf += 4;
561 *pos += 4;
562 size -= 4;
563 }
564
565 r = result;
566out:
567 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
568 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
569 amdgpu_virt_disable_access_debugfs(adev);
570 return r;
571}
572
573/**
574 * amdgpu_debugfs_regs_smc_read - Read from a SMC register
575 *
576 * @f: open file handle
577 * @buf: User buffer to store read data in
578 * @size: Number of bytes to read
579 * @pos: Offset to seek to
580 *
581 * The lower bits are the BYTE offset of the register to read. This
582 * allows reading multiple registers in a single call and having
583 * the returned size reflect that.
584 */
585static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
586 size_t size, loff_t *pos)
587{
588 struct amdgpu_device *adev = file_inode(f)->i_private;
589 ssize_t result = 0;
590 int r;
591
592 if (size & 0x3 || *pos & 0x3)
593 return -EINVAL;
594
595 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
596 if (r < 0) {
597 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
598 return r;
599 }
600
601 r = amdgpu_virt_enable_access_debugfs(adev);
602 if (r < 0) {
603 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
604 return r;
605 }
606
607 while (size) {
608 uint32_t value;
609
610 value = RREG32_SMC(*pos);
611 r = put_user(value, (uint32_t *)buf);
612 if (r)
613 goto out;
614
615 result += 4;
616 buf += 4;
617 *pos += 4;
618 size -= 4;
619 }
620
621 r = result;
622out:
623 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
624 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
625 amdgpu_virt_disable_access_debugfs(adev);
626 return r;
627}
628
629/**
630 * amdgpu_debugfs_regs_smc_write - Write to a SMC register
631 *
632 * @f: open file handle
633 * @buf: User buffer to write data from
634 * @size: Number of bytes to write
635 * @pos: Offset to seek to
636 *
637 * The lower bits are the BYTE offset of the register to write. This
638 * allows writing multiple registers in a single call and having
639 * the returned size reflect that.
640 */
641static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
642 size_t size, loff_t *pos)
643{
644 struct amdgpu_device *adev = file_inode(f)->i_private;
645 ssize_t result = 0;
646 int r;
647
648 if (size & 0x3 || *pos & 0x3)
649 return -EINVAL;
650
651 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
652 if (r < 0) {
653 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
654 return r;
655 }
656
657 r = amdgpu_virt_enable_access_debugfs(adev);
658 if (r < 0) {
659 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
660 return r;
661 }
662
663 while (size) {
664 uint32_t value;
665
666 r = get_user(value, (uint32_t *)buf);
667 if (r)
668 goto out;
669
670 WREG32_SMC(*pos, value);
671
672 result += 4;
673 buf += 4;
674 *pos += 4;
675 size -= 4;
676 }
677
678 r = result;
679out:
680 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
681 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
682 amdgpu_virt_disable_access_debugfs(adev);
683 return r;
684}
685
686/**
687 * amdgpu_debugfs_gca_config_read - Read from gfx config data
688 *
689 * @f: open file handle
690 * @buf: User buffer to store read data in
691 * @size: Number of bytes to read
692 * @pos: Offset to seek to
693 *
694 * This file is used to access configuration data in a somewhat
695 * stable fashion. The format is a series of DWORDs with the first
696 * indicating which revision it is. New content is appended to the
697 * end so that older software can still read the data.
698 */
699
700static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
701 size_t size, loff_t *pos)
702{
703 struct amdgpu_device *adev = file_inode(f)->i_private;
704 ssize_t result = 0;
705 int r;
706 uint32_t *config, no_regs = 0;
707
708 if (size & 0x3 || *pos & 0x3)
709 return -EINVAL;
710
711 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
712 if (!config)
713 return -ENOMEM;
714
715 /* version, increment each time something is added */
716 config[no_regs++] = 5;
717 config[no_regs++] = adev->gfx.config.max_shader_engines;
718 config[no_regs++] = adev->gfx.config.max_tile_pipes;
719 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
720 config[no_regs++] = adev->gfx.config.max_sh_per_se;
721 config[no_regs++] = adev->gfx.config.max_backends_per_se;
722 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
723 config[no_regs++] = adev->gfx.config.max_gprs;
724 config[no_regs++] = adev->gfx.config.max_gs_threads;
725 config[no_regs++] = adev->gfx.config.max_hw_contexts;
726 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
727 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
728 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
729 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
730 config[no_regs++] = adev->gfx.config.num_tile_pipes;
731 config[no_regs++] = adev->gfx.config.backend_enable_mask;
732 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
733 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
734 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
735 config[no_regs++] = adev->gfx.config.num_gpus;
736 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
737 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
738 config[no_regs++] = adev->gfx.config.gb_addr_config;
739 config[no_regs++] = adev->gfx.config.num_rbs;
740
741 /* rev==1 */
742 config[no_regs++] = adev->rev_id;
743 config[no_regs++] = lower_32_bits(adev->pg_flags);
744 config[no_regs++] = lower_32_bits(adev->cg_flags);
745
746 /* rev==2 */
747 config[no_regs++] = adev->family;
748 config[no_regs++] = adev->external_rev_id;
749
750 /* rev==3 */
751 config[no_regs++] = adev->pdev->device;
752 config[no_regs++] = adev->pdev->revision;
753 config[no_regs++] = adev->pdev->subsystem_device;
754 config[no_regs++] = adev->pdev->subsystem_vendor;
755
756 /* rev==4 APU flag */
757 config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
758
759 /* rev==5 PG/CG flag upper 32bit */
760 config[no_regs++] = upper_32_bits(adev->pg_flags);
761 config[no_regs++] = upper_32_bits(adev->cg_flags);
762
763 while (size && (*pos < no_regs * 4)) {
764 uint32_t value;
765
766 value = config[*pos >> 2];
767 r = put_user(value, (uint32_t *)buf);
768 if (r) {
769 kfree(config);
770 return r;
771 }
772
773 result += 4;
774 buf += 4;
775 *pos += 4;
776 size -= 4;
777 }
778
779 kfree(config);
780 return result;
781}
782
783/**
784 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
785 *
786 * @f: open file handle
787 * @buf: User buffer to store read data in
788 * @size: Number of bytes to read
789 * @pos: Offset to seek to
790 *
791 * The offset is treated as the BYTE address of one of the sensors
792 * enumerated in amd/include/kgd_pp_interface.h under the
793 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
794 * you would use the offset 3 * 4 = 12.
795 */
796static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
797 size_t size, loff_t *pos)
798{
799 struct amdgpu_device *adev = file_inode(f)->i_private;
800 int idx, x, outsize, r, valuesize;
801 uint32_t values[16];
802
803 if (size & 3 || *pos & 0x3)
804 return -EINVAL;
805
806 if (!adev->pm.dpm_enabled)
807 return -EINVAL;
808
809 /* convert offset to sensor number */
810 idx = *pos >> 2;
811
812 valuesize = sizeof(values);
813
814 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
815 if (r < 0) {
816 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
817 return r;
818 }
819
820 r = amdgpu_virt_enable_access_debugfs(adev);
821 if (r < 0) {
822 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
823 return r;
824 }
825
826 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
827
828 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
829 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
830
831 if (r) {
832 amdgpu_virt_disable_access_debugfs(adev);
833 return r;
834 }
835
836 if (size > valuesize) {
837 amdgpu_virt_disable_access_debugfs(adev);
838 return -EINVAL;
839 }
840
841 outsize = 0;
842 x = 0;
843 if (!r) {
844 while (size) {
845 r = put_user(values[x++], (int32_t *)buf);
846 buf += 4;
847 size -= 4;
848 outsize += 4;
849 }
850 }
851
852 amdgpu_virt_disable_access_debugfs(adev);
853 return !r ? outsize : r;
854}
855
856/** amdgpu_debugfs_wave_read - Read WAVE STATUS data
857 *
858 * @f: open file handle
859 * @buf: User buffer to store read data in
860 * @size: Number of bytes to read
861 * @pos: Offset to seek to
862 *
863 * The offset being sought changes which wave that the status data
864 * will be returned for. The bits are used as follows:
865 *
866 * Bits 0..6: Byte offset into data
867 * Bits 7..14: SE selector
868 * Bits 15..22: SH/SA selector
869 * Bits 23..30: CU/{WGP+SIMD} selector
870 * Bits 31..36: WAVE ID selector
871 * Bits 37..44: SIMD ID selector
872 *
873 * The returned data begins with one DWORD of version information
874 * Followed by WAVE STATUS registers relevant to the GFX IP version
875 * being used. See gfx_v8_0_read_wave_data() for an example output.
876 */
877static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
878 size_t size, loff_t *pos)
879{
880 struct amdgpu_device *adev = f->f_inode->i_private;
881 int r, x;
882 ssize_t result = 0;
883 uint32_t offset, se, sh, cu, wave, simd, data[32];
884
885 if (size & 3 || *pos & 3)
886 return -EINVAL;
887
888 /* decode offset */
889 offset = (*pos & GENMASK_ULL(6, 0));
890 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
891 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
892 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
893 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
894 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
895
896 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
897 if (r < 0) {
898 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
899 return r;
900 }
901
902 r = amdgpu_virt_enable_access_debugfs(adev);
903 if (r < 0) {
904 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
905 return r;
906 }
907
908 /* switch to the specific se/sh/cu */
909 mutex_lock(&adev->grbm_idx_mutex);
910 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
911
912 x = 0;
913 if (adev->gfx.funcs->read_wave_data)
914 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
915
916 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
917 mutex_unlock(&adev->grbm_idx_mutex);
918
919 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
920 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
921
922 if (!x) {
923 amdgpu_virt_disable_access_debugfs(adev);
924 return -EINVAL;
925 }
926
927 while (size && (offset < x * 4)) {
928 uint32_t value;
929
930 value = data[offset >> 2];
931 r = put_user(value, (uint32_t *)buf);
932 if (r) {
933 amdgpu_virt_disable_access_debugfs(adev);
934 return r;
935 }
936
937 result += 4;
938 buf += 4;
939 offset += 4;
940 size -= 4;
941 }
942
943 amdgpu_virt_disable_access_debugfs(adev);
944 return result;
945}
946
947/** amdgpu_debugfs_gpr_read - Read wave gprs
948 *
949 * @f: open file handle
950 * @buf: User buffer to store read data in
951 * @size: Number of bytes to read
952 * @pos: Offset to seek to
953 *
954 * The offset being sought changes which wave that the status data
955 * will be returned for. The bits are used as follows:
956 *
957 * Bits 0..11: Byte offset into data
958 * Bits 12..19: SE selector
959 * Bits 20..27: SH/SA selector
960 * Bits 28..35: CU/{WGP+SIMD} selector
961 * Bits 36..43: WAVE ID selector
962 * Bits 37..44: SIMD ID selector
963 * Bits 52..59: Thread selector
964 * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
965 *
966 * The return data comes from the SGPR or VGPR register bank for
967 * the selected operational unit.
968 */
969static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
970 size_t size, loff_t *pos)
971{
972 struct amdgpu_device *adev = f->f_inode->i_private;
973 int r;
974 ssize_t result = 0;
975 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
976
977 if (size > 4096 || size & 3 || *pos & 3)
978 return -EINVAL;
979
980 /* decode offset */
981 offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
982 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
983 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
984 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
985 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
986 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
987 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
988 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
989
990 data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
991 if (!data)
992 return -ENOMEM;
993
994 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
995 if (r < 0)
996 goto err;
997
998 r = amdgpu_virt_enable_access_debugfs(adev);
999 if (r < 0)
1000 goto err;
1001
1002 /* switch to the specific se/sh/cu */
1003 mutex_lock(&adev->grbm_idx_mutex);
1004 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
1005
1006 if (bank == 0) {
1007 if (adev->gfx.funcs->read_wave_vgprs)
1008 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
1009 } else {
1010 if (adev->gfx.funcs->read_wave_sgprs)
1011 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
1012 }
1013
1014 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1015 mutex_unlock(&adev->grbm_idx_mutex);
1016
1017 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1018 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1019
1020 while (size) {
1021 uint32_t value;
1022
1023 value = data[result >> 2];
1024 r = put_user(value, (uint32_t *)buf);
1025 if (r) {
1026 amdgpu_virt_disable_access_debugfs(adev);
1027 goto err;
1028 }
1029
1030 result += 4;
1031 buf += 4;
1032 size -= 4;
1033 }
1034
1035 kfree(data);
1036 amdgpu_virt_disable_access_debugfs(adev);
1037 return result;
1038
1039err:
1040 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1041 kfree(data);
1042 return r;
1043}
1044
1045/**
1046 * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
1047 *
1048 * @f: open file handle
1049 * @buf: User buffer to store read data in
1050 * @size: Number of bytes to read
1051 * @pos: Offset to seek to
1052 *
1053 * Read the last residency value logged. It doesn't auto update, one needs to
1054 * stop logging before getting the current value.
1055 */
1056static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char __user *buf,
1057 size_t size, loff_t *pos)
1058{
1059 struct amdgpu_device *adev = file_inode(f)->i_private;
1060 ssize_t result = 0;
1061 int r;
1062
1063 if (size & 0x3 || *pos & 0x3)
1064 return -EINVAL;
1065
1066 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1067 if (r < 0) {
1068 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1069 return r;
1070 }
1071
1072 while (size) {
1073 uint32_t value;
1074
1075 r = amdgpu_get_gfx_off_residency(adev, &value);
1076 if (r)
1077 goto out;
1078
1079 r = put_user(value, (uint32_t *)buf);
1080 if (r)
1081 goto out;
1082
1083 result += 4;
1084 buf += 4;
1085 *pos += 4;
1086 size -= 4;
1087 }
1088
1089 r = result;
1090out:
1091 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1092 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1093
1094 return r;
1095}
1096
1097/**
1098 * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
1099 *
1100 * @f: open file handle
1101 * @buf: User buffer to write data from
1102 * @size: Number of bytes to write
1103 * @pos: Offset to seek to
1104 *
1105 * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
1106 */
1107static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const char __user *buf,
1108 size_t size, loff_t *pos)
1109{
1110 struct amdgpu_device *adev = file_inode(f)->i_private;
1111 ssize_t result = 0;
1112 int r;
1113
1114 if (size & 0x3 || *pos & 0x3)
1115 return -EINVAL;
1116
1117 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1118 if (r < 0) {
1119 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1120 return r;
1121 }
1122
1123 while (size) {
1124 u32 value;
1125
1126 r = get_user(value, (uint32_t *)buf);
1127 if (r)
1128 goto out;
1129
1130 amdgpu_set_gfx_off_residency(adev, value ? true : false);
1131
1132 result += 4;
1133 buf += 4;
1134 *pos += 4;
1135 size -= 4;
1136 }
1137
1138 r = result;
1139out:
1140 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1141 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1142
1143 return r;
1144}
1145
1146
1147/**
1148 * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
1149 *
1150 * @f: open file handle
1151 * @buf: User buffer to store read data in
1152 * @size: Number of bytes to read
1153 * @pos: Offset to seek to
1154 */
1155static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user *buf,
1156 size_t size, loff_t *pos)
1157{
1158 struct amdgpu_device *adev = file_inode(f)->i_private;
1159 ssize_t result = 0;
1160 int r;
1161
1162 if (size & 0x3 || *pos & 0x3)
1163 return -EINVAL;
1164
1165 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1166 if (r < 0) {
1167 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1168 return r;
1169 }
1170
1171 while (size) {
1172 u64 value = 0;
1173
1174 r = amdgpu_get_gfx_off_entrycount(adev, &value);
1175 if (r)
1176 goto out;
1177
1178 r = put_user(value, (u64 *)buf);
1179 if (r)
1180 goto out;
1181
1182 result += 4;
1183 buf += 4;
1184 *pos += 4;
1185 size -= 4;
1186 }
1187
1188 r = result;
1189out:
1190 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1191 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1192
1193 return r;
1194}
1195
1196/**
1197 * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1198 *
1199 * @f: open file handle
1200 * @buf: User buffer to write data from
1201 * @size: Number of bytes to write
1202 * @pos: Offset to seek to
1203 *
1204 * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1205 */
1206static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1207 size_t size, loff_t *pos)
1208{
1209 struct amdgpu_device *adev = file_inode(f)->i_private;
1210 ssize_t result = 0;
1211 int r;
1212
1213 if (size & 0x3 || *pos & 0x3)
1214 return -EINVAL;
1215
1216 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1217 if (r < 0) {
1218 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1219 return r;
1220 }
1221
1222 while (size) {
1223 uint32_t value;
1224
1225 r = get_user(value, (uint32_t *)buf);
1226 if (r)
1227 goto out;
1228
1229 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1230
1231 result += 4;
1232 buf += 4;
1233 *pos += 4;
1234 size -= 4;
1235 }
1236
1237 r = result;
1238out:
1239 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1240 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1241
1242 return r;
1243}
1244
1245
1246/**
1247 * amdgpu_debugfs_gfxoff_read - read gfxoff status
1248 *
1249 * @f: open file handle
1250 * @buf: User buffer to store read data in
1251 * @size: Number of bytes to read
1252 * @pos: Offset to seek to
1253 */
1254static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1255 size_t size, loff_t *pos)
1256{
1257 struct amdgpu_device *adev = file_inode(f)->i_private;
1258 ssize_t result = 0;
1259 int r;
1260
1261 if (size & 0x3 || *pos & 0x3)
1262 return -EINVAL;
1263
1264 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1265 if (r < 0) {
1266 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1267 return r;
1268 }
1269
1270 while (size) {
1271 u32 value = adev->gfx.gfx_off_state;
1272
1273 r = put_user(value, (u32 *)buf);
1274 if (r)
1275 goto out;
1276
1277 result += 4;
1278 buf += 4;
1279 *pos += 4;
1280 size -= 4;
1281 }
1282
1283 r = result;
1284out:
1285 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1286 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1287
1288 return r;
1289}
1290
1291static ssize_t amdgpu_debugfs_gfxoff_status_read(struct file *f, char __user *buf,
1292 size_t size, loff_t *pos)
1293{
1294 struct amdgpu_device *adev = file_inode(f)->i_private;
1295 ssize_t result = 0;
1296 int r;
1297
1298 if (size & 0x3 || *pos & 0x3)
1299 return -EINVAL;
1300
1301 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1302 if (r < 0) {
1303 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1304 return r;
1305 }
1306
1307 while (size) {
1308 u32 value;
1309
1310 r = amdgpu_get_gfx_off_status(adev, &value);
1311 if (r)
1312 goto out;
1313
1314 r = put_user(value, (u32 *)buf);
1315 if (r)
1316 goto out;
1317
1318 result += 4;
1319 buf += 4;
1320 *pos += 4;
1321 size -= 4;
1322 }
1323
1324 r = result;
1325out:
1326 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1327 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1328
1329 return r;
1330}
1331
1332static const struct file_operations amdgpu_debugfs_regs2_fops = {
1333 .owner = THIS_MODULE,
1334 .unlocked_ioctl = amdgpu_debugfs_regs2_ioctl,
1335 .read = amdgpu_debugfs_regs2_read,
1336 .write = amdgpu_debugfs_regs2_write,
1337 .open = amdgpu_debugfs_regs2_open,
1338 .release = amdgpu_debugfs_regs2_release,
1339 .llseek = default_llseek
1340};
1341
1342static const struct file_operations amdgpu_debugfs_regs_fops = {
1343 .owner = THIS_MODULE,
1344 .read = amdgpu_debugfs_regs_read,
1345 .write = amdgpu_debugfs_regs_write,
1346 .llseek = default_llseek
1347};
1348static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1349 .owner = THIS_MODULE,
1350 .read = amdgpu_debugfs_regs_didt_read,
1351 .write = amdgpu_debugfs_regs_didt_write,
1352 .llseek = default_llseek
1353};
1354static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1355 .owner = THIS_MODULE,
1356 .read = amdgpu_debugfs_regs_pcie_read,
1357 .write = amdgpu_debugfs_regs_pcie_write,
1358 .llseek = default_llseek
1359};
1360static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1361 .owner = THIS_MODULE,
1362 .read = amdgpu_debugfs_regs_smc_read,
1363 .write = amdgpu_debugfs_regs_smc_write,
1364 .llseek = default_llseek
1365};
1366
1367static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1368 .owner = THIS_MODULE,
1369 .read = amdgpu_debugfs_gca_config_read,
1370 .llseek = default_llseek
1371};
1372
1373static const struct file_operations amdgpu_debugfs_sensors_fops = {
1374 .owner = THIS_MODULE,
1375 .read = amdgpu_debugfs_sensor_read,
1376 .llseek = default_llseek
1377};
1378
1379static const struct file_operations amdgpu_debugfs_wave_fops = {
1380 .owner = THIS_MODULE,
1381 .read = amdgpu_debugfs_wave_read,
1382 .llseek = default_llseek
1383};
1384static const struct file_operations amdgpu_debugfs_gpr_fops = {
1385 .owner = THIS_MODULE,
1386 .read = amdgpu_debugfs_gpr_read,
1387 .llseek = default_llseek
1388};
1389
1390static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1391 .owner = THIS_MODULE,
1392 .read = amdgpu_debugfs_gfxoff_read,
1393 .write = amdgpu_debugfs_gfxoff_write,
1394 .llseek = default_llseek
1395};
1396
1397static const struct file_operations amdgpu_debugfs_gfxoff_status_fops = {
1398 .owner = THIS_MODULE,
1399 .read = amdgpu_debugfs_gfxoff_status_read,
1400 .llseek = default_llseek
1401};
1402
1403static const struct file_operations amdgpu_debugfs_gfxoff_count_fops = {
1404 .owner = THIS_MODULE,
1405 .read = amdgpu_debugfs_gfxoff_count_read,
1406 .llseek = default_llseek
1407};
1408
1409static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = {
1410 .owner = THIS_MODULE,
1411 .read = amdgpu_debugfs_gfxoff_residency_read,
1412 .write = amdgpu_debugfs_gfxoff_residency_write,
1413 .llseek = default_llseek
1414};
1415
1416static const struct file_operations *debugfs_regs[] = {
1417 &amdgpu_debugfs_regs_fops,
1418 &amdgpu_debugfs_regs2_fops,
1419 &amdgpu_debugfs_regs_didt_fops,
1420 &amdgpu_debugfs_regs_pcie_fops,
1421 &amdgpu_debugfs_regs_smc_fops,
1422 &amdgpu_debugfs_gca_config_fops,
1423 &amdgpu_debugfs_sensors_fops,
1424 &amdgpu_debugfs_wave_fops,
1425 &amdgpu_debugfs_gpr_fops,
1426 &amdgpu_debugfs_gfxoff_fops,
1427 &amdgpu_debugfs_gfxoff_status_fops,
1428 &amdgpu_debugfs_gfxoff_count_fops,
1429 &amdgpu_debugfs_gfxoff_residency_fops,
1430};
1431
1432static const char *debugfs_regs_names[] = {
1433 "amdgpu_regs",
1434 "amdgpu_regs2",
1435 "amdgpu_regs_didt",
1436 "amdgpu_regs_pcie",
1437 "amdgpu_regs_smc",
1438 "amdgpu_gca_config",
1439 "amdgpu_sensors",
1440 "amdgpu_wave",
1441 "amdgpu_gpr",
1442 "amdgpu_gfxoff",
1443 "amdgpu_gfxoff_status",
1444 "amdgpu_gfxoff_count",
1445 "amdgpu_gfxoff_residency",
1446};
1447
1448/**
1449 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
1450 * register access.
1451 *
1452 * @adev: The device to attach the debugfs entries to
1453 */
1454int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1455{
1456 struct drm_minor *minor = adev_to_drm(adev)->primary;
1457 struct dentry *ent, *root = minor->debugfs_root;
1458 unsigned int i;
1459
1460 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1461 ent = debugfs_create_file(debugfs_regs_names[i],
1462 S_IFREG | S_IRUGO, root,
1463 adev, debugfs_regs[i]);
1464 if (!i && !IS_ERR_OR_NULL(ent))
1465 i_size_write(ent->d_inode, adev->rmmio_size);
1466 }
1467
1468 return 0;
1469}
1470
1471static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)
1472{
1473 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1474 struct drm_device *dev = adev_to_drm(adev);
1475 int r = 0, i;
1476
1477 r = pm_runtime_get_sync(dev->dev);
1478 if (r < 0) {
1479 pm_runtime_put_autosuspend(dev->dev);
1480 return r;
1481 }
1482
1483 /* Avoid accidently unparking the sched thread during GPU reset */
1484 r = down_write_killable(&adev->reset_domain->sem);
1485 if (r)
1486 return r;
1487
1488 /* hold on the scheduler */
1489 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1490 struct amdgpu_ring *ring = adev->rings[i];
1491
1492 if (!ring || !ring->sched.thread)
1493 continue;
1494 kthread_park(ring->sched.thread);
1495 }
1496
1497 seq_printf(m, "run ib test:\n");
1498 r = amdgpu_ib_ring_tests(adev);
1499 if (r)
1500 seq_printf(m, "ib ring tests failed (%d).\n", r);
1501 else
1502 seq_printf(m, "ib ring tests passed.\n");
1503
1504 /* go on the scheduler */
1505 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1506 struct amdgpu_ring *ring = adev->rings[i];
1507
1508 if (!ring || !ring->sched.thread)
1509 continue;
1510 kthread_unpark(ring->sched.thread);
1511 }
1512
1513 up_write(&adev->reset_domain->sem);
1514
1515 pm_runtime_mark_last_busy(dev->dev);
1516 pm_runtime_put_autosuspend(dev->dev);
1517
1518 return 0;
1519}
1520
1521static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
1522{
1523 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1524 struct drm_device *dev = adev_to_drm(adev);
1525 int r;
1526
1527 r = pm_runtime_get_sync(dev->dev);
1528 if (r < 0) {
1529 pm_runtime_put_autosuspend(dev->dev);
1530 return r;
1531 }
1532
1533 *val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
1534
1535 pm_runtime_mark_last_busy(dev->dev);
1536 pm_runtime_put_autosuspend(dev->dev);
1537
1538 return 0;
1539}
1540
1541
1542static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
1543{
1544 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1545 struct drm_device *dev = adev_to_drm(adev);
1546 int r;
1547
1548 r = pm_runtime_get_sync(dev->dev);
1549 if (r < 0) {
1550 pm_runtime_put_autosuspend(dev->dev);
1551 return r;
1552 }
1553
1554 *val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);
1555
1556 pm_runtime_mark_last_busy(dev->dev);
1557 pm_runtime_put_autosuspend(dev->dev);
1558
1559 return 0;
1560}
1561
1562static int amdgpu_debugfs_benchmark(void *data, u64 val)
1563{
1564 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1565 struct drm_device *dev = adev_to_drm(adev);
1566 int r;
1567
1568 r = pm_runtime_get_sync(dev->dev);
1569 if (r < 0) {
1570 pm_runtime_put_autosuspend(dev->dev);
1571 return r;
1572 }
1573
1574 r = amdgpu_benchmark(adev, val);
1575
1576 pm_runtime_mark_last_busy(dev->dev);
1577 pm_runtime_put_autosuspend(dev->dev);
1578
1579 return r;
1580}
1581
1582static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
1583{
1584 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1585 struct drm_device *dev = adev_to_drm(adev);
1586 struct drm_file *file;
1587 int r;
1588
1589 r = mutex_lock_interruptible(&dev->filelist_mutex);
1590 if (r)
1591 return r;
1592
1593 list_for_each_entry(file, &dev->filelist, lhead) {
1594 struct amdgpu_fpriv *fpriv = file->driver_priv;
1595 struct amdgpu_vm *vm = &fpriv->vm;
1596
1597 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1598 vm->task_info.pid, vm->task_info.process_name);
1599 r = amdgpu_bo_reserve(vm->root.bo, true);
1600 if (r)
1601 break;
1602 amdgpu_debugfs_vm_bo_info(vm, m);
1603 amdgpu_bo_unreserve(vm->root.bo);
1604 }
1605
1606 mutex_unlock(&dev->filelist_mutex);
1607
1608 return r;
1609}
1610
1611DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib);
1612DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info);
1613DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
1614 NULL, "%lld\n");
1615DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
1616 NULL, "%lld\n");
1617DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark,
1618 "%lld\n");
1619
1620static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1621 struct dma_fence **fences)
1622{
1623 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1624 uint32_t sync_seq, last_seq;
1625
1626 last_seq = atomic_read(&ring->fence_drv.last_seq);
1627 sync_seq = ring->fence_drv.sync_seq;
1628
1629 last_seq &= drv->num_fences_mask;
1630 sync_seq &= drv->num_fences_mask;
1631
1632 do {
1633 struct dma_fence *fence, **ptr;
1634
1635 ++last_seq;
1636 last_seq &= drv->num_fences_mask;
1637 ptr = &drv->fences[last_seq];
1638
1639 fence = rcu_dereference_protected(*ptr, 1);
1640 RCU_INIT_POINTER(*ptr, NULL);
1641
1642 if (!fence)
1643 continue;
1644
1645 fences[last_seq] = fence;
1646
1647 } while (last_seq != sync_seq);
1648}
1649
1650static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1651 int length)
1652{
1653 int i;
1654 struct dma_fence *fence;
1655
1656 for (i = 0; i < length; i++) {
1657 fence = fences[i];
1658 if (!fence)
1659 continue;
1660 dma_fence_signal(fence);
1661 dma_fence_put(fence);
1662 }
1663}
1664
1665static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1666{
1667 struct drm_sched_job *s_job;
1668 struct dma_fence *fence;
1669
1670 spin_lock(&sched->job_list_lock);
1671 list_for_each_entry(s_job, &sched->pending_list, list) {
1672 fence = sched->ops->run_job(s_job);
1673 dma_fence_put(fence);
1674 }
1675 spin_unlock(&sched->job_list_lock);
1676}
1677
1678static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1679{
1680 struct amdgpu_job *job;
1681 struct drm_sched_job *s_job, *tmp;
1682 uint32_t preempt_seq;
1683 struct dma_fence *fence, **ptr;
1684 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1685 struct drm_gpu_scheduler *sched = &ring->sched;
1686 bool preempted = true;
1687
1688 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1689 return;
1690
1691 preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1692 if (preempt_seq <= atomic_read(&drv->last_seq)) {
1693 preempted = false;
1694 goto no_preempt;
1695 }
1696
1697 preempt_seq &= drv->num_fences_mask;
1698 ptr = &drv->fences[preempt_seq];
1699 fence = rcu_dereference_protected(*ptr, 1);
1700
1701no_preempt:
1702 spin_lock(&sched->job_list_lock);
1703 list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
1704 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1705 /* remove job from ring_mirror_list */
1706 list_del_init(&s_job->list);
1707 sched->ops->free_job(s_job);
1708 continue;
1709 }
1710 job = to_amdgpu_job(s_job);
1711 if (preempted && (&job->hw_fence) == fence)
1712 /* mark the job as preempted */
1713 job->preemption_status |= AMDGPU_IB_PREEMPTED;
1714 }
1715 spin_unlock(&sched->job_list_lock);
1716}
1717
1718static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1719{
1720 int r, resched, length;
1721 struct amdgpu_ring *ring;
1722 struct dma_fence **fences = NULL;
1723 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1724
1725 if (val >= AMDGPU_MAX_RINGS)
1726 return -EINVAL;
1727
1728 ring = adev->rings[val];
1729
1730 if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1731 return -EINVAL;
1732
1733 /* the last preemption failed */
1734 if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1735 return -EBUSY;
1736
1737 length = ring->fence_drv.num_fences_mask + 1;
1738 fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1739 if (!fences)
1740 return -ENOMEM;
1741
1742 /* Avoid accidently unparking the sched thread during GPU reset */
1743 r = down_read_killable(&adev->reset_domain->sem);
1744 if (r)
1745 goto pro_end;
1746
1747 /* stop the scheduler */
1748 kthread_park(ring->sched.thread);
1749
1750 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1751
1752 /* preempt the IB */
1753 r = amdgpu_ring_preempt_ib(ring);
1754 if (r) {
1755 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1756 goto failure;
1757 }
1758
1759 amdgpu_fence_process(ring);
1760
1761 if (atomic_read(&ring->fence_drv.last_seq) !=
1762 ring->fence_drv.sync_seq) {
1763 DRM_INFO("ring %d was preempted\n", ring->idx);
1764
1765 amdgpu_ib_preempt_mark_partial_job(ring);
1766
1767 /* swap out the old fences */
1768 amdgpu_ib_preempt_fences_swap(ring, fences);
1769
1770 amdgpu_fence_driver_force_completion(ring);
1771
1772 /* resubmit unfinished jobs */
1773 amdgpu_ib_preempt_job_recovery(&ring->sched);
1774
1775 /* wait for jobs finished */
1776 amdgpu_fence_wait_empty(ring);
1777
1778 /* signal the old fences */
1779 amdgpu_ib_preempt_signal_fences(fences, length);
1780 }
1781
1782failure:
1783 /* restart the scheduler */
1784 kthread_unpark(ring->sched.thread);
1785
1786 up_read(&adev->reset_domain->sem);
1787
1788 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1789
1790pro_end:
1791 kfree(fences);
1792
1793 return r;
1794}
1795
1796static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1797{
1798 int ret = 0;
1799 uint32_t max_freq, min_freq;
1800 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1801
1802 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1803 return -EINVAL;
1804
1805 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1806 if (ret < 0) {
1807 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1808 return ret;
1809 }
1810
1811 ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
1812 if (ret == -EOPNOTSUPP) {
1813 ret = 0;
1814 goto out;
1815 }
1816 if (ret || val > max_freq || val < min_freq) {
1817 ret = -EINVAL;
1818 goto out;
1819 }
1820
1821 ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
1822 if (ret)
1823 ret = -EINVAL;
1824
1825out:
1826 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1827 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1828
1829 return ret;
1830}
1831
1832DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
1833 amdgpu_debugfs_ib_preempt, "%llu\n");
1834
1835DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
1836 amdgpu_debugfs_sclk_set, "%llu\n");
1837
1838static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
1839 char __user *buf, size_t size, loff_t *pos)
1840{
1841 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1842 char reg_offset[12];
1843 int i, ret, len = 0;
1844
1845 if (*pos)
1846 return 0;
1847
1848 memset(reg_offset, 0, 12);
1849 ret = down_read_killable(&adev->reset_domain->sem);
1850 if (ret)
1851 return ret;
1852
1853 for (i = 0; i < adev->num_regs; i++) {
1854 sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
1855 up_read(&adev->reset_domain->sem);
1856 if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
1857 return -EFAULT;
1858
1859 len += strlen(reg_offset);
1860 ret = down_read_killable(&adev->reset_domain->sem);
1861 if (ret)
1862 return ret;
1863 }
1864
1865 up_read(&adev->reset_domain->sem);
1866 *pos += len;
1867
1868 return len;
1869}
1870
1871static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
1872 const char __user *buf, size_t size, loff_t *pos)
1873{
1874 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1875 char reg_offset[11];
1876 uint32_t *new = NULL, *tmp = NULL;
1877 int ret, i = 0, len = 0;
1878
1879 do {
1880 memset(reg_offset, 0, 11);
1881 if (copy_from_user(reg_offset, buf + len,
1882 min(10, ((int)size-len)))) {
1883 ret = -EFAULT;
1884 goto error_free;
1885 }
1886
1887 new = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
1888 if (!new) {
1889 ret = -ENOMEM;
1890 goto error_free;
1891 }
1892 tmp = new;
1893 if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
1894 ret = -EINVAL;
1895 goto error_free;
1896 }
1897
1898 len += ret;
1899 i++;
1900 } while (len < size);
1901
1902 new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
1903 if (!new) {
1904 ret = -ENOMEM;
1905 goto error_free;
1906 }
1907 ret = down_write_killable(&adev->reset_domain->sem);
1908 if (ret)
1909 goto error_free;
1910
1911 swap(adev->reset_dump_reg_list, tmp);
1912 swap(adev->reset_dump_reg_value, new);
1913 adev->num_regs = i;
1914 up_write(&adev->reset_domain->sem);
1915 ret = size;
1916
1917error_free:
1918 if (tmp != new)
1919 kfree(tmp);
1920 kfree(new);
1921 return ret;
1922}
1923
1924static const struct file_operations amdgpu_reset_dump_register_list = {
1925 .owner = THIS_MODULE,
1926 .read = amdgpu_reset_dump_register_list_read,
1927 .write = amdgpu_reset_dump_register_list_write,
1928 .llseek = default_llseek
1929};
1930
1931int amdgpu_debugfs_init(struct amdgpu_device *adev)
1932{
1933 struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
1934 struct dentry *ent;
1935 int r, i;
1936
1937 if (!debugfs_initialized())
1938 return 0;
1939
1940 debugfs_create_x32("amdgpu_smu_debug", 0600, root,
1941 &adev->pm.smu_debug_mask);
1942
1943 ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
1944 &fops_ib_preempt);
1945 if (IS_ERR(ent)) {
1946 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1947 return PTR_ERR(ent);
1948 }
1949
1950 ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
1951 &fops_sclk_set);
1952 if (IS_ERR(ent)) {
1953 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1954 return PTR_ERR(ent);
1955 }
1956
1957 /* Register debugfs entries for amdgpu_ttm */
1958 amdgpu_ttm_debugfs_init(adev);
1959 amdgpu_debugfs_pm_init(adev);
1960 amdgpu_debugfs_sa_init(adev);
1961 amdgpu_debugfs_fence_init(adev);
1962 amdgpu_debugfs_gem_init(adev);
1963
1964 r = amdgpu_debugfs_regs_init(adev);
1965 if (r)
1966 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1967
1968 amdgpu_debugfs_firmware_init(adev);
1969 amdgpu_ta_if_debugfs_init(adev);
1970
1971#if defined(CONFIG_DRM_AMD_DC)
1972 if (adev->dc_enabled)
1973 dtn_debugfs_init(adev);
1974#endif
1975
1976 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1977 struct amdgpu_ring *ring = adev->rings[i];
1978
1979 if (!ring)
1980 continue;
1981
1982 amdgpu_debugfs_ring_init(adev, ring);
1983 }
1984
1985 for ( i = 0; i < adev->vcn.num_vcn_inst; i++) {
1986 if (!amdgpu_vcnfw_log)
1987 break;
1988
1989 if (adev->vcn.harvest_config & (1 << i))
1990 continue;
1991
1992 amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
1993 }
1994
1995 amdgpu_ras_debugfs_create_all(adev);
1996 amdgpu_rap_debugfs_init(adev);
1997 amdgpu_securedisplay_debugfs_init(adev);
1998 amdgpu_fw_attestation_debugfs_init(adev);
1999
2000 debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
2001 &amdgpu_evict_vram_fops);
2002 debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
2003 &amdgpu_evict_gtt_fops);
2004 debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
2005 &amdgpu_debugfs_test_ib_fops);
2006 debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
2007 &amdgpu_debugfs_vm_info_fops);
2008 debugfs_create_file("amdgpu_benchmark", 0200, root, adev,
2009 &amdgpu_benchmark_fops);
2010 debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
2011 &amdgpu_reset_dump_register_list);
2012
2013 adev->debugfs_vbios_blob.data = adev->bios;
2014 adev->debugfs_vbios_blob.size = adev->bios_size;
2015 debugfs_create_blob("amdgpu_vbios", 0444, root,
2016 &adev->debugfs_vbios_blob);
2017
2018 adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
2019 adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
2020 debugfs_create_blob("amdgpu_discovery", 0444, root,
2021 &adev->debugfs_discovery_blob);
2022
2023 return 0;
2024}
2025
2026#else
2027int amdgpu_debugfs_init(struct amdgpu_device *adev)
2028{
2029 return 0;
2030}
2031int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2032{
2033 return 0;
2034}
2035#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#include <linux/kthread.h>
27#include <linux/pci.h>
28#include <linux/uaccess.h>
29#include <linux/pm_runtime.h>
30#include <linux/poll.h>
31
32#include "amdgpu.h"
33#include "amdgpu_pm.h"
34#include "amdgpu_dm_debugfs.h"
35#include "amdgpu_ras.h"
36#include "amdgpu_rap.h"
37#include "amdgpu_securedisplay.h"
38#include "amdgpu_fw_attestation.h"
39
40int amdgpu_debugfs_wait_dump(struct amdgpu_device *adev)
41{
42#if defined(CONFIG_DEBUG_FS)
43 unsigned long timeout = 600 * HZ;
44 int ret;
45
46 wake_up_interruptible(&adev->autodump.gpu_hang);
47
48 ret = wait_for_completion_interruptible_timeout(&adev->autodump.dumping, timeout);
49 if (ret == 0) {
50 pr_err("autodump: timeout, move on to gpu recovery\n");
51 return -ETIMEDOUT;
52 }
53#endif
54 return 0;
55}
56
57#if defined(CONFIG_DEBUG_FS)
58
59static int amdgpu_debugfs_autodump_open(struct inode *inode, struct file *file)
60{
61 struct amdgpu_device *adev = inode->i_private;
62 int ret;
63
64 file->private_data = adev;
65
66 ret = down_read_killable(&adev->reset_sem);
67 if (ret)
68 return ret;
69
70 if (adev->autodump.dumping.done) {
71 reinit_completion(&adev->autodump.dumping);
72 ret = 0;
73 } else {
74 ret = -EBUSY;
75 }
76
77 up_read(&adev->reset_sem);
78
79 return ret;
80}
81
82static int amdgpu_debugfs_autodump_release(struct inode *inode, struct file *file)
83{
84 struct amdgpu_device *adev = file->private_data;
85
86 complete_all(&adev->autodump.dumping);
87 return 0;
88}
89
90static unsigned int amdgpu_debugfs_autodump_poll(struct file *file, struct poll_table_struct *poll_table)
91{
92 struct amdgpu_device *adev = file->private_data;
93
94 poll_wait(file, &adev->autodump.gpu_hang, poll_table);
95
96 if (amdgpu_in_reset(adev))
97 return POLLIN | POLLRDNORM | POLLWRNORM;
98
99 return 0;
100}
101
102static const struct file_operations autodump_debug_fops = {
103 .owner = THIS_MODULE,
104 .open = amdgpu_debugfs_autodump_open,
105 .poll = amdgpu_debugfs_autodump_poll,
106 .release = amdgpu_debugfs_autodump_release,
107};
108
109static void amdgpu_debugfs_autodump_init(struct amdgpu_device *adev)
110{
111 init_completion(&adev->autodump.dumping);
112 complete_all(&adev->autodump.dumping);
113 init_waitqueue_head(&adev->autodump.gpu_hang);
114
115 debugfs_create_file("amdgpu_autodump", 0600,
116 adev_to_drm(adev)->primary->debugfs_root,
117 adev, &autodump_debug_fops);
118}
119
120/**
121 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
122 *
123 * @read: True if reading
124 * @f: open file handle
125 * @buf: User buffer to write/read to
126 * @size: Number of bytes to write/read
127 * @pos: Offset to seek to
128 *
129 * This debugfs entry has special meaning on the offset being sought.
130 * Various bits have different meanings:
131 *
132 * Bit 62: Indicates a GRBM bank switch is needed
133 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
134 * zero)
135 * Bits 24..33: The SE or ME selector if needed
136 * Bits 34..43: The SH (or SA) or PIPE selector if needed
137 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
138 *
139 * Bit 23: Indicates that the PM power gating lock should be held
140 * This is necessary to read registers that might be
141 * unreliable during a power gating transistion.
142 *
143 * The lower bits are the BYTE offset of the register to read. This
144 * allows reading multiple registers in a single call and having
145 * the returned size reflect that.
146 */
147static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
148 char __user *buf, size_t size, loff_t *pos)
149{
150 struct amdgpu_device *adev = file_inode(f)->i_private;
151 ssize_t result = 0;
152 int r;
153 bool pm_pg_lock, use_bank, use_ring;
154 unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
155
156 pm_pg_lock = use_bank = use_ring = false;
157 instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
158
159 if (size & 0x3 || *pos & 0x3 ||
160 ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
161 return -EINVAL;
162
163 /* are we reading registers for which a PG lock is necessary? */
164 pm_pg_lock = (*pos >> 23) & 1;
165
166 if (*pos & (1ULL << 62)) {
167 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
168 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
169 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
170
171 if (se_bank == 0x3FF)
172 se_bank = 0xFFFFFFFF;
173 if (sh_bank == 0x3FF)
174 sh_bank = 0xFFFFFFFF;
175 if (instance_bank == 0x3FF)
176 instance_bank = 0xFFFFFFFF;
177 use_bank = true;
178 } else if (*pos & (1ULL << 61)) {
179
180 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
181 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
182 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
183 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
184
185 use_ring = true;
186 } else {
187 use_bank = use_ring = false;
188 }
189
190 *pos &= (1UL << 22) - 1;
191
192 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
193 if (r < 0) {
194 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
195 return r;
196 }
197
198 r = amdgpu_virt_enable_access_debugfs(adev);
199 if (r < 0) {
200 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
201 return r;
202 }
203
204 if (use_bank) {
205 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
206 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
207 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
208 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
209 amdgpu_virt_disable_access_debugfs(adev);
210 return -EINVAL;
211 }
212 mutex_lock(&adev->grbm_idx_mutex);
213 amdgpu_gfx_select_se_sh(adev, se_bank,
214 sh_bank, instance_bank);
215 } else if (use_ring) {
216 mutex_lock(&adev->srbm_mutex);
217 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
218 }
219
220 if (pm_pg_lock)
221 mutex_lock(&adev->pm.mutex);
222
223 while (size) {
224 uint32_t value;
225
226 if (read) {
227 value = RREG32(*pos >> 2);
228 r = put_user(value, (uint32_t *)buf);
229 } else {
230 r = get_user(value, (uint32_t *)buf);
231 if (!r)
232 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
233 }
234 if (r) {
235 result = r;
236 goto end;
237 }
238
239 result += 4;
240 buf += 4;
241 *pos += 4;
242 size -= 4;
243 }
244
245end:
246 if (use_bank) {
247 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
248 mutex_unlock(&adev->grbm_idx_mutex);
249 } else if (use_ring) {
250 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
251 mutex_unlock(&adev->srbm_mutex);
252 }
253
254 if (pm_pg_lock)
255 mutex_unlock(&adev->pm.mutex);
256
257 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
258 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
259
260 amdgpu_virt_disable_access_debugfs(adev);
261 return result;
262}
263
264/*
265 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
266 */
267static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
268 size_t size, loff_t *pos)
269{
270 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
271}
272
273/*
274 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
275 */
276static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
277 size_t size, loff_t *pos)
278{
279 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
280}
281
282
283/**
284 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
285 *
286 * @f: open file handle
287 * @buf: User buffer to store read data in
288 * @size: Number of bytes to read
289 * @pos: Offset to seek to
290 *
291 * The lower bits are the BYTE offset of the register to read. This
292 * allows reading multiple registers in a single call and having
293 * the returned size reflect that.
294 */
295static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
296 size_t size, loff_t *pos)
297{
298 struct amdgpu_device *adev = file_inode(f)->i_private;
299 ssize_t result = 0;
300 int r;
301
302 if (size & 0x3 || *pos & 0x3)
303 return -EINVAL;
304
305 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
306 if (r < 0) {
307 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
308 return r;
309 }
310
311 r = amdgpu_virt_enable_access_debugfs(adev);
312 if (r < 0) {
313 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
314 return r;
315 }
316
317 while (size) {
318 uint32_t value;
319
320 value = RREG32_PCIE(*pos);
321 r = put_user(value, (uint32_t *)buf);
322 if (r) {
323 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
324 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
325 amdgpu_virt_disable_access_debugfs(adev);
326 return r;
327 }
328
329 result += 4;
330 buf += 4;
331 *pos += 4;
332 size -= 4;
333 }
334
335 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
336 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
337
338 amdgpu_virt_disable_access_debugfs(adev);
339 return result;
340}
341
342/**
343 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
344 *
345 * @f: open file handle
346 * @buf: User buffer to write data from
347 * @size: Number of bytes to write
348 * @pos: Offset to seek to
349 *
350 * The lower bits are the BYTE offset of the register to write. This
351 * allows writing multiple registers in a single call and having
352 * the returned size reflect that.
353 */
354static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
355 size_t size, loff_t *pos)
356{
357 struct amdgpu_device *adev = file_inode(f)->i_private;
358 ssize_t result = 0;
359 int r;
360
361 if (size & 0x3 || *pos & 0x3)
362 return -EINVAL;
363
364 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
365 if (r < 0) {
366 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
367 return r;
368 }
369
370 r = amdgpu_virt_enable_access_debugfs(adev);
371 if (r < 0) {
372 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
373 return r;
374 }
375
376 while (size) {
377 uint32_t value;
378
379 r = get_user(value, (uint32_t *)buf);
380 if (r) {
381 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
382 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
383 amdgpu_virt_disable_access_debugfs(adev);
384 return r;
385 }
386
387 WREG32_PCIE(*pos, value);
388
389 result += 4;
390 buf += 4;
391 *pos += 4;
392 size -= 4;
393 }
394
395 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
396 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
397
398 amdgpu_virt_disable_access_debugfs(adev);
399 return result;
400}
401
402/**
403 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
404 *
405 * @f: open file handle
406 * @buf: User buffer to store read data in
407 * @size: Number of bytes to read
408 * @pos: Offset to seek to
409 *
410 * The lower bits are the BYTE offset of the register to read. This
411 * allows reading multiple registers in a single call and having
412 * the returned size reflect that.
413 */
414static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
415 size_t size, loff_t *pos)
416{
417 struct amdgpu_device *adev = file_inode(f)->i_private;
418 ssize_t result = 0;
419 int r;
420
421 if (size & 0x3 || *pos & 0x3)
422 return -EINVAL;
423
424 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
425 if (r < 0) {
426 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
427 return r;
428 }
429
430 r = amdgpu_virt_enable_access_debugfs(adev);
431 if (r < 0) {
432 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
433 return r;
434 }
435
436 while (size) {
437 uint32_t value;
438
439 value = RREG32_DIDT(*pos >> 2);
440 r = put_user(value, (uint32_t *)buf);
441 if (r) {
442 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
443 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
444 amdgpu_virt_disable_access_debugfs(adev);
445 return r;
446 }
447
448 result += 4;
449 buf += 4;
450 *pos += 4;
451 size -= 4;
452 }
453
454 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
455 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
456
457 amdgpu_virt_disable_access_debugfs(adev);
458 return result;
459}
460
461/**
462 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
463 *
464 * @f: open file handle
465 * @buf: User buffer to write data from
466 * @size: Number of bytes to write
467 * @pos: Offset to seek to
468 *
469 * The lower bits are the BYTE offset of the register to write. This
470 * allows writing multiple registers in a single call and having
471 * the returned size reflect that.
472 */
473static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
474 size_t size, loff_t *pos)
475{
476 struct amdgpu_device *adev = file_inode(f)->i_private;
477 ssize_t result = 0;
478 int r;
479
480 if (size & 0x3 || *pos & 0x3)
481 return -EINVAL;
482
483 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
484 if (r < 0) {
485 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
486 return r;
487 }
488
489 r = amdgpu_virt_enable_access_debugfs(adev);
490 if (r < 0) {
491 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
492 return r;
493 }
494
495 while (size) {
496 uint32_t value;
497
498 r = get_user(value, (uint32_t *)buf);
499 if (r) {
500 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
501 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
502 amdgpu_virt_disable_access_debugfs(adev);
503 return r;
504 }
505
506 WREG32_DIDT(*pos >> 2, value);
507
508 result += 4;
509 buf += 4;
510 *pos += 4;
511 size -= 4;
512 }
513
514 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
515 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
516
517 amdgpu_virt_disable_access_debugfs(adev);
518 return result;
519}
520
521/**
522 * amdgpu_debugfs_regs_smc_read - Read from a SMC register
523 *
524 * @f: open file handle
525 * @buf: User buffer to store read data in
526 * @size: Number of bytes to read
527 * @pos: Offset to seek to
528 *
529 * The lower bits are the BYTE offset of the register to read. This
530 * allows reading multiple registers in a single call and having
531 * the returned size reflect that.
532 */
533static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
534 size_t size, loff_t *pos)
535{
536 struct amdgpu_device *adev = file_inode(f)->i_private;
537 ssize_t result = 0;
538 int r;
539
540 if (size & 0x3 || *pos & 0x3)
541 return -EINVAL;
542
543 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
544 if (r < 0) {
545 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
546 return r;
547 }
548
549 r = amdgpu_virt_enable_access_debugfs(adev);
550 if (r < 0) {
551 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
552 return r;
553 }
554
555 while (size) {
556 uint32_t value;
557
558 value = RREG32_SMC(*pos);
559 r = put_user(value, (uint32_t *)buf);
560 if (r) {
561 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
562 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
563 amdgpu_virt_disable_access_debugfs(adev);
564 return r;
565 }
566
567 result += 4;
568 buf += 4;
569 *pos += 4;
570 size -= 4;
571 }
572
573 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
574 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
575
576 amdgpu_virt_disable_access_debugfs(adev);
577 return result;
578}
579
580/**
581 * amdgpu_debugfs_regs_smc_write - Write to a SMC register
582 *
583 * @f: open file handle
584 * @buf: User buffer to write data from
585 * @size: Number of bytes to write
586 * @pos: Offset to seek to
587 *
588 * The lower bits are the BYTE offset of the register to write. This
589 * allows writing multiple registers in a single call and having
590 * the returned size reflect that.
591 */
592static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
593 size_t size, loff_t *pos)
594{
595 struct amdgpu_device *adev = file_inode(f)->i_private;
596 ssize_t result = 0;
597 int r;
598
599 if (size & 0x3 || *pos & 0x3)
600 return -EINVAL;
601
602 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
603 if (r < 0) {
604 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
605 return r;
606 }
607
608 r = amdgpu_virt_enable_access_debugfs(adev);
609 if (r < 0) {
610 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
611 return r;
612 }
613
614 while (size) {
615 uint32_t value;
616
617 r = get_user(value, (uint32_t *)buf);
618 if (r) {
619 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
620 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
621 amdgpu_virt_disable_access_debugfs(adev);
622 return r;
623 }
624
625 WREG32_SMC(*pos, value);
626
627 result += 4;
628 buf += 4;
629 *pos += 4;
630 size -= 4;
631 }
632
633 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
634 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
635
636 amdgpu_virt_disable_access_debugfs(adev);
637 return result;
638}
639
640/**
641 * amdgpu_debugfs_gca_config_read - Read from gfx config data
642 *
643 * @f: open file handle
644 * @buf: User buffer to store read data in
645 * @size: Number of bytes to read
646 * @pos: Offset to seek to
647 *
648 * This file is used to access configuration data in a somewhat
649 * stable fashion. The format is a series of DWORDs with the first
650 * indicating which revision it is. New content is appended to the
651 * end so that older software can still read the data.
652 */
653
654static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
655 size_t size, loff_t *pos)
656{
657 struct amdgpu_device *adev = file_inode(f)->i_private;
658 ssize_t result = 0;
659 int r;
660 uint32_t *config, no_regs = 0;
661
662 if (size & 0x3 || *pos & 0x3)
663 return -EINVAL;
664
665 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
666 if (!config)
667 return -ENOMEM;
668
669 /* version, increment each time something is added */
670 config[no_regs++] = 3;
671 config[no_regs++] = adev->gfx.config.max_shader_engines;
672 config[no_regs++] = adev->gfx.config.max_tile_pipes;
673 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
674 config[no_regs++] = adev->gfx.config.max_sh_per_se;
675 config[no_regs++] = adev->gfx.config.max_backends_per_se;
676 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
677 config[no_regs++] = adev->gfx.config.max_gprs;
678 config[no_regs++] = adev->gfx.config.max_gs_threads;
679 config[no_regs++] = adev->gfx.config.max_hw_contexts;
680 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
681 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
682 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
683 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
684 config[no_regs++] = adev->gfx.config.num_tile_pipes;
685 config[no_regs++] = adev->gfx.config.backend_enable_mask;
686 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
687 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
688 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
689 config[no_regs++] = adev->gfx.config.num_gpus;
690 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
691 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
692 config[no_regs++] = adev->gfx.config.gb_addr_config;
693 config[no_regs++] = adev->gfx.config.num_rbs;
694
695 /* rev==1 */
696 config[no_regs++] = adev->rev_id;
697 config[no_regs++] = adev->pg_flags;
698 config[no_regs++] = adev->cg_flags;
699
700 /* rev==2 */
701 config[no_regs++] = adev->family;
702 config[no_regs++] = adev->external_rev_id;
703
704 /* rev==3 */
705 config[no_regs++] = adev->pdev->device;
706 config[no_regs++] = adev->pdev->revision;
707 config[no_regs++] = adev->pdev->subsystem_device;
708 config[no_regs++] = adev->pdev->subsystem_vendor;
709
710 while (size && (*pos < no_regs * 4)) {
711 uint32_t value;
712
713 value = config[*pos >> 2];
714 r = put_user(value, (uint32_t *)buf);
715 if (r) {
716 kfree(config);
717 return r;
718 }
719
720 result += 4;
721 buf += 4;
722 *pos += 4;
723 size -= 4;
724 }
725
726 kfree(config);
727 return result;
728}
729
730/**
731 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
732 *
733 * @f: open file handle
734 * @buf: User buffer to store read data in
735 * @size: Number of bytes to read
736 * @pos: Offset to seek to
737 *
738 * The offset is treated as the BYTE address of one of the sensors
739 * enumerated in amd/include/kgd_pp_interface.h under the
740 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
741 * you would use the offset 3 * 4 = 12.
742 */
743static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
744 size_t size, loff_t *pos)
745{
746 struct amdgpu_device *adev = file_inode(f)->i_private;
747 int idx, x, outsize, r, valuesize;
748 uint32_t values[16];
749
750 if (size & 3 || *pos & 0x3)
751 return -EINVAL;
752
753 if (!adev->pm.dpm_enabled)
754 return -EINVAL;
755
756 /* convert offset to sensor number */
757 idx = *pos >> 2;
758
759 valuesize = sizeof(values);
760
761 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
762 if (r < 0) {
763 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
764 return r;
765 }
766
767 r = amdgpu_virt_enable_access_debugfs(adev);
768 if (r < 0) {
769 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
770 return r;
771 }
772
773 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
774
775 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
776 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
777
778 if (r) {
779 amdgpu_virt_disable_access_debugfs(adev);
780 return r;
781 }
782
783 if (size > valuesize) {
784 amdgpu_virt_disable_access_debugfs(adev);
785 return -EINVAL;
786 }
787
788 outsize = 0;
789 x = 0;
790 if (!r) {
791 while (size) {
792 r = put_user(values[x++], (int32_t *)buf);
793 buf += 4;
794 size -= 4;
795 outsize += 4;
796 }
797 }
798
799 amdgpu_virt_disable_access_debugfs(adev);
800 return !r ? outsize : r;
801}
802
803/** amdgpu_debugfs_wave_read - Read WAVE STATUS data
804 *
805 * @f: open file handle
806 * @buf: User buffer to store read data in
807 * @size: Number of bytes to read
808 * @pos: Offset to seek to
809 *
810 * The offset being sought changes which wave that the status data
811 * will be returned for. The bits are used as follows:
812 *
813 * Bits 0..6: Byte offset into data
814 * Bits 7..14: SE selector
815 * Bits 15..22: SH/SA selector
816 * Bits 23..30: CU/{WGP+SIMD} selector
817 * Bits 31..36: WAVE ID selector
818 * Bits 37..44: SIMD ID selector
819 *
820 * The returned data begins with one DWORD of version information
821 * Followed by WAVE STATUS registers relevant to the GFX IP version
822 * being used. See gfx_v8_0_read_wave_data() for an example output.
823 */
824static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
825 size_t size, loff_t *pos)
826{
827 struct amdgpu_device *adev = f->f_inode->i_private;
828 int r, x;
829 ssize_t result = 0;
830 uint32_t offset, se, sh, cu, wave, simd, data[32];
831
832 if (size & 3 || *pos & 3)
833 return -EINVAL;
834
835 /* decode offset */
836 offset = (*pos & GENMASK_ULL(6, 0));
837 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
838 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
839 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
840 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
841 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
842
843 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
844 if (r < 0) {
845 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
846 return r;
847 }
848
849 r = amdgpu_virt_enable_access_debugfs(adev);
850 if (r < 0) {
851 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
852 return r;
853 }
854
855 /* switch to the specific se/sh/cu */
856 mutex_lock(&adev->grbm_idx_mutex);
857 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
858
859 x = 0;
860 if (adev->gfx.funcs->read_wave_data)
861 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
862
863 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
864 mutex_unlock(&adev->grbm_idx_mutex);
865
866 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
867 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
868
869 if (!x) {
870 amdgpu_virt_disable_access_debugfs(adev);
871 return -EINVAL;
872 }
873
874 while (size && (offset < x * 4)) {
875 uint32_t value;
876
877 value = data[offset >> 2];
878 r = put_user(value, (uint32_t *)buf);
879 if (r) {
880 amdgpu_virt_disable_access_debugfs(adev);
881 return r;
882 }
883
884 result += 4;
885 buf += 4;
886 offset += 4;
887 size -= 4;
888 }
889
890 amdgpu_virt_disable_access_debugfs(adev);
891 return result;
892}
893
894/** amdgpu_debugfs_gpr_read - Read wave gprs
895 *
896 * @f: open file handle
897 * @buf: User buffer to store read data in
898 * @size: Number of bytes to read
899 * @pos: Offset to seek to
900 *
901 * The offset being sought changes which wave that the status data
902 * will be returned for. The bits are used as follows:
903 *
904 * Bits 0..11: Byte offset into data
905 * Bits 12..19: SE selector
906 * Bits 20..27: SH/SA selector
907 * Bits 28..35: CU/{WGP+SIMD} selector
908 * Bits 36..43: WAVE ID selector
909 * Bits 37..44: SIMD ID selector
910 * Bits 52..59: Thread selector
911 * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
912 *
913 * The return data comes from the SGPR or VGPR register bank for
914 * the selected operational unit.
915 */
916static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
917 size_t size, loff_t *pos)
918{
919 struct amdgpu_device *adev = f->f_inode->i_private;
920 int r;
921 ssize_t result = 0;
922 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
923
924 if (size > 4096 || size & 3 || *pos & 3)
925 return -EINVAL;
926
927 /* decode offset */
928 offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
929 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
930 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
931 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
932 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
933 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
934 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
935 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
936
937 data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
938 if (!data)
939 return -ENOMEM;
940
941 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
942 if (r < 0)
943 goto err;
944
945 r = amdgpu_virt_enable_access_debugfs(adev);
946 if (r < 0)
947 goto err;
948
949 /* switch to the specific se/sh/cu */
950 mutex_lock(&adev->grbm_idx_mutex);
951 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
952
953 if (bank == 0) {
954 if (adev->gfx.funcs->read_wave_vgprs)
955 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
956 } else {
957 if (adev->gfx.funcs->read_wave_sgprs)
958 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
959 }
960
961 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
962 mutex_unlock(&adev->grbm_idx_mutex);
963
964 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
965 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
966
967 while (size) {
968 uint32_t value;
969
970 value = data[result >> 2];
971 r = put_user(value, (uint32_t *)buf);
972 if (r) {
973 amdgpu_virt_disable_access_debugfs(adev);
974 goto err;
975 }
976
977 result += 4;
978 buf += 4;
979 size -= 4;
980 }
981
982 kfree(data);
983 amdgpu_virt_disable_access_debugfs(adev);
984 return result;
985
986err:
987 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
988 kfree(data);
989 return r;
990}
991
992/**
993 * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
994 *
995 * @f: open file handle
996 * @buf: User buffer to write data from
997 * @size: Number of bytes to write
998 * @pos: Offset to seek to
999 *
1000 * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1001 */
1002static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1003 size_t size, loff_t *pos)
1004{
1005 struct amdgpu_device *adev = file_inode(f)->i_private;
1006 ssize_t result = 0;
1007 int r;
1008
1009 if (size & 0x3 || *pos & 0x3)
1010 return -EINVAL;
1011
1012 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1013 if (r < 0) {
1014 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1015 return r;
1016 }
1017
1018 while (size) {
1019 uint32_t value;
1020
1021 r = get_user(value, (uint32_t *)buf);
1022 if (r) {
1023 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1024 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1025 return r;
1026 }
1027
1028 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1029
1030 result += 4;
1031 buf += 4;
1032 *pos += 4;
1033 size -= 4;
1034 }
1035
1036 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1037 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1038
1039 return result;
1040}
1041
1042
1043/**
1044 * amdgpu_debugfs_gfxoff_read - read gfxoff status
1045 *
1046 * @f: open file handle
1047 * @buf: User buffer to store read data in
1048 * @size: Number of bytes to read
1049 * @pos: Offset to seek to
1050 */
1051static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1052 size_t size, loff_t *pos)
1053{
1054 struct amdgpu_device *adev = file_inode(f)->i_private;
1055 ssize_t result = 0;
1056 int r;
1057
1058 if (size & 0x3 || *pos & 0x3)
1059 return -EINVAL;
1060
1061 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1062 if (r < 0)
1063 return r;
1064
1065 while (size) {
1066 uint32_t value;
1067
1068 r = amdgpu_get_gfx_off_status(adev, &value);
1069 if (r) {
1070 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1071 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1072 return r;
1073 }
1074
1075 r = put_user(value, (uint32_t *)buf);
1076 if (r) {
1077 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1078 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1079 return r;
1080 }
1081
1082 result += 4;
1083 buf += 4;
1084 *pos += 4;
1085 size -= 4;
1086 }
1087
1088 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1089 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1090
1091 return result;
1092}
1093
1094static const struct file_operations amdgpu_debugfs_regs_fops = {
1095 .owner = THIS_MODULE,
1096 .read = amdgpu_debugfs_regs_read,
1097 .write = amdgpu_debugfs_regs_write,
1098 .llseek = default_llseek
1099};
1100static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1101 .owner = THIS_MODULE,
1102 .read = amdgpu_debugfs_regs_didt_read,
1103 .write = amdgpu_debugfs_regs_didt_write,
1104 .llseek = default_llseek
1105};
1106static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1107 .owner = THIS_MODULE,
1108 .read = amdgpu_debugfs_regs_pcie_read,
1109 .write = amdgpu_debugfs_regs_pcie_write,
1110 .llseek = default_llseek
1111};
1112static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1113 .owner = THIS_MODULE,
1114 .read = amdgpu_debugfs_regs_smc_read,
1115 .write = amdgpu_debugfs_regs_smc_write,
1116 .llseek = default_llseek
1117};
1118
1119static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1120 .owner = THIS_MODULE,
1121 .read = amdgpu_debugfs_gca_config_read,
1122 .llseek = default_llseek
1123};
1124
1125static const struct file_operations amdgpu_debugfs_sensors_fops = {
1126 .owner = THIS_MODULE,
1127 .read = amdgpu_debugfs_sensor_read,
1128 .llseek = default_llseek
1129};
1130
1131static const struct file_operations amdgpu_debugfs_wave_fops = {
1132 .owner = THIS_MODULE,
1133 .read = amdgpu_debugfs_wave_read,
1134 .llseek = default_llseek
1135};
1136static const struct file_operations amdgpu_debugfs_gpr_fops = {
1137 .owner = THIS_MODULE,
1138 .read = amdgpu_debugfs_gpr_read,
1139 .llseek = default_llseek
1140};
1141
1142static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1143 .owner = THIS_MODULE,
1144 .read = amdgpu_debugfs_gfxoff_read,
1145 .write = amdgpu_debugfs_gfxoff_write,
1146 .llseek = default_llseek
1147};
1148
1149static const struct file_operations *debugfs_regs[] = {
1150 &amdgpu_debugfs_regs_fops,
1151 &amdgpu_debugfs_regs_didt_fops,
1152 &amdgpu_debugfs_regs_pcie_fops,
1153 &amdgpu_debugfs_regs_smc_fops,
1154 &amdgpu_debugfs_gca_config_fops,
1155 &amdgpu_debugfs_sensors_fops,
1156 &amdgpu_debugfs_wave_fops,
1157 &amdgpu_debugfs_gpr_fops,
1158 &amdgpu_debugfs_gfxoff_fops,
1159};
1160
1161static const char *debugfs_regs_names[] = {
1162 "amdgpu_regs",
1163 "amdgpu_regs_didt",
1164 "amdgpu_regs_pcie",
1165 "amdgpu_regs_smc",
1166 "amdgpu_gca_config",
1167 "amdgpu_sensors",
1168 "amdgpu_wave",
1169 "amdgpu_gpr",
1170 "amdgpu_gfxoff",
1171};
1172
1173/**
1174 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
1175 * register access.
1176 *
1177 * @adev: The device to attach the debugfs entries to
1178 */
1179int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1180{
1181 struct drm_minor *minor = adev_to_drm(adev)->primary;
1182 struct dentry *ent, *root = minor->debugfs_root;
1183 unsigned int i;
1184
1185 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1186 ent = debugfs_create_file(debugfs_regs_names[i],
1187 S_IFREG | S_IRUGO, root,
1188 adev, debugfs_regs[i]);
1189 if (!i && !IS_ERR_OR_NULL(ent))
1190 i_size_write(ent->d_inode, adev->rmmio_size);
1191 }
1192
1193 return 0;
1194}
1195
1196static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)
1197{
1198 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1199 struct drm_device *dev = adev_to_drm(adev);
1200 int r = 0, i;
1201
1202 r = pm_runtime_get_sync(dev->dev);
1203 if (r < 0) {
1204 pm_runtime_put_autosuspend(dev->dev);
1205 return r;
1206 }
1207
1208 /* Avoid accidently unparking the sched thread during GPU reset */
1209 r = down_read_killable(&adev->reset_sem);
1210 if (r)
1211 return r;
1212
1213 /* hold on the scheduler */
1214 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1215 struct amdgpu_ring *ring = adev->rings[i];
1216
1217 if (!ring || !ring->sched.thread)
1218 continue;
1219 kthread_park(ring->sched.thread);
1220 }
1221
1222 seq_printf(m, "run ib test:\n");
1223 r = amdgpu_ib_ring_tests(adev);
1224 if (r)
1225 seq_printf(m, "ib ring tests failed (%d).\n", r);
1226 else
1227 seq_printf(m, "ib ring tests passed.\n");
1228
1229 /* go on the scheduler */
1230 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1231 struct amdgpu_ring *ring = adev->rings[i];
1232
1233 if (!ring || !ring->sched.thread)
1234 continue;
1235 kthread_unpark(ring->sched.thread);
1236 }
1237
1238 up_read(&adev->reset_sem);
1239
1240 pm_runtime_mark_last_busy(dev->dev);
1241 pm_runtime_put_autosuspend(dev->dev);
1242
1243 return 0;
1244}
1245
1246static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
1247{
1248 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1249 struct drm_device *dev = adev_to_drm(adev);
1250 int r;
1251
1252 r = pm_runtime_get_sync(dev->dev);
1253 if (r < 0) {
1254 pm_runtime_put_autosuspend(dev->dev);
1255 return r;
1256 }
1257
1258 *val = amdgpu_bo_evict_vram(adev);
1259
1260 pm_runtime_mark_last_busy(dev->dev);
1261 pm_runtime_put_autosuspend(dev->dev);
1262
1263 return 0;
1264}
1265
1266
1267static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
1268{
1269 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1270 struct drm_device *dev = adev_to_drm(adev);
1271 struct ttm_resource_manager *man;
1272 int r;
1273
1274 r = pm_runtime_get_sync(dev->dev);
1275 if (r < 0) {
1276 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1277 return r;
1278 }
1279
1280 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
1281 *val = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
1282
1283 pm_runtime_mark_last_busy(dev->dev);
1284 pm_runtime_put_autosuspend(dev->dev);
1285
1286 return 0;
1287}
1288
1289
1290static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
1291{
1292 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1293 struct drm_device *dev = adev_to_drm(adev);
1294 struct drm_file *file;
1295 int r;
1296
1297 r = mutex_lock_interruptible(&dev->filelist_mutex);
1298 if (r)
1299 return r;
1300
1301 list_for_each_entry(file, &dev->filelist, lhead) {
1302 struct amdgpu_fpriv *fpriv = file->driver_priv;
1303 struct amdgpu_vm *vm = &fpriv->vm;
1304
1305 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1306 vm->task_info.pid, vm->task_info.process_name);
1307 r = amdgpu_bo_reserve(vm->root.bo, true);
1308 if (r)
1309 break;
1310 amdgpu_debugfs_vm_bo_info(vm, m);
1311 amdgpu_bo_unreserve(vm->root.bo);
1312 }
1313
1314 mutex_unlock(&dev->filelist_mutex);
1315
1316 return r;
1317}
1318
1319DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib);
1320DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info);
1321DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
1322 NULL, "%lld\n");
1323DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
1324 NULL, "%lld\n");
1325
1326static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1327 struct dma_fence **fences)
1328{
1329 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1330 uint32_t sync_seq, last_seq;
1331
1332 last_seq = atomic_read(&ring->fence_drv.last_seq);
1333 sync_seq = ring->fence_drv.sync_seq;
1334
1335 last_seq &= drv->num_fences_mask;
1336 sync_seq &= drv->num_fences_mask;
1337
1338 do {
1339 struct dma_fence *fence, **ptr;
1340
1341 ++last_seq;
1342 last_seq &= drv->num_fences_mask;
1343 ptr = &drv->fences[last_seq];
1344
1345 fence = rcu_dereference_protected(*ptr, 1);
1346 RCU_INIT_POINTER(*ptr, NULL);
1347
1348 if (!fence)
1349 continue;
1350
1351 fences[last_seq] = fence;
1352
1353 } while (last_seq != sync_seq);
1354}
1355
1356static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1357 int length)
1358{
1359 int i;
1360 struct dma_fence *fence;
1361
1362 for (i = 0; i < length; i++) {
1363 fence = fences[i];
1364 if (!fence)
1365 continue;
1366 dma_fence_signal(fence);
1367 dma_fence_put(fence);
1368 }
1369}
1370
1371static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1372{
1373 struct drm_sched_job *s_job;
1374 struct dma_fence *fence;
1375
1376 spin_lock(&sched->job_list_lock);
1377 list_for_each_entry(s_job, &sched->pending_list, list) {
1378 fence = sched->ops->run_job(s_job);
1379 dma_fence_put(fence);
1380 }
1381 spin_unlock(&sched->job_list_lock);
1382}
1383
1384static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1385{
1386 struct amdgpu_job *job;
1387 struct drm_sched_job *s_job, *tmp;
1388 uint32_t preempt_seq;
1389 struct dma_fence *fence, **ptr;
1390 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1391 struct drm_gpu_scheduler *sched = &ring->sched;
1392 bool preempted = true;
1393
1394 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1395 return;
1396
1397 preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1398 if (preempt_seq <= atomic_read(&drv->last_seq)) {
1399 preempted = false;
1400 goto no_preempt;
1401 }
1402
1403 preempt_seq &= drv->num_fences_mask;
1404 ptr = &drv->fences[preempt_seq];
1405 fence = rcu_dereference_protected(*ptr, 1);
1406
1407no_preempt:
1408 spin_lock(&sched->job_list_lock);
1409 list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
1410 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1411 /* remove job from ring_mirror_list */
1412 list_del_init(&s_job->list);
1413 sched->ops->free_job(s_job);
1414 continue;
1415 }
1416 job = to_amdgpu_job(s_job);
1417 if (preempted && job->fence == fence)
1418 /* mark the job as preempted */
1419 job->preemption_status |= AMDGPU_IB_PREEMPTED;
1420 }
1421 spin_unlock(&sched->job_list_lock);
1422}
1423
1424static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1425{
1426 int r, resched, length;
1427 struct amdgpu_ring *ring;
1428 struct dma_fence **fences = NULL;
1429 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1430
1431 if (val >= AMDGPU_MAX_RINGS)
1432 return -EINVAL;
1433
1434 ring = adev->rings[val];
1435
1436 if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1437 return -EINVAL;
1438
1439 /* the last preemption failed */
1440 if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1441 return -EBUSY;
1442
1443 length = ring->fence_drv.num_fences_mask + 1;
1444 fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1445 if (!fences)
1446 return -ENOMEM;
1447
1448 /* Avoid accidently unparking the sched thread during GPU reset */
1449 r = down_read_killable(&adev->reset_sem);
1450 if (r)
1451 goto pro_end;
1452
1453 /* stop the scheduler */
1454 kthread_park(ring->sched.thread);
1455
1456 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1457
1458 /* preempt the IB */
1459 r = amdgpu_ring_preempt_ib(ring);
1460 if (r) {
1461 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1462 goto failure;
1463 }
1464
1465 amdgpu_fence_process(ring);
1466
1467 if (atomic_read(&ring->fence_drv.last_seq) !=
1468 ring->fence_drv.sync_seq) {
1469 DRM_INFO("ring %d was preempted\n", ring->idx);
1470
1471 amdgpu_ib_preempt_mark_partial_job(ring);
1472
1473 /* swap out the old fences */
1474 amdgpu_ib_preempt_fences_swap(ring, fences);
1475
1476 amdgpu_fence_driver_force_completion(ring);
1477
1478 /* resubmit unfinished jobs */
1479 amdgpu_ib_preempt_job_recovery(&ring->sched);
1480
1481 /* wait for jobs finished */
1482 amdgpu_fence_wait_empty(ring);
1483
1484 /* signal the old fences */
1485 amdgpu_ib_preempt_signal_fences(fences, length);
1486 }
1487
1488failure:
1489 /* restart the scheduler */
1490 kthread_unpark(ring->sched.thread);
1491
1492 up_read(&adev->reset_sem);
1493
1494 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1495
1496pro_end:
1497 kfree(fences);
1498
1499 return r;
1500}
1501
1502static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1503{
1504 int ret = 0;
1505 uint32_t max_freq, min_freq;
1506 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1507
1508 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1509 return -EINVAL;
1510
1511 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1512 if (ret < 0) {
1513 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1514 return ret;
1515 }
1516
1517 if (is_support_sw_smu(adev)) {
1518 ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq);
1519 if (ret || val > max_freq || val < min_freq)
1520 return -EINVAL;
1521 ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val);
1522 } else {
1523 return 0;
1524 }
1525
1526 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1527 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1528
1529 if (ret)
1530 return -EINVAL;
1531
1532 return 0;
1533}
1534
1535DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
1536 amdgpu_debugfs_ib_preempt, "%llu\n");
1537
1538DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
1539 amdgpu_debugfs_sclk_set, "%llu\n");
1540
1541int amdgpu_debugfs_init(struct amdgpu_device *adev)
1542{
1543 struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
1544 struct dentry *ent;
1545 int r, i;
1546
1547 ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
1548 &fops_ib_preempt);
1549 if (IS_ERR(ent)) {
1550 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1551 return PTR_ERR(ent);
1552 }
1553
1554 ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
1555 &fops_sclk_set);
1556 if (IS_ERR(ent)) {
1557 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1558 return PTR_ERR(ent);
1559 }
1560
1561 /* Register debugfs entries for amdgpu_ttm */
1562 amdgpu_ttm_debugfs_init(adev);
1563 amdgpu_debugfs_pm_init(adev);
1564 amdgpu_debugfs_sa_init(adev);
1565 amdgpu_debugfs_fence_init(adev);
1566 amdgpu_debugfs_gem_init(adev);
1567
1568 r = amdgpu_debugfs_regs_init(adev);
1569 if (r)
1570 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1571
1572 amdgpu_debugfs_firmware_init(adev);
1573
1574#if defined(CONFIG_DRM_AMD_DC)
1575 if (amdgpu_device_has_dc_support(adev))
1576 dtn_debugfs_init(adev);
1577#endif
1578
1579 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1580 struct amdgpu_ring *ring = adev->rings[i];
1581
1582 if (!ring)
1583 continue;
1584
1585 if (amdgpu_debugfs_ring_init(adev, ring)) {
1586 DRM_ERROR("Failed to register debugfs file for rings !\n");
1587 }
1588 }
1589
1590 amdgpu_ras_debugfs_create_all(adev);
1591 amdgpu_debugfs_autodump_init(adev);
1592 amdgpu_rap_debugfs_init(adev);
1593 amdgpu_securedisplay_debugfs_init(adev);
1594 amdgpu_fw_attestation_debugfs_init(adev);
1595
1596 debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
1597 &amdgpu_evict_vram_fops);
1598 debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
1599 &amdgpu_evict_gtt_fops);
1600 debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
1601 &amdgpu_debugfs_test_ib_fops);
1602 debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
1603 &amdgpu_debugfs_vm_info_fops);
1604
1605 adev->debugfs_vbios_blob.data = adev->bios;
1606 adev->debugfs_vbios_blob.size = adev->bios_size;
1607 debugfs_create_blob("amdgpu_vbios", 0444, root,
1608 &adev->debugfs_vbios_blob);
1609
1610 return 0;
1611}
1612
1613#else
1614int amdgpu_debugfs_init(struct amdgpu_device *adev)
1615{
1616 return 0;
1617}
1618int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1619{
1620 return 0;
1621}
1622#endif