Loading...
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004 Thiemo Seufer
10 * Copyright (C) 2013 Imagination Technologies Ltd.
11 */
12#include <linux/cpu.h>
13#include <linux/errno.h>
14#include <linux/init.h>
15#include <linux/kallsyms.h>
16#include <linux/kernel.h>
17#include <linux/nmi.h>
18#include <linux/personality.h>
19#include <linux/prctl.h>
20#include <linux/random.h>
21#include <linux/sched.h>
22#include <linux/sched/debug.h>
23#include <linux/sched/task_stack.h>
24
25#include <asm/abi.h>
26#include <asm/asm.h>
27#include <asm/dsemul.h>
28#include <asm/dsp.h>
29#include <asm/exec.h>
30#include <asm/fpu.h>
31#include <asm/inst.h>
32#include <asm/irq.h>
33#include <asm/irq_regs.h>
34#include <asm/isadep.h>
35#include <asm/msa.h>
36#include <asm/mips-cps.h>
37#include <asm/mipsregs.h>
38#include <asm/processor.h>
39#include <asm/reg.h>
40#include <asm/stacktrace.h>
41
42#ifdef CONFIG_HOTPLUG_CPU
43void arch_cpu_idle_dead(void)
44{
45 play_dead();
46}
47#endif
48
49asmlinkage void ret_from_fork(void);
50asmlinkage void ret_from_kernel_thread(void);
51
52void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
53{
54 unsigned long status;
55
56 /* New thread loses kernel privileges. */
57 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK);
58 status |= KU_USER;
59 regs->cp0_status = status;
60 lose_fpu(0);
61 clear_thread_flag(TIF_MSA_CTX_LIVE);
62 clear_used_math();
63#ifdef CONFIG_MIPS_FP_SUPPORT
64 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE);
65#endif
66 init_dsp();
67 regs->cp0_epc = pc;
68 regs->regs[29] = sp;
69}
70
71void exit_thread(struct task_struct *tsk)
72{
73 /*
74 * User threads may have allocated a delay slot emulation frame.
75 * If so, clean up that allocation.
76 */
77 if (!(current->flags & PF_KTHREAD))
78 dsemul_thread_cleanup(tsk);
79}
80
81int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
82{
83 /*
84 * Save any process state which is live in hardware registers to the
85 * parent context prior to duplication. This prevents the new child
86 * state becoming stale if the parent is preempted before copy_thread()
87 * gets a chance to save the parent's live hardware registers to the
88 * child context.
89 */
90 preempt_disable();
91
92 if (is_msa_enabled())
93 save_msa(current);
94 else if (is_fpu_owner())
95 _save_fp(current);
96
97 save_dsp(current);
98
99 preempt_enable();
100
101 *dst = *src;
102 return 0;
103}
104
105/*
106 * Copy architecture-specific thread state
107 */
108int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
109{
110 unsigned long clone_flags = args->flags;
111 unsigned long usp = args->stack;
112 unsigned long tls = args->tls;
113 struct thread_info *ti = task_thread_info(p);
114 struct pt_regs *childregs, *regs = current_pt_regs();
115 unsigned long childksp;
116
117 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
118
119 /* set up new TSS. */
120 childregs = (struct pt_regs *) childksp - 1;
121 /* Put the stack after the struct pt_regs. */
122 childksp = (unsigned long) childregs;
123 p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK;
124 if (unlikely(args->fn)) {
125 /* kernel thread */
126 unsigned long status = p->thread.cp0_status;
127 memset(childregs, 0, sizeof(struct pt_regs));
128 p->thread.reg16 = (unsigned long)args->fn;
129 p->thread.reg17 = (unsigned long)args->fn_arg;
130 p->thread.reg29 = childksp;
131 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
132#if defined(CONFIG_CPU_R3000)
133 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
134 ((status & (ST0_KUC | ST0_IEC)) << 2);
135#else
136 status |= ST0_EXL;
137#endif
138 childregs->cp0_status = status;
139 return 0;
140 }
141
142 /* user thread */
143 *childregs = *regs;
144 childregs->regs[7] = 0; /* Clear error flag */
145 childregs->regs[2] = 0; /* Child gets zero as return value */
146 if (usp)
147 childregs->regs[29] = usp;
148
149 p->thread.reg29 = (unsigned long) childregs;
150 p->thread.reg31 = (unsigned long) ret_from_fork;
151
152 /*
153 * New tasks lose permission to use the fpu. This accelerates context
154 * switching for most programs since they don't use the fpu.
155 */
156 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
157
158 clear_tsk_thread_flag(p, TIF_USEDFPU);
159 clear_tsk_thread_flag(p, TIF_USEDMSA);
160 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
161
162#ifdef CONFIG_MIPS_MT_FPAFF
163 clear_tsk_thread_flag(p, TIF_FPUBOUND);
164#endif /* CONFIG_MIPS_MT_FPAFF */
165
166#ifdef CONFIG_MIPS_FP_SUPPORT
167 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
168#endif
169
170 if (clone_flags & CLONE_SETTLS)
171 ti->tp_value = tls;
172
173 return 0;
174}
175
176#ifdef CONFIG_STACKPROTECTOR
177#include <linux/stackprotector.h>
178unsigned long __stack_chk_guard __read_mostly;
179EXPORT_SYMBOL(__stack_chk_guard);
180#endif
181
182struct mips_frame_info {
183 void *func;
184 unsigned long func_size;
185 int frame_size;
186 int pc_offset;
187};
188
189#define J_TARGET(pc,target) \
190 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
191
192static inline int is_jr_ra_ins(union mips_instruction *ip)
193{
194#ifdef CONFIG_CPU_MICROMIPS
195 /*
196 * jr16 ra
197 * jr ra
198 */
199 if (mm_insn_16bit(ip->word >> 16)) {
200 if (ip->mm16_r5_format.opcode == mm_pool16c_op &&
201 ip->mm16_r5_format.rt == mm_jr16_op &&
202 ip->mm16_r5_format.imm == 31)
203 return 1;
204 return 0;
205 }
206
207 if (ip->r_format.opcode == mm_pool32a_op &&
208 ip->r_format.func == mm_pool32axf_op &&
209 ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op &&
210 ip->r_format.rt == 31)
211 return 1;
212 return 0;
213#else
214 if (ip->r_format.opcode == spec_op &&
215 ip->r_format.func == jr_op &&
216 ip->r_format.rs == 31)
217 return 1;
218 return 0;
219#endif
220}
221
222static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
223{
224#ifdef CONFIG_CPU_MICROMIPS
225 /*
226 * swsp ra,offset
227 * swm16 reglist,offset(sp)
228 * swm32 reglist,offset(sp)
229 * sw32 ra,offset(sp)
230 * jradiussp - NOT SUPPORTED
231 *
232 * microMIPS is way more fun...
233 */
234 if (mm_insn_16bit(ip->word >> 16)) {
235 switch (ip->mm16_r5_format.opcode) {
236 case mm_swsp16_op:
237 if (ip->mm16_r5_format.rt != 31)
238 return 0;
239
240 *poff = ip->mm16_r5_format.imm;
241 *poff = (*poff << 2) / sizeof(ulong);
242 return 1;
243
244 case mm_pool16c_op:
245 switch (ip->mm16_m_format.func) {
246 case mm_swm16_op:
247 *poff = ip->mm16_m_format.imm;
248 *poff += 1 + ip->mm16_m_format.rlist;
249 *poff = (*poff << 2) / sizeof(ulong);
250 return 1;
251
252 default:
253 return 0;
254 }
255
256 default:
257 return 0;
258 }
259 }
260
261 switch (ip->i_format.opcode) {
262 case mm_sw32_op:
263 if (ip->i_format.rs != 29)
264 return 0;
265 if (ip->i_format.rt != 31)
266 return 0;
267
268 *poff = ip->i_format.simmediate / sizeof(ulong);
269 return 1;
270
271 case mm_pool32b_op:
272 switch (ip->mm_m_format.func) {
273 case mm_swm32_func:
274 if (ip->mm_m_format.rd < 0x10)
275 return 0;
276 if (ip->mm_m_format.base != 29)
277 return 0;
278
279 *poff = ip->mm_m_format.simmediate;
280 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32);
281 *poff /= sizeof(ulong);
282 return 1;
283 default:
284 return 0;
285 }
286
287 default:
288 return 0;
289 }
290#else
291 /* sw / sd $ra, offset($sp) */
292 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
293 ip->i_format.rs == 29 && ip->i_format.rt == 31) {
294 *poff = ip->i_format.simmediate / sizeof(ulong);
295 return 1;
296 }
297#ifdef CONFIG_CPU_LOONGSON64
298 if ((ip->loongson3_lswc2_format.opcode == swc2_op) &&
299 (ip->loongson3_lswc2_format.ls == 1) &&
300 (ip->loongson3_lswc2_format.fr == 0) &&
301 (ip->loongson3_lswc2_format.base == 29)) {
302 if (ip->loongson3_lswc2_format.rt == 31) {
303 *poff = ip->loongson3_lswc2_format.offset << 1;
304 return 1;
305 }
306 if (ip->loongson3_lswc2_format.rq == 31) {
307 *poff = (ip->loongson3_lswc2_format.offset << 1) + 1;
308 return 1;
309 }
310 }
311#endif
312 return 0;
313#endif
314}
315
316static inline int is_jump_ins(union mips_instruction *ip)
317{
318#ifdef CONFIG_CPU_MICROMIPS
319 /*
320 * jr16,jrc,jalr16,jalr16
321 * jal
322 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
323 * jraddiusp - NOT SUPPORTED
324 *
325 * microMIPS is kind of more fun...
326 */
327 if (mm_insn_16bit(ip->word >> 16)) {
328 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
329 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
330 return 1;
331 return 0;
332 }
333
334 if (ip->j_format.opcode == mm_j32_op)
335 return 1;
336 if (ip->j_format.opcode == mm_jal32_op)
337 return 1;
338 if (ip->r_format.opcode != mm_pool32a_op ||
339 ip->r_format.func != mm_pool32axf_op)
340 return 0;
341 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
342#else
343 if (ip->j_format.opcode == j_op)
344 return 1;
345 if (ip->j_format.opcode == jal_op)
346 return 1;
347 if (ip->r_format.opcode != spec_op)
348 return 0;
349 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
350#endif
351}
352
353static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
354{
355#ifdef CONFIG_CPU_MICROMIPS
356 unsigned short tmp;
357
358 /*
359 * addiusp -imm
360 * addius5 sp,-imm
361 * addiu32 sp,sp,-imm
362 * jradiussp - NOT SUPPORTED
363 *
364 * microMIPS is not more fun...
365 */
366 if (mm_insn_16bit(ip->word >> 16)) {
367 if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
368 ip->mm16_r3_format.simmediate & mm_addiusp_func) {
369 tmp = ip->mm_b0_format.simmediate >> 1;
370 tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
371 if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
372 tmp ^= 0x100;
373 *frame_size = -(signed short)(tmp << 2);
374 return 1;
375 }
376 if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
377 ip->mm16_r5_format.rt == 29) {
378 tmp = ip->mm16_r5_format.imm >> 1;
379 *frame_size = -(signed short)(tmp & 0xf);
380 return 1;
381 }
382 return 0;
383 }
384
385 if (ip->mm_i_format.opcode == mm_addiu32_op &&
386 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
387 *frame_size = -ip->i_format.simmediate;
388 return 1;
389 }
390#else
391 /* addiu/daddiu sp,sp,-imm */
392 if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
393 return 0;
394
395 if (ip->i_format.opcode == addiu_op ||
396 ip->i_format.opcode == daddiu_op) {
397 *frame_size = -ip->i_format.simmediate;
398 return 1;
399 }
400#endif
401 return 0;
402}
403
404static int get_frame_info(struct mips_frame_info *info)
405{
406 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
407 union mips_instruction insn, *ip, *ip_end;
408 unsigned int last_insn_size = 0;
409 bool saw_jump = false;
410
411 info->pc_offset = -1;
412 info->frame_size = 0;
413
414 ip = (void *)msk_isa16_mode((ulong)info->func);
415 if (!ip)
416 goto err;
417
418 ip_end = (void *)ip + (info->func_size ? info->func_size : 512);
419
420 while (ip < ip_end) {
421 ip = (void *)ip + last_insn_size;
422
423 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
424 insn.word = ip->halfword[0] << 16;
425 last_insn_size = 2;
426 } else if (is_mmips) {
427 insn.word = ip->halfword[0] << 16 | ip->halfword[1];
428 last_insn_size = 4;
429 } else {
430 insn.word = ip->word;
431 last_insn_size = 4;
432 }
433
434 if (is_jr_ra_ins(ip)) {
435 break;
436 } else if (!info->frame_size) {
437 is_sp_move_ins(&insn, &info->frame_size);
438 continue;
439 } else if (!saw_jump && is_jump_ins(ip)) {
440 /*
441 * If we see a jump instruction, we are finished
442 * with the frame save.
443 *
444 * Some functions can have a shortcut return at
445 * the beginning of the function, so don't start
446 * looking for jump instruction until we see the
447 * frame setup.
448 *
449 * The RA save instruction can get put into the
450 * delay slot of the jump instruction, so look
451 * at the next instruction, too.
452 */
453 saw_jump = true;
454 continue;
455 }
456 if (info->pc_offset == -1 &&
457 is_ra_save_ins(&insn, &info->pc_offset))
458 break;
459 if (saw_jump)
460 break;
461 }
462 if (info->frame_size && info->pc_offset >= 0) /* nested */
463 return 0;
464 if (info->pc_offset < 0) /* leaf */
465 return 1;
466 /* prologue seems bogus... */
467err:
468 return -1;
469}
470
471static struct mips_frame_info schedule_mfi __read_mostly;
472
473#ifdef CONFIG_KALLSYMS
474static unsigned long get___schedule_addr(void)
475{
476 return kallsyms_lookup_name("__schedule");
477}
478#else
479static unsigned long get___schedule_addr(void)
480{
481 union mips_instruction *ip = (void *)schedule;
482 int max_insns = 8;
483 int i;
484
485 for (i = 0; i < max_insns; i++, ip++) {
486 if (ip->j_format.opcode == j_op)
487 return J_TARGET(ip, ip->j_format.target);
488 }
489 return 0;
490}
491#endif
492
493static int __init frame_info_init(void)
494{
495 unsigned long size = 0;
496#ifdef CONFIG_KALLSYMS
497 unsigned long ofs;
498#endif
499 unsigned long addr;
500
501 addr = get___schedule_addr();
502 if (!addr)
503 addr = (unsigned long)schedule;
504
505#ifdef CONFIG_KALLSYMS
506 kallsyms_lookup_size_offset(addr, &size, &ofs);
507#endif
508 schedule_mfi.func = (void *)addr;
509 schedule_mfi.func_size = size;
510
511 get_frame_info(&schedule_mfi);
512
513 /*
514 * Without schedule() frame info, result given by
515 * thread_saved_pc() and __get_wchan() are not reliable.
516 */
517 if (schedule_mfi.pc_offset < 0)
518 printk("Can't analyze schedule() prologue at %p\n", schedule);
519
520 return 0;
521}
522
523arch_initcall(frame_info_init);
524
525/*
526 * Return saved PC of a blocked thread.
527 */
528static unsigned long thread_saved_pc(struct task_struct *tsk)
529{
530 struct thread_struct *t = &tsk->thread;
531
532 /* New born processes are a special case */
533 if (t->reg31 == (unsigned long) ret_from_fork)
534 return t->reg31;
535 if (schedule_mfi.pc_offset < 0)
536 return 0;
537 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
538}
539
540
541#ifdef CONFIG_KALLSYMS
542/* generic stack unwinding function */
543unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
544 unsigned long *sp,
545 unsigned long pc,
546 unsigned long *ra)
547{
548 unsigned long low, high, irq_stack_high;
549 struct mips_frame_info info;
550 unsigned long size, ofs;
551 struct pt_regs *regs;
552 int leaf;
553
554 if (!stack_page)
555 return 0;
556
557 /*
558 * IRQ stacks start at IRQ_STACK_START
559 * task stacks at THREAD_SIZE - 32
560 */
561 low = stack_page;
562 if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
563 high = stack_page + IRQ_STACK_START;
564 irq_stack_high = high;
565 } else {
566 high = stack_page + THREAD_SIZE - 32;
567 irq_stack_high = 0;
568 }
569
570 /*
571 * If we reached the top of the interrupt stack, start unwinding
572 * the interrupted task stack.
573 */
574 if (unlikely(*sp == irq_stack_high)) {
575 unsigned long task_sp = *(unsigned long *)*sp;
576
577 /*
578 * Check that the pointer saved in the IRQ stack head points to
579 * something within the stack of the current task
580 */
581 if (!object_is_on_stack((void *)task_sp))
582 return 0;
583
584 /*
585 * Follow pointer to tasks kernel stack frame where interrupted
586 * state was saved.
587 */
588 regs = (struct pt_regs *)task_sp;
589 pc = regs->cp0_epc;
590 if (!user_mode(regs) && __kernel_text_address(pc)) {
591 *sp = regs->regs[29];
592 *ra = regs->regs[31];
593 return pc;
594 }
595 return 0;
596 }
597 if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
598 return 0;
599 /*
600 * Return ra if an exception occurred at the first instruction
601 */
602 if (unlikely(ofs == 0)) {
603 pc = *ra;
604 *ra = 0;
605 return pc;
606 }
607
608 info.func = (void *)(pc - ofs);
609 info.func_size = ofs; /* analyze from start to ofs */
610 leaf = get_frame_info(&info);
611 if (leaf < 0)
612 return 0;
613
614 if (*sp < low || *sp + info.frame_size > high)
615 return 0;
616
617 if (leaf)
618 /*
619 * For some extreme cases, get_frame_info() can
620 * consider wrongly a nested function as a leaf
621 * one. In that cases avoid to return always the
622 * same value.
623 */
624 pc = pc != *ra ? *ra : 0;
625 else
626 pc = ((unsigned long *)(*sp))[info.pc_offset];
627
628 *sp += info.frame_size;
629 *ra = 0;
630 return __kernel_text_address(pc) ? pc : 0;
631}
632EXPORT_SYMBOL(unwind_stack_by_address);
633
634/* used by show_backtrace() */
635unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
636 unsigned long pc, unsigned long *ra)
637{
638 unsigned long stack_page = 0;
639 int cpu;
640
641 for_each_possible_cpu(cpu) {
642 if (on_irq_stack(cpu, *sp)) {
643 stack_page = (unsigned long)irq_stack[cpu];
644 break;
645 }
646 }
647
648 if (!stack_page)
649 stack_page = (unsigned long)task_stack_page(task);
650
651 return unwind_stack_by_address(stack_page, sp, pc, ra);
652}
653#endif
654
655/*
656 * __get_wchan - a maintenance nightmare^W^Wpain in the ass ...
657 */
658unsigned long __get_wchan(struct task_struct *task)
659{
660 unsigned long pc = 0;
661#ifdef CONFIG_KALLSYMS
662 unsigned long sp;
663 unsigned long ra = 0;
664#endif
665
666 if (!task_stack_page(task))
667 goto out;
668
669 pc = thread_saved_pc(task);
670
671#ifdef CONFIG_KALLSYMS
672 sp = task->thread.reg29 + schedule_mfi.frame_size;
673
674 while (in_sched_functions(pc))
675 pc = unwind_stack(task, &sp, pc, &ra);
676#endif
677
678out:
679 return pc;
680}
681
682unsigned long mips_stack_top(void)
683{
684 unsigned long top = TASK_SIZE & PAGE_MASK;
685
686 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) {
687 /* One page for branch delay slot "emulation" */
688 top -= PAGE_SIZE;
689 }
690
691 /* Space for the VDSO, data page & GIC user page */
692 top -= PAGE_ALIGN(current->thread.abi->vdso->size);
693 top -= PAGE_SIZE;
694 top -= mips_gic_present() ? PAGE_SIZE : 0;
695
696 /* Space for cache colour alignment */
697 if (cpu_has_dc_aliases)
698 top -= shm_align_mask + 1;
699
700 /* Space to randomize the VDSO base */
701 if (current->flags & PF_RANDOMIZE)
702 top -= VDSO_RANDOMIZE_SIZE;
703
704 return top;
705}
706
707/*
708 * Don't forget that the stack pointer must be aligned on a 8 bytes
709 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
710 */
711unsigned long arch_align_stack(unsigned long sp)
712{
713 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
714 sp -= get_random_u32_below(PAGE_SIZE);
715
716 return sp & ALMASK;
717}
718
719static struct cpumask backtrace_csd_busy;
720
721static void handle_backtrace(void *info)
722{
723 nmi_cpu_backtrace(get_irq_regs());
724 cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
725}
726
727static DEFINE_PER_CPU(call_single_data_t, backtrace_csd) =
728 CSD_INIT(handle_backtrace, NULL);
729
730static void raise_backtrace(cpumask_t *mask)
731{
732 call_single_data_t *csd;
733 int cpu;
734
735 for_each_cpu(cpu, mask) {
736 /*
737 * If we previously sent an IPI to the target CPU & it hasn't
738 * cleared its bit in the busy cpumask then it didn't handle
739 * our previous IPI & it's not safe for us to reuse the
740 * call_single_data_t.
741 */
742 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
743 pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
744 cpu);
745 continue;
746 }
747
748 csd = &per_cpu(backtrace_csd, cpu);
749 smp_call_function_single_async(cpu, csd);
750 }
751}
752
753void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
754{
755 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
756}
757
758int mips_get_process_fp_mode(struct task_struct *task)
759{
760 int value = 0;
761
762 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
763 value |= PR_FP_MODE_FR;
764 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
765 value |= PR_FP_MODE_FRE;
766
767 return value;
768}
769
770static long prepare_for_fp_mode_switch(void *unused)
771{
772 /*
773 * This is icky, but we use this to simply ensure that all CPUs have
774 * context switched, regardless of whether they were previously running
775 * kernel or user code. This ensures that no CPU that a mode-switching
776 * program may execute on keeps its FPU enabled (& in the old mode)
777 * throughout the mode switch.
778 */
779 return 0;
780}
781
782int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
783{
784 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
785 struct task_struct *t;
786 struct cpumask process_cpus;
787 int cpu;
788
789 /* If nothing to change, return right away, successfully. */
790 if (value == mips_get_process_fp_mode(task))
791 return 0;
792
793 /* Only accept a mode change if 64-bit FP enabled for o32. */
794 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
795 return -EOPNOTSUPP;
796
797 /* And only for o32 tasks. */
798 if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))
799 return -EOPNOTSUPP;
800
801 /* Check the value is valid */
802 if (value & ~known_bits)
803 return -EOPNOTSUPP;
804
805 /* Setting FRE without FR is not supported. */
806 if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE)
807 return -EOPNOTSUPP;
808
809 /* Avoid inadvertently triggering emulation */
810 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
811 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
812 return -EOPNOTSUPP;
813 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
814 return -EOPNOTSUPP;
815
816 /* FR = 0 not supported in MIPS R6 */
817 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
818 return -EOPNOTSUPP;
819
820 /* Indicate the new FP mode in each thread */
821 for_each_thread(task, t) {
822 /* Update desired FP register width */
823 if (value & PR_FP_MODE_FR) {
824 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
825 } else {
826 set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
827 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
828 }
829
830 /* Update desired FP single layout */
831 if (value & PR_FP_MODE_FRE)
832 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
833 else
834 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
835 }
836
837 /*
838 * We need to ensure that all threads in the process have switched mode
839 * before returning, in order to allow userland to not worry about
840 * races. We can do this by forcing all CPUs that any thread in the
841 * process may be running on to schedule something else - in this case
842 * prepare_for_fp_mode_switch().
843 *
844 * We begin by generating a mask of all CPUs that any thread in the
845 * process may be running on.
846 */
847 cpumask_clear(&process_cpus);
848 for_each_thread(task, t)
849 cpumask_set_cpu(task_cpu(t), &process_cpus);
850
851 /*
852 * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs.
853 *
854 * The CPUs may have rescheduled already since we switched mode or
855 * generated the cpumask, but that doesn't matter. If the task in this
856 * process is scheduled out then our scheduling
857 * prepare_for_fp_mode_switch() will simply be redundant. If it's
858 * scheduled in then it will already have picked up the new FP mode
859 * whilst doing so.
860 */
861 cpus_read_lock();
862 for_each_cpu_and(cpu, &process_cpus, cpu_online_mask)
863 work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL);
864 cpus_read_unlock();
865
866 return 0;
867}
868
869#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
870void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs)
871{
872 unsigned int i;
873
874 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
875 /* k0/k1 are copied as zero. */
876 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
877 uregs[i] = 0;
878 else
879 uregs[i] = regs->regs[i - MIPS32_EF_R0];
880 }
881
882 uregs[MIPS32_EF_LO] = regs->lo;
883 uregs[MIPS32_EF_HI] = regs->hi;
884 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
885 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
886 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
887 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
888}
889#endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
890
891#ifdef CONFIG_64BIT
892void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs)
893{
894 unsigned int i;
895
896 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
897 /* k0/k1 are copied as zero. */
898 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
899 uregs[i] = 0;
900 else
901 uregs[i] = regs->regs[i - MIPS64_EF_R0];
902 }
903
904 uregs[MIPS64_EF_LO] = regs->lo;
905 uregs[MIPS64_EF_HI] = regs->hi;
906 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
907 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
908 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
909 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
910}
911#endif /* CONFIG_64BIT */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004 Thiemo Seufer
10 * Copyright (C) 2013 Imagination Technologies Ltd.
11 */
12#include <linux/cpu.h>
13#include <linux/errno.h>
14#include <linux/init.h>
15#include <linux/kallsyms.h>
16#include <linux/kernel.h>
17#include <linux/nmi.h>
18#include <linux/personality.h>
19#include <linux/prctl.h>
20#include <linux/random.h>
21#include <linux/sched.h>
22#include <linux/sched/debug.h>
23#include <linux/sched/task_stack.h>
24
25#include <asm/abi.h>
26#include <asm/asm.h>
27#include <asm/dsemul.h>
28#include <asm/dsp.h>
29#include <asm/exec.h>
30#include <asm/fpu.h>
31#include <asm/inst.h>
32#include <asm/irq.h>
33#include <asm/irq_regs.h>
34#include <asm/isadep.h>
35#include <asm/msa.h>
36#include <asm/mips-cps.h>
37#include <asm/mipsregs.h>
38#include <asm/processor.h>
39#include <asm/reg.h>
40#include <asm/stacktrace.h>
41
42#ifdef CONFIG_HOTPLUG_CPU
43void arch_cpu_idle_dead(void)
44{
45 play_dead();
46}
47#endif
48
49asmlinkage void ret_from_fork(void);
50asmlinkage void ret_from_kernel_thread(void);
51
52void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
53{
54 unsigned long status;
55
56 /* New thread loses kernel privileges. */
57 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK);
58 status |= KU_USER;
59 regs->cp0_status = status;
60 lose_fpu(0);
61 clear_thread_flag(TIF_MSA_CTX_LIVE);
62 clear_used_math();
63#ifdef CONFIG_MIPS_FP_SUPPORT
64 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE);
65#endif
66 init_dsp();
67 regs->cp0_epc = pc;
68 regs->regs[29] = sp;
69}
70
71void exit_thread(struct task_struct *tsk)
72{
73 /*
74 * User threads may have allocated a delay slot emulation frame.
75 * If so, clean up that allocation.
76 */
77 if (!(current->flags & PF_KTHREAD))
78 dsemul_thread_cleanup(tsk);
79}
80
81int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
82{
83 /*
84 * Save any process state which is live in hardware registers to the
85 * parent context prior to duplication. This prevents the new child
86 * state becoming stale if the parent is preempted before copy_thread()
87 * gets a chance to save the parent's live hardware registers to the
88 * child context.
89 */
90 preempt_disable();
91
92 if (is_msa_enabled())
93 save_msa(current);
94 else if (is_fpu_owner())
95 _save_fp(current);
96
97 save_dsp(current);
98
99 preempt_enable();
100
101 *dst = *src;
102 return 0;
103}
104
105/*
106 * Copy architecture-specific thread state
107 */
108int copy_thread(unsigned long clone_flags, unsigned long usp,
109 unsigned long kthread_arg, struct task_struct *p,
110 unsigned long tls)
111{
112 struct thread_info *ti = task_thread_info(p);
113 struct pt_regs *childregs, *regs = current_pt_regs();
114 unsigned long childksp;
115
116 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
117
118 /* set up new TSS. */
119 childregs = (struct pt_regs *) childksp - 1;
120 /* Put the stack after the struct pt_regs. */
121 childksp = (unsigned long) childregs;
122 p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK;
123 if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) {
124 /* kernel thread */
125 unsigned long status = p->thread.cp0_status;
126 memset(childregs, 0, sizeof(struct pt_regs));
127 p->thread.reg16 = usp; /* fn */
128 p->thread.reg17 = kthread_arg;
129 p->thread.reg29 = childksp;
130 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
131#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
132 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
133 ((status & (ST0_KUC | ST0_IEC)) << 2);
134#else
135 status |= ST0_EXL;
136#endif
137 childregs->cp0_status = status;
138 return 0;
139 }
140
141 /* user thread */
142 *childregs = *regs;
143 childregs->regs[7] = 0; /* Clear error flag */
144 childregs->regs[2] = 0; /* Child gets zero as return value */
145 if (usp)
146 childregs->regs[29] = usp;
147
148 p->thread.reg29 = (unsigned long) childregs;
149 p->thread.reg31 = (unsigned long) ret_from_fork;
150
151 /*
152 * New tasks lose permission to use the fpu. This accelerates context
153 * switching for most programs since they don't use the fpu.
154 */
155 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
156
157 clear_tsk_thread_flag(p, TIF_USEDFPU);
158 clear_tsk_thread_flag(p, TIF_USEDMSA);
159 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
160
161#ifdef CONFIG_MIPS_MT_FPAFF
162 clear_tsk_thread_flag(p, TIF_FPUBOUND);
163#endif /* CONFIG_MIPS_MT_FPAFF */
164
165#ifdef CONFIG_MIPS_FP_SUPPORT
166 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
167#endif
168
169 if (clone_flags & CLONE_SETTLS)
170 ti->tp_value = tls;
171
172 return 0;
173}
174
175#ifdef CONFIG_STACKPROTECTOR
176#include <linux/stackprotector.h>
177unsigned long __stack_chk_guard __read_mostly;
178EXPORT_SYMBOL(__stack_chk_guard);
179#endif
180
181struct mips_frame_info {
182 void *func;
183 unsigned long func_size;
184 int frame_size;
185 int pc_offset;
186};
187
188#define J_TARGET(pc,target) \
189 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
190
191static inline int is_jr_ra_ins(union mips_instruction *ip)
192{
193#ifdef CONFIG_CPU_MICROMIPS
194 /*
195 * jr16 ra
196 * jr ra
197 */
198 if (mm_insn_16bit(ip->word >> 16)) {
199 if (ip->mm16_r5_format.opcode == mm_pool16c_op &&
200 ip->mm16_r5_format.rt == mm_jr16_op &&
201 ip->mm16_r5_format.imm == 31)
202 return 1;
203 return 0;
204 }
205
206 if (ip->r_format.opcode == mm_pool32a_op &&
207 ip->r_format.func == mm_pool32axf_op &&
208 ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op &&
209 ip->r_format.rt == 31)
210 return 1;
211 return 0;
212#else
213 if (ip->r_format.opcode == spec_op &&
214 ip->r_format.func == jr_op &&
215 ip->r_format.rs == 31)
216 return 1;
217 return 0;
218#endif
219}
220
221static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
222{
223#ifdef CONFIG_CPU_MICROMIPS
224 /*
225 * swsp ra,offset
226 * swm16 reglist,offset(sp)
227 * swm32 reglist,offset(sp)
228 * sw32 ra,offset(sp)
229 * jradiussp - NOT SUPPORTED
230 *
231 * microMIPS is way more fun...
232 */
233 if (mm_insn_16bit(ip->word >> 16)) {
234 switch (ip->mm16_r5_format.opcode) {
235 case mm_swsp16_op:
236 if (ip->mm16_r5_format.rt != 31)
237 return 0;
238
239 *poff = ip->mm16_r5_format.imm;
240 *poff = (*poff << 2) / sizeof(ulong);
241 return 1;
242
243 case mm_pool16c_op:
244 switch (ip->mm16_m_format.func) {
245 case mm_swm16_op:
246 *poff = ip->mm16_m_format.imm;
247 *poff += 1 + ip->mm16_m_format.rlist;
248 *poff = (*poff << 2) / sizeof(ulong);
249 return 1;
250
251 default:
252 return 0;
253 }
254
255 default:
256 return 0;
257 }
258 }
259
260 switch (ip->i_format.opcode) {
261 case mm_sw32_op:
262 if (ip->i_format.rs != 29)
263 return 0;
264 if (ip->i_format.rt != 31)
265 return 0;
266
267 *poff = ip->i_format.simmediate / sizeof(ulong);
268 return 1;
269
270 case mm_pool32b_op:
271 switch (ip->mm_m_format.func) {
272 case mm_swm32_func:
273 if (ip->mm_m_format.rd < 0x10)
274 return 0;
275 if (ip->mm_m_format.base != 29)
276 return 0;
277
278 *poff = ip->mm_m_format.simmediate;
279 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32);
280 *poff /= sizeof(ulong);
281 return 1;
282 default:
283 return 0;
284 }
285
286 default:
287 return 0;
288 }
289#else
290 /* sw / sd $ra, offset($sp) */
291 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
292 ip->i_format.rs == 29 && ip->i_format.rt == 31) {
293 *poff = ip->i_format.simmediate / sizeof(ulong);
294 return 1;
295 }
296#ifdef CONFIG_CPU_LOONGSON64
297 if ((ip->loongson3_lswc2_format.opcode == swc2_op) &&
298 (ip->loongson3_lswc2_format.ls == 1) &&
299 (ip->loongson3_lswc2_format.fr == 0) &&
300 (ip->loongson3_lswc2_format.base == 29)) {
301 if (ip->loongson3_lswc2_format.rt == 31) {
302 *poff = ip->loongson3_lswc2_format.offset << 1;
303 return 1;
304 }
305 if (ip->loongson3_lswc2_format.rq == 31) {
306 *poff = (ip->loongson3_lswc2_format.offset << 1) + 1;
307 return 1;
308 }
309 }
310#endif
311 return 0;
312#endif
313}
314
315static inline int is_jump_ins(union mips_instruction *ip)
316{
317#ifdef CONFIG_CPU_MICROMIPS
318 /*
319 * jr16,jrc,jalr16,jalr16
320 * jal
321 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
322 * jraddiusp - NOT SUPPORTED
323 *
324 * microMIPS is kind of more fun...
325 */
326 if (mm_insn_16bit(ip->word >> 16)) {
327 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
328 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
329 return 1;
330 return 0;
331 }
332
333 if (ip->j_format.opcode == mm_j32_op)
334 return 1;
335 if (ip->j_format.opcode == mm_jal32_op)
336 return 1;
337 if (ip->r_format.opcode != mm_pool32a_op ||
338 ip->r_format.func != mm_pool32axf_op)
339 return 0;
340 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
341#else
342 if (ip->j_format.opcode == j_op)
343 return 1;
344 if (ip->j_format.opcode == jal_op)
345 return 1;
346 if (ip->r_format.opcode != spec_op)
347 return 0;
348 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
349#endif
350}
351
352static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
353{
354#ifdef CONFIG_CPU_MICROMIPS
355 unsigned short tmp;
356
357 /*
358 * addiusp -imm
359 * addius5 sp,-imm
360 * addiu32 sp,sp,-imm
361 * jradiussp - NOT SUPPORTED
362 *
363 * microMIPS is not more fun...
364 */
365 if (mm_insn_16bit(ip->word >> 16)) {
366 if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
367 ip->mm16_r3_format.simmediate & mm_addiusp_func) {
368 tmp = ip->mm_b0_format.simmediate >> 1;
369 tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
370 if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
371 tmp ^= 0x100;
372 *frame_size = -(signed short)(tmp << 2);
373 return 1;
374 }
375 if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
376 ip->mm16_r5_format.rt == 29) {
377 tmp = ip->mm16_r5_format.imm >> 1;
378 *frame_size = -(signed short)(tmp & 0xf);
379 return 1;
380 }
381 return 0;
382 }
383
384 if (ip->mm_i_format.opcode == mm_addiu32_op &&
385 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
386 *frame_size = -ip->i_format.simmediate;
387 return 1;
388 }
389#else
390 /* addiu/daddiu sp,sp,-imm */
391 if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
392 return 0;
393
394 if (ip->i_format.opcode == addiu_op ||
395 ip->i_format.opcode == daddiu_op) {
396 *frame_size = -ip->i_format.simmediate;
397 return 1;
398 }
399#endif
400 return 0;
401}
402
403static int get_frame_info(struct mips_frame_info *info)
404{
405 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
406 union mips_instruction insn, *ip, *ip_end;
407 unsigned int last_insn_size = 0;
408 bool saw_jump = false;
409
410 info->pc_offset = -1;
411 info->frame_size = 0;
412
413 ip = (void *)msk_isa16_mode((ulong)info->func);
414 if (!ip)
415 goto err;
416
417 ip_end = (void *)ip + (info->func_size ? info->func_size : 512);
418
419 while (ip < ip_end) {
420 ip = (void *)ip + last_insn_size;
421
422 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
423 insn.word = ip->halfword[0] << 16;
424 last_insn_size = 2;
425 } else if (is_mmips) {
426 insn.word = ip->halfword[0] << 16 | ip->halfword[1];
427 last_insn_size = 4;
428 } else {
429 insn.word = ip->word;
430 last_insn_size = 4;
431 }
432
433 if (is_jr_ra_ins(ip)) {
434 break;
435 } else if (!info->frame_size) {
436 is_sp_move_ins(&insn, &info->frame_size);
437 continue;
438 } else if (!saw_jump && is_jump_ins(ip)) {
439 /*
440 * If we see a jump instruction, we are finished
441 * with the frame save.
442 *
443 * Some functions can have a shortcut return at
444 * the beginning of the function, so don't start
445 * looking for jump instruction until we see the
446 * frame setup.
447 *
448 * The RA save instruction can get put into the
449 * delay slot of the jump instruction, so look
450 * at the next instruction, too.
451 */
452 saw_jump = true;
453 continue;
454 }
455 if (info->pc_offset == -1 &&
456 is_ra_save_ins(&insn, &info->pc_offset))
457 break;
458 if (saw_jump)
459 break;
460 }
461 if (info->frame_size && info->pc_offset >= 0) /* nested */
462 return 0;
463 if (info->pc_offset < 0) /* leaf */
464 return 1;
465 /* prologue seems bogus... */
466err:
467 return -1;
468}
469
470static struct mips_frame_info schedule_mfi __read_mostly;
471
472#ifdef CONFIG_KALLSYMS
473static unsigned long get___schedule_addr(void)
474{
475 return kallsyms_lookup_name("__schedule");
476}
477#else
478static unsigned long get___schedule_addr(void)
479{
480 union mips_instruction *ip = (void *)schedule;
481 int max_insns = 8;
482 int i;
483
484 for (i = 0; i < max_insns; i++, ip++) {
485 if (ip->j_format.opcode == j_op)
486 return J_TARGET(ip, ip->j_format.target);
487 }
488 return 0;
489}
490#endif
491
492static int __init frame_info_init(void)
493{
494 unsigned long size = 0;
495#ifdef CONFIG_KALLSYMS
496 unsigned long ofs;
497#endif
498 unsigned long addr;
499
500 addr = get___schedule_addr();
501 if (!addr)
502 addr = (unsigned long)schedule;
503
504#ifdef CONFIG_KALLSYMS
505 kallsyms_lookup_size_offset(addr, &size, &ofs);
506#endif
507 schedule_mfi.func = (void *)addr;
508 schedule_mfi.func_size = size;
509
510 get_frame_info(&schedule_mfi);
511
512 /*
513 * Without schedule() frame info, result given by
514 * thread_saved_pc() and get_wchan() are not reliable.
515 */
516 if (schedule_mfi.pc_offset < 0)
517 printk("Can't analyze schedule() prologue at %p\n", schedule);
518
519 return 0;
520}
521
522arch_initcall(frame_info_init);
523
524/*
525 * Return saved PC of a blocked thread.
526 */
527static unsigned long thread_saved_pc(struct task_struct *tsk)
528{
529 struct thread_struct *t = &tsk->thread;
530
531 /* New born processes are a special case */
532 if (t->reg31 == (unsigned long) ret_from_fork)
533 return t->reg31;
534 if (schedule_mfi.pc_offset < 0)
535 return 0;
536 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
537}
538
539
540#ifdef CONFIG_KALLSYMS
541/* generic stack unwinding function */
542unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
543 unsigned long *sp,
544 unsigned long pc,
545 unsigned long *ra)
546{
547 unsigned long low, high, irq_stack_high;
548 struct mips_frame_info info;
549 unsigned long size, ofs;
550 struct pt_regs *regs;
551 int leaf;
552
553 if (!stack_page)
554 return 0;
555
556 /*
557 * IRQ stacks start at IRQ_STACK_START
558 * task stacks at THREAD_SIZE - 32
559 */
560 low = stack_page;
561 if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
562 high = stack_page + IRQ_STACK_START;
563 irq_stack_high = high;
564 } else {
565 high = stack_page + THREAD_SIZE - 32;
566 irq_stack_high = 0;
567 }
568
569 /*
570 * If we reached the top of the interrupt stack, start unwinding
571 * the interrupted task stack.
572 */
573 if (unlikely(*sp == irq_stack_high)) {
574 unsigned long task_sp = *(unsigned long *)*sp;
575
576 /*
577 * Check that the pointer saved in the IRQ stack head points to
578 * something within the stack of the current task
579 */
580 if (!object_is_on_stack((void *)task_sp))
581 return 0;
582
583 /*
584 * Follow pointer to tasks kernel stack frame where interrupted
585 * state was saved.
586 */
587 regs = (struct pt_regs *)task_sp;
588 pc = regs->cp0_epc;
589 if (!user_mode(regs) && __kernel_text_address(pc)) {
590 *sp = regs->regs[29];
591 *ra = regs->regs[31];
592 return pc;
593 }
594 return 0;
595 }
596 if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
597 return 0;
598 /*
599 * Return ra if an exception occurred at the first instruction
600 */
601 if (unlikely(ofs == 0)) {
602 pc = *ra;
603 *ra = 0;
604 return pc;
605 }
606
607 info.func = (void *)(pc - ofs);
608 info.func_size = ofs; /* analyze from start to ofs */
609 leaf = get_frame_info(&info);
610 if (leaf < 0)
611 return 0;
612
613 if (*sp < low || *sp + info.frame_size > high)
614 return 0;
615
616 if (leaf)
617 /*
618 * For some extreme cases, get_frame_info() can
619 * consider wrongly a nested function as a leaf
620 * one. In that cases avoid to return always the
621 * same value.
622 */
623 pc = pc != *ra ? *ra : 0;
624 else
625 pc = ((unsigned long *)(*sp))[info.pc_offset];
626
627 *sp += info.frame_size;
628 *ra = 0;
629 return __kernel_text_address(pc) ? pc : 0;
630}
631EXPORT_SYMBOL(unwind_stack_by_address);
632
633/* used by show_backtrace() */
634unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
635 unsigned long pc, unsigned long *ra)
636{
637 unsigned long stack_page = 0;
638 int cpu;
639
640 for_each_possible_cpu(cpu) {
641 if (on_irq_stack(cpu, *sp)) {
642 stack_page = (unsigned long)irq_stack[cpu];
643 break;
644 }
645 }
646
647 if (!stack_page)
648 stack_page = (unsigned long)task_stack_page(task);
649
650 return unwind_stack_by_address(stack_page, sp, pc, ra);
651}
652#endif
653
654/*
655 * get_wchan - a maintenance nightmare^W^Wpain in the ass ...
656 */
657unsigned long get_wchan(struct task_struct *task)
658{
659 unsigned long pc = 0;
660#ifdef CONFIG_KALLSYMS
661 unsigned long sp;
662 unsigned long ra = 0;
663#endif
664
665 if (!task || task == current || task_is_running(task))
666 goto out;
667 if (!task_stack_page(task))
668 goto out;
669
670 pc = thread_saved_pc(task);
671
672#ifdef CONFIG_KALLSYMS
673 sp = task->thread.reg29 + schedule_mfi.frame_size;
674
675 while (in_sched_functions(pc))
676 pc = unwind_stack(task, &sp, pc, &ra);
677#endif
678
679out:
680 return pc;
681}
682
683unsigned long mips_stack_top(void)
684{
685 unsigned long top = TASK_SIZE & PAGE_MASK;
686
687 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) {
688 /* One page for branch delay slot "emulation" */
689 top -= PAGE_SIZE;
690 }
691
692 /* Space for the VDSO, data page & GIC user page */
693 top -= PAGE_ALIGN(current->thread.abi->vdso->size);
694 top -= PAGE_SIZE;
695 top -= mips_gic_present() ? PAGE_SIZE : 0;
696
697 /* Space for cache colour alignment */
698 if (cpu_has_dc_aliases)
699 top -= shm_align_mask + 1;
700
701 /* Space to randomize the VDSO base */
702 if (current->flags & PF_RANDOMIZE)
703 top -= VDSO_RANDOMIZE_SIZE;
704
705 return top;
706}
707
708/*
709 * Don't forget that the stack pointer must be aligned on a 8 bytes
710 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
711 */
712unsigned long arch_align_stack(unsigned long sp)
713{
714 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
715 sp -= get_random_int() & ~PAGE_MASK;
716
717 return sp & ALMASK;
718}
719
720static struct cpumask backtrace_csd_busy;
721
722static void handle_backtrace(void *info)
723{
724 nmi_cpu_backtrace(get_irq_regs());
725 cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
726}
727
728static DEFINE_PER_CPU(call_single_data_t, backtrace_csd) =
729 CSD_INIT(handle_backtrace, NULL);
730
731static void raise_backtrace(cpumask_t *mask)
732{
733 call_single_data_t *csd;
734 int cpu;
735
736 for_each_cpu(cpu, mask) {
737 /*
738 * If we previously sent an IPI to the target CPU & it hasn't
739 * cleared its bit in the busy cpumask then it didn't handle
740 * our previous IPI & it's not safe for us to reuse the
741 * call_single_data_t.
742 */
743 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
744 pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
745 cpu);
746 continue;
747 }
748
749 csd = &per_cpu(backtrace_csd, cpu);
750 smp_call_function_single_async(cpu, csd);
751 }
752}
753
754void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
755{
756 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
757}
758
759int mips_get_process_fp_mode(struct task_struct *task)
760{
761 int value = 0;
762
763 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
764 value |= PR_FP_MODE_FR;
765 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
766 value |= PR_FP_MODE_FRE;
767
768 return value;
769}
770
771static long prepare_for_fp_mode_switch(void *unused)
772{
773 /*
774 * This is icky, but we use this to simply ensure that all CPUs have
775 * context switched, regardless of whether they were previously running
776 * kernel or user code. This ensures that no CPU that a mode-switching
777 * program may execute on keeps its FPU enabled (& in the old mode)
778 * throughout the mode switch.
779 */
780 return 0;
781}
782
783int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
784{
785 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
786 struct task_struct *t;
787 struct cpumask process_cpus;
788 int cpu;
789
790 /* If nothing to change, return right away, successfully. */
791 if (value == mips_get_process_fp_mode(task))
792 return 0;
793
794 /* Only accept a mode change if 64-bit FP enabled for o32. */
795 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
796 return -EOPNOTSUPP;
797
798 /* And only for o32 tasks. */
799 if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))
800 return -EOPNOTSUPP;
801
802 /* Check the value is valid */
803 if (value & ~known_bits)
804 return -EOPNOTSUPP;
805
806 /* Setting FRE without FR is not supported. */
807 if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE)
808 return -EOPNOTSUPP;
809
810 /* Avoid inadvertently triggering emulation */
811 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
812 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
813 return -EOPNOTSUPP;
814 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
815 return -EOPNOTSUPP;
816
817 /* FR = 0 not supported in MIPS R6 */
818 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
819 return -EOPNOTSUPP;
820
821 /* Indicate the new FP mode in each thread */
822 for_each_thread(task, t) {
823 /* Update desired FP register width */
824 if (value & PR_FP_MODE_FR) {
825 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
826 } else {
827 set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
828 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
829 }
830
831 /* Update desired FP single layout */
832 if (value & PR_FP_MODE_FRE)
833 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
834 else
835 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
836 }
837
838 /*
839 * We need to ensure that all threads in the process have switched mode
840 * before returning, in order to allow userland to not worry about
841 * races. We can do this by forcing all CPUs that any thread in the
842 * process may be running on to schedule something else - in this case
843 * prepare_for_fp_mode_switch().
844 *
845 * We begin by generating a mask of all CPUs that any thread in the
846 * process may be running on.
847 */
848 cpumask_clear(&process_cpus);
849 for_each_thread(task, t)
850 cpumask_set_cpu(task_cpu(t), &process_cpus);
851
852 /*
853 * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs.
854 *
855 * The CPUs may have rescheduled already since we switched mode or
856 * generated the cpumask, but that doesn't matter. If the task in this
857 * process is scheduled out then our scheduling
858 * prepare_for_fp_mode_switch() will simply be redundant. If it's
859 * scheduled in then it will already have picked up the new FP mode
860 * whilst doing so.
861 */
862 get_online_cpus();
863 for_each_cpu_and(cpu, &process_cpus, cpu_online_mask)
864 work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL);
865 put_online_cpus();
866
867 return 0;
868}
869
870#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
871void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs)
872{
873 unsigned int i;
874
875 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
876 /* k0/k1 are copied as zero. */
877 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
878 uregs[i] = 0;
879 else
880 uregs[i] = regs->regs[i - MIPS32_EF_R0];
881 }
882
883 uregs[MIPS32_EF_LO] = regs->lo;
884 uregs[MIPS32_EF_HI] = regs->hi;
885 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
886 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
887 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
888 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
889}
890#endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
891
892#ifdef CONFIG_64BIT
893void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs)
894{
895 unsigned int i;
896
897 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
898 /* k0/k1 are copied as zero. */
899 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
900 uregs[i] = 0;
901 else
902 uregs[i] = regs->regs[i - MIPS64_EF_R0];
903 }
904
905 uregs[MIPS64_EF_LO] = regs->lo;
906 uregs[MIPS64_EF_HI] = regs->hi;
907 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
908 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
909 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
910 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
911}
912#endif /* CONFIG_64BIT */