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1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra114-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra114-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/soc/tegra-pmc.h>
8
9/ {
10 compatible = "nvidia,tegra114";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 memory@80000000 {
16 device_type = "memory";
17 reg = <0x80000000 0x0>;
18 };
19
20 sram@40000000 {
21 compatible = "mmio-sram";
22 reg = <0x40000000 0x40000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0 0x40000000 0x40000>;
26
27 vde_pool: sram@400 {
28 reg = <0x400 0x3fc00>;
29 pool;
30 };
31 };
32
33 host1x@50000000 {
34 compatible = "nvidia,tegra114-host1x";
35 reg = <0x50000000 0x00028000>;
36 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
37 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
38 interrupt-names = "syncpt", "host1x";
39 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
40 clock-names = "host1x";
41 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>;
42 reset-names = "host1x", "mc";
43 iommus = <&mc TEGRA_SWGROUP_HC>;
44
45 #address-cells = <1>;
46 #size-cells = <1>;
47
48 ranges = <0x54000000 0x54000000 0x01000000>;
49
50 gr2d@54140000 {
51 compatible = "nvidia,tegra114-gr2d";
52 reg = <0x54140000 0x00040000>;
53 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
55 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>;
56 reset-names = "2d", "mc";
57
58 iommus = <&mc TEGRA_SWGROUP_G2>;
59 };
60
61 gr3d@54180000 {
62 compatible = "nvidia,tegra114-gr3d";
63 reg = <0x54180000 0x00040000>;
64 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
65 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>;
66 reset-names = "3d", "mc";
67
68 iommus = <&mc TEGRA_SWGROUP_NV>;
69 };
70
71 dc@54200000 {
72 compatible = "nvidia,tegra114-dc";
73 reg = <0x54200000 0x00040000>;
74 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
75 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
76 <&tegra_car TEGRA114_CLK_PLL_P>;
77 clock-names = "dc", "parent";
78 resets = <&tegra_car 27>;
79 reset-names = "dc";
80
81 iommus = <&mc TEGRA_SWGROUP_DC>;
82
83 nvidia,head = <0>;
84
85 rgb {
86 status = "disabled";
87 };
88 };
89
90 dc@54240000 {
91 compatible = "nvidia,tegra114-dc";
92 reg = <0x54240000 0x00040000>;
93 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
95 <&tegra_car TEGRA114_CLK_PLL_P>;
96 clock-names = "dc", "parent";
97 resets = <&tegra_car 26>;
98 reset-names = "dc";
99
100 iommus = <&mc TEGRA_SWGROUP_DCB>;
101
102 nvidia,head = <1>;
103
104 rgb {
105 status = "disabled";
106 };
107 };
108
109 hdmi@54280000 {
110 compatible = "nvidia,tegra114-hdmi";
111 reg = <0x54280000 0x00040000>;
112 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
114 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
115 clock-names = "hdmi", "parent";
116 resets = <&tegra_car 51>;
117 reset-names = "hdmi";
118 status = "disabled";
119 };
120
121 dsia: dsi@54300000 {
122 compatible = "nvidia,tegra114-dsi";
123 reg = <0x54300000 0x00040000>;
124 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
125 <&tegra_car TEGRA114_CLK_DSIALP>,
126 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
127 clock-names = "dsi", "lp", "parent";
128 resets = <&tegra_car 48>;
129 reset-names = "dsi";
130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
131 status = "disabled";
132
133 #address-cells = <1>;
134 #size-cells = <0>;
135 };
136
137 dsib: dsi@54400000 {
138 compatible = "nvidia,tegra114-dsi";
139 reg = <0x54400000 0x00040000>;
140 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
141 <&tegra_car TEGRA114_CLK_DSIBLP>,
142 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
143 clock-names = "dsi", "lp", "parent";
144 resets = <&tegra_car 82>;
145 reset-names = "dsi";
146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
147 status = "disabled";
148
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152 };
153
154 gic: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a15-gic";
156 #interrupt-cells = <3>;
157 interrupt-controller;
158 reg = <0x50041000 0x1000>,
159 <0x50042000 0x1000>,
160 <0x50044000 0x2000>,
161 <0x50046000 0x2000>;
162 interrupts = <GIC_PPI 9
163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
164 interrupt-parent = <&gic>;
165 };
166
167 lic: interrupt-controller@60004000 {
168 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
169 reg = <0x60004000 0x100>,
170 <0x60004100 0x50>,
171 <0x60004200 0x50>,
172 <0x60004300 0x50>,
173 <0x60004400 0x50>;
174 interrupt-controller;
175 #interrupt-cells = <3>;
176 interrupt-parent = <&gic>;
177 };
178
179 timer@60005000 {
180 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
181 reg = <0x60005000 0x400>;
182 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
189 };
190
191 tegra_car: clock@60006000 {
192 compatible = "nvidia,tegra114-car";
193 reg = <0x60006000 0x1000>;
194 #clock-cells = <1>;
195 #reset-cells = <1>;
196 };
197
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra114-flowctrl";
200 reg = <0x60007000 0x1000>;
201 };
202
203 apbdma: dma@6000a000 {
204 compatible = "nvidia,tegra114-apbdma";
205 reg = <0x6000a000 0x1400>;
206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
239 resets = <&tegra_car 34>;
240 reset-names = "dma";
241 #dma-cells = <1>;
242 };
243
244 ahb: ahb@6000c000 {
245 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
246 reg = <0x6000c000 0x150>;
247 };
248
249 gpio: gpio@6000d000 {
250 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
251 reg = <0x6000d000 0x1000>;
252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
260 #gpio-cells = <2>;
261 gpio-controller;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 gpio-ranges = <&pinmux 0 0 246>;
265 };
266
267 vde@6001a000 {
268 compatible = "nvidia,tegra114-vde";
269 reg = <0x6001a000 0x1000>, /* Syntax Engine */
270 <0x6001b000 0x1000>, /* Video Bitstream Engine */
271 <0x6001c000 0x100>, /* Macroblock Engine */
272 <0x6001c200 0x100>, /* Post-processing Engine */
273 <0x6001c400 0x100>, /* Motion Compensation Engine */
274 <0x6001c600 0x100>, /* Transform Engine */
275 <0x6001c800 0x100>, /* Pixel prediction block */
276 <0x6001ca00 0x100>, /* Video DMA */
277 <0x6001d800 0x400>; /* Video frame controls */
278 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
279 "tfe", "ppb", "vdma", "frameid";
280 iram = <&vde_pool>; /* IRAM region */
281 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
282 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
283 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
284 interrupt-names = "sync-token", "bsev", "sxe";
285 clocks = <&tegra_car TEGRA114_CLK_VDE>;
286 reset-names = "vde", "mc";
287 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
288 iommus = <&mc TEGRA_SWGROUP_VDE>;
289 };
290
291 apbmisc@70000800 {
292 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
293 reg = <0x70000800 0x64>, /* Chip revision */
294 <0x70000008 0x04>; /* Strapping options */
295 };
296
297 pinmux: pinmux@70000868 {
298 compatible = "nvidia,tegra114-pinmux";
299 reg = <0x70000868 0x148>, /* Pad control registers */
300 <0x70003000 0x40c>; /* Mux registers */
301 };
302
303 /*
304 * There are two serial driver i.e. 8250 based simple serial
305 * driver and APB DMA based serial driver for higher baudrate
306 * and performace. To enable the 8250 based driver, the compatible
307 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
308 * the APB DMA based serial driver, the compatible is
309 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
310 */
311 uarta: serial@70006000 {
312 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
313 reg = <0x70006000 0x40>;
314 reg-shift = <2>;
315 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
317 resets = <&tegra_car 6>;
318 reset-names = "serial";
319 dmas = <&apbdma 8>, <&apbdma 8>;
320 dma-names = "rx", "tx";
321 status = "disabled";
322 };
323
324 uartb: serial@70006040 {
325 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
326 reg = <0x70006040 0x40>;
327 reg-shift = <2>;
328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
330 resets = <&tegra_car 7>;
331 reset-names = "serial";
332 dmas = <&apbdma 9>, <&apbdma 9>;
333 dma-names = "rx", "tx";
334 status = "disabled";
335 };
336
337 uartc: serial@70006200 {
338 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
339 reg = <0x70006200 0x100>;
340 reg-shift = <2>;
341 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
343 resets = <&tegra_car 55>;
344 reset-names = "serial";
345 dmas = <&apbdma 10>, <&apbdma 10>;
346 dma-names = "rx", "tx";
347 status = "disabled";
348 };
349
350 uartd: serial@70006300 {
351 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
352 reg = <0x70006300 0x100>;
353 reg-shift = <2>;
354 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
356 resets = <&tegra_car 65>;
357 reset-names = "serial";
358 dmas = <&apbdma 19>, <&apbdma 19>;
359 dma-names = "rx", "tx";
360 status = "disabled";
361 };
362
363 pwm: pwm@7000a000 {
364 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
365 reg = <0x7000a000 0x100>;
366 #pwm-cells = <2>;
367 clocks = <&tegra_car TEGRA114_CLK_PWM>;
368 resets = <&tegra_car 17>;
369 reset-names = "pwm";
370 status = "disabled";
371 };
372
373 i2c@7000c000 {
374 compatible = "nvidia,tegra114-i2c";
375 reg = <0x7000c000 0x100>;
376 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
380 clock-names = "div-clk";
381 resets = <&tegra_car 12>;
382 reset-names = "i2c";
383 dmas = <&apbdma 21>, <&apbdma 21>;
384 dma-names = "rx", "tx";
385 status = "disabled";
386 };
387
388 i2c@7000c400 {
389 compatible = "nvidia,tegra114-i2c";
390 reg = <0x7000c400 0x100>;
391 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
395 clock-names = "div-clk";
396 resets = <&tegra_car 54>;
397 reset-names = "i2c";
398 dmas = <&apbdma 22>, <&apbdma 22>;
399 dma-names = "rx", "tx";
400 status = "disabled";
401 };
402
403 i2c@7000c500 {
404 compatible = "nvidia,tegra114-i2c";
405 reg = <0x7000c500 0x100>;
406 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
410 clock-names = "div-clk";
411 resets = <&tegra_car 67>;
412 reset-names = "i2c";
413 dmas = <&apbdma 23>, <&apbdma 23>;
414 dma-names = "rx", "tx";
415 status = "disabled";
416 };
417
418 i2c@7000c700 {
419 compatible = "nvidia,tegra114-i2c";
420 reg = <0x7000c700 0x100>;
421 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
423 #size-cells = <0>;
424 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
425 clock-names = "div-clk";
426 resets = <&tegra_car 103>;
427 reset-names = "i2c";
428 dmas = <&apbdma 26>, <&apbdma 26>;
429 dma-names = "rx", "tx";
430 status = "disabled";
431 };
432
433 i2c@7000d000 {
434 compatible = "nvidia,tegra114-i2c";
435 reg = <0x7000d000 0x100>;
436 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
440 clock-names = "div-clk";
441 resets = <&tegra_car 47>;
442 reset-names = "i2c";
443 dmas = <&apbdma 24>, <&apbdma 24>;
444 dma-names = "rx", "tx";
445 status = "disabled";
446 };
447
448 spi@7000d400 {
449 compatible = "nvidia,tegra114-spi";
450 reg = <0x7000d400 0x200>;
451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
455 clock-names = "spi";
456 resets = <&tegra_car 41>;
457 reset-names = "spi";
458 dmas = <&apbdma 15>, <&apbdma 15>;
459 dma-names = "rx", "tx";
460 status = "disabled";
461 };
462
463 spi@7000d600 {
464 compatible = "nvidia,tegra114-spi";
465 reg = <0x7000d600 0x200>;
466 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
470 clock-names = "spi";
471 resets = <&tegra_car 44>;
472 reset-names = "spi";
473 dmas = <&apbdma 16>, <&apbdma 16>;
474 dma-names = "rx", "tx";
475 status = "disabled";
476 };
477
478 spi@7000d800 {
479 compatible = "nvidia,tegra114-spi";
480 reg = <0x7000d800 0x200>;
481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
485 clock-names = "spi";
486 resets = <&tegra_car 46>;
487 reset-names = "spi";
488 dmas = <&apbdma 17>, <&apbdma 17>;
489 dma-names = "rx", "tx";
490 status = "disabled";
491 };
492
493 spi@7000da00 {
494 compatible = "nvidia,tegra114-spi";
495 reg = <0x7000da00 0x200>;
496 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
500 clock-names = "spi";
501 resets = <&tegra_car 68>;
502 reset-names = "spi";
503 dmas = <&apbdma 18>, <&apbdma 18>;
504 dma-names = "rx", "tx";
505 status = "disabled";
506 };
507
508 spi@7000dc00 {
509 compatible = "nvidia,tegra114-spi";
510 reg = <0x7000dc00 0x200>;
511 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
515 clock-names = "spi";
516 resets = <&tegra_car 104>;
517 reset-names = "spi";
518 dmas = <&apbdma 27>, <&apbdma 27>;
519 dma-names = "rx", "tx";
520 status = "disabled";
521 };
522
523 spi@7000de00 {
524 compatible = "nvidia,tegra114-spi";
525 reg = <0x7000de00 0x200>;
526 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
530 clock-names = "spi";
531 resets = <&tegra_car 105>;
532 reset-names = "spi";
533 dmas = <&apbdma 28>, <&apbdma 28>;
534 dma-names = "rx", "tx";
535 status = "disabled";
536 };
537
538 rtc@7000e000 {
539 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
540 reg = <0x7000e000 0x100>;
541 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&tegra_car TEGRA114_CLK_RTC>;
543 };
544
545 kbc@7000e200 {
546 compatible = "nvidia,tegra114-kbc";
547 reg = <0x7000e200 0x100>;
548 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&tegra_car TEGRA114_CLK_KBC>;
550 resets = <&tegra_car 36>;
551 reset-names = "kbc";
552 status = "disabled";
553 };
554
555 tegra_pmc: pmc@7000e400 {
556 compatible = "nvidia,tegra114-pmc";
557 reg = <0x7000e400 0x400>;
558 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
559 clock-names = "pclk", "clk32k_in";
560 #clock-cells = <1>;
561 };
562
563 fuse@7000f800 {
564 compatible = "nvidia,tegra114-efuse";
565 reg = <0x7000f800 0x400>;
566 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
567 clock-names = "fuse";
568 resets = <&tegra_car 39>;
569 reset-names = "fuse";
570 };
571
572 mc: memory-controller@70019000 {
573 compatible = "nvidia,tegra114-mc";
574 reg = <0x70019000 0x1000>;
575 clocks = <&tegra_car TEGRA114_CLK_MC>;
576 clock-names = "mc";
577
578 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
579
580 #reset-cells = <1>;
581 #iommu-cells = <1>;
582 };
583
584 ahub@70080000 {
585 compatible = "nvidia,tegra114-ahub";
586 reg = <0x70080000 0x200>,
587 <0x70080200 0x100>,
588 <0x70081000 0x200>;
589 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
591 <&tegra_car TEGRA114_CLK_APBIF>;
592 clock-names = "d_audio", "apbif";
593 resets = <&tegra_car 106>, /* d_audio */
594 <&tegra_car 107>, /* apbif */
595 <&tegra_car 30>, /* i2s0 */
596 <&tegra_car 11>, /* i2s1 */
597 <&tegra_car 18>, /* i2s2 */
598 <&tegra_car 101>, /* i2s3 */
599 <&tegra_car 102>, /* i2s4 */
600 <&tegra_car 108>, /* dam0 */
601 <&tegra_car 109>, /* dam1 */
602 <&tegra_car 110>, /* dam2 */
603 <&tegra_car 10>, /* spdif */
604 <&tegra_car 153>, /* amx */
605 <&tegra_car 154>; /* adx */
606 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
607 "i2s3", "i2s4", "dam0", "dam1", "dam2",
608 "spdif", "amx", "adx";
609 dmas = <&apbdma 1>, <&apbdma 1>,
610 <&apbdma 2>, <&apbdma 2>,
611 <&apbdma 3>, <&apbdma 3>,
612 <&apbdma 4>, <&apbdma 4>,
613 <&apbdma 6>, <&apbdma 6>,
614 <&apbdma 7>, <&apbdma 7>,
615 <&apbdma 12>, <&apbdma 12>,
616 <&apbdma 13>, <&apbdma 13>,
617 <&apbdma 14>, <&apbdma 14>,
618 <&apbdma 29>, <&apbdma 29>;
619 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
620 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
621 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
622 "rx9", "tx9";
623 ranges;
624 #address-cells = <1>;
625 #size-cells = <1>;
626
627 tegra_i2s0: i2s@70080300 {
628 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
629 reg = <0x70080300 0x100>;
630 nvidia,ahub-cif-ids = <4 4>;
631 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
632 resets = <&tegra_car 30>;
633 reset-names = "i2s";
634 status = "disabled";
635 };
636
637 tegra_i2s1: i2s@70080400 {
638 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
639 reg = <0x70080400 0x100>;
640 nvidia,ahub-cif-ids = <5 5>;
641 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
642 resets = <&tegra_car 11>;
643 reset-names = "i2s";
644 status = "disabled";
645 };
646
647 tegra_i2s2: i2s@70080500 {
648 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
649 reg = <0x70080500 0x100>;
650 nvidia,ahub-cif-ids = <6 6>;
651 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
652 resets = <&tegra_car 18>;
653 reset-names = "i2s";
654 status = "disabled";
655 };
656
657 tegra_i2s3: i2s@70080600 {
658 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
659 reg = <0x70080600 0x100>;
660 nvidia,ahub-cif-ids = <7 7>;
661 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
662 resets = <&tegra_car 101>;
663 reset-names = "i2s";
664 status = "disabled";
665 };
666
667 tegra_i2s4: i2s@70080700 {
668 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
669 reg = <0x70080700 0x100>;
670 nvidia,ahub-cif-ids = <8 8>;
671 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
672 resets = <&tegra_car 102>;
673 reset-names = "i2s";
674 status = "disabled";
675 };
676 };
677
678 mipi: mipi@700e3000 {
679 compatible = "nvidia,tegra114-mipi";
680 reg = <0x700e3000 0x100>;
681 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
682 #nvidia,mipi-calibrate-cells = <1>;
683 };
684
685 mmc@78000000 {
686 compatible = "nvidia,tegra114-sdhci";
687 reg = <0x78000000 0x200>;
688 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
690 clock-names = "sdhci";
691 resets = <&tegra_car 14>;
692 reset-names = "sdhci";
693 status = "disabled";
694 };
695
696 mmc@78000200 {
697 compatible = "nvidia,tegra114-sdhci";
698 reg = <0x78000200 0x200>;
699 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
701 clock-names = "sdhci";
702 resets = <&tegra_car 9>;
703 reset-names = "sdhci";
704 status = "disabled";
705 };
706
707 mmc@78000400 {
708 compatible = "nvidia,tegra114-sdhci";
709 reg = <0x78000400 0x200>;
710 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
712 clock-names = "sdhci";
713 resets = <&tegra_car 69>;
714 reset-names = "sdhci";
715 status = "disabled";
716 };
717
718 mmc@78000600 {
719 compatible = "nvidia,tegra114-sdhci";
720 reg = <0x78000600 0x200>;
721 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
723 clock-names = "sdhci";
724 resets = <&tegra_car 15>;
725 reset-names = "sdhci";
726 status = "disabled";
727 };
728
729 usb@7d000000 {
730 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
731 reg = <0x7d000000 0x4000>;
732 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
733 phy_type = "utmi";
734 clocks = <&tegra_car TEGRA114_CLK_USBD>;
735 resets = <&tegra_car 22>;
736 reset-names = "usb";
737 nvidia,phy = <&phy1>;
738 status = "disabled";
739 };
740
741 phy1: usb-phy@7d000000 {
742 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
743 reg = <0x7d000000 0x4000>,
744 <0x7d000000 0x4000>;
745 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
746 phy_type = "utmi";
747 clocks = <&tegra_car TEGRA114_CLK_USBD>,
748 <&tegra_car TEGRA114_CLK_PLL_U>,
749 <&tegra_car TEGRA114_CLK_USBD>;
750 clock-names = "reg", "pll_u", "utmi-pads";
751 resets = <&tegra_car 22>, <&tegra_car 22>;
752 reset-names = "usb", "utmi-pads";
753 #phy-cells = <0>;
754 nvidia,hssync-start-delay = <0>;
755 nvidia,idle-wait-delay = <17>;
756 nvidia,elastic-limit = <16>;
757 nvidia,term-range-adj = <6>;
758 nvidia,xcvr-setup = <9>;
759 nvidia,xcvr-lsfslew = <0>;
760 nvidia,xcvr-lsrslew = <3>;
761 nvidia,hssquelch-level = <2>;
762 nvidia,hsdiscon-level = <5>;
763 nvidia,xcvr-hsslew = <12>;
764 nvidia,has-utmi-pad-registers;
765 nvidia,pmc = <&tegra_pmc 0>;
766 status = "disabled";
767 };
768
769 usb@7d008000 {
770 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
771 reg = <0x7d008000 0x4000>;
772 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
773 phy_type = "utmi";
774 clocks = <&tegra_car TEGRA114_CLK_USB3>;
775 resets = <&tegra_car 59>;
776 reset-names = "usb";
777 nvidia,phy = <&phy3>;
778 status = "disabled";
779 };
780
781 phy3: usb-phy@7d008000 {
782 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
783 reg = <0x7d008000 0x4000>,
784 <0x7d000000 0x4000>;
785 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
786 phy_type = "utmi";
787 clocks = <&tegra_car TEGRA114_CLK_USB3>,
788 <&tegra_car TEGRA114_CLK_PLL_U>,
789 <&tegra_car TEGRA114_CLK_USBD>;
790 clock-names = "reg", "pll_u", "utmi-pads";
791 resets = <&tegra_car 59>, <&tegra_car 22>;
792 reset-names = "usb", "utmi-pads";
793 #phy-cells = <0>;
794 nvidia,hssync-start-delay = <0>;
795 nvidia,idle-wait-delay = <17>;
796 nvidia,elastic-limit = <16>;
797 nvidia,term-range-adj = <6>;
798 nvidia,xcvr-setup = <9>;
799 nvidia,xcvr-lsfslew = <0>;
800 nvidia,xcvr-lsrslew = <3>;
801 nvidia,hssquelch-level = <2>;
802 nvidia,hsdiscon-level = <5>;
803 nvidia,xcvr-hsslew = <12>;
804 nvidia,pmc = <&tegra_pmc 2>;
805 status = "disabled";
806 };
807
808 cpus {
809 #address-cells = <1>;
810 #size-cells = <0>;
811
812 cpu@0 {
813 device_type = "cpu";
814 compatible = "arm,cortex-a15";
815 reg = <0>;
816 };
817
818 cpu@1 {
819 device_type = "cpu";
820 compatible = "arm,cortex-a15";
821 reg = <1>;
822 };
823
824 cpu@2 {
825 device_type = "cpu";
826 compatible = "arm,cortex-a15";
827 reg = <2>;
828 };
829
830 cpu@3 {
831 device_type = "cpu";
832 compatible = "arm,cortex-a15";
833 reg = <3>;
834 };
835 };
836
837 timer {
838 compatible = "arm,armv7-timer";
839 interrupts =
840 <GIC_PPI 13
841 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
842 <GIC_PPI 14
843 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
844 <GIC_PPI 11
845 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
846 <GIC_PPI 10
847 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
848 interrupt-parent = <&gic>;
849 };
850};
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra114-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra114-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/soc/tegra-pmc.h>
8
9/ {
10 compatible = "nvidia,tegra114";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 memory@80000000 {
16 device_type = "memory";
17 reg = <0x80000000 0x0>;
18 };
19
20 host1x@50000000 {
21 compatible = "nvidia,tegra114-host1x";
22 reg = <0x50000000 0x00028000>;
23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
24 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
25 interrupt-names = "syncpt", "host1x";
26 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
27 clock-names = "host1x";
28 resets = <&tegra_car 28>;
29 reset-names = "host1x";
30 iommus = <&mc TEGRA_SWGROUP_HC>;
31
32 #address-cells = <1>;
33 #size-cells = <1>;
34
35 ranges = <0x54000000 0x54000000 0x01000000>;
36
37 gr2d@54140000 {
38 compatible = "nvidia,tegra114-gr2d";
39 reg = <0x54140000 0x00040000>;
40 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
41 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
42 resets = <&tegra_car 21>;
43 reset-names = "2d";
44
45 iommus = <&mc TEGRA_SWGROUP_G2>;
46 };
47
48 gr3d@54180000 {
49 compatible = "nvidia,tegra114-gr3d";
50 reg = <0x54180000 0x00040000>;
51 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
52 resets = <&tegra_car 24>;
53 reset-names = "3d";
54
55 iommus = <&mc TEGRA_SWGROUP_NV>;
56 };
57
58 dc@54200000 {
59 compatible = "nvidia,tegra114-dc";
60 reg = <0x54200000 0x00040000>;
61 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
62 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
63 <&tegra_car TEGRA114_CLK_PLL_P>;
64 clock-names = "dc", "parent";
65 resets = <&tegra_car 27>;
66 reset-names = "dc";
67
68 iommus = <&mc TEGRA_SWGROUP_DC>;
69
70 nvidia,head = <0>;
71
72 rgb {
73 status = "disabled";
74 };
75 };
76
77 dc@54240000 {
78 compatible = "nvidia,tegra114-dc";
79 reg = <0x54240000 0x00040000>;
80 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
82 <&tegra_car TEGRA114_CLK_PLL_P>;
83 clock-names = "dc", "parent";
84 resets = <&tegra_car 26>;
85 reset-names = "dc";
86
87 iommus = <&mc TEGRA_SWGROUP_DCB>;
88
89 nvidia,head = <1>;
90
91 rgb {
92 status = "disabled";
93 };
94 };
95
96 hdmi@54280000 {
97 compatible = "nvidia,tegra114-hdmi";
98 reg = <0x54280000 0x00040000>;
99 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
101 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
102 clock-names = "hdmi", "parent";
103 resets = <&tegra_car 51>;
104 reset-names = "hdmi";
105 status = "disabled";
106 };
107
108 dsi@54300000 {
109 compatible = "nvidia,tegra114-dsi";
110 reg = <0x54300000 0x00040000>;
111 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
112 <&tegra_car TEGRA114_CLK_DSIALP>,
113 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
114 clock-names = "dsi", "lp", "parent";
115 resets = <&tegra_car 48>;
116 reset-names = "dsi";
117 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
118 status = "disabled";
119
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
123
124 dsi@54400000 {
125 compatible = "nvidia,tegra114-dsi";
126 reg = <0x54400000 0x00040000>;
127 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
128 <&tegra_car TEGRA114_CLK_DSIBLP>,
129 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
130 clock-names = "dsi", "lp", "parent";
131 resets = <&tegra_car 82>;
132 reset-names = "dsi";
133 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
134 status = "disabled";
135
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139 };
140
141 gic: interrupt-controller@50041000 {
142 compatible = "arm,cortex-a15-gic";
143 #interrupt-cells = <3>;
144 interrupt-controller;
145 reg = <0x50041000 0x1000>,
146 <0x50042000 0x1000>,
147 <0x50044000 0x2000>,
148 <0x50046000 0x2000>;
149 interrupts = <GIC_PPI 9
150 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151 interrupt-parent = <&gic>;
152 };
153
154 lic: interrupt-controller@60004000 {
155 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
156 reg = <0x60004000 0x100>,
157 <0x60004100 0x50>,
158 <0x60004200 0x50>,
159 <0x60004300 0x50>,
160 <0x60004400 0x50>;
161 interrupt-controller;
162 #interrupt-cells = <3>;
163 interrupt-parent = <&gic>;
164 };
165
166 timer@60005000 {
167 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
168 reg = <0x60005000 0x400>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
176 };
177
178 tegra_car: clock@60006000 {
179 compatible = "nvidia,tegra114-car";
180 reg = <0x60006000 0x1000>;
181 #clock-cells = <1>;
182 #reset-cells = <1>;
183 };
184
185 flow-controller@60007000 {
186 compatible = "nvidia,tegra114-flowctrl";
187 reg = <0x60007000 0x1000>;
188 };
189
190 apbdma: dma@6000a000 {
191 compatible = "nvidia,tegra114-apbdma";
192 reg = <0x6000a000 0x1400>;
193 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
226 resets = <&tegra_car 34>;
227 reset-names = "dma";
228 #dma-cells = <1>;
229 };
230
231 ahb: ahb@6000c000 {
232 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
233 reg = <0x6000c000 0x150>;
234 };
235
236 gpio: gpio@6000d000 {
237 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
238 reg = <0x6000d000 0x1000>;
239 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 #interrupt-cells = <2>;
250 interrupt-controller;
251 /*
252 gpio-ranges = <&pinmux 0 0 246>;
253 */
254 };
255
256 apbmisc@70000800 {
257 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
258 reg = <0x70000800 0x64>, /* Chip revision */
259 <0x70000008 0x04>; /* Strapping options */
260 };
261
262 pinmux: pinmux@70000868 {
263 compatible = "nvidia,tegra114-pinmux";
264 reg = <0x70000868 0x148>, /* Pad control registers */
265 <0x70003000 0x40c>; /* Mux registers */
266 };
267
268 /*
269 * There are two serial driver i.e. 8250 based simple serial
270 * driver and APB DMA based serial driver for higher baudrate
271 * and performace. To enable the 8250 based driver, the compatible
272 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
273 * the APB DMA based serial driver, the compatible is
274 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
275 */
276 uarta: serial@70006000 {
277 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
278 reg = <0x70006000 0x40>;
279 reg-shift = <2>;
280 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
282 resets = <&tegra_car 6>;
283 reset-names = "serial";
284 dmas = <&apbdma 8>, <&apbdma 8>;
285 dma-names = "rx", "tx";
286 status = "disabled";
287 };
288
289 uartb: serial@70006040 {
290 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
291 reg = <0x70006040 0x40>;
292 reg-shift = <2>;
293 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
295 resets = <&tegra_car 7>;
296 reset-names = "serial";
297 dmas = <&apbdma 9>, <&apbdma 9>;
298 dma-names = "rx", "tx";
299 status = "disabled";
300 };
301
302 uartc: serial@70006200 {
303 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
304 reg = <0x70006200 0x100>;
305 reg-shift = <2>;
306 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
308 resets = <&tegra_car 55>;
309 reset-names = "serial";
310 dmas = <&apbdma 10>, <&apbdma 10>;
311 dma-names = "rx", "tx";
312 status = "disabled";
313 };
314
315 uartd: serial@70006300 {
316 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
317 reg = <0x70006300 0x100>;
318 reg-shift = <2>;
319 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
321 resets = <&tegra_car 65>;
322 reset-names = "serial";
323 dmas = <&apbdma 19>, <&apbdma 19>;
324 dma-names = "rx", "tx";
325 status = "disabled";
326 };
327
328 pwm: pwm@7000a000 {
329 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
330 reg = <0x7000a000 0x100>;
331 #pwm-cells = <2>;
332 clocks = <&tegra_car TEGRA114_CLK_PWM>;
333 resets = <&tegra_car 17>;
334 reset-names = "pwm";
335 status = "disabled";
336 };
337
338 i2c@7000c000 {
339 compatible = "nvidia,tegra114-i2c";
340 reg = <0x7000c000 0x100>;
341 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
345 clock-names = "div-clk";
346 resets = <&tegra_car 12>;
347 reset-names = "i2c";
348 dmas = <&apbdma 21>, <&apbdma 21>;
349 dma-names = "rx", "tx";
350 status = "disabled";
351 };
352
353 i2c@7000c400 {
354 compatible = "nvidia,tegra114-i2c";
355 reg = <0x7000c400 0x100>;
356 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
360 clock-names = "div-clk";
361 resets = <&tegra_car 54>;
362 reset-names = "i2c";
363 dmas = <&apbdma 22>, <&apbdma 22>;
364 dma-names = "rx", "tx";
365 status = "disabled";
366 };
367
368 i2c@7000c500 {
369 compatible = "nvidia,tegra114-i2c";
370 reg = <0x7000c500 0x100>;
371 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
375 clock-names = "div-clk";
376 resets = <&tegra_car 67>;
377 reset-names = "i2c";
378 dmas = <&apbdma 23>, <&apbdma 23>;
379 dma-names = "rx", "tx";
380 status = "disabled";
381 };
382
383 i2c@7000c700 {
384 compatible = "nvidia,tegra114-i2c";
385 reg = <0x7000c700 0x100>;
386 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
390 clock-names = "div-clk";
391 resets = <&tegra_car 103>;
392 reset-names = "i2c";
393 dmas = <&apbdma 26>, <&apbdma 26>;
394 dma-names = "rx", "tx";
395 status = "disabled";
396 };
397
398 i2c@7000d000 {
399 compatible = "nvidia,tegra114-i2c";
400 reg = <0x7000d000 0x100>;
401 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
405 clock-names = "div-clk";
406 resets = <&tegra_car 47>;
407 reset-names = "i2c";
408 dmas = <&apbdma 24>, <&apbdma 24>;
409 dma-names = "rx", "tx";
410 status = "disabled";
411 };
412
413 spi@7000d400 {
414 compatible = "nvidia,tegra114-spi";
415 reg = <0x7000d400 0x200>;
416 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
420 clock-names = "spi";
421 resets = <&tegra_car 41>;
422 reset-names = "spi";
423 dmas = <&apbdma 15>, <&apbdma 15>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 };
427
428 spi@7000d600 {
429 compatible = "nvidia,tegra114-spi";
430 reg = <0x7000d600 0x200>;
431 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
435 clock-names = "spi";
436 resets = <&tegra_car 44>;
437 reset-names = "spi";
438 dmas = <&apbdma 16>, <&apbdma 16>;
439 dma-names = "rx", "tx";
440 status = "disabled";
441 };
442
443 spi@7000d800 {
444 compatible = "nvidia,tegra114-spi";
445 reg = <0x7000d800 0x200>;
446 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
450 clock-names = "spi";
451 resets = <&tegra_car 46>;
452 reset-names = "spi";
453 dmas = <&apbdma 17>, <&apbdma 17>;
454 dma-names = "rx", "tx";
455 status = "disabled";
456 };
457
458 spi@7000da00 {
459 compatible = "nvidia,tegra114-spi";
460 reg = <0x7000da00 0x200>;
461 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
465 clock-names = "spi";
466 resets = <&tegra_car 68>;
467 reset-names = "spi";
468 dmas = <&apbdma 18>, <&apbdma 18>;
469 dma-names = "rx", "tx";
470 status = "disabled";
471 };
472
473 spi@7000dc00 {
474 compatible = "nvidia,tegra114-spi";
475 reg = <0x7000dc00 0x200>;
476 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
480 clock-names = "spi";
481 resets = <&tegra_car 104>;
482 reset-names = "spi";
483 dmas = <&apbdma 27>, <&apbdma 27>;
484 dma-names = "rx", "tx";
485 status = "disabled";
486 };
487
488 spi@7000de00 {
489 compatible = "nvidia,tegra114-spi";
490 reg = <0x7000de00 0x200>;
491 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
495 clock-names = "spi";
496 resets = <&tegra_car 105>;
497 reset-names = "spi";
498 dmas = <&apbdma 28>, <&apbdma 28>;
499 dma-names = "rx", "tx";
500 status = "disabled";
501 };
502
503 rtc@7000e000 {
504 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
505 reg = <0x7000e000 0x100>;
506 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&tegra_car TEGRA114_CLK_RTC>;
508 };
509
510 kbc@7000e200 {
511 compatible = "nvidia,tegra114-kbc";
512 reg = <0x7000e200 0x100>;
513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&tegra_car TEGRA114_CLK_KBC>;
515 resets = <&tegra_car 36>;
516 reset-names = "kbc";
517 status = "disabled";
518 };
519
520 tegra_pmc: pmc@7000e400 {
521 compatible = "nvidia,tegra114-pmc";
522 reg = <0x7000e400 0x400>;
523 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
524 clock-names = "pclk", "clk32k_in";
525 #clock-cells = <1>;
526 };
527
528 fuse@7000f800 {
529 compatible = "nvidia,tegra114-efuse";
530 reg = <0x7000f800 0x400>;
531 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
532 clock-names = "fuse";
533 resets = <&tegra_car 39>;
534 reset-names = "fuse";
535 };
536
537 mc: memory-controller@70019000 {
538 compatible = "nvidia,tegra114-mc";
539 reg = <0x70019000 0x1000>;
540 clocks = <&tegra_car TEGRA114_CLK_MC>;
541 clock-names = "mc";
542
543 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
544
545 #iommu-cells = <1>;
546 };
547
548 ahub@70080000 {
549 compatible = "nvidia,tegra114-ahub";
550 reg = <0x70080000 0x200>,
551 <0x70080200 0x100>,
552 <0x70081000 0x200>;
553 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
555 <&tegra_car TEGRA114_CLK_APBIF>;
556 clock-names = "d_audio", "apbif";
557 resets = <&tegra_car 106>, /* d_audio */
558 <&tegra_car 107>, /* apbif */
559 <&tegra_car 30>, /* i2s0 */
560 <&tegra_car 11>, /* i2s1 */
561 <&tegra_car 18>, /* i2s2 */
562 <&tegra_car 101>, /* i2s3 */
563 <&tegra_car 102>, /* i2s4 */
564 <&tegra_car 108>, /* dam0 */
565 <&tegra_car 109>, /* dam1 */
566 <&tegra_car 110>, /* dam2 */
567 <&tegra_car 10>, /* spdif */
568 <&tegra_car 153>, /* amx */
569 <&tegra_car 154>; /* adx */
570 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
571 "i2s3", "i2s4", "dam0", "dam1", "dam2",
572 "spdif", "amx", "adx";
573 dmas = <&apbdma 1>, <&apbdma 1>,
574 <&apbdma 2>, <&apbdma 2>,
575 <&apbdma 3>, <&apbdma 3>,
576 <&apbdma 4>, <&apbdma 4>,
577 <&apbdma 6>, <&apbdma 6>,
578 <&apbdma 7>, <&apbdma 7>,
579 <&apbdma 12>, <&apbdma 12>,
580 <&apbdma 13>, <&apbdma 13>,
581 <&apbdma 14>, <&apbdma 14>,
582 <&apbdma 29>, <&apbdma 29>;
583 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
584 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
585 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
586 "rx9", "tx9";
587 ranges;
588 #address-cells = <1>;
589 #size-cells = <1>;
590
591 tegra_i2s0: i2s@70080300 {
592 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
593 reg = <0x70080300 0x100>;
594 nvidia,ahub-cif-ids = <4 4>;
595 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
596 resets = <&tegra_car 30>;
597 reset-names = "i2s";
598 status = "disabled";
599 };
600
601 tegra_i2s1: i2s@70080400 {
602 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
603 reg = <0x70080400 0x100>;
604 nvidia,ahub-cif-ids = <5 5>;
605 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
606 resets = <&tegra_car 11>;
607 reset-names = "i2s";
608 status = "disabled";
609 };
610
611 tegra_i2s2: i2s@70080500 {
612 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
613 reg = <0x70080500 0x100>;
614 nvidia,ahub-cif-ids = <6 6>;
615 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
616 resets = <&tegra_car 18>;
617 reset-names = "i2s";
618 status = "disabled";
619 };
620
621 tegra_i2s3: i2s@70080600 {
622 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
623 reg = <0x70080600 0x100>;
624 nvidia,ahub-cif-ids = <7 7>;
625 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
626 resets = <&tegra_car 101>;
627 reset-names = "i2s";
628 status = "disabled";
629 };
630
631 tegra_i2s4: i2s@70080700 {
632 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
633 reg = <0x70080700 0x100>;
634 nvidia,ahub-cif-ids = <8 8>;
635 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
636 resets = <&tegra_car 102>;
637 reset-names = "i2s";
638 status = "disabled";
639 };
640 };
641
642 mipi: mipi@700e3000 {
643 compatible = "nvidia,tegra114-mipi";
644 reg = <0x700e3000 0x100>;
645 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
646 #nvidia,mipi-calibrate-cells = <1>;
647 };
648
649 mmc@78000000 {
650 compatible = "nvidia,tegra114-sdhci";
651 reg = <0x78000000 0x200>;
652 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
654 clock-names = "sdhci";
655 resets = <&tegra_car 14>;
656 reset-names = "sdhci";
657 status = "disabled";
658 };
659
660 mmc@78000200 {
661 compatible = "nvidia,tegra114-sdhci";
662 reg = <0x78000200 0x200>;
663 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
665 clock-names = "sdhci";
666 resets = <&tegra_car 9>;
667 reset-names = "sdhci";
668 status = "disabled";
669 };
670
671 mmc@78000400 {
672 compatible = "nvidia,tegra114-sdhci";
673 reg = <0x78000400 0x200>;
674 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
676 clock-names = "sdhci";
677 resets = <&tegra_car 69>;
678 reset-names = "sdhci";
679 status = "disabled";
680 };
681
682 mmc@78000600 {
683 compatible = "nvidia,tegra114-sdhci";
684 reg = <0x78000600 0x200>;
685 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
687 clock-names = "sdhci";
688 resets = <&tegra_car 15>;
689 reset-names = "sdhci";
690 status = "disabled";
691 };
692
693 usb@7d000000 {
694 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
695 reg = <0x7d000000 0x4000>;
696 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
697 phy_type = "utmi";
698 clocks = <&tegra_car TEGRA114_CLK_USBD>;
699 resets = <&tegra_car 22>;
700 reset-names = "usb";
701 nvidia,phy = <&phy1>;
702 status = "disabled";
703 };
704
705 phy1: usb-phy@7d000000 {
706 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
707 reg = <0x7d000000 0x4000>,
708 <0x7d000000 0x4000>;
709 phy_type = "utmi";
710 clocks = <&tegra_car TEGRA114_CLK_USBD>,
711 <&tegra_car TEGRA114_CLK_PLL_U>,
712 <&tegra_car TEGRA114_CLK_USBD>;
713 clock-names = "reg", "pll_u", "utmi-pads";
714 resets = <&tegra_car 22>, <&tegra_car 22>;
715 reset-names = "usb", "utmi-pads";
716 #phy-cells = <0>;
717 nvidia,hssync-start-delay = <0>;
718 nvidia,idle-wait-delay = <17>;
719 nvidia,elastic-limit = <16>;
720 nvidia,term-range-adj = <6>;
721 nvidia,xcvr-setup = <9>;
722 nvidia,xcvr-lsfslew = <0>;
723 nvidia,xcvr-lsrslew = <3>;
724 nvidia,hssquelch-level = <2>;
725 nvidia,hsdiscon-level = <5>;
726 nvidia,xcvr-hsslew = <12>;
727 nvidia,has-utmi-pad-registers;
728 status = "disabled";
729 };
730
731 usb@7d008000 {
732 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
733 reg = <0x7d008000 0x4000>;
734 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
735 phy_type = "utmi";
736 clocks = <&tegra_car TEGRA114_CLK_USB3>;
737 resets = <&tegra_car 59>;
738 reset-names = "usb";
739 nvidia,phy = <&phy3>;
740 status = "disabled";
741 };
742
743 phy3: usb-phy@7d008000 {
744 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
745 reg = <0x7d008000 0x4000>,
746 <0x7d000000 0x4000>;
747 phy_type = "utmi";
748 clocks = <&tegra_car TEGRA114_CLK_USB3>,
749 <&tegra_car TEGRA114_CLK_PLL_U>,
750 <&tegra_car TEGRA114_CLK_USBD>;
751 clock-names = "reg", "pll_u", "utmi-pads";
752 resets = <&tegra_car 59>, <&tegra_car 22>;
753 reset-names = "usb", "utmi-pads";
754 #phy-cells = <0>;
755 nvidia,hssync-start-delay = <0>;
756 nvidia,idle-wait-delay = <17>;
757 nvidia,elastic-limit = <16>;
758 nvidia,term-range-adj = <6>;
759 nvidia,xcvr-setup = <9>;
760 nvidia,xcvr-lsfslew = <0>;
761 nvidia,xcvr-lsrslew = <3>;
762 nvidia,hssquelch-level = <2>;
763 nvidia,hsdiscon-level = <5>;
764 nvidia,xcvr-hsslew = <12>;
765 status = "disabled";
766 };
767
768 cpus {
769 #address-cells = <1>;
770 #size-cells = <0>;
771
772 cpu@0 {
773 device_type = "cpu";
774 compatible = "arm,cortex-a15";
775 reg = <0>;
776 };
777
778 cpu@1 {
779 device_type = "cpu";
780 compatible = "arm,cortex-a15";
781 reg = <1>;
782 };
783
784 cpu@2 {
785 device_type = "cpu";
786 compatible = "arm,cortex-a15";
787 reg = <2>;
788 };
789
790 cpu@3 {
791 device_type = "cpu";
792 compatible = "arm,cortex-a15";
793 reg = <3>;
794 };
795 };
796
797 timer {
798 compatible = "arm,armv7-timer";
799 interrupts =
800 <GIC_PPI 13
801 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
802 <GIC_PPI 14
803 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
804 <GIC_PPI 11
805 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
806 <GIC_PPI 10
807 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
808 interrupt-parent = <&gic>;
809 };
810};