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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 arm-pmu {
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
31 };
32
33 psci {
34 compatible = "arm,psci-1.0";
35 method = "smc";
36 };
37
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
53 };
54
55 clocks {
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
66 };
67
68 clk_lse: clk-lse {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 clk_lsi: clk-lsi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 };
79
80 clk_csi: clk-csi {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
84 };
85 };
86
87 thermal-zones {
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
90 polling-delay = <0>;
91 thermal-sensors = <&dts>;
92
93 trips {
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
96 hysteresis = <0>;
97 type = "passive";
98 };
99
100 cpu-crit {
101 temperature = <120000>;
102 hysteresis = <0>;
103 type = "critical";
104 };
105 };
106
107 cooling-maps {
108 };
109 };
110 };
111
112 booster: regulator-booster {
113 compatible = "st,stm32mp1-booster";
114 st,syscfg = <&syscfg>;
115 status = "disabled";
116 };
117
118 soc {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 interrupt-parent = <&intc>;
123 ranges;
124
125 timers2: timer@40000000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "st,stm32-timers";
129 reg = <0x40000000 0x400>;
130 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-names = "global";
132 clocks = <&rcc TIM2_K>;
133 clock-names = "int";
134 dmas = <&dmamux1 18 0x400 0x1>,
135 <&dmamux1 19 0x400 0x1>,
136 <&dmamux1 20 0x400 0x1>,
137 <&dmamux1 21 0x400 0x1>,
138 <&dmamux1 22 0x400 0x1>;
139 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
140 status = "disabled";
141
142 pwm {
143 compatible = "st,stm32-pwm";
144 #pwm-cells = <3>;
145 status = "disabled";
146 };
147
148 timer@1 {
149 compatible = "st,stm32h7-timer-trigger";
150 reg = <1>;
151 status = "disabled";
152 };
153
154 counter {
155 compatible = "st,stm32-timer-counter";
156 status = "disabled";
157 };
158 };
159
160 timers3: timer@40001000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "st,stm32-timers";
164 reg = <0x40001000 0x400>;
165 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "global";
167 clocks = <&rcc TIM3_K>;
168 clock-names = "int";
169 dmas = <&dmamux1 23 0x400 0x1>,
170 <&dmamux1 24 0x400 0x1>,
171 <&dmamux1 25 0x400 0x1>,
172 <&dmamux1 26 0x400 0x1>,
173 <&dmamux1 27 0x400 0x1>,
174 <&dmamux1 28 0x400 0x1>;
175 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
176 status = "disabled";
177
178 pwm {
179 compatible = "st,stm32-pwm";
180 #pwm-cells = <3>;
181 status = "disabled";
182 };
183
184 timer@2 {
185 compatible = "st,stm32h7-timer-trigger";
186 reg = <2>;
187 status = "disabled";
188 };
189
190 counter {
191 compatible = "st,stm32-timer-counter";
192 status = "disabled";
193 };
194 };
195
196 timers4: timer@40002000 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "st,stm32-timers";
200 reg = <0x40002000 0x400>;
201 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "global";
203 clocks = <&rcc TIM4_K>;
204 clock-names = "int";
205 dmas = <&dmamux1 29 0x400 0x1>,
206 <&dmamux1 30 0x400 0x1>,
207 <&dmamux1 31 0x400 0x1>,
208 <&dmamux1 32 0x400 0x1>;
209 dma-names = "ch1", "ch2", "ch3", "ch4";
210 status = "disabled";
211
212 pwm {
213 compatible = "st,stm32-pwm";
214 #pwm-cells = <3>;
215 status = "disabled";
216 };
217
218 timer@3 {
219 compatible = "st,stm32h7-timer-trigger";
220 reg = <3>;
221 status = "disabled";
222 };
223
224 counter {
225 compatible = "st,stm32-timer-counter";
226 status = "disabled";
227 };
228 };
229
230 timers5: timer@40003000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "st,stm32-timers";
234 reg = <0x40003000 0x400>;
235 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "global";
237 clocks = <&rcc TIM5_K>;
238 clock-names = "int";
239 dmas = <&dmamux1 55 0x400 0x1>,
240 <&dmamux1 56 0x400 0x1>,
241 <&dmamux1 57 0x400 0x1>,
242 <&dmamux1 58 0x400 0x1>,
243 <&dmamux1 59 0x400 0x1>,
244 <&dmamux1 60 0x400 0x1>;
245 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
246 status = "disabled";
247
248 pwm {
249 compatible = "st,stm32-pwm";
250 #pwm-cells = <3>;
251 status = "disabled";
252 };
253
254 timer@4 {
255 compatible = "st,stm32h7-timer-trigger";
256 reg = <4>;
257 status = "disabled";
258 };
259
260 counter {
261 compatible = "st,stm32-timer-counter";
262 status = "disabled";
263 };
264 };
265
266 timers6: timer@40004000 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "st,stm32-timers";
270 reg = <0x40004000 0x400>;
271 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "global";
273 clocks = <&rcc TIM6_K>;
274 clock-names = "int";
275 dmas = <&dmamux1 69 0x400 0x1>;
276 dma-names = "up";
277 status = "disabled";
278
279 timer@5 {
280 compatible = "st,stm32h7-timer-trigger";
281 reg = <5>;
282 status = "disabled";
283 };
284 };
285
286 timers7: timer@40005000 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32-timers";
290 reg = <0x40005000 0x400>;
291 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-names = "global";
293 clocks = <&rcc TIM7_K>;
294 clock-names = "int";
295 dmas = <&dmamux1 70 0x400 0x1>;
296 dma-names = "up";
297 status = "disabled";
298
299 timer@6 {
300 compatible = "st,stm32h7-timer-trigger";
301 reg = <6>;
302 status = "disabled";
303 };
304 };
305
306 timers12: timer@40006000 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 compatible = "st,stm32-timers";
310 reg = <0x40006000 0x400>;
311 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "global";
313 clocks = <&rcc TIM12_K>;
314 clock-names = "int";
315 status = "disabled";
316
317 pwm {
318 compatible = "st,stm32-pwm";
319 #pwm-cells = <3>;
320 status = "disabled";
321 };
322
323 timer@11 {
324 compatible = "st,stm32h7-timer-trigger";
325 reg = <11>;
326 status = "disabled";
327 };
328 };
329
330 timers13: timer@40007000 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 compatible = "st,stm32-timers";
334 reg = <0x40007000 0x400>;
335 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "global";
337 clocks = <&rcc TIM13_K>;
338 clock-names = "int";
339 status = "disabled";
340
341 pwm {
342 compatible = "st,stm32-pwm";
343 #pwm-cells = <3>;
344 status = "disabled";
345 };
346
347 timer@12 {
348 compatible = "st,stm32h7-timer-trigger";
349 reg = <12>;
350 status = "disabled";
351 };
352 };
353
354 timers14: timer@40008000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "st,stm32-timers";
358 reg = <0x40008000 0x400>;
359 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "global";
361 clocks = <&rcc TIM14_K>;
362 clock-names = "int";
363 status = "disabled";
364
365 pwm {
366 compatible = "st,stm32-pwm";
367 #pwm-cells = <3>;
368 status = "disabled";
369 };
370
371 timer@13 {
372 compatible = "st,stm32h7-timer-trigger";
373 reg = <13>;
374 status = "disabled";
375 };
376 };
377
378 lptimer1: timer@40009000 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "st,stm32-lptimer";
382 reg = <0x40009000 0x400>;
383 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&rcc LPTIM1_K>;
385 clock-names = "mux";
386 wakeup-source;
387 status = "disabled";
388
389 pwm {
390 compatible = "st,stm32-pwm-lp";
391 #pwm-cells = <3>;
392 status = "disabled";
393 };
394
395 trigger@0 {
396 compatible = "st,stm32-lptimer-trigger";
397 reg = <0>;
398 status = "disabled";
399 };
400
401 counter {
402 compatible = "st,stm32-lptimer-counter";
403 status = "disabled";
404 };
405 };
406
407 spi2: spi@4000b000 {
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "st,stm32h7-spi";
411 reg = <0x4000b000 0x400>;
412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&rcc SPI2_K>;
414 resets = <&rcc SPI2_R>;
415 dmas = <&dmamux1 39 0x400 0x05>,
416 <&dmamux1 40 0x400 0x05>;
417 dma-names = "rx", "tx";
418 status = "disabled";
419 };
420
421 i2s2: audio-controller@4000b000 {
422 compatible = "st,stm32h7-i2s";
423 #sound-dai-cells = <0>;
424 reg = <0x4000b000 0x400>;
425 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&dmamux1 39 0x400 0x01>,
427 <&dmamux1 40 0x400 0x01>;
428 dma-names = "rx", "tx";
429 status = "disabled";
430 };
431
432 spi3: spi@4000c000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "st,stm32h7-spi";
436 reg = <0x4000c000 0x400>;
437 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&rcc SPI3_K>;
439 resets = <&rcc SPI3_R>;
440 dmas = <&dmamux1 61 0x400 0x05>,
441 <&dmamux1 62 0x400 0x05>;
442 dma-names = "rx", "tx";
443 status = "disabled";
444 };
445
446 i2s3: audio-controller@4000c000 {
447 compatible = "st,stm32h7-i2s";
448 #sound-dai-cells = <0>;
449 reg = <0x4000c000 0x400>;
450 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
451 dmas = <&dmamux1 61 0x400 0x01>,
452 <&dmamux1 62 0x400 0x01>;
453 dma-names = "rx", "tx";
454 status = "disabled";
455 };
456
457 spdifrx: audio-controller@4000d000 {
458 compatible = "st,stm32h7-spdifrx";
459 #sound-dai-cells = <0>;
460 reg = <0x4000d000 0x400>;
461 clocks = <&rcc SPDIF_K>;
462 clock-names = "kclk";
463 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
464 dmas = <&dmamux1 93 0x400 0x01>,
465 <&dmamux1 94 0x400 0x01>;
466 dma-names = "rx", "rx-ctrl";
467 status = "disabled";
468 };
469
470 usart2: serial@4000e000 {
471 compatible = "st,stm32h7-uart";
472 reg = <0x4000e000 0x400>;
473 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&rcc USART2_K>;
475 wakeup-source;
476 dmas = <&dmamux1 43 0x400 0x15>,
477 <&dmamux1 44 0x400 0x11>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
481
482 usart3: serial@4000f000 {
483 compatible = "st,stm32h7-uart";
484 reg = <0x4000f000 0x400>;
485 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&rcc USART3_K>;
487 wakeup-source;
488 dmas = <&dmamux1 45 0x400 0x15>,
489 <&dmamux1 46 0x400 0x11>;
490 dma-names = "rx", "tx";
491 status = "disabled";
492 };
493
494 uart4: serial@40010000 {
495 compatible = "st,stm32h7-uart";
496 reg = <0x40010000 0x400>;
497 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&rcc UART4_K>;
499 wakeup-source;
500 dmas = <&dmamux1 63 0x400 0x15>,
501 <&dmamux1 64 0x400 0x11>;
502 dma-names = "rx", "tx";
503 status = "disabled";
504 };
505
506 uart5: serial@40011000 {
507 compatible = "st,stm32h7-uart";
508 reg = <0x40011000 0x400>;
509 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&rcc UART5_K>;
511 wakeup-source;
512 dmas = <&dmamux1 65 0x400 0x15>,
513 <&dmamux1 66 0x400 0x11>;
514 dma-names = "rx", "tx";
515 status = "disabled";
516 };
517
518 i2c1: i2c@40012000 {
519 compatible = "st,stm32mp15-i2c";
520 reg = <0x40012000 0x400>;
521 interrupt-names = "event", "error";
522 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&rcc I2C1_K>;
525 resets = <&rcc I2C1_R>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 st,syscfg-fmp = <&syscfg 0x4 0x1>;
529 wakeup-source;
530 i2c-analog-filter;
531 status = "disabled";
532 };
533
534 i2c2: i2c@40013000 {
535 compatible = "st,stm32mp15-i2c";
536 reg = <0x40013000 0x400>;
537 interrupt-names = "event", "error";
538 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&rcc I2C2_K>;
541 resets = <&rcc I2C2_R>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 st,syscfg-fmp = <&syscfg 0x4 0x2>;
545 wakeup-source;
546 i2c-analog-filter;
547 status = "disabled";
548 };
549
550 i2c3: i2c@40014000 {
551 compatible = "st,stm32mp15-i2c";
552 reg = <0x40014000 0x400>;
553 interrupt-names = "event", "error";
554 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&rcc I2C3_K>;
557 resets = <&rcc I2C3_R>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 st,syscfg-fmp = <&syscfg 0x4 0x4>;
561 wakeup-source;
562 i2c-analog-filter;
563 status = "disabled";
564 };
565
566 i2c5: i2c@40015000 {
567 compatible = "st,stm32mp15-i2c";
568 reg = <0x40015000 0x400>;
569 interrupt-names = "event", "error";
570 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&rcc I2C5_K>;
573 resets = <&rcc I2C5_R>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 st,syscfg-fmp = <&syscfg 0x4 0x10>;
577 wakeup-source;
578 i2c-analog-filter;
579 status = "disabled";
580 };
581
582 cec: cec@40016000 {
583 compatible = "st,stm32-cec";
584 reg = <0x40016000 0x400>;
585 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&rcc CEC_K>, <&rcc CEC>;
587 clock-names = "cec", "hdmi-cec";
588 status = "disabled";
589 };
590
591 dac: dac@40017000 {
592 compatible = "st,stm32h7-dac-core";
593 reg = <0x40017000 0x400>;
594 clocks = <&rcc DAC12>;
595 clock-names = "pclk";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 status = "disabled";
599
600 dac1: dac@1 {
601 compatible = "st,stm32-dac";
602 #io-channel-cells = <1>;
603 reg = <1>;
604 status = "disabled";
605 };
606
607 dac2: dac@2 {
608 compatible = "st,stm32-dac";
609 #io-channel-cells = <1>;
610 reg = <2>;
611 status = "disabled";
612 };
613 };
614
615 uart7: serial@40018000 {
616 compatible = "st,stm32h7-uart";
617 reg = <0x40018000 0x400>;
618 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&rcc UART7_K>;
620 wakeup-source;
621 dmas = <&dmamux1 79 0x400 0x15>,
622 <&dmamux1 80 0x400 0x11>;
623 dma-names = "rx", "tx";
624 status = "disabled";
625 };
626
627 uart8: serial@40019000 {
628 compatible = "st,stm32h7-uart";
629 reg = <0x40019000 0x400>;
630 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&rcc UART8_K>;
632 wakeup-source;
633 dmas = <&dmamux1 81 0x400 0x15>,
634 <&dmamux1 82 0x400 0x11>;
635 dma-names = "rx", "tx";
636 status = "disabled";
637 };
638
639 timers1: timer@44000000 {
640 #address-cells = <1>;
641 #size-cells = <0>;
642 compatible = "st,stm32-timers";
643 reg = <0x44000000 0x400>;
644 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
648 interrupt-names = "brk", "up", "trg-com", "cc";
649 clocks = <&rcc TIM1_K>;
650 clock-names = "int";
651 dmas = <&dmamux1 11 0x400 0x1>,
652 <&dmamux1 12 0x400 0x1>,
653 <&dmamux1 13 0x400 0x1>,
654 <&dmamux1 14 0x400 0x1>,
655 <&dmamux1 15 0x400 0x1>,
656 <&dmamux1 16 0x400 0x1>,
657 <&dmamux1 17 0x400 0x1>;
658 dma-names = "ch1", "ch2", "ch3", "ch4",
659 "up", "trig", "com";
660 status = "disabled";
661
662 pwm {
663 compatible = "st,stm32-pwm";
664 #pwm-cells = <3>;
665 status = "disabled";
666 };
667
668 timer@0 {
669 compatible = "st,stm32h7-timer-trigger";
670 reg = <0>;
671 status = "disabled";
672 };
673
674 counter {
675 compatible = "st,stm32-timer-counter";
676 status = "disabled";
677 };
678 };
679
680 timers8: timer@44001000 {
681 #address-cells = <1>;
682 #size-cells = <0>;
683 compatible = "st,stm32-timers";
684 reg = <0x44001000 0x400>;
685 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
689 interrupt-names = "brk", "up", "trg-com", "cc";
690 clocks = <&rcc TIM8_K>;
691 clock-names = "int";
692 dmas = <&dmamux1 47 0x400 0x1>,
693 <&dmamux1 48 0x400 0x1>,
694 <&dmamux1 49 0x400 0x1>,
695 <&dmamux1 50 0x400 0x1>,
696 <&dmamux1 51 0x400 0x1>,
697 <&dmamux1 52 0x400 0x1>,
698 <&dmamux1 53 0x400 0x1>;
699 dma-names = "ch1", "ch2", "ch3", "ch4",
700 "up", "trig", "com";
701 status = "disabled";
702
703 pwm {
704 compatible = "st,stm32-pwm";
705 #pwm-cells = <3>;
706 status = "disabled";
707 };
708
709 timer@7 {
710 compatible = "st,stm32h7-timer-trigger";
711 reg = <7>;
712 status = "disabled";
713 };
714
715 counter {
716 compatible = "st,stm32-timer-counter";
717 status = "disabled";
718 };
719 };
720
721 usart6: serial@44003000 {
722 compatible = "st,stm32h7-uart";
723 reg = <0x44003000 0x400>;
724 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&rcc USART6_K>;
726 wakeup-source;
727 dmas = <&dmamux1 71 0x400 0x15>,
728 <&dmamux1 72 0x400 0x11>;
729 dma-names = "rx", "tx";
730 status = "disabled";
731 };
732
733 spi1: spi@44004000 {
734 #address-cells = <1>;
735 #size-cells = <0>;
736 compatible = "st,stm32h7-spi";
737 reg = <0x44004000 0x400>;
738 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&rcc SPI1_K>;
740 resets = <&rcc SPI1_R>;
741 dmas = <&dmamux1 37 0x400 0x05>,
742 <&dmamux1 38 0x400 0x05>;
743 dma-names = "rx", "tx";
744 status = "disabled";
745 };
746
747 i2s1: audio-controller@44004000 {
748 compatible = "st,stm32h7-i2s";
749 #sound-dai-cells = <0>;
750 reg = <0x44004000 0x400>;
751 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
752 dmas = <&dmamux1 37 0x400 0x01>,
753 <&dmamux1 38 0x400 0x01>;
754 dma-names = "rx", "tx";
755 status = "disabled";
756 };
757
758 spi4: spi@44005000 {
759 #address-cells = <1>;
760 #size-cells = <0>;
761 compatible = "st,stm32h7-spi";
762 reg = <0x44005000 0x400>;
763 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&rcc SPI4_K>;
765 resets = <&rcc SPI4_R>;
766 dmas = <&dmamux1 83 0x400 0x05>,
767 <&dmamux1 84 0x400 0x05>;
768 dma-names = "rx", "tx";
769 status = "disabled";
770 };
771
772 timers15: timer@44006000 {
773 #address-cells = <1>;
774 #size-cells = <0>;
775 compatible = "st,stm32-timers";
776 reg = <0x44006000 0x400>;
777 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
778 interrupt-names = "global";
779 clocks = <&rcc TIM15_K>;
780 clock-names = "int";
781 dmas = <&dmamux1 105 0x400 0x1>,
782 <&dmamux1 106 0x400 0x1>,
783 <&dmamux1 107 0x400 0x1>,
784 <&dmamux1 108 0x400 0x1>;
785 dma-names = "ch1", "up", "trig", "com";
786 status = "disabled";
787
788 pwm {
789 compatible = "st,stm32-pwm";
790 #pwm-cells = <3>;
791 status = "disabled";
792 };
793
794 timer@14 {
795 compatible = "st,stm32h7-timer-trigger";
796 reg = <14>;
797 status = "disabled";
798 };
799 };
800
801 timers16: timer@44007000 {
802 #address-cells = <1>;
803 #size-cells = <0>;
804 compatible = "st,stm32-timers";
805 reg = <0x44007000 0x400>;
806 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
807 interrupt-names = "global";
808 clocks = <&rcc TIM16_K>;
809 clock-names = "int";
810 dmas = <&dmamux1 109 0x400 0x1>,
811 <&dmamux1 110 0x400 0x1>;
812 dma-names = "ch1", "up";
813 status = "disabled";
814
815 pwm {
816 compatible = "st,stm32-pwm";
817 #pwm-cells = <3>;
818 status = "disabled";
819 };
820 timer@15 {
821 compatible = "st,stm32h7-timer-trigger";
822 reg = <15>;
823 status = "disabled";
824 };
825 };
826
827 timers17: timer@44008000 {
828 #address-cells = <1>;
829 #size-cells = <0>;
830 compatible = "st,stm32-timers";
831 reg = <0x44008000 0x400>;
832 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-names = "global";
834 clocks = <&rcc TIM17_K>;
835 clock-names = "int";
836 dmas = <&dmamux1 111 0x400 0x1>,
837 <&dmamux1 112 0x400 0x1>;
838 dma-names = "ch1", "up";
839 status = "disabled";
840
841 pwm {
842 compatible = "st,stm32-pwm";
843 #pwm-cells = <3>;
844 status = "disabled";
845 };
846
847 timer@16 {
848 compatible = "st,stm32h7-timer-trigger";
849 reg = <16>;
850 status = "disabled";
851 };
852 };
853
854 spi5: spi@44009000 {
855 #address-cells = <1>;
856 #size-cells = <0>;
857 compatible = "st,stm32h7-spi";
858 reg = <0x44009000 0x400>;
859 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&rcc SPI5_K>;
861 resets = <&rcc SPI5_R>;
862 dmas = <&dmamux1 85 0x400 0x05>,
863 <&dmamux1 86 0x400 0x05>;
864 dma-names = "rx", "tx";
865 status = "disabled";
866 };
867
868 sai1: sai@4400a000 {
869 compatible = "st,stm32h7-sai";
870 #address-cells = <1>;
871 #size-cells = <1>;
872 ranges = <0 0x4400a000 0x400>;
873 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
874 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
875 resets = <&rcc SAI1_R>;
876 status = "disabled";
877
878 sai1a: audio-controller@4400a004 {
879 #sound-dai-cells = <0>;
880
881 compatible = "st,stm32-sai-sub-a";
882 reg = <0x4 0x20>;
883 clocks = <&rcc SAI1_K>;
884 clock-names = "sai_ck";
885 dmas = <&dmamux1 87 0x400 0x01>;
886 status = "disabled";
887 };
888
889 sai1b: audio-controller@4400a024 {
890 #sound-dai-cells = <0>;
891 compatible = "st,stm32-sai-sub-b";
892 reg = <0x24 0x20>;
893 clocks = <&rcc SAI1_K>;
894 clock-names = "sai_ck";
895 dmas = <&dmamux1 88 0x400 0x01>;
896 status = "disabled";
897 };
898 };
899
900 sai2: sai@4400b000 {
901 compatible = "st,stm32h7-sai";
902 #address-cells = <1>;
903 #size-cells = <1>;
904 ranges = <0 0x4400b000 0x400>;
905 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
906 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
907 resets = <&rcc SAI2_R>;
908 status = "disabled";
909
910 sai2a: audio-controller@4400b004 {
911 #sound-dai-cells = <0>;
912 compatible = "st,stm32-sai-sub-a";
913 reg = <0x4 0x20>;
914 clocks = <&rcc SAI2_K>;
915 clock-names = "sai_ck";
916 dmas = <&dmamux1 89 0x400 0x01>;
917 status = "disabled";
918 };
919
920 sai2b: audio-controller@4400b024 {
921 #sound-dai-cells = <0>;
922 compatible = "st,stm32-sai-sub-b";
923 reg = <0x24 0x20>;
924 clocks = <&rcc SAI2_K>;
925 clock-names = "sai_ck";
926 dmas = <&dmamux1 90 0x400 0x01>;
927 status = "disabled";
928 };
929 };
930
931 sai3: sai@4400c000 {
932 compatible = "st,stm32h7-sai";
933 #address-cells = <1>;
934 #size-cells = <1>;
935 ranges = <0 0x4400c000 0x400>;
936 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
937 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
938 resets = <&rcc SAI3_R>;
939 status = "disabled";
940
941 sai3a: audio-controller@4400c004 {
942 #sound-dai-cells = <0>;
943 compatible = "st,stm32-sai-sub-a";
944 reg = <0x04 0x20>;
945 clocks = <&rcc SAI3_K>;
946 clock-names = "sai_ck";
947 dmas = <&dmamux1 113 0x400 0x01>;
948 status = "disabled";
949 };
950
951 sai3b: audio-controller@4400c024 {
952 #sound-dai-cells = <0>;
953 compatible = "st,stm32-sai-sub-b";
954 reg = <0x24 0x20>;
955 clocks = <&rcc SAI3_K>;
956 clock-names = "sai_ck";
957 dmas = <&dmamux1 114 0x400 0x01>;
958 status = "disabled";
959 };
960 };
961
962 dfsdm: dfsdm@4400d000 {
963 compatible = "st,stm32mp1-dfsdm";
964 reg = <0x4400d000 0x800>;
965 clocks = <&rcc DFSDM_K>;
966 clock-names = "dfsdm";
967 #address-cells = <1>;
968 #size-cells = <0>;
969 status = "disabled";
970
971 dfsdm0: filter@0 {
972 compatible = "st,stm32-dfsdm-adc";
973 #io-channel-cells = <1>;
974 reg = <0>;
975 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
976 dmas = <&dmamux1 101 0x400 0x01>;
977 dma-names = "rx";
978 status = "disabled";
979 };
980
981 dfsdm1: filter@1 {
982 compatible = "st,stm32-dfsdm-adc";
983 #io-channel-cells = <1>;
984 reg = <1>;
985 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
986 dmas = <&dmamux1 102 0x400 0x01>;
987 dma-names = "rx";
988 status = "disabled";
989 };
990
991 dfsdm2: filter@2 {
992 compatible = "st,stm32-dfsdm-adc";
993 #io-channel-cells = <1>;
994 reg = <2>;
995 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
996 dmas = <&dmamux1 103 0x400 0x01>;
997 dma-names = "rx";
998 status = "disabled";
999 };
1000
1001 dfsdm3: filter@3 {
1002 compatible = "st,stm32-dfsdm-adc";
1003 #io-channel-cells = <1>;
1004 reg = <3>;
1005 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1006 dmas = <&dmamux1 104 0x400 0x01>;
1007 dma-names = "rx";
1008 status = "disabled";
1009 };
1010
1011 dfsdm4: filter@4 {
1012 compatible = "st,stm32-dfsdm-adc";
1013 #io-channel-cells = <1>;
1014 reg = <4>;
1015 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1016 dmas = <&dmamux1 91 0x400 0x01>;
1017 dma-names = "rx";
1018 status = "disabled";
1019 };
1020
1021 dfsdm5: filter@5 {
1022 compatible = "st,stm32-dfsdm-adc";
1023 #io-channel-cells = <1>;
1024 reg = <5>;
1025 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1026 dmas = <&dmamux1 92 0x400 0x01>;
1027 dma-names = "rx";
1028 status = "disabled";
1029 };
1030 };
1031
1032 dma1: dma-controller@48000000 {
1033 compatible = "st,stm32-dma";
1034 reg = <0x48000000 0x400>;
1035 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&rcc DMA1>;
1044 resets = <&rcc DMA1_R>;
1045 #dma-cells = <4>;
1046 st,mem2mem;
1047 dma-requests = <8>;
1048 };
1049
1050 dma2: dma-controller@48001000 {
1051 compatible = "st,stm32-dma";
1052 reg = <0x48001000 0x400>;
1053 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&rcc DMA2>;
1062 resets = <&rcc DMA2_R>;
1063 #dma-cells = <4>;
1064 st,mem2mem;
1065 dma-requests = <8>;
1066 };
1067
1068 dmamux1: dma-router@48002000 {
1069 compatible = "st,stm32h7-dmamux";
1070 reg = <0x48002000 0x40>;
1071 #dma-cells = <3>;
1072 dma-requests = <128>;
1073 dma-masters = <&dma1 &dma2>;
1074 dma-channels = <16>;
1075 clocks = <&rcc DMAMUX>;
1076 resets = <&rcc DMAMUX_R>;
1077 };
1078
1079 adc: adc@48003000 {
1080 compatible = "st,stm32mp1-adc-core";
1081 reg = <0x48003000 0x400>;
1082 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1083 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1085 clock-names = "bus", "adc";
1086 interrupt-controller;
1087 st,syscfg = <&syscfg>;
1088 #interrupt-cells = <1>;
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 status = "disabled";
1092
1093 adc1: adc@0 {
1094 compatible = "st,stm32mp1-adc";
1095 #io-channel-cells = <1>;
1096 reg = <0x0>;
1097 interrupt-parent = <&adc>;
1098 interrupts = <0>;
1099 dmas = <&dmamux1 9 0x400 0x01>;
1100 dma-names = "rx";
1101 status = "disabled";
1102 };
1103
1104 adc2: adc@100 {
1105 compatible = "st,stm32mp1-adc";
1106 #io-channel-cells = <1>;
1107 reg = <0x100>;
1108 interrupt-parent = <&adc>;
1109 interrupts = <1>;
1110 dmas = <&dmamux1 10 0x400 0x01>;
1111 dma-names = "rx";
1112 status = "disabled";
1113 };
1114 };
1115
1116 sdmmc3: mmc@48004000 {
1117 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1118 arm,primecell-periphid = <0x00253180>;
1119 reg = <0x48004000 0x400>;
1120 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&rcc SDMMC3_K>;
1122 clock-names = "apb_pclk";
1123 resets = <&rcc SDMMC3_R>;
1124 cap-sd-highspeed;
1125 cap-mmc-highspeed;
1126 max-frequency = <120000000>;
1127 status = "disabled";
1128 };
1129
1130 usbotg_hs: usb-otg@49000000 {
1131 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1132 reg = <0x49000000 0x10000>;
1133 clocks = <&rcc USBO_K>;
1134 clock-names = "otg";
1135 resets = <&rcc USBO_R>;
1136 reset-names = "dwc2";
1137 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1138 g-rx-fifo-size = <512>;
1139 g-np-tx-fifo-size = <32>;
1140 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1141 dr_mode = "otg";
1142 otg-rev = <0x200>;
1143 usb33d-supply = <&usb33>;
1144 status = "disabled";
1145 };
1146
1147 ipcc: mailbox@4c001000 {
1148 compatible = "st,stm32mp1-ipcc";
1149 #mbox-cells = <1>;
1150 reg = <0x4c001000 0x400>;
1151 st,proc-id = <0>;
1152 interrupts-extended =
1153 <&exti 61 1>,
1154 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-names = "rx", "tx";
1156 clocks = <&rcc IPCC>;
1157 wakeup-source;
1158 status = "disabled";
1159 };
1160
1161 dcmi: dcmi@4c006000 {
1162 compatible = "st,stm32-dcmi";
1163 reg = <0x4c006000 0x400>;
1164 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1165 resets = <&rcc CAMITF_R>;
1166 clocks = <&rcc DCMI>;
1167 clock-names = "mclk";
1168 dmas = <&dmamux1 75 0x400 0x01>;
1169 dma-names = "tx";
1170 status = "disabled";
1171 };
1172
1173 rcc: rcc@50000000 {
1174 compatible = "st,stm32mp1-rcc", "syscon";
1175 reg = <0x50000000 0x1000>;
1176 #clock-cells = <1>;
1177 #reset-cells = <1>;
1178 };
1179
1180 pwr_regulators: pwr@50001000 {
1181 compatible = "st,stm32mp1,pwr-reg";
1182 reg = <0x50001000 0x10>;
1183
1184 reg11: reg11 {
1185 regulator-name = "reg11";
1186 regulator-min-microvolt = <1100000>;
1187 regulator-max-microvolt = <1100000>;
1188 };
1189
1190 reg18: reg18 {
1191 regulator-name = "reg18";
1192 regulator-min-microvolt = <1800000>;
1193 regulator-max-microvolt = <1800000>;
1194 };
1195
1196 usb33: usb33 {
1197 regulator-name = "usb33";
1198 regulator-min-microvolt = <3300000>;
1199 regulator-max-microvolt = <3300000>;
1200 };
1201 };
1202
1203 pwr_mcu: pwr_mcu@50001014 {
1204 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1205 reg = <0x50001014 0x4>;
1206 };
1207
1208 exti: interrupt-controller@5000d000 {
1209 compatible = "st,stm32mp1-exti", "syscon";
1210 interrupt-controller;
1211 #interrupt-cells = <2>;
1212 reg = <0x5000d000 0x400>;
1213 };
1214
1215 syscfg: syscon@50020000 {
1216 compatible = "st,stm32mp157-syscfg", "syscon";
1217 reg = <0x50020000 0x400>;
1218 clocks = <&rcc SYSCFG>;
1219 };
1220
1221 lptimer2: timer@50021000 {
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 compatible = "st,stm32-lptimer";
1225 reg = <0x50021000 0x400>;
1226 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1227 clocks = <&rcc LPTIM2_K>;
1228 clock-names = "mux";
1229 wakeup-source;
1230 status = "disabled";
1231
1232 pwm {
1233 compatible = "st,stm32-pwm-lp";
1234 #pwm-cells = <3>;
1235 status = "disabled";
1236 };
1237
1238 trigger@1 {
1239 compatible = "st,stm32-lptimer-trigger";
1240 reg = <1>;
1241 status = "disabled";
1242 };
1243
1244 counter {
1245 compatible = "st,stm32-lptimer-counter";
1246 status = "disabled";
1247 };
1248 };
1249
1250 lptimer3: timer@50022000 {
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 compatible = "st,stm32-lptimer";
1254 reg = <0x50022000 0x400>;
1255 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&rcc LPTIM3_K>;
1257 clock-names = "mux";
1258 wakeup-source;
1259 status = "disabled";
1260
1261 pwm {
1262 compatible = "st,stm32-pwm-lp";
1263 #pwm-cells = <3>;
1264 status = "disabled";
1265 };
1266
1267 trigger@2 {
1268 compatible = "st,stm32-lptimer-trigger";
1269 reg = <2>;
1270 status = "disabled";
1271 };
1272 };
1273
1274 lptimer4: timer@50023000 {
1275 compatible = "st,stm32-lptimer";
1276 reg = <0x50023000 0x400>;
1277 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&rcc LPTIM4_K>;
1279 clock-names = "mux";
1280 wakeup-source;
1281 status = "disabled";
1282
1283 pwm {
1284 compatible = "st,stm32-pwm-lp";
1285 #pwm-cells = <3>;
1286 status = "disabled";
1287 };
1288 };
1289
1290 lptimer5: timer@50024000 {
1291 compatible = "st,stm32-lptimer";
1292 reg = <0x50024000 0x400>;
1293 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&rcc LPTIM5_K>;
1295 clock-names = "mux";
1296 wakeup-source;
1297 status = "disabled";
1298
1299 pwm {
1300 compatible = "st,stm32-pwm-lp";
1301 #pwm-cells = <3>;
1302 status = "disabled";
1303 };
1304 };
1305
1306 vrefbuf: vrefbuf@50025000 {
1307 compatible = "st,stm32-vrefbuf";
1308 reg = <0x50025000 0x8>;
1309 regulator-min-microvolt = <1500000>;
1310 regulator-max-microvolt = <2500000>;
1311 clocks = <&rcc VREF>;
1312 status = "disabled";
1313 };
1314
1315 sai4: sai@50027000 {
1316 compatible = "st,stm32h7-sai";
1317 #address-cells = <1>;
1318 #size-cells = <1>;
1319 ranges = <0 0x50027000 0x400>;
1320 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1321 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1322 resets = <&rcc SAI4_R>;
1323 status = "disabled";
1324
1325 sai4a: audio-controller@50027004 {
1326 #sound-dai-cells = <0>;
1327 compatible = "st,stm32-sai-sub-a";
1328 reg = <0x04 0x20>;
1329 clocks = <&rcc SAI4_K>;
1330 clock-names = "sai_ck";
1331 dmas = <&dmamux1 99 0x400 0x01>;
1332 status = "disabled";
1333 };
1334
1335 sai4b: audio-controller@50027024 {
1336 #sound-dai-cells = <0>;
1337 compatible = "st,stm32-sai-sub-b";
1338 reg = <0x24 0x20>;
1339 clocks = <&rcc SAI4_K>;
1340 clock-names = "sai_ck";
1341 dmas = <&dmamux1 100 0x400 0x01>;
1342 status = "disabled";
1343 };
1344 };
1345
1346 dts: thermal@50028000 {
1347 compatible = "st,stm32-thermal";
1348 reg = <0x50028000 0x100>;
1349 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1350 clocks = <&rcc TMPSENS>;
1351 clock-names = "pclk";
1352 #thermal-sensor-cells = <0>;
1353 status = "disabled";
1354 };
1355
1356 hash1: hash@54002000 {
1357 compatible = "st,stm32f756-hash";
1358 reg = <0x54002000 0x400>;
1359 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1360 clocks = <&rcc HASH1>;
1361 resets = <&rcc HASH1_R>;
1362 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1363 dma-names = "in";
1364 dma-maxburst = <2>;
1365 status = "disabled";
1366 };
1367
1368 rng1: rng@54003000 {
1369 compatible = "st,stm32-rng";
1370 reg = <0x54003000 0x400>;
1371 clocks = <&rcc RNG1_K>;
1372 resets = <&rcc RNG1_R>;
1373 status = "disabled";
1374 };
1375
1376 mdma1: dma-controller@58000000 {
1377 compatible = "st,stm32h7-mdma";
1378 reg = <0x58000000 0x1000>;
1379 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1380 clocks = <&rcc MDMA>;
1381 resets = <&rcc MDMA_R>;
1382 #dma-cells = <5>;
1383 dma-channels = <32>;
1384 dma-requests = <48>;
1385 };
1386
1387 fmc: memory-controller@58002000 {
1388 #address-cells = <2>;
1389 #size-cells = <1>;
1390 compatible = "st,stm32mp1-fmc2-ebi";
1391 reg = <0x58002000 0x1000>;
1392 clocks = <&rcc FMC_K>;
1393 resets = <&rcc FMC_R>;
1394 status = "disabled";
1395
1396 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1397 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1398 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1399 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1400 <4 0 0x80000000 0x10000000>; /* NAND */
1401
1402 nand-controller@4,0 {
1403 #address-cells = <1>;
1404 #size-cells = <0>;
1405 compatible = "st,stm32mp1-fmc2-nfc";
1406 reg = <4 0x00000000 0x1000>,
1407 <4 0x08010000 0x1000>,
1408 <4 0x08020000 0x1000>,
1409 <4 0x01000000 0x1000>,
1410 <4 0x09010000 0x1000>,
1411 <4 0x09020000 0x1000>;
1412 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1413 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1414 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1415 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1416 dma-names = "tx", "rx", "ecc";
1417 status = "disabled";
1418 };
1419 };
1420
1421 qspi: spi@58003000 {
1422 compatible = "st,stm32f469-qspi";
1423 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1424 reg-names = "qspi", "qspi_mm";
1425 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1426 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1427 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1428 dma-names = "tx", "rx";
1429 clocks = <&rcc QSPI_K>;
1430 resets = <&rcc QSPI_R>;
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1433 status = "disabled";
1434 };
1435
1436 sdmmc1: mmc@58005000 {
1437 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1438 arm,primecell-periphid = <0x00253180>;
1439 reg = <0x58005000 0x1000>;
1440 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&rcc SDMMC1_K>;
1442 clock-names = "apb_pclk";
1443 resets = <&rcc SDMMC1_R>;
1444 cap-sd-highspeed;
1445 cap-mmc-highspeed;
1446 max-frequency = <120000000>;
1447 status = "disabled";
1448 };
1449
1450 sdmmc2: mmc@58007000 {
1451 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1452 arm,primecell-periphid = <0x00253180>;
1453 reg = <0x58007000 0x1000>;
1454 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1455 clocks = <&rcc SDMMC2_K>;
1456 clock-names = "apb_pclk";
1457 resets = <&rcc SDMMC2_R>;
1458 cap-sd-highspeed;
1459 cap-mmc-highspeed;
1460 max-frequency = <120000000>;
1461 status = "disabled";
1462 };
1463
1464 crc1: crc@58009000 {
1465 compatible = "st,stm32f7-crc";
1466 reg = <0x58009000 0x400>;
1467 clocks = <&rcc CRC1>;
1468 status = "disabled";
1469 };
1470
1471 ethernet0: ethernet@5800a000 {
1472 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1473 reg = <0x5800a000 0x2000>;
1474 reg-names = "stmmaceth";
1475 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1476 interrupt-names = "macirq";
1477 clock-names = "stmmaceth",
1478 "mac-clk-tx",
1479 "mac-clk-rx",
1480 "eth-ck",
1481 "ptp_ref",
1482 "ethstp";
1483 clocks = <&rcc ETHMAC>,
1484 <&rcc ETHTX>,
1485 <&rcc ETHRX>,
1486 <&rcc ETHCK_K>,
1487 <&rcc ETHPTP_K>,
1488 <&rcc ETHSTP>;
1489 st,syscon = <&syscfg 0x4>;
1490 snps,mixed-burst;
1491 snps,pbl = <2>;
1492 snps,en-tx-lpi-clockgating;
1493 snps,axi-config = <&stmmac_axi_config_0>;
1494 snps,tso;
1495 status = "disabled";
1496
1497 stmmac_axi_config_0: stmmac-axi-config {
1498 snps,wr_osr_lmt = <0x7>;
1499 snps,rd_osr_lmt = <0x7>;
1500 snps,blen = <0 0 0 0 16 8 4>;
1501 };
1502 };
1503
1504 usbh_ohci: usb@5800c000 {
1505 compatible = "generic-ohci";
1506 reg = <0x5800c000 0x1000>;
1507 clocks = <&usbphyc>, <&rcc USBH>;
1508 resets = <&rcc USBH_R>;
1509 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1510 status = "disabled";
1511 };
1512
1513 usbh_ehci: usb@5800d000 {
1514 compatible = "generic-ehci";
1515 reg = <0x5800d000 0x1000>;
1516 clocks = <&usbphyc>, <&rcc USBH>;
1517 resets = <&rcc USBH_R>;
1518 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1519 companion = <&usbh_ohci>;
1520 status = "disabled";
1521 };
1522
1523 ltdc: display-controller@5a001000 {
1524 compatible = "st,stm32-ltdc";
1525 reg = <0x5a001000 0x400>;
1526 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1528 clocks = <&rcc LTDC_PX>;
1529 clock-names = "lcd";
1530 resets = <&rcc LTDC_R>;
1531 status = "disabled";
1532
1533 port {
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1536 };
1537 };
1538
1539 iwdg2: watchdog@5a002000 {
1540 compatible = "st,stm32mp1-iwdg";
1541 reg = <0x5a002000 0x400>;
1542 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1543 clock-names = "pclk", "lsi";
1544 status = "disabled";
1545 };
1546
1547 usbphyc: usbphyc@5a006000 {
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550 #clock-cells = <0>;
1551 compatible = "st,stm32mp1-usbphyc";
1552 reg = <0x5a006000 0x1000>;
1553 clocks = <&rcc USBPHY_K>;
1554 resets = <&rcc USBPHY_R>;
1555 vdda1v1-supply = <®11>;
1556 vdda1v8-supply = <®18>;
1557 status = "disabled";
1558
1559 usbphyc_port0: usb-phy@0 {
1560 #phy-cells = <0>;
1561 reg = <0>;
1562 };
1563
1564 usbphyc_port1: usb-phy@1 {
1565 #phy-cells = <1>;
1566 reg = <1>;
1567 };
1568 };
1569
1570 usart1: serial@5c000000 {
1571 compatible = "st,stm32h7-uart";
1572 reg = <0x5c000000 0x400>;
1573 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1574 clocks = <&rcc USART1_K>;
1575 wakeup-source;
1576 status = "disabled";
1577 };
1578
1579 spi6: spi@5c001000 {
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1582 compatible = "st,stm32h7-spi";
1583 reg = <0x5c001000 0x400>;
1584 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&rcc SPI6_K>;
1586 resets = <&rcc SPI6_R>;
1587 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1588 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1589 dma-names = "rx", "tx";
1590 status = "disabled";
1591 };
1592
1593 i2c4: i2c@5c002000 {
1594 compatible = "st,stm32mp15-i2c";
1595 reg = <0x5c002000 0x400>;
1596 interrupt-names = "event", "error";
1597 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1599 clocks = <&rcc I2C4_K>;
1600 resets = <&rcc I2C4_R>;
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1603 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1604 wakeup-source;
1605 i2c-analog-filter;
1606 status = "disabled";
1607 };
1608
1609 rtc: rtc@5c004000 {
1610 compatible = "st,stm32mp1-rtc";
1611 reg = <0x5c004000 0x400>;
1612 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1613 clock-names = "pclk", "rtc_ck";
1614 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1615 status = "disabled";
1616 };
1617
1618 bsec: efuse@5c005000 {
1619 compatible = "st,stm32mp15-bsec";
1620 reg = <0x5c005000 0x400>;
1621 #address-cells = <1>;
1622 #size-cells = <1>;
1623 ts_cal1: calib@5c {
1624 reg = <0x5c 0x2>;
1625 };
1626 ts_cal2: calib@5e {
1627 reg = <0x5e 0x2>;
1628 };
1629 };
1630
1631 i2c6: i2c@5c009000 {
1632 compatible = "st,stm32mp15-i2c";
1633 reg = <0x5c009000 0x400>;
1634 interrupt-names = "event", "error";
1635 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1636 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1637 clocks = <&rcc I2C6_K>;
1638 resets = <&rcc I2C6_R>;
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1641 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1642 wakeup-source;
1643 i2c-analog-filter;
1644 status = "disabled";
1645 };
1646
1647 tamp: tamp@5c00a000 {
1648 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1649 reg = <0x5c00a000 0x400>;
1650 };
1651
1652 /*
1653 * Break node order to solve dependency probe issue between
1654 * pinctrl and exti.
1655 */
1656 pinctrl: pinctrl@50002000 {
1657 #address-cells = <1>;
1658 #size-cells = <1>;
1659 compatible = "st,stm32mp157-pinctrl";
1660 ranges = <0 0x50002000 0xa400>;
1661 interrupt-parent = <&exti>;
1662 st,syscfg = <&exti 0x60 0xff>;
1663 pins-are-numbered;
1664
1665 gpioa: gpio@50002000 {
1666 gpio-controller;
1667 #gpio-cells = <2>;
1668 interrupt-controller;
1669 #interrupt-cells = <2>;
1670 reg = <0x0 0x400>;
1671 clocks = <&rcc GPIOA>;
1672 st,bank-name = "GPIOA";
1673 status = "disabled";
1674 };
1675
1676 gpiob: gpio@50003000 {
1677 gpio-controller;
1678 #gpio-cells = <2>;
1679 interrupt-controller;
1680 #interrupt-cells = <2>;
1681 reg = <0x1000 0x400>;
1682 clocks = <&rcc GPIOB>;
1683 st,bank-name = "GPIOB";
1684 status = "disabled";
1685 };
1686
1687 gpioc: gpio@50004000 {
1688 gpio-controller;
1689 #gpio-cells = <2>;
1690 interrupt-controller;
1691 #interrupt-cells = <2>;
1692 reg = <0x2000 0x400>;
1693 clocks = <&rcc GPIOC>;
1694 st,bank-name = "GPIOC";
1695 status = "disabled";
1696 };
1697
1698 gpiod: gpio@50005000 {
1699 gpio-controller;
1700 #gpio-cells = <2>;
1701 interrupt-controller;
1702 #interrupt-cells = <2>;
1703 reg = <0x3000 0x400>;
1704 clocks = <&rcc GPIOD>;
1705 st,bank-name = "GPIOD";
1706 status = "disabled";
1707 };
1708
1709 gpioe: gpio@50006000 {
1710 gpio-controller;
1711 #gpio-cells = <2>;
1712 interrupt-controller;
1713 #interrupt-cells = <2>;
1714 reg = <0x4000 0x400>;
1715 clocks = <&rcc GPIOE>;
1716 st,bank-name = "GPIOE";
1717 status = "disabled";
1718 };
1719
1720 gpiof: gpio@50007000 {
1721 gpio-controller;
1722 #gpio-cells = <2>;
1723 interrupt-controller;
1724 #interrupt-cells = <2>;
1725 reg = <0x5000 0x400>;
1726 clocks = <&rcc GPIOF>;
1727 st,bank-name = "GPIOF";
1728 status = "disabled";
1729 };
1730
1731 gpiog: gpio@50008000 {
1732 gpio-controller;
1733 #gpio-cells = <2>;
1734 interrupt-controller;
1735 #interrupt-cells = <2>;
1736 reg = <0x6000 0x400>;
1737 clocks = <&rcc GPIOG>;
1738 st,bank-name = "GPIOG";
1739 status = "disabled";
1740 };
1741
1742 gpioh: gpio@50009000 {
1743 gpio-controller;
1744 #gpio-cells = <2>;
1745 interrupt-controller;
1746 #interrupt-cells = <2>;
1747 reg = <0x7000 0x400>;
1748 clocks = <&rcc GPIOH>;
1749 st,bank-name = "GPIOH";
1750 status = "disabled";
1751 };
1752
1753 gpioi: gpio@5000a000 {
1754 gpio-controller;
1755 #gpio-cells = <2>;
1756 interrupt-controller;
1757 #interrupt-cells = <2>;
1758 reg = <0x8000 0x400>;
1759 clocks = <&rcc GPIOI>;
1760 st,bank-name = "GPIOI";
1761 status = "disabled";
1762 };
1763
1764 gpioj: gpio@5000b000 {
1765 gpio-controller;
1766 #gpio-cells = <2>;
1767 interrupt-controller;
1768 #interrupt-cells = <2>;
1769 reg = <0x9000 0x400>;
1770 clocks = <&rcc GPIOJ>;
1771 st,bank-name = "GPIOJ";
1772 status = "disabled";
1773 };
1774
1775 gpiok: gpio@5000c000 {
1776 gpio-controller;
1777 #gpio-cells = <2>;
1778 interrupt-controller;
1779 #interrupt-cells = <2>;
1780 reg = <0xa000 0x400>;
1781 clocks = <&rcc GPIOK>;
1782 st,bank-name = "GPIOK";
1783 status = "disabled";
1784 };
1785 };
1786
1787 pinctrl_z: pinctrl@54004000 {
1788 #address-cells = <1>;
1789 #size-cells = <1>;
1790 compatible = "st,stm32mp157-z-pinctrl";
1791 ranges = <0 0x54004000 0x400>;
1792 pins-are-numbered;
1793 interrupt-parent = <&exti>;
1794 st,syscfg = <&exti 0x60 0xff>;
1795
1796 gpioz: gpio@54004000 {
1797 gpio-controller;
1798 #gpio-cells = <2>;
1799 interrupt-controller;
1800 #interrupt-cells = <2>;
1801 reg = <0 0x400>;
1802 clocks = <&rcc GPIOZ>;
1803 st,bank-name = "GPIOZ";
1804 st,bank-ioport = <11>;
1805 status = "disabled";
1806 };
1807 };
1808 };
1809
1810 mlahb: ahb {
1811 compatible = "st,mlahb", "simple-bus";
1812 #address-cells = <1>;
1813 #size-cells = <1>;
1814 ranges;
1815 dma-ranges = <0x00000000 0x38000000 0x10000>,
1816 <0x10000000 0x10000000 0x60000>,
1817 <0x30000000 0x30000000 0x60000>;
1818
1819 m4_rproc: m4@10000000 {
1820 compatible = "st,stm32mp1-m4";
1821 reg = <0x10000000 0x40000>,
1822 <0x30000000 0x40000>,
1823 <0x38000000 0x10000>;
1824 resets = <&rcc MCU_R>;
1825 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1826 st,syscfg-tz = <&rcc 0x000 0x1>;
1827 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1828 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1829 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1830 status = "disabled";
1831 };
1832 };
1833};
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 arm-pmu {
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
31 };
32
33 psci {
34 compatible = "arm,psci-1.0";
35 method = "smc";
36 };
37
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
53 };
54
55 clocks {
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
66 };
67
68 clk_lse: clk-lse {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 clk_lsi: clk-lsi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 };
79
80 clk_csi: clk-csi {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
84 };
85 };
86
87 thermal-zones {
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
90 polling-delay = <0>;
91 thermal-sensors = <&dts>;
92
93 trips {
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
96 hysteresis = <0>;
97 type = "passive";
98 };
99
100 cpu-crit {
101 temperature = <120000>;
102 hysteresis = <0>;
103 type = "critical";
104 };
105 };
106
107 cooling-maps {
108 };
109 };
110 };
111
112 booster: regulator-booster {
113 compatible = "st,stm32mp1-booster";
114 st,syscfg = <&syscfg>;
115 status = "disabled";
116 };
117
118 soc {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 interrupt-parent = <&intc>;
123 ranges;
124
125 timers2: timer@40000000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "st,stm32-timers";
129 reg = <0x40000000 0x400>;
130 clocks = <&rcc TIM2_K>;
131 clock-names = "int";
132 dmas = <&dmamux1 18 0x400 0x1>,
133 <&dmamux1 19 0x400 0x1>,
134 <&dmamux1 20 0x400 0x1>,
135 <&dmamux1 21 0x400 0x1>,
136 <&dmamux1 22 0x400 0x1>;
137 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
138 status = "disabled";
139
140 pwm {
141 compatible = "st,stm32-pwm";
142 #pwm-cells = <3>;
143 status = "disabled";
144 };
145
146 timer@1 {
147 compatible = "st,stm32h7-timer-trigger";
148 reg = <1>;
149 status = "disabled";
150 };
151
152 counter {
153 compatible = "st,stm32-timer-counter";
154 status = "disabled";
155 };
156 };
157
158 timers3: timer@40001000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "st,stm32-timers";
162 reg = <0x40001000 0x400>;
163 clocks = <&rcc TIM3_K>;
164 clock-names = "int";
165 dmas = <&dmamux1 23 0x400 0x1>,
166 <&dmamux1 24 0x400 0x1>,
167 <&dmamux1 25 0x400 0x1>,
168 <&dmamux1 26 0x400 0x1>,
169 <&dmamux1 27 0x400 0x1>,
170 <&dmamux1 28 0x400 0x1>;
171 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
172 status = "disabled";
173
174 pwm {
175 compatible = "st,stm32-pwm";
176 #pwm-cells = <3>;
177 status = "disabled";
178 };
179
180 timer@2 {
181 compatible = "st,stm32h7-timer-trigger";
182 reg = <2>;
183 status = "disabled";
184 };
185
186 counter {
187 compatible = "st,stm32-timer-counter";
188 status = "disabled";
189 };
190 };
191
192 timers4: timer@40002000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "st,stm32-timers";
196 reg = <0x40002000 0x400>;
197 clocks = <&rcc TIM4_K>;
198 clock-names = "int";
199 dmas = <&dmamux1 29 0x400 0x1>,
200 <&dmamux1 30 0x400 0x1>,
201 <&dmamux1 31 0x400 0x1>,
202 <&dmamux1 32 0x400 0x1>;
203 dma-names = "ch1", "ch2", "ch3", "ch4";
204 status = "disabled";
205
206 pwm {
207 compatible = "st,stm32-pwm";
208 #pwm-cells = <3>;
209 status = "disabled";
210 };
211
212 timer@3 {
213 compatible = "st,stm32h7-timer-trigger";
214 reg = <3>;
215 status = "disabled";
216 };
217
218 counter {
219 compatible = "st,stm32-timer-counter";
220 status = "disabled";
221 };
222 };
223
224 timers5: timer@40003000 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "st,stm32-timers";
228 reg = <0x40003000 0x400>;
229 clocks = <&rcc TIM5_K>;
230 clock-names = "int";
231 dmas = <&dmamux1 55 0x400 0x1>,
232 <&dmamux1 56 0x400 0x1>,
233 <&dmamux1 57 0x400 0x1>,
234 <&dmamux1 58 0x400 0x1>,
235 <&dmamux1 59 0x400 0x1>,
236 <&dmamux1 60 0x400 0x1>;
237 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
238 status = "disabled";
239
240 pwm {
241 compatible = "st,stm32-pwm";
242 #pwm-cells = <3>;
243 status = "disabled";
244 };
245
246 timer@4 {
247 compatible = "st,stm32h7-timer-trigger";
248 reg = <4>;
249 status = "disabled";
250 };
251
252 counter {
253 compatible = "st,stm32-timer-counter";
254 status = "disabled";
255 };
256 };
257
258 timers6: timer@40004000 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 compatible = "st,stm32-timers";
262 reg = <0x40004000 0x400>;
263 clocks = <&rcc TIM6_K>;
264 clock-names = "int";
265 dmas = <&dmamux1 69 0x400 0x1>;
266 dma-names = "up";
267 status = "disabled";
268
269 timer@5 {
270 compatible = "st,stm32h7-timer-trigger";
271 reg = <5>;
272 status = "disabled";
273 };
274 };
275
276 timers7: timer@40005000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "st,stm32-timers";
280 reg = <0x40005000 0x400>;
281 clocks = <&rcc TIM7_K>;
282 clock-names = "int";
283 dmas = <&dmamux1 70 0x400 0x1>;
284 dma-names = "up";
285 status = "disabled";
286
287 timer@6 {
288 compatible = "st,stm32h7-timer-trigger";
289 reg = <6>;
290 status = "disabled";
291 };
292 };
293
294 timers12: timer@40006000 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "st,stm32-timers";
298 reg = <0x40006000 0x400>;
299 clocks = <&rcc TIM12_K>;
300 clock-names = "int";
301 status = "disabled";
302
303 pwm {
304 compatible = "st,stm32-pwm";
305 #pwm-cells = <3>;
306 status = "disabled";
307 };
308
309 timer@11 {
310 compatible = "st,stm32h7-timer-trigger";
311 reg = <11>;
312 status = "disabled";
313 };
314 };
315
316 timers13: timer@40007000 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 compatible = "st,stm32-timers";
320 reg = <0x40007000 0x400>;
321 clocks = <&rcc TIM13_K>;
322 clock-names = "int";
323 status = "disabled";
324
325 pwm {
326 compatible = "st,stm32-pwm";
327 #pwm-cells = <3>;
328 status = "disabled";
329 };
330
331 timer@12 {
332 compatible = "st,stm32h7-timer-trigger";
333 reg = <12>;
334 status = "disabled";
335 };
336 };
337
338 timers14: timer@40008000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 compatible = "st,stm32-timers";
342 reg = <0x40008000 0x400>;
343 clocks = <&rcc TIM14_K>;
344 clock-names = "int";
345 status = "disabled";
346
347 pwm {
348 compatible = "st,stm32-pwm";
349 #pwm-cells = <3>;
350 status = "disabled";
351 };
352
353 timer@13 {
354 compatible = "st,stm32h7-timer-trigger";
355 reg = <13>;
356 status = "disabled";
357 };
358 };
359
360 lptimer1: timer@40009000 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "st,stm32-lptimer";
364 reg = <0x40009000 0x400>;
365 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&rcc LPTIM1_K>;
367 clock-names = "mux";
368 wakeup-source;
369 status = "disabled";
370
371 pwm {
372 compatible = "st,stm32-pwm-lp";
373 #pwm-cells = <3>;
374 status = "disabled";
375 };
376
377 trigger@0 {
378 compatible = "st,stm32-lptimer-trigger";
379 reg = <0>;
380 status = "disabled";
381 };
382
383 counter {
384 compatible = "st,stm32-lptimer-counter";
385 status = "disabled";
386 };
387 };
388
389 spi2: spi@4000b000 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 compatible = "st,stm32h7-spi";
393 reg = <0x4000b000 0x400>;
394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&rcc SPI2_K>;
396 resets = <&rcc SPI2_R>;
397 dmas = <&dmamux1 39 0x400 0x05>,
398 <&dmamux1 40 0x400 0x05>;
399 dma-names = "rx", "tx";
400 status = "disabled";
401 };
402
403 i2s2: audio-controller@4000b000 {
404 compatible = "st,stm32h7-i2s";
405 #sound-dai-cells = <0>;
406 reg = <0x4000b000 0x400>;
407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
408 dmas = <&dmamux1 39 0x400 0x01>,
409 <&dmamux1 40 0x400 0x01>;
410 dma-names = "rx", "tx";
411 status = "disabled";
412 };
413
414 spi3: spi@4000c000 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "st,stm32h7-spi";
418 reg = <0x4000c000 0x400>;
419 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&rcc SPI3_K>;
421 resets = <&rcc SPI3_R>;
422 dmas = <&dmamux1 61 0x400 0x05>,
423 <&dmamux1 62 0x400 0x05>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 };
427
428 i2s3: audio-controller@4000c000 {
429 compatible = "st,stm32h7-i2s";
430 #sound-dai-cells = <0>;
431 reg = <0x4000c000 0x400>;
432 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
433 dmas = <&dmamux1 61 0x400 0x01>,
434 <&dmamux1 62 0x400 0x01>;
435 dma-names = "rx", "tx";
436 status = "disabled";
437 };
438
439 spdifrx: audio-controller@4000d000 {
440 compatible = "st,stm32h7-spdifrx";
441 #sound-dai-cells = <0>;
442 reg = <0x4000d000 0x400>;
443 clocks = <&rcc SPDIF_K>;
444 clock-names = "kclk";
445 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
446 dmas = <&dmamux1 93 0x400 0x01>,
447 <&dmamux1 94 0x400 0x01>;
448 dma-names = "rx", "rx-ctrl";
449 status = "disabled";
450 };
451
452 usart2: serial@4000e000 {
453 compatible = "st,stm32h7-uart";
454 reg = <0x4000e000 0x400>;
455 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&rcc USART2_K>;
457 wakeup-source;
458 status = "disabled";
459 };
460
461 usart3: serial@4000f000 {
462 compatible = "st,stm32h7-uart";
463 reg = <0x4000f000 0x400>;
464 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&rcc USART3_K>;
466 wakeup-source;
467 status = "disabled";
468 };
469
470 uart4: serial@40010000 {
471 compatible = "st,stm32h7-uart";
472 reg = <0x40010000 0x400>;
473 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&rcc UART4_K>;
475 wakeup-source;
476 status = "disabled";
477 };
478
479 uart5: serial@40011000 {
480 compatible = "st,stm32h7-uart";
481 reg = <0x40011000 0x400>;
482 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&rcc UART5_K>;
484 wakeup-source;
485 status = "disabled";
486 };
487
488 i2c1: i2c@40012000 {
489 compatible = "st,stm32mp15-i2c";
490 reg = <0x40012000 0x400>;
491 interrupt-names = "event", "error";
492 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&rcc I2C1_K>;
495 resets = <&rcc I2C1_R>;
496 #address-cells = <1>;
497 #size-cells = <0>;
498 st,syscfg-fmp = <&syscfg 0x4 0x1>;
499 wakeup-source;
500 i2c-analog-filter;
501 status = "disabled";
502 };
503
504 i2c2: i2c@40013000 {
505 compatible = "st,stm32mp15-i2c";
506 reg = <0x40013000 0x400>;
507 interrupt-names = "event", "error";
508 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&rcc I2C2_K>;
511 resets = <&rcc I2C2_R>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 st,syscfg-fmp = <&syscfg 0x4 0x2>;
515 wakeup-source;
516 i2c-analog-filter;
517 status = "disabled";
518 };
519
520 i2c3: i2c@40014000 {
521 compatible = "st,stm32mp15-i2c";
522 reg = <0x40014000 0x400>;
523 interrupt-names = "event", "error";
524 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&rcc I2C3_K>;
527 resets = <&rcc I2C3_R>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 st,syscfg-fmp = <&syscfg 0x4 0x4>;
531 wakeup-source;
532 i2c-analog-filter;
533 status = "disabled";
534 };
535
536 i2c5: i2c@40015000 {
537 compatible = "st,stm32mp15-i2c";
538 reg = <0x40015000 0x400>;
539 interrupt-names = "event", "error";
540 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&rcc I2C5_K>;
543 resets = <&rcc I2C5_R>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 st,syscfg-fmp = <&syscfg 0x4 0x10>;
547 wakeup-source;
548 i2c-analog-filter;
549 status = "disabled";
550 };
551
552 cec: cec@40016000 {
553 compatible = "st,stm32-cec";
554 reg = <0x40016000 0x400>;
555 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&rcc CEC_K>, <&clk_lse>;
557 clock-names = "cec", "hdmi-cec";
558 status = "disabled";
559 };
560
561 dac: dac@40017000 {
562 compatible = "st,stm32h7-dac-core";
563 reg = <0x40017000 0x400>;
564 clocks = <&rcc DAC12>;
565 clock-names = "pclk";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569
570 dac1: dac@1 {
571 compatible = "st,stm32-dac";
572 #io-channel-cells = <1>;
573 reg = <1>;
574 status = "disabled";
575 };
576
577 dac2: dac@2 {
578 compatible = "st,stm32-dac";
579 #io-channel-cells = <1>;
580 reg = <2>;
581 status = "disabled";
582 };
583 };
584
585 uart7: serial@40018000 {
586 compatible = "st,stm32h7-uart";
587 reg = <0x40018000 0x400>;
588 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&rcc UART7_K>;
590 wakeup-source;
591 status = "disabled";
592 };
593
594 uart8: serial@40019000 {
595 compatible = "st,stm32h7-uart";
596 reg = <0x40019000 0x400>;
597 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&rcc UART8_K>;
599 wakeup-source;
600 status = "disabled";
601 };
602
603 timers1: timer@44000000 {
604 #address-cells = <1>;
605 #size-cells = <0>;
606 compatible = "st,stm32-timers";
607 reg = <0x44000000 0x400>;
608 clocks = <&rcc TIM1_K>;
609 clock-names = "int";
610 dmas = <&dmamux1 11 0x400 0x1>,
611 <&dmamux1 12 0x400 0x1>,
612 <&dmamux1 13 0x400 0x1>,
613 <&dmamux1 14 0x400 0x1>,
614 <&dmamux1 15 0x400 0x1>,
615 <&dmamux1 16 0x400 0x1>,
616 <&dmamux1 17 0x400 0x1>;
617 dma-names = "ch1", "ch2", "ch3", "ch4",
618 "up", "trig", "com";
619 status = "disabled";
620
621 pwm {
622 compatible = "st,stm32-pwm";
623 #pwm-cells = <3>;
624 status = "disabled";
625 };
626
627 timer@0 {
628 compatible = "st,stm32h7-timer-trigger";
629 reg = <0>;
630 status = "disabled";
631 };
632
633 counter {
634 compatible = "st,stm32-timer-counter";
635 status = "disabled";
636 };
637 };
638
639 timers8: timer@44001000 {
640 #address-cells = <1>;
641 #size-cells = <0>;
642 compatible = "st,stm32-timers";
643 reg = <0x44001000 0x400>;
644 clocks = <&rcc TIM8_K>;
645 clock-names = "int";
646 dmas = <&dmamux1 47 0x400 0x1>,
647 <&dmamux1 48 0x400 0x1>,
648 <&dmamux1 49 0x400 0x1>,
649 <&dmamux1 50 0x400 0x1>,
650 <&dmamux1 51 0x400 0x1>,
651 <&dmamux1 52 0x400 0x1>,
652 <&dmamux1 53 0x400 0x1>;
653 dma-names = "ch1", "ch2", "ch3", "ch4",
654 "up", "trig", "com";
655 status = "disabled";
656
657 pwm {
658 compatible = "st,stm32-pwm";
659 #pwm-cells = <3>;
660 status = "disabled";
661 };
662
663 timer@7 {
664 compatible = "st,stm32h7-timer-trigger";
665 reg = <7>;
666 status = "disabled";
667 };
668
669 counter {
670 compatible = "st,stm32-timer-counter";
671 status = "disabled";
672 };
673 };
674
675 usart6: serial@44003000 {
676 compatible = "st,stm32h7-uart";
677 reg = <0x44003000 0x400>;
678 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&rcc USART6_K>;
680 wakeup-source;
681 status = "disabled";
682 };
683
684 spi1: spi@44004000 {
685 #address-cells = <1>;
686 #size-cells = <0>;
687 compatible = "st,stm32h7-spi";
688 reg = <0x44004000 0x400>;
689 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&rcc SPI1_K>;
691 resets = <&rcc SPI1_R>;
692 dmas = <&dmamux1 37 0x400 0x05>,
693 <&dmamux1 38 0x400 0x05>;
694 dma-names = "rx", "tx";
695 status = "disabled";
696 };
697
698 i2s1: audio-controller@44004000 {
699 compatible = "st,stm32h7-i2s";
700 #sound-dai-cells = <0>;
701 reg = <0x44004000 0x400>;
702 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
703 dmas = <&dmamux1 37 0x400 0x01>,
704 <&dmamux1 38 0x400 0x01>;
705 dma-names = "rx", "tx";
706 status = "disabled";
707 };
708
709 spi4: spi@44005000 {
710 #address-cells = <1>;
711 #size-cells = <0>;
712 compatible = "st,stm32h7-spi";
713 reg = <0x44005000 0x400>;
714 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&rcc SPI4_K>;
716 resets = <&rcc SPI4_R>;
717 dmas = <&dmamux1 83 0x400 0x05>,
718 <&dmamux1 84 0x400 0x05>;
719 dma-names = "rx", "tx";
720 status = "disabled";
721 };
722
723 timers15: timer@44006000 {
724 #address-cells = <1>;
725 #size-cells = <0>;
726 compatible = "st,stm32-timers";
727 reg = <0x44006000 0x400>;
728 clocks = <&rcc TIM15_K>;
729 clock-names = "int";
730 dmas = <&dmamux1 105 0x400 0x1>,
731 <&dmamux1 106 0x400 0x1>,
732 <&dmamux1 107 0x400 0x1>,
733 <&dmamux1 108 0x400 0x1>;
734 dma-names = "ch1", "up", "trig", "com";
735 status = "disabled";
736
737 pwm {
738 compatible = "st,stm32-pwm";
739 #pwm-cells = <3>;
740 status = "disabled";
741 };
742
743 timer@14 {
744 compatible = "st,stm32h7-timer-trigger";
745 reg = <14>;
746 status = "disabled";
747 };
748 };
749
750 timers16: timer@44007000 {
751 #address-cells = <1>;
752 #size-cells = <0>;
753 compatible = "st,stm32-timers";
754 reg = <0x44007000 0x400>;
755 clocks = <&rcc TIM16_K>;
756 clock-names = "int";
757 dmas = <&dmamux1 109 0x400 0x1>,
758 <&dmamux1 110 0x400 0x1>;
759 dma-names = "ch1", "up";
760 status = "disabled";
761
762 pwm {
763 compatible = "st,stm32-pwm";
764 #pwm-cells = <3>;
765 status = "disabled";
766 };
767 timer@15 {
768 compatible = "st,stm32h7-timer-trigger";
769 reg = <15>;
770 status = "disabled";
771 };
772 };
773
774 timers17: timer@44008000 {
775 #address-cells = <1>;
776 #size-cells = <0>;
777 compatible = "st,stm32-timers";
778 reg = <0x44008000 0x400>;
779 clocks = <&rcc TIM17_K>;
780 clock-names = "int";
781 dmas = <&dmamux1 111 0x400 0x1>,
782 <&dmamux1 112 0x400 0x1>;
783 dma-names = "ch1", "up";
784 status = "disabled";
785
786 pwm {
787 compatible = "st,stm32-pwm";
788 #pwm-cells = <3>;
789 status = "disabled";
790 };
791
792 timer@16 {
793 compatible = "st,stm32h7-timer-trigger";
794 reg = <16>;
795 status = "disabled";
796 };
797 };
798
799 spi5: spi@44009000 {
800 #address-cells = <1>;
801 #size-cells = <0>;
802 compatible = "st,stm32h7-spi";
803 reg = <0x44009000 0x400>;
804 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&rcc SPI5_K>;
806 resets = <&rcc SPI5_R>;
807 dmas = <&dmamux1 85 0x400 0x05>,
808 <&dmamux1 86 0x400 0x05>;
809 dma-names = "rx", "tx";
810 status = "disabled";
811 };
812
813 sai1: sai@4400a000 {
814 compatible = "st,stm32h7-sai";
815 #address-cells = <1>;
816 #size-cells = <1>;
817 ranges = <0 0x4400a000 0x400>;
818 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
819 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
820 resets = <&rcc SAI1_R>;
821 status = "disabled";
822
823 sai1a: audio-controller@4400a004 {
824 #sound-dai-cells = <0>;
825
826 compatible = "st,stm32-sai-sub-a";
827 reg = <0x4 0x1c>;
828 clocks = <&rcc SAI1_K>;
829 clock-names = "sai_ck";
830 dmas = <&dmamux1 87 0x400 0x01>;
831 status = "disabled";
832 };
833
834 sai1b: audio-controller@4400a024 {
835 #sound-dai-cells = <0>;
836 compatible = "st,stm32-sai-sub-b";
837 reg = <0x24 0x1c>;
838 clocks = <&rcc SAI1_K>;
839 clock-names = "sai_ck";
840 dmas = <&dmamux1 88 0x400 0x01>;
841 status = "disabled";
842 };
843 };
844
845 sai2: sai@4400b000 {
846 compatible = "st,stm32h7-sai";
847 #address-cells = <1>;
848 #size-cells = <1>;
849 ranges = <0 0x4400b000 0x400>;
850 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
851 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
852 resets = <&rcc SAI2_R>;
853 status = "disabled";
854
855 sai2a: audio-controller@4400b004 {
856 #sound-dai-cells = <0>;
857 compatible = "st,stm32-sai-sub-a";
858 reg = <0x4 0x1c>;
859 clocks = <&rcc SAI2_K>;
860 clock-names = "sai_ck";
861 dmas = <&dmamux1 89 0x400 0x01>;
862 status = "disabled";
863 };
864
865 sai2b: audio-controller@4400b024 {
866 #sound-dai-cells = <0>;
867 compatible = "st,stm32-sai-sub-b";
868 reg = <0x24 0x1c>;
869 clocks = <&rcc SAI2_K>;
870 clock-names = "sai_ck";
871 dmas = <&dmamux1 90 0x400 0x01>;
872 status = "disabled";
873 };
874 };
875
876 sai3: sai@4400c000 {
877 compatible = "st,stm32h7-sai";
878 #address-cells = <1>;
879 #size-cells = <1>;
880 ranges = <0 0x4400c000 0x400>;
881 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
882 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
883 resets = <&rcc SAI3_R>;
884 status = "disabled";
885
886 sai3a: audio-controller@4400c004 {
887 #sound-dai-cells = <0>;
888 compatible = "st,stm32-sai-sub-a";
889 reg = <0x04 0x1c>;
890 clocks = <&rcc SAI3_K>;
891 clock-names = "sai_ck";
892 dmas = <&dmamux1 113 0x400 0x01>;
893 status = "disabled";
894 };
895
896 sai3b: audio-controller@4400c024 {
897 #sound-dai-cells = <0>;
898 compatible = "st,stm32-sai-sub-b";
899 reg = <0x24 0x1c>;
900 clocks = <&rcc SAI3_K>;
901 clock-names = "sai_ck";
902 dmas = <&dmamux1 114 0x400 0x01>;
903 status = "disabled";
904 };
905 };
906
907 dfsdm: dfsdm@4400d000 {
908 compatible = "st,stm32mp1-dfsdm";
909 reg = <0x4400d000 0x800>;
910 clocks = <&rcc DFSDM_K>;
911 clock-names = "dfsdm";
912 #address-cells = <1>;
913 #size-cells = <0>;
914 status = "disabled";
915
916 dfsdm0: filter@0 {
917 compatible = "st,stm32-dfsdm-adc";
918 #io-channel-cells = <1>;
919 reg = <0>;
920 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
921 dmas = <&dmamux1 101 0x400 0x01>;
922 dma-names = "rx";
923 status = "disabled";
924 };
925
926 dfsdm1: filter@1 {
927 compatible = "st,stm32-dfsdm-adc";
928 #io-channel-cells = <1>;
929 reg = <1>;
930 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
931 dmas = <&dmamux1 102 0x400 0x01>;
932 dma-names = "rx";
933 status = "disabled";
934 };
935
936 dfsdm2: filter@2 {
937 compatible = "st,stm32-dfsdm-adc";
938 #io-channel-cells = <1>;
939 reg = <2>;
940 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
941 dmas = <&dmamux1 103 0x400 0x01>;
942 dma-names = "rx";
943 status = "disabled";
944 };
945
946 dfsdm3: filter@3 {
947 compatible = "st,stm32-dfsdm-adc";
948 #io-channel-cells = <1>;
949 reg = <3>;
950 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
951 dmas = <&dmamux1 104 0x400 0x01>;
952 dma-names = "rx";
953 status = "disabled";
954 };
955
956 dfsdm4: filter@4 {
957 compatible = "st,stm32-dfsdm-adc";
958 #io-channel-cells = <1>;
959 reg = <4>;
960 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
961 dmas = <&dmamux1 91 0x400 0x01>;
962 dma-names = "rx";
963 status = "disabled";
964 };
965
966 dfsdm5: filter@5 {
967 compatible = "st,stm32-dfsdm-adc";
968 #io-channel-cells = <1>;
969 reg = <5>;
970 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
971 dmas = <&dmamux1 92 0x400 0x01>;
972 dma-names = "rx";
973 status = "disabled";
974 };
975 };
976
977 dma1: dma-controller@48000000 {
978 compatible = "st,stm32-dma";
979 reg = <0x48000000 0x400>;
980 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&rcc DMA1>;
989 resets = <&rcc DMA1_R>;
990 #dma-cells = <4>;
991 st,mem2mem;
992 dma-requests = <8>;
993 };
994
995 dma2: dma-controller@48001000 {
996 compatible = "st,stm32-dma";
997 reg = <0x48001000 0x400>;
998 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&rcc DMA2>;
1007 resets = <&rcc DMA2_R>;
1008 #dma-cells = <4>;
1009 st,mem2mem;
1010 dma-requests = <8>;
1011 };
1012
1013 dmamux1: dma-router@48002000 {
1014 compatible = "st,stm32h7-dmamux";
1015 reg = <0x48002000 0x40>;
1016 #dma-cells = <3>;
1017 dma-requests = <128>;
1018 dma-masters = <&dma1 &dma2>;
1019 dma-channels = <16>;
1020 clocks = <&rcc DMAMUX>;
1021 resets = <&rcc DMAMUX_R>;
1022 };
1023
1024 adc: adc@48003000 {
1025 compatible = "st,stm32mp1-adc-core";
1026 reg = <0x48003000 0x400>;
1027 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1030 clock-names = "bus", "adc";
1031 interrupt-controller;
1032 st,syscfg = <&syscfg>;
1033 #interrupt-cells = <1>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 status = "disabled";
1037
1038 adc1: adc@0 {
1039 compatible = "st,stm32mp1-adc";
1040 #io-channel-cells = <1>;
1041 reg = <0x0>;
1042 interrupt-parent = <&adc>;
1043 interrupts = <0>;
1044 dmas = <&dmamux1 9 0x400 0x01>;
1045 dma-names = "rx";
1046 status = "disabled";
1047 };
1048
1049 adc2: adc@100 {
1050 compatible = "st,stm32mp1-adc";
1051 #io-channel-cells = <1>;
1052 reg = <0x100>;
1053 interrupt-parent = <&adc>;
1054 interrupts = <1>;
1055 dmas = <&dmamux1 10 0x400 0x01>;
1056 dma-names = "rx";
1057 status = "disabled";
1058 };
1059 };
1060
1061 sdmmc3: mmc@48004000 {
1062 compatible = "arm,pl18x", "arm,primecell";
1063 arm,primecell-periphid = <0x00253180>;
1064 reg = <0x48004000 0x400>;
1065 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1066 interrupt-names = "cmd_irq";
1067 clocks = <&rcc SDMMC3_K>;
1068 clock-names = "apb_pclk";
1069 resets = <&rcc SDMMC3_R>;
1070 cap-sd-highspeed;
1071 cap-mmc-highspeed;
1072 max-frequency = <120000000>;
1073 status = "disabled";
1074 };
1075
1076 usbotg_hs: usb-otg@49000000 {
1077 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1078 reg = <0x49000000 0x10000>;
1079 clocks = <&rcc USBO_K>;
1080 clock-names = "otg";
1081 resets = <&rcc USBO_R>;
1082 reset-names = "dwc2";
1083 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1084 g-rx-fifo-size = <512>;
1085 g-np-tx-fifo-size = <32>;
1086 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1087 dr_mode = "otg";
1088 usb33d-supply = <&usb33>;
1089 status = "disabled";
1090 };
1091
1092 ipcc: mailbox@4c001000 {
1093 compatible = "st,stm32mp1-ipcc";
1094 #mbox-cells = <1>;
1095 reg = <0x4c001000 0x400>;
1096 st,proc-id = <0>;
1097 interrupts-extended =
1098 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1099 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1100 <&exti 61 1>;
1101 interrupt-names = "rx", "tx", "wakeup";
1102 clocks = <&rcc IPCC>;
1103 wakeup-source;
1104 status = "disabled";
1105 };
1106
1107 dcmi: dcmi@4c006000 {
1108 compatible = "st,stm32-dcmi";
1109 reg = <0x4c006000 0x400>;
1110 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1111 resets = <&rcc CAMITF_R>;
1112 clocks = <&rcc DCMI>;
1113 clock-names = "mclk";
1114 dmas = <&dmamux1 75 0x400 0x01>;
1115 dma-names = "tx";
1116 status = "disabled";
1117 };
1118
1119 rcc: rcc@50000000 {
1120 compatible = "st,stm32mp1-rcc", "syscon";
1121 reg = <0x50000000 0x1000>;
1122 #clock-cells = <1>;
1123 #reset-cells = <1>;
1124 };
1125
1126 pwr_regulators: pwr@50001000 {
1127 compatible = "st,stm32mp1,pwr-reg";
1128 reg = <0x50001000 0x10>;
1129
1130 reg11: reg11 {
1131 regulator-name = "reg11";
1132 regulator-min-microvolt = <1100000>;
1133 regulator-max-microvolt = <1100000>;
1134 };
1135
1136 reg18: reg18 {
1137 regulator-name = "reg18";
1138 regulator-min-microvolt = <1800000>;
1139 regulator-max-microvolt = <1800000>;
1140 };
1141
1142 usb33: usb33 {
1143 regulator-name = "usb33";
1144 regulator-min-microvolt = <3300000>;
1145 regulator-max-microvolt = <3300000>;
1146 };
1147 };
1148
1149 pwr_mcu: pwr_mcu@50001014 {
1150 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1151 reg = <0x50001014 0x4>;
1152 };
1153
1154 exti: interrupt-controller@5000d000 {
1155 compatible = "st,stm32mp1-exti", "syscon";
1156 interrupt-controller;
1157 #interrupt-cells = <2>;
1158 reg = <0x5000d000 0x400>;
1159 };
1160
1161 syscfg: syscon@50020000 {
1162 compatible = "st,stm32mp157-syscfg", "syscon";
1163 reg = <0x50020000 0x400>;
1164 clocks = <&rcc SYSCFG>;
1165 };
1166
1167 lptimer2: timer@50021000 {
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170 compatible = "st,stm32-lptimer";
1171 reg = <0x50021000 0x400>;
1172 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1173 clocks = <&rcc LPTIM2_K>;
1174 clock-names = "mux";
1175 wakeup-source;
1176 status = "disabled";
1177
1178 pwm {
1179 compatible = "st,stm32-pwm-lp";
1180 #pwm-cells = <3>;
1181 status = "disabled";
1182 };
1183
1184 trigger@1 {
1185 compatible = "st,stm32-lptimer-trigger";
1186 reg = <1>;
1187 status = "disabled";
1188 };
1189
1190 counter {
1191 compatible = "st,stm32-lptimer-counter";
1192 status = "disabled";
1193 };
1194 };
1195
1196 lptimer3: timer@50022000 {
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 compatible = "st,stm32-lptimer";
1200 reg = <0x50022000 0x400>;
1201 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&rcc LPTIM3_K>;
1203 clock-names = "mux";
1204 wakeup-source;
1205 status = "disabled";
1206
1207 pwm {
1208 compatible = "st,stm32-pwm-lp";
1209 #pwm-cells = <3>;
1210 status = "disabled";
1211 };
1212
1213 trigger@2 {
1214 compatible = "st,stm32-lptimer-trigger";
1215 reg = <2>;
1216 status = "disabled";
1217 };
1218 };
1219
1220 lptimer4: timer@50023000 {
1221 compatible = "st,stm32-lptimer";
1222 reg = <0x50023000 0x400>;
1223 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&rcc LPTIM4_K>;
1225 clock-names = "mux";
1226 wakeup-source;
1227 status = "disabled";
1228
1229 pwm {
1230 compatible = "st,stm32-pwm-lp";
1231 #pwm-cells = <3>;
1232 status = "disabled";
1233 };
1234 };
1235
1236 lptimer5: timer@50024000 {
1237 compatible = "st,stm32-lptimer";
1238 reg = <0x50024000 0x400>;
1239 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&rcc LPTIM5_K>;
1241 clock-names = "mux";
1242 wakeup-source;
1243 status = "disabled";
1244
1245 pwm {
1246 compatible = "st,stm32-pwm-lp";
1247 #pwm-cells = <3>;
1248 status = "disabled";
1249 };
1250 };
1251
1252 vrefbuf: vrefbuf@50025000 {
1253 compatible = "st,stm32-vrefbuf";
1254 reg = <0x50025000 0x8>;
1255 regulator-min-microvolt = <1500000>;
1256 regulator-max-microvolt = <2500000>;
1257 clocks = <&rcc VREF>;
1258 status = "disabled";
1259 };
1260
1261 sai4: sai@50027000 {
1262 compatible = "st,stm32h7-sai";
1263 #address-cells = <1>;
1264 #size-cells = <1>;
1265 ranges = <0 0x50027000 0x400>;
1266 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1267 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1268 resets = <&rcc SAI4_R>;
1269 status = "disabled";
1270
1271 sai4a: audio-controller@50027004 {
1272 #sound-dai-cells = <0>;
1273 compatible = "st,stm32-sai-sub-a";
1274 reg = <0x04 0x1c>;
1275 clocks = <&rcc SAI4_K>;
1276 clock-names = "sai_ck";
1277 dmas = <&dmamux1 99 0x400 0x01>;
1278 status = "disabled";
1279 };
1280
1281 sai4b: audio-controller@50027024 {
1282 #sound-dai-cells = <0>;
1283 compatible = "st,stm32-sai-sub-b";
1284 reg = <0x24 0x1c>;
1285 clocks = <&rcc SAI4_K>;
1286 clock-names = "sai_ck";
1287 dmas = <&dmamux1 100 0x400 0x01>;
1288 status = "disabled";
1289 };
1290 };
1291
1292 dts: thermal@50028000 {
1293 compatible = "st,stm32-thermal";
1294 reg = <0x50028000 0x100>;
1295 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&rcc TMPSENS>;
1297 clock-names = "pclk";
1298 #thermal-sensor-cells = <0>;
1299 status = "disabled";
1300 };
1301
1302 hash1: hash@54002000 {
1303 compatible = "st,stm32f756-hash";
1304 reg = <0x54002000 0x400>;
1305 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1306 clocks = <&rcc HASH1>;
1307 resets = <&rcc HASH1_R>;
1308 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1309 dma-names = "in";
1310 dma-maxburst = <2>;
1311 status = "disabled";
1312 };
1313
1314 rng1: rng@54003000 {
1315 compatible = "st,stm32-rng";
1316 reg = <0x54003000 0x400>;
1317 clocks = <&rcc RNG1_K>;
1318 resets = <&rcc RNG1_R>;
1319 status = "disabled";
1320 };
1321
1322 mdma1: dma-controller@58000000 {
1323 compatible = "st,stm32h7-mdma";
1324 reg = <0x58000000 0x1000>;
1325 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&rcc MDMA>;
1327 resets = <&rcc MDMA_R>;
1328 #dma-cells = <5>;
1329 dma-channels = <32>;
1330 dma-requests = <48>;
1331 };
1332
1333 fmc: memory-controller@58002000 {
1334 #address-cells = <2>;
1335 #size-cells = <1>;
1336 compatible = "st,stm32mp1-fmc2-ebi";
1337 reg = <0x58002000 0x1000>;
1338 clocks = <&rcc FMC_K>;
1339 resets = <&rcc FMC_R>;
1340 status = "disabled";
1341
1342 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1343 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1344 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1345 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1346 <4 0 0x80000000 0x10000000>; /* NAND */
1347
1348 nand-controller@4,0 {
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1351 compatible = "st,stm32mp1-fmc2-nfc";
1352 reg = <4 0x00000000 0x1000>,
1353 <4 0x08010000 0x1000>,
1354 <4 0x08020000 0x1000>,
1355 <4 0x01000000 0x1000>,
1356 <4 0x09010000 0x1000>,
1357 <4 0x09020000 0x1000>;
1358 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1359 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1360 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1361 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1362 dma-names = "tx", "rx", "ecc";
1363 status = "disabled";
1364 };
1365 };
1366
1367 qspi: spi@58003000 {
1368 compatible = "st,stm32f469-qspi";
1369 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1370 reg-names = "qspi", "qspi_mm";
1371 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1372 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1373 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1374 dma-names = "tx", "rx";
1375 clocks = <&rcc QSPI_K>;
1376 resets = <&rcc QSPI_R>;
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1379 status = "disabled";
1380 };
1381
1382 sdmmc1: mmc@58005000 {
1383 compatible = "arm,pl18x", "arm,primecell";
1384 arm,primecell-periphid = <0x00253180>;
1385 reg = <0x58005000 0x1000>;
1386 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1387 interrupt-names = "cmd_irq";
1388 clocks = <&rcc SDMMC1_K>;
1389 clock-names = "apb_pclk";
1390 resets = <&rcc SDMMC1_R>;
1391 cap-sd-highspeed;
1392 cap-mmc-highspeed;
1393 max-frequency = <120000000>;
1394 status = "disabled";
1395 };
1396
1397 sdmmc2: mmc@58007000 {
1398 compatible = "arm,pl18x", "arm,primecell";
1399 arm,primecell-periphid = <0x00253180>;
1400 reg = <0x58007000 0x1000>;
1401 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1402 interrupt-names = "cmd_irq";
1403 clocks = <&rcc SDMMC2_K>;
1404 clock-names = "apb_pclk";
1405 resets = <&rcc SDMMC2_R>;
1406 cap-sd-highspeed;
1407 cap-mmc-highspeed;
1408 max-frequency = <120000000>;
1409 status = "disabled";
1410 };
1411
1412 crc1: crc@58009000 {
1413 compatible = "st,stm32f7-crc";
1414 reg = <0x58009000 0x400>;
1415 clocks = <&rcc CRC1>;
1416 status = "disabled";
1417 };
1418
1419 ethernet0: ethernet@5800a000 {
1420 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1421 reg = <0x5800a000 0x2000>;
1422 reg-names = "stmmaceth";
1423 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1424 interrupt-names = "macirq";
1425 clock-names = "stmmaceth",
1426 "mac-clk-tx",
1427 "mac-clk-rx",
1428 "eth-ck",
1429 "ptp_ref",
1430 "ethstp";
1431 clocks = <&rcc ETHMAC>,
1432 <&rcc ETHTX>,
1433 <&rcc ETHRX>,
1434 <&rcc ETHCK_K>,
1435 <&rcc ETHPTP_K>,
1436 <&rcc ETHSTP>;
1437 st,syscon = <&syscfg 0x4>;
1438 snps,mixed-burst;
1439 snps,pbl = <2>;
1440 snps,en-tx-lpi-clockgating;
1441 snps,axi-config = <&stmmac_axi_config_0>;
1442 snps,tso;
1443 status = "disabled";
1444
1445 stmmac_axi_config_0: stmmac-axi-config {
1446 snps,wr_osr_lmt = <0x7>;
1447 snps,rd_osr_lmt = <0x7>;
1448 snps,blen = <0 0 0 0 16 8 4>;
1449 };
1450 };
1451
1452 usbh_ohci: usb@5800c000 {
1453 compatible = "generic-ohci";
1454 reg = <0x5800c000 0x1000>;
1455 clocks = <&rcc USBH>;
1456 resets = <&rcc USBH_R>;
1457 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1458 status = "disabled";
1459 };
1460
1461 usbh_ehci: usb@5800d000 {
1462 compatible = "generic-ehci";
1463 reg = <0x5800d000 0x1000>;
1464 clocks = <&rcc USBH>;
1465 resets = <&rcc USBH_R>;
1466 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1467 companion = <&usbh_ohci>;
1468 status = "disabled";
1469 };
1470
1471 ltdc: display-controller@5a001000 {
1472 compatible = "st,stm32-ltdc";
1473 reg = <0x5a001000 0x400>;
1474 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&rcc LTDC_PX>;
1477 clock-names = "lcd";
1478 resets = <&rcc LTDC_R>;
1479 status = "disabled";
1480
1481 port {
1482 #address-cells = <1>;
1483 #size-cells = <0>;
1484 };
1485 };
1486
1487 iwdg2: watchdog@5a002000 {
1488 compatible = "st,stm32mp1-iwdg";
1489 reg = <0x5a002000 0x400>;
1490 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1491 clock-names = "pclk", "lsi";
1492 status = "disabled";
1493 };
1494
1495 usbphyc: usbphyc@5a006000 {
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 #clock-cells = <0>;
1499 compatible = "st,stm32mp1-usbphyc";
1500 reg = <0x5a006000 0x1000>;
1501 clocks = <&rcc USBPHY_K>;
1502 resets = <&rcc USBPHY_R>;
1503 vdda1v1-supply = <®11>;
1504 vdda1v8-supply = <®18>;
1505 status = "disabled";
1506
1507 usbphyc_port0: usb-phy@0 {
1508 #phy-cells = <0>;
1509 reg = <0>;
1510 };
1511
1512 usbphyc_port1: usb-phy@1 {
1513 #phy-cells = <1>;
1514 reg = <1>;
1515 };
1516 };
1517
1518 usart1: serial@5c000000 {
1519 compatible = "st,stm32h7-uart";
1520 reg = <0x5c000000 0x400>;
1521 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1522 clocks = <&rcc USART1_K>;
1523 wakeup-source;
1524 status = "disabled";
1525 };
1526
1527 spi6: spi@5c001000 {
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 compatible = "st,stm32h7-spi";
1531 reg = <0x5c001000 0x400>;
1532 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&rcc SPI6_K>;
1534 resets = <&rcc SPI6_R>;
1535 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1536 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1537 dma-names = "rx", "tx";
1538 status = "disabled";
1539 };
1540
1541 i2c4: i2c@5c002000 {
1542 compatible = "st,stm32mp15-i2c";
1543 reg = <0x5c002000 0x400>;
1544 interrupt-names = "event", "error";
1545 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1547 clocks = <&rcc I2C4_K>;
1548 resets = <&rcc I2C4_R>;
1549 #address-cells = <1>;
1550 #size-cells = <0>;
1551 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1552 wakeup-source;
1553 i2c-analog-filter;
1554 status = "disabled";
1555 };
1556
1557 rtc: rtc@5c004000 {
1558 compatible = "st,stm32mp1-rtc";
1559 reg = <0x5c004000 0x400>;
1560 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1561 clock-names = "pclk", "rtc_ck";
1562 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1563 status = "disabled";
1564 };
1565
1566 bsec: efuse@5c005000 {
1567 compatible = "st,stm32mp15-bsec";
1568 reg = <0x5c005000 0x400>;
1569 #address-cells = <1>;
1570 #size-cells = <1>;
1571 ts_cal1: calib@5c {
1572 reg = <0x5c 0x2>;
1573 };
1574 ts_cal2: calib@5e {
1575 reg = <0x5e 0x2>;
1576 };
1577 };
1578
1579 i2c6: i2c@5c009000 {
1580 compatible = "st,stm32mp15-i2c";
1581 reg = <0x5c009000 0x400>;
1582 interrupt-names = "event", "error";
1583 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&rcc I2C6_K>;
1586 resets = <&rcc I2C6_R>;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1590 wakeup-source;
1591 i2c-analog-filter;
1592 status = "disabled";
1593 };
1594
1595 tamp: tamp@5c00a000 {
1596 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1597 reg = <0x5c00a000 0x400>;
1598 };
1599
1600 /*
1601 * Break node order to solve dependency probe issue between
1602 * pinctrl and exti.
1603 */
1604 pinctrl: pin-controller@50002000 {
1605 #address-cells = <1>;
1606 #size-cells = <1>;
1607 compatible = "st,stm32mp157-pinctrl";
1608 ranges = <0 0x50002000 0xa400>;
1609 interrupt-parent = <&exti>;
1610 st,syscfg = <&exti 0x60 0xff>;
1611 pins-are-numbered;
1612
1613 gpioa: gpio@50002000 {
1614 gpio-controller;
1615 #gpio-cells = <2>;
1616 interrupt-controller;
1617 #interrupt-cells = <2>;
1618 reg = <0x0 0x400>;
1619 clocks = <&rcc GPIOA>;
1620 st,bank-name = "GPIOA";
1621 status = "disabled";
1622 };
1623
1624 gpiob: gpio@50003000 {
1625 gpio-controller;
1626 #gpio-cells = <2>;
1627 interrupt-controller;
1628 #interrupt-cells = <2>;
1629 reg = <0x1000 0x400>;
1630 clocks = <&rcc GPIOB>;
1631 st,bank-name = "GPIOB";
1632 status = "disabled";
1633 };
1634
1635 gpioc: gpio@50004000 {
1636 gpio-controller;
1637 #gpio-cells = <2>;
1638 interrupt-controller;
1639 #interrupt-cells = <2>;
1640 reg = <0x2000 0x400>;
1641 clocks = <&rcc GPIOC>;
1642 st,bank-name = "GPIOC";
1643 status = "disabled";
1644 };
1645
1646 gpiod: gpio@50005000 {
1647 gpio-controller;
1648 #gpio-cells = <2>;
1649 interrupt-controller;
1650 #interrupt-cells = <2>;
1651 reg = <0x3000 0x400>;
1652 clocks = <&rcc GPIOD>;
1653 st,bank-name = "GPIOD";
1654 status = "disabled";
1655 };
1656
1657 gpioe: gpio@50006000 {
1658 gpio-controller;
1659 #gpio-cells = <2>;
1660 interrupt-controller;
1661 #interrupt-cells = <2>;
1662 reg = <0x4000 0x400>;
1663 clocks = <&rcc GPIOE>;
1664 st,bank-name = "GPIOE";
1665 status = "disabled";
1666 };
1667
1668 gpiof: gpio@50007000 {
1669 gpio-controller;
1670 #gpio-cells = <2>;
1671 interrupt-controller;
1672 #interrupt-cells = <2>;
1673 reg = <0x5000 0x400>;
1674 clocks = <&rcc GPIOF>;
1675 st,bank-name = "GPIOF";
1676 status = "disabled";
1677 };
1678
1679 gpiog: gpio@50008000 {
1680 gpio-controller;
1681 #gpio-cells = <2>;
1682 interrupt-controller;
1683 #interrupt-cells = <2>;
1684 reg = <0x6000 0x400>;
1685 clocks = <&rcc GPIOG>;
1686 st,bank-name = "GPIOG";
1687 status = "disabled";
1688 };
1689
1690 gpioh: gpio@50009000 {
1691 gpio-controller;
1692 #gpio-cells = <2>;
1693 interrupt-controller;
1694 #interrupt-cells = <2>;
1695 reg = <0x7000 0x400>;
1696 clocks = <&rcc GPIOH>;
1697 st,bank-name = "GPIOH";
1698 status = "disabled";
1699 };
1700
1701 gpioi: gpio@5000a000 {
1702 gpio-controller;
1703 #gpio-cells = <2>;
1704 interrupt-controller;
1705 #interrupt-cells = <2>;
1706 reg = <0x8000 0x400>;
1707 clocks = <&rcc GPIOI>;
1708 st,bank-name = "GPIOI";
1709 status = "disabled";
1710 };
1711
1712 gpioj: gpio@5000b000 {
1713 gpio-controller;
1714 #gpio-cells = <2>;
1715 interrupt-controller;
1716 #interrupt-cells = <2>;
1717 reg = <0x9000 0x400>;
1718 clocks = <&rcc GPIOJ>;
1719 st,bank-name = "GPIOJ";
1720 status = "disabled";
1721 };
1722
1723 gpiok: gpio@5000c000 {
1724 gpio-controller;
1725 #gpio-cells = <2>;
1726 interrupt-controller;
1727 #interrupt-cells = <2>;
1728 reg = <0xa000 0x400>;
1729 clocks = <&rcc GPIOK>;
1730 st,bank-name = "GPIOK";
1731 status = "disabled";
1732 };
1733 };
1734
1735 pinctrl_z: pin-controller-z@54004000 {
1736 #address-cells = <1>;
1737 #size-cells = <1>;
1738 compatible = "st,stm32mp157-z-pinctrl";
1739 ranges = <0 0x54004000 0x400>;
1740 pins-are-numbered;
1741 interrupt-parent = <&exti>;
1742 st,syscfg = <&exti 0x60 0xff>;
1743
1744 gpioz: gpio@54004000 {
1745 gpio-controller;
1746 #gpio-cells = <2>;
1747 interrupt-controller;
1748 #interrupt-cells = <2>;
1749 reg = <0 0x400>;
1750 clocks = <&rcc GPIOZ>;
1751 st,bank-name = "GPIOZ";
1752 st,bank-ioport = <11>;
1753 status = "disabled";
1754 };
1755 };
1756 };
1757
1758 mlahb: ahb {
1759 compatible = "st,mlahb", "simple-bus";
1760 #address-cells = <1>;
1761 #size-cells = <1>;
1762 ranges;
1763 dma-ranges = <0x00000000 0x38000000 0x10000>,
1764 <0x10000000 0x10000000 0x60000>,
1765 <0x30000000 0x30000000 0x60000>;
1766
1767 m4_rproc: m4@10000000 {
1768 compatible = "st,stm32mp1-m4";
1769 reg = <0x10000000 0x40000>,
1770 <0x30000000 0x40000>,
1771 <0x38000000 0x10000>;
1772 resets = <&rcc MCU_R>;
1773 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1774 st,syscfg-tz = <&rcc 0x000 0x1>;
1775 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1776 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1777 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1778 status = "disabled";
1779 };
1780 };
1781};