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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-apq8084.h>
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 model = "Qualcomm APQ 8084";
12 compatible = "qcom,apq8084";
13 interrupt-parent = <&intc>;
14
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 smem_mem: smem_region@fa00000 {
21 reg = <0xfa00000 0x200000>;
22 no-map;
23 };
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "qcom,krait";
33 reg = <0>;
34 enable-method = "qcom,kpss-acc-v2";
35 next-level-cache = <&L2>;
36 qcom,acc = <&acc0>;
37 qcom,saw = <&saw0>;
38 cpu-idle-states = <&CPU_SPC>;
39 };
40
41 cpu@1 {
42 device_type = "cpu";
43 compatible = "qcom,krait";
44 reg = <1>;
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc1>;
48 qcom,saw = <&saw1>;
49 cpu-idle-states = <&CPU_SPC>;
50 };
51
52 cpu@2 {
53 device_type = "cpu";
54 compatible = "qcom,krait";
55 reg = <2>;
56 enable-method = "qcom,kpss-acc-v2";
57 next-level-cache = <&L2>;
58 qcom,acc = <&acc2>;
59 qcom,saw = <&saw2>;
60 cpu-idle-states = <&CPU_SPC>;
61 };
62
63 cpu@3 {
64 device_type = "cpu";
65 compatible = "qcom,krait";
66 reg = <3>;
67 enable-method = "qcom,kpss-acc-v2";
68 next-level-cache = <&L2>;
69 qcom,acc = <&acc3>;
70 qcom,saw = <&saw3>;
71 cpu-idle-states = <&CPU_SPC>;
72 };
73
74 L2: l2-cache {
75 compatible = "cache";
76 cache-level = <2>;
77 qcom,saw = <&saw_l2>;
78 };
79
80 idle-states {
81 CPU_SPC: spc {
82 compatible = "qcom,idle-state-spc",
83 "arm,idle-state";
84 entry-latency-us = <150>;
85 exit-latency-us = <200>;
86 min-residency-us = <2000>;
87 };
88 };
89 };
90
91 memory {
92 device_type = "memory";
93 reg = <0x0 0x0>;
94 };
95
96 firmware {
97 scm {
98 compatible = "qcom,scm-apq8084", "qcom,scm";
99 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
100 clock-names = "core", "bus", "iface";
101 };
102 };
103
104 thermal-zones {
105 cpu0-thermal {
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
108
109 thermal-sensors = <&tsens 5>;
110
111 trips {
112 cpu_alert0: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit0: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu1-thermal {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&tsens 6>;
130
131 trips {
132 cpu_alert1: trip0 {
133 temperature = <75000>;
134 hysteresis = <2000>;
135 type = "passive";
136 };
137 cpu_crit1: trip1 {
138 temperature = <110000>;
139 hysteresis = <2000>;
140 type = "critical";
141 };
142 };
143 };
144
145 cpu2-thermal {
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
148
149 thermal-sensors = <&tsens 7>;
150
151 trips {
152 cpu_alert2: trip0 {
153 temperature = <75000>;
154 hysteresis = <2000>;
155 type = "passive";
156 };
157 cpu_crit2: trip1 {
158 temperature = <110000>;
159 hysteresis = <2000>;
160 type = "critical";
161 };
162 };
163 };
164
165 cpu3-thermal {
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
168
169 thermal-sensors = <&tsens 8>;
170
171 trips {
172 cpu_alert3: trip0 {
173 temperature = <75000>;
174 hysteresis = <2000>;
175 type = "passive";
176 };
177 cpu_crit3: trip1 {
178 temperature = <110000>;
179 hysteresis = <2000>;
180 type = "critical";
181 };
182 };
183 };
184 };
185
186 cpu-pmu {
187 compatible = "qcom,krait-pmu";
188 interrupts = <GIC_PPI 7 0xf04>;
189 };
190
191 clocks {
192 xo_board: xo_board {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <19200000>;
196 };
197
198 sleep_clk: sleep_clk {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <32768>;
202 };
203 };
204
205 timer {
206 compatible = "arm,armv7-timer";
207 interrupts = <GIC_PPI 2 0xf08>,
208 <GIC_PPI 3 0xf08>,
209 <GIC_PPI 4 0xf08>,
210 <GIC_PPI 1 0xf08>;
211 clock-frequency = <19200000>;
212 };
213
214 smem {
215 compatible = "qcom,smem";
216
217 qcom,rpm-msg-ram = <&rpm_msg_ram>;
218 memory-region = <&smem_mem>;
219
220 hwlocks = <&tcsr_mutex 3>;
221 };
222
223 soc: soc {
224 #address-cells = <1>;
225 #size-cells = <1>;
226 ranges;
227 compatible = "simple-bus";
228
229 intc: interrupt-controller@f9000000 {
230 compatible = "qcom,msm-qgic2";
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 reg = <0xf9000000 0x1000>,
234 <0xf9002000 0x1000>;
235 };
236
237 apcs: syscon@f9011000 {
238 compatible = "syscon";
239 reg = <0xf9011000 0x1000>;
240 };
241
242 sram@fc190000 {
243 compatible = "qcom,apq8084-rpm-stats";
244 reg = <0xfc190000 0x10000>;
245 };
246
247 qfprom: qfprom@fc4bc000 {
248 compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
249 reg = <0xfc4bc000 0x1000>;
250 #address-cells = <1>;
251 #size-cells = <1>;
252 tsens_calib: calib@d0 {
253 reg = <0xd0 0x18>;
254 };
255 tsens_backup: backup@440 {
256 reg = <0x440 0x10>;
257 };
258 };
259
260 tsens: thermal-sensor@fc4a8000 {
261 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
262 reg = <0xfc4a9000 0x1000>, /* TM */
263 <0xfc4a8000 0x1000>; /* SROT */
264 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
265 nvmem-cell-names = "calib", "calib_backup";
266 #qcom,sensors = <11>;
267 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-names = "uplow";
269 #thermal-sensor-cells = <1>;
270 };
271 timer@f9020000 {
272 #address-cells = <1>;
273 #size-cells = <1>;
274 ranges;
275 compatible = "arm,armv7-timer-mem";
276 reg = <0xf9020000 0x1000>;
277 clock-frequency = <19200000>;
278
279 frame@f9021000 {
280 frame-number = <0>;
281 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
283 reg = <0xf9021000 0x1000>,
284 <0xf9022000 0x1000>;
285 };
286
287 frame@f9023000 {
288 frame-number = <1>;
289 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
290 reg = <0xf9023000 0x1000>;
291 status = "disabled";
292 };
293
294 frame@f9024000 {
295 frame-number = <2>;
296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
297 reg = <0xf9024000 0x1000>;
298 status = "disabled";
299 };
300
301 frame@f9025000 {
302 frame-number = <3>;
303 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
304 reg = <0xf9025000 0x1000>;
305 status = "disabled";
306 };
307
308 frame@f9026000 {
309 frame-number = <4>;
310 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
311 reg = <0xf9026000 0x1000>;
312 status = "disabled";
313 };
314
315 frame@f9027000 {
316 frame-number = <5>;
317 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
318 reg = <0xf9027000 0x1000>;
319 status = "disabled";
320 };
321
322 frame@f9028000 {
323 frame-number = <6>;
324 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
325 reg = <0xf9028000 0x1000>;
326 status = "disabled";
327 };
328 };
329
330 saw0: power-controller@f9089000 {
331 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
332 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
333 };
334
335 saw1: power-controller@f9099000 {
336 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
337 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
338 };
339
340 saw2: power-controller@f90a9000 {
341 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
342 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
343 };
344
345 saw3: power-controller@f90b9000 {
346 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
347 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
348 };
349
350 saw_l2: power-controller@f9012000 {
351 compatible = "qcom,saw2";
352 reg = <0xf9012000 0x1000>;
353 regulator;
354 };
355
356 acc0: clock-controller@f9088000 {
357 compatible = "qcom,kpss-acc-v2";
358 reg = <0xf9088000 0x1000>,
359 <0xf9008000 0x1000>;
360 };
361
362 acc1: clock-controller@f9098000 {
363 compatible = "qcom,kpss-acc-v2";
364 reg = <0xf9098000 0x1000>,
365 <0xf9008000 0x1000>;
366 };
367
368 acc2: clock-controller@f90a8000 {
369 compatible = "qcom,kpss-acc-v2";
370 reg = <0xf90a8000 0x1000>,
371 <0xf9008000 0x1000>;
372 };
373
374 acc3: clock-controller@f90b8000 {
375 compatible = "qcom,kpss-acc-v2";
376 reg = <0xf90b8000 0x1000>,
377 <0xf9008000 0x1000>;
378 };
379
380 restart@fc4ab000 {
381 compatible = "qcom,pshold";
382 reg = <0xfc4ab000 0x4>;
383 };
384
385 gcc: clock-controller@fc400000 {
386 compatible = "qcom,gcc-apq8084";
387 #clock-cells = <1>;
388 #reset-cells = <1>;
389 #power-domain-cells = <1>;
390 reg = <0xfc400000 0x4000>;
391 };
392
393 tcsr_mutex: hwlock@fd484000 {
394 compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
395 reg = <0xfd484000 0x1000>;
396 #hwlock-cells = <1>;
397 };
398
399 rpm_msg_ram: sram@fc428000 {
400 compatible = "qcom,rpm-msg-ram";
401 reg = <0xfc428000 0x4000>;
402 };
403
404 tlmm: pinctrl@fd510000 {
405 compatible = "qcom,apq8084-pinctrl";
406 reg = <0xfd510000 0x4000>;
407 gpio-controller;
408 gpio-ranges = <&tlmm 0 0 147>;
409 #gpio-cells = <2>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
413 };
414
415 blsp2_uart2: serial@f995e000 {
416 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
417 reg = <0xf995e000 0x1000>;
418 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
420 clock-names = "core", "iface";
421 status = "disabled";
422 };
423
424 sdhc_1: mmc@f9824900 {
425 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
426 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
427 reg-names = "hc", "core";
428 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "hc_irq", "pwr_irq";
430 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
431 <&gcc GCC_SDCC1_APPS_CLK>,
432 <&xo_board>;
433 clock-names = "iface", "core", "xo";
434 status = "disabled";
435 };
436
437 sdhc_2: mmc@f98a4900 {
438 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
439 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
440 reg-names = "hc", "core";
441 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-names = "hc_irq", "pwr_irq";
443 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
444 <&gcc GCC_SDCC2_APPS_CLK>,
445 <&xo_board>;
446 clock-names = "iface", "core", "xo";
447 status = "disabled";
448 };
449
450 spmi_bus: spmi@fc4cf000 {
451 compatible = "qcom,spmi-pmic-arb";
452 reg-names = "core", "intr", "cnfg";
453 reg = <0xfc4cf000 0x1000>,
454 <0xfc4cb000 0x1000>,
455 <0xfc4ca000 0x1000>;
456 interrupt-names = "periph_irq";
457 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
458 qcom,ee = <0>;
459 qcom,channel = <0>;
460 #address-cells = <2>;
461 #size-cells = <0>;
462 interrupt-controller;
463 #interrupt-cells = <4>;
464 };
465 };
466
467 smd {
468 compatible = "qcom,smd";
469
470 rpm {
471 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
472 qcom,ipc = <&apcs 8 0>;
473 qcom,smd-edge = <15>;
474
475 rpm-requests {
476 compatible = "qcom,rpm-apq8084";
477 qcom,smd-channels = "rpm_requests";
478
479 regulators-0 {
480 compatible = "qcom,rpm-pma8084-regulators";
481
482 pma8084_s1: s1 {};
483 pma8084_s2: s2 {};
484 pma8084_s3: s3 {};
485 pma8084_s4: s4 {};
486 pma8084_s5: s5 {};
487 pma8084_s6: s6 {};
488 pma8084_s7: s7 {};
489 pma8084_s8: s8 {};
490 pma8084_s9: s9 {};
491 pma8084_s10: s10 {};
492 pma8084_s11: s11 {};
493 pma8084_s12: s12 {};
494
495 pma8084_l1: l1 {};
496 pma8084_l2: l2 {};
497 pma8084_l3: l3 {};
498 pma8084_l4: l4 {};
499 pma8084_l5: l5 {};
500 pma8084_l6: l6 {};
501 pma8084_l7: l7 {};
502 pma8084_l8: l8 {};
503 pma8084_l9: l9 {};
504 pma8084_l10: l10 {};
505 pma8084_l11: l11 {};
506 pma8084_l12: l12 {};
507 pma8084_l13: l13 {};
508 pma8084_l14: l14 {};
509 pma8084_l15: l15 {};
510 pma8084_l16: l16 {};
511 pma8084_l17: l17 {};
512 pma8084_l18: l18 {};
513 pma8084_l19: l19 {};
514 pma8084_l20: l20 {};
515 pma8084_l21: l21 {};
516 pma8084_l22: l22 {};
517 pma8084_l23: l23 {};
518 pma8084_l24: l24 {};
519 pma8084_l25: l25 {};
520 pma8084_l26: l26 {};
521 pma8084_l27: l27 {};
522
523 pma8084_lvs1: lvs1 {};
524 pma8084_lvs2: lvs2 {};
525 pma8084_lvs3: lvs3 {};
526 pma8084_lvs4: lvs4 {};
527
528 pma8084_5vs1: 5vs1 {};
529 };
530 };
531 };
532 };
533};
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-apq8084.h>
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 model = "Qualcomm APQ 8084";
12 compatible = "qcom,apq8084";
13 interrupt-parent = <&intc>;
14
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 smem_mem: smem_region@fa00000 {
21 reg = <0xfa00000 0x200000>;
22 no-map;
23 };
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "qcom,krait";
33 reg = <0>;
34 enable-method = "qcom,kpss-acc-v2";
35 next-level-cache = <&L2>;
36 qcom,acc = <&acc0>;
37 qcom,saw = <&saw0>;
38 cpu-idle-states = <&CPU_SPC>;
39 };
40
41 cpu@1 {
42 device_type = "cpu";
43 compatible = "qcom,krait";
44 reg = <1>;
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc1>;
48 qcom,saw = <&saw1>;
49 cpu-idle-states = <&CPU_SPC>;
50 };
51
52 cpu@2 {
53 device_type = "cpu";
54 compatible = "qcom,krait";
55 reg = <2>;
56 enable-method = "qcom,kpss-acc-v2";
57 next-level-cache = <&L2>;
58 qcom,acc = <&acc2>;
59 qcom,saw = <&saw2>;
60 cpu-idle-states = <&CPU_SPC>;
61 };
62
63 cpu@3 {
64 device_type = "cpu";
65 compatible = "qcom,krait";
66 reg = <3>;
67 enable-method = "qcom,kpss-acc-v2";
68 next-level-cache = <&L2>;
69 qcom,acc = <&acc3>;
70 qcom,saw = <&saw3>;
71 cpu-idle-states = <&CPU_SPC>;
72 };
73
74 L2: l2-cache {
75 compatible = "qcom,arch-cache";
76 cache-level = <2>;
77 qcom,saw = <&saw_l2>;
78 };
79
80 idle-states {
81 CPU_SPC: spc {
82 compatible = "qcom,idle-state-spc",
83 "arm,idle-state";
84 entry-latency-us = <150>;
85 exit-latency-us = <200>;
86 min-residency-us = <2000>;
87 };
88 };
89 };
90
91 memory {
92 device_type = "memory";
93 reg = <0x0 0x0>;
94 };
95
96 firmware {
97 scm {
98 compatible = "qcom,scm";
99 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
100 clock-names = "core", "bus", "iface";
101 };
102 };
103
104 thermal-zones {
105 cpu-thermal0 {
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
108
109 thermal-sensors = <&tsens 5>;
110
111 trips {
112 cpu_alert0: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit0: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&tsens 6>;
130
131 trips {
132 cpu_alert1: trip0 {
133 temperature = <75000>;
134 hysteresis = <2000>;
135 type = "passive";
136 };
137 cpu_crit1: trip1 {
138 temperature = <110000>;
139 hysteresis = <2000>;
140 type = "critical";
141 };
142 };
143 };
144
145 cpu-thermal2 {
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
148
149 thermal-sensors = <&tsens 7>;
150
151 trips {
152 cpu_alert2: trip0 {
153 temperature = <75000>;
154 hysteresis = <2000>;
155 type = "passive";
156 };
157 cpu_crit2: trip1 {
158 temperature = <110000>;
159 hysteresis = <2000>;
160 type = "critical";
161 };
162 };
163 };
164
165 cpu-thermal3 {
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
168
169 thermal-sensors = <&tsens 8>;
170
171 trips {
172 cpu_alert3: trip0 {
173 temperature = <75000>;
174 hysteresis = <2000>;
175 type = "passive";
176 };
177 cpu_crit3: trip1 {
178 temperature = <110000>;
179 hysteresis = <2000>;
180 type = "critical";
181 };
182 };
183 };
184 };
185
186 cpu-pmu {
187 compatible = "qcom,krait-pmu";
188 interrupts = <GIC_PPI 7 0xf04>;
189 };
190
191 clocks {
192 xo_board: xo_board {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <19200000>;
196 };
197
198 sleep_clk: sleep_clk {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <32768>;
202 };
203 };
204
205 timer {
206 compatible = "arm,armv7-timer";
207 interrupts = <GIC_PPI 2 0xf08>,
208 <GIC_PPI 3 0xf08>,
209 <GIC_PPI 4 0xf08>,
210 <GIC_PPI 1 0xf08>;
211 clock-frequency = <19200000>;
212 };
213
214 smem {
215 compatible = "qcom,smem";
216
217 qcom,rpm-msg-ram = <&rpm_msg_ram>;
218 memory-region = <&smem_mem>;
219
220 hwlocks = <&tcsr_mutex 3>;
221 };
222
223 soc: soc {
224 #address-cells = <1>;
225 #size-cells = <1>;
226 ranges;
227 compatible = "simple-bus";
228
229 intc: interrupt-controller@f9000000 {
230 compatible = "qcom,msm-qgic2";
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 reg = <0xf9000000 0x1000>,
234 <0xf9002000 0x1000>;
235 };
236
237 apcs: syscon@f9011000 {
238 compatible = "syscon";
239 reg = <0xf9011000 0x1000>;
240 };
241
242 qfprom: qfprom@fc4bc000 {
243 #address-cells = <1>;
244 #size-cells = <1>;
245 compatible = "qcom,qfprom";
246 reg = <0xfc4bc000 0x1000>;
247 tsens_calib: calib@d0 {
248 reg = <0xd0 0x18>;
249 };
250 tsens_backup: backup@440 {
251 reg = <0x440 0x10>;
252 };
253 };
254
255 tsens: thermal-sensor@fc4a8000 {
256 compatible = "qcom,msm8974-tsens";
257 reg = <0xfc4a9000 0x1000>, /* TM */
258 <0xfc4a8000 0x1000>; /* SROT */
259 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
260 nvmem-cell-names = "calib", "calib_backup";
261 #qcom,sensors = <11>;
262 #thermal-sensor-cells = <1>;
263 };
264 timer@f9020000 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges;
268 compatible = "arm,armv7-timer-mem";
269 reg = <0xf9020000 0x1000>;
270 clock-frequency = <19200000>;
271
272 frame@f9021000 {
273 frame-number = <0>;
274 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
276 reg = <0xf9021000 0x1000>,
277 <0xf9022000 0x1000>;
278 };
279
280 frame@f9023000 {
281 frame-number = <1>;
282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
283 reg = <0xf9023000 0x1000>;
284 status = "disabled";
285 };
286
287 frame@f9024000 {
288 frame-number = <2>;
289 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
290 reg = <0xf9024000 0x1000>;
291 status = "disabled";
292 };
293
294 frame@f9025000 {
295 frame-number = <3>;
296 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
297 reg = <0xf9025000 0x1000>;
298 status = "disabled";
299 };
300
301 frame@f9026000 {
302 frame-number = <4>;
303 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
304 reg = <0xf9026000 0x1000>;
305 status = "disabled";
306 };
307
308 frame@f9027000 {
309 frame-number = <5>;
310 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
311 reg = <0xf9027000 0x1000>;
312 status = "disabled";
313 };
314
315 frame@f9028000 {
316 frame-number = <6>;
317 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
318 reg = <0xf9028000 0x1000>;
319 status = "disabled";
320 };
321 };
322
323 saw0: power-controller@f9089000 {
324 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
325 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
326 };
327
328 saw1: power-controller@f9099000 {
329 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
330 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
331 };
332
333 saw2: power-controller@f90a9000 {
334 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
335 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
336 };
337
338 saw3: power-controller@f90b9000 {
339 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
340 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
341 };
342
343 saw_l2: power-controller@f9012000 {
344 compatible = "qcom,saw2";
345 reg = <0xf9012000 0x1000>;
346 regulator;
347 };
348
349 acc0: clock-controller@f9088000 {
350 compatible = "qcom,kpss-acc-v2";
351 reg = <0xf9088000 0x1000>,
352 <0xf9008000 0x1000>;
353 };
354
355 acc1: clock-controller@f9098000 {
356 compatible = "qcom,kpss-acc-v2";
357 reg = <0xf9098000 0x1000>,
358 <0xf9008000 0x1000>;
359 };
360
361 acc2: clock-controller@f90a8000 {
362 compatible = "qcom,kpss-acc-v2";
363 reg = <0xf90a8000 0x1000>,
364 <0xf9008000 0x1000>;
365 };
366
367 acc3: clock-controller@f90b8000 {
368 compatible = "qcom,kpss-acc-v2";
369 reg = <0xf90b8000 0x1000>,
370 <0xf9008000 0x1000>;
371 };
372
373 restart@fc4ab000 {
374 compatible = "qcom,pshold";
375 reg = <0xfc4ab000 0x4>;
376 };
377
378 gcc: clock-controller@fc400000 {
379 compatible = "qcom,gcc-apq8084";
380 #clock-cells = <1>;
381 #reset-cells = <1>;
382 #power-domain-cells = <1>;
383 reg = <0xfc400000 0x4000>;
384 };
385
386 tcsr_mutex_regs: syscon@fd484000 {
387 compatible = "syscon";
388 reg = <0xfd484000 0x2000>;
389 };
390
391 tcsr_mutex: hwlock {
392 compatible = "qcom,tcsr-mutex";
393 syscon = <&tcsr_mutex_regs 0 0x80>;
394 #hwlock-cells = <1>;
395 };
396
397 rpm_msg_ram: memory@fc428000 {
398 compatible = "qcom,rpm-msg-ram";
399 reg = <0xfc428000 0x4000>;
400 };
401
402 tlmm: pinctrl@fd510000 {
403 compatible = "qcom,apq8084-pinctrl";
404 reg = <0xfd510000 0x4000>;
405 gpio-controller;
406 gpio-ranges = <&tlmm 0 0 147>;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
411 };
412
413 blsp2_uart2: serial@f995e000 {
414 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
415 reg = <0xf995e000 0x1000>;
416 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
418 clock-names = "core", "iface";
419 status = "disabled";
420 };
421
422 sdhci@f9824900 {
423 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
424 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
425 reg-names = "hc_mem", "core_mem";
426 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "hc_irq", "pwr_irq";
428 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
429 <&gcc GCC_SDCC1_AHB_CLK>,
430 <&xo_board>;
431 clock-names = "core", "iface", "xo";
432 status = "disabled";
433 };
434
435 sdhci@f98a4900 {
436 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
437 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
438 reg-names = "hc_mem", "core_mem";
439 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "hc_irq", "pwr_irq";
441 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
442 <&gcc GCC_SDCC2_AHB_CLK>,
443 <&xo_board>;
444 clock-names = "core", "iface", "xo";
445 status = "disabled";
446 };
447
448 spmi_bus: spmi@fc4cf000 {
449 compatible = "qcom,spmi-pmic-arb";
450 reg-names = "core", "intr", "cnfg";
451 reg = <0xfc4cf000 0x1000>,
452 <0xfc4cb000 0x1000>,
453 <0xfc4ca000 0x1000>;
454 interrupt-names = "periph_irq";
455 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
456 qcom,ee = <0>;
457 qcom,channel = <0>;
458 #address-cells = <2>;
459 #size-cells = <0>;
460 interrupt-controller;
461 #interrupt-cells = <4>;
462 };
463 };
464
465 smd {
466 compatible = "qcom,smd";
467
468 rpm {
469 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
470 qcom,ipc = <&apcs 8 0>;
471 qcom,smd-edge = <15>;
472
473 rpm_requests {
474 compatible = "qcom,rpm-apq8084";
475 qcom,smd-channels = "rpm_requests";
476
477 pma8084-regulators {
478 compatible = "qcom,rpm-pma8084-regulators";
479
480 pma8084_s1: s1 {};
481 pma8084_s2: s2 {};
482 pma8084_s3: s3 {};
483 pma8084_s4: s4 {};
484 pma8084_s5: s5 {};
485 pma8084_s6: s6 {};
486 pma8084_s7: s7 {};
487 pma8084_s8: s8 {};
488 pma8084_s9: s9 {};
489 pma8084_s10: s10 {};
490 pma8084_s11: s11 {};
491 pma8084_s12: s12 {};
492
493 pma8084_l1: l1 {};
494 pma8084_l2: l2 {};
495 pma8084_l3: l3 {};
496 pma8084_l4: l4 {};
497 pma8084_l5: l5 {};
498 pma8084_l6: l6 {};
499 pma8084_l7: l7 {};
500 pma8084_l8: l8 {};
501 pma8084_l9: l9 {};
502 pma8084_l10: l10 {};
503 pma8084_l11: l11 {};
504 pma8084_l12: l12 {};
505 pma8084_l13: l13 {};
506 pma8084_l14: l14 {};
507 pma8084_l15: l15 {};
508 pma8084_l16: l16 {};
509 pma8084_l17: l17 {};
510 pma8084_l18: l18 {};
511 pma8084_l19: l19 {};
512 pma8084_l20: l20 {};
513 pma8084_l21: l21 {};
514 pma8084_l22: l22 {};
515 pma8084_l23: l23 {};
516 pma8084_l24: l24 {};
517 pma8084_l25: l25 {};
518 pma8084_l26: l26 {};
519 pma8084_l27: l27 {};
520
521 pma8084_lvs1: lvs1 {};
522 pma8084_lvs2: lvs2 {};
523 pma8084_lvs3: lvs3 {};
524 pma8084_lvs4: lvs4 {};
525
526 pma8084_5vs1: 5vs1 {};
527 };
528 };
529 };
530 };
531};