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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: John Crispin <john@phrozen.org>
5 * Sean Wang <sean.wang@mediatek.com>
6 * Ryder Lee <ryder.lee@mediatek.com>
7 *
8 */
9
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/clock/mt2701-clk.h>
13#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14#include <dt-bindings/power/mt2701-power.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17#include <dt-bindings/reset/mt2701-resets.h>
18#include <dt-bindings/thermal/thermal.h>
19
20/ {
21 compatible = "mediatek,mt7623";
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
29
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
33 };
34
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
38 };
39
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
43 };
44
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
48 };
49
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
53 };
54
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
58 };
59
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
63 };
64
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
68 };
69 };
70
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
75
76 cpu0: cpu@0 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <0x0>;
80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
81 <&apmixedsys CLK_APMIXED_MAINPLL>;
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
86 };
87
88 cpu1: cpu@1 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a7";
91 reg = <0x1>;
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
93 <&apmixedsys CLK_APMIXED_MAINPLL>;
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
98 };
99
100 cpu2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a7";
103 reg = <0x2>;
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
105 <&apmixedsys CLK_APMIXED_MAINPLL>;
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
110 };
111
112 cpu3: cpu@3 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a7";
115 reg = <0x3>;
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
117 <&apmixedsys CLK_APMIXED_MAINPLL>;
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
122 };
123 };
124
125 pmu {
126 compatible = "arm,cortex-a7-pmu";
127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
132 };
133
134 system_clk: dummy13m {
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
138 };
139
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
145 };
146
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
152 };
153
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
158
159 thermal-sensors = <&thermal 0>;
160
161 trips {
162 cpu_passive: cpu-passive {
163 temperature = <57000>;
164 hysteresis = <2000>;
165 type = "passive";
166 };
167
168 cpu_active: cpu-active {
169 temperature = <67000>;
170 hysteresis = <2000>;
171 type = "active";
172 };
173
174 cpu_hot: cpu-hot {
175 temperature = <87000>;
176 hysteresis = <2000>;
177 type = "hot";
178 };
179
180 cpu-crit {
181 temperature = <107000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186
187 cooling-maps {
188 map0 {
189 trip = <&cpu_passive>;
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
192 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 };
195
196 map1 {
197 trip = <&cpu_active>;
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202 };
203
204 map2 {
205 trip = <&cpu_hot>;
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 };
211 };
212 };
213 };
214
215 timer {
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
224 };
225
226 topckgen: syscon@10000000 {
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
229 "syscon";
230 reg = <0 0x10000000 0 0x1000>;
231 #clock-cells = <1>;
232 };
233
234 infracfg: syscon@10001000 {
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
237 "syscon";
238 reg = <0 0x10001000 0 0x1000>;
239 #clock-cells = <1>;
240 #reset-cells = <1>;
241 };
242
243 pericfg: syscon@10003000 {
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
246 "syscon";
247 reg = <0 0x10003000 0 0x1000>;
248 #clock-cells = <1>;
249 #reset-cells = <1>;
250 };
251
252 pio: pinctrl@10005000 {
253 compatible = "mediatek,mt7623-pinctrl";
254 reg = <0 0x1000b000 0 0x1000>;
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 pins-are-numbered;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 interrupt-parent = <&gic>;
261 #interrupt-cells = <2>;
262 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
264 };
265
266 syscfg_pctl_a: syscfg@10005000 {
267 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
268 reg = <0 0x10005000 0 0x1000>;
269 };
270
271 scpsys: power-controller@10006000 {
272 compatible = "mediatek,mt7623-scpsys",
273 "mediatek,mt2701-scpsys",
274 "syscon";
275 #power-domain-cells = <1>;
276 reg = <0 0x10006000 0 0x1000>;
277 infracfg = <&infracfg>;
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
281 clock-names = "mm", "mfg", "ethif";
282 };
283
284 watchdog: watchdog@10007000 {
285 compatible = "mediatek,mt7623-wdt",
286 "mediatek,mt6589-wdt";
287 reg = <0 0x10007000 0 0x100>;
288 };
289
290 timer: timer@10008000 {
291 compatible = "mediatek,mt7623-timer",
292 "mediatek,mt6577-timer";
293 reg = <0 0x10008000 0 0x80>;
294 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
295 clocks = <&system_clk>, <&rtc32k>;
296 clock-names = "system-clk", "rtc-clk";
297 };
298
299 pwrap: pwrap@1000d000 {
300 compatible = "mediatek,mt7623-pwrap",
301 "mediatek,mt2701-pwrap";
302 reg = <0 0x1000d000 0 0x1000>;
303 reg-names = "pwrap";
304 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
306 reset-names = "pwrap";
307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
308 <&infracfg CLK_INFRA_PMICWRAP>;
309 clock-names = "spi", "wrap";
310 };
311
312 cir: cir@10013000 {
313 compatible = "mediatek,mt7623-cir";
314 reg = <0 0x10013000 0 0x1000>;
315 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
316 clocks = <&infracfg CLK_INFRA_IRRX>;
317 clock-names = "clk";
318 status = "disabled";
319 };
320
321 sysirq: interrupt-controller@10200100 {
322 compatible = "mediatek,mt7623-sysirq",
323 "mediatek,mt6577-sysirq";
324 interrupt-controller;
325 #interrupt-cells = <3>;
326 interrupt-parent = <&gic>;
327 reg = <0 0x10200100 0 0x1c>;
328 };
329
330 efuse: efuse@10206000 {
331 compatible = "mediatek,mt7623-efuse",
332 "mediatek,mt8173-efuse";
333 reg = <0 0x10206000 0 0x1000>;
334 #address-cells = <1>;
335 #size-cells = <1>;
336 thermal_calibration_data: calib@424 {
337 reg = <0x424 0xc>;
338 };
339 };
340
341 apmixedsys: syscon@10209000 {
342 compatible = "mediatek,mt7623-apmixedsys",
343 "mediatek,mt2701-apmixedsys",
344 "syscon";
345 reg = <0 0x10209000 0 0x1000>;
346 #clock-cells = <1>;
347 };
348
349 rng: rng@1020f000 {
350 compatible = "mediatek,mt7623-rng";
351 reg = <0 0x1020f000 0 0x1000>;
352 clocks = <&infracfg CLK_INFRA_TRNG>;
353 clock-names = "rng";
354 };
355
356 gic: interrupt-controller@10211000 {
357 compatible = "arm,cortex-a7-gic";
358 interrupt-controller;
359 #interrupt-cells = <3>;
360 interrupt-parent = <&gic>;
361 reg = <0 0x10211000 0 0x1000>,
362 <0 0x10212000 0 0x2000>,
363 <0 0x10214000 0 0x2000>,
364 <0 0x10216000 0 0x2000>;
365 };
366
367 auxadc: adc@11001000 {
368 compatible = "mediatek,mt7623-auxadc",
369 "mediatek,mt2701-auxadc";
370 reg = <0 0x11001000 0 0x1000>;
371 clocks = <&pericfg CLK_PERI_AUXADC>;
372 clock-names = "main";
373 #io-channel-cells = <1>;
374 };
375
376 uart0: serial@11002000 {
377 compatible = "mediatek,mt7623-uart",
378 "mediatek,mt6577-uart";
379 reg = <0 0x11002000 0 0x400>;
380 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
381 clocks = <&pericfg CLK_PERI_UART0_SEL>,
382 <&pericfg CLK_PERI_UART0>;
383 clock-names = "baud", "bus";
384 status = "disabled";
385 };
386
387 uart1: serial@11003000 {
388 compatible = "mediatek,mt7623-uart",
389 "mediatek,mt6577-uart";
390 reg = <0 0x11003000 0 0x400>;
391 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
392 clocks = <&pericfg CLK_PERI_UART1_SEL>,
393 <&pericfg CLK_PERI_UART1>;
394 clock-names = "baud", "bus";
395 status = "disabled";
396 };
397
398 uart2: serial@11004000 {
399 compatible = "mediatek,mt7623-uart",
400 "mediatek,mt6577-uart";
401 reg = <0 0x11004000 0 0x400>;
402 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
403 clocks = <&pericfg CLK_PERI_UART2_SEL>,
404 <&pericfg CLK_PERI_UART2>;
405 clock-names = "baud", "bus";
406 status = "disabled";
407 };
408
409 uart3: serial@11005000 {
410 compatible = "mediatek,mt7623-uart",
411 "mediatek,mt6577-uart";
412 reg = <0 0x11005000 0 0x400>;
413 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
414 clocks = <&pericfg CLK_PERI_UART3_SEL>,
415 <&pericfg CLK_PERI_UART3>;
416 clock-names = "baud", "bus";
417 status = "disabled";
418 };
419
420 pwm: pwm@11006000 {
421 compatible = "mediatek,mt7623-pwm";
422 reg = <0 0x11006000 0 0x1000>;
423 #pwm-cells = <2>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
425 <&pericfg CLK_PERI_PWM>,
426 <&pericfg CLK_PERI_PWM1>,
427 <&pericfg CLK_PERI_PWM2>,
428 <&pericfg CLK_PERI_PWM3>,
429 <&pericfg CLK_PERI_PWM4>,
430 <&pericfg CLK_PERI_PWM5>;
431 clock-names = "top", "main", "pwm1", "pwm2",
432 "pwm3", "pwm4", "pwm5";
433 status = "disabled";
434 };
435
436 i2c0: i2c@11007000 {
437 compatible = "mediatek,mt7623-i2c",
438 "mediatek,mt6577-i2c";
439 reg = <0 0x11007000 0 0x70>,
440 <0 0x11000200 0 0x80>;
441 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
442 clock-div = <16>;
443 clocks = <&pericfg CLK_PERI_I2C0>,
444 <&pericfg CLK_PERI_AP_DMA>;
445 clock-names = "main", "dma";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
450
451 i2c1: i2c@11008000 {
452 compatible = "mediatek,mt7623-i2c",
453 "mediatek,mt6577-i2c";
454 reg = <0 0x11008000 0 0x70>,
455 <0 0x11000280 0 0x80>;
456 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
457 clock-div = <16>;
458 clocks = <&pericfg CLK_PERI_I2C1>,
459 <&pericfg CLK_PERI_AP_DMA>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 status = "disabled";
464 };
465
466 i2c2: i2c@11009000 {
467 compatible = "mediatek,mt7623-i2c",
468 "mediatek,mt6577-i2c";
469 reg = <0 0x11009000 0 0x70>,
470 <0 0x11000300 0 0x80>;
471 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
472 clock-div = <16>;
473 clocks = <&pericfg CLK_PERI_I2C2>,
474 <&pericfg CLK_PERI_AP_DMA>;
475 clock-names = "main", "dma";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480
481 spi0: spi@1100a000 {
482 compatible = "mediatek,mt7623-spi",
483 "mediatek,mt2701-spi";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 reg = <0 0x1100a000 0 0x100>;
487 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
490 <&pericfg CLK_PERI_SPI0>;
491 clock-names = "parent-clk", "sel-clk", "spi-clk";
492 status = "disabled";
493 };
494
495 thermal: thermal@1100b000 {
496 #thermal-sensor-cells = <1>;
497 compatible = "mediatek,mt7623-thermal",
498 "mediatek,mt2701-thermal";
499 reg = <0 0x1100b000 0 0x1000>;
500 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
501 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
502 clock-names = "therm", "auxadc";
503 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
504 reset-names = "therm";
505 mediatek,auxadc = <&auxadc>;
506 mediatek,apmixedsys = <&apmixedsys>;
507 nvmem-cells = <&thermal_calibration_data>;
508 nvmem-cell-names = "calibration-data";
509 };
510
511 btif: serial@1100c000 {
512 compatible = "mediatek,mt7623-btif",
513 "mediatek,mtk-btif";
514 reg = <0 0x1100c000 0 0x1000>;
515 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
516 clocks = <&pericfg CLK_PERI_BTIF>;
517 clock-names = "main";
518 reg-shift = <2>;
519 reg-io-width = <4>;
520 status = "disabled";
521 };
522
523 nandc: nfi@1100d000 {
524 compatible = "mediatek,mt7623-nfc",
525 "mediatek,mt2701-nfc";
526 reg = <0 0x1100d000 0 0x1000>;
527 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
528 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
529 clocks = <&pericfg CLK_PERI_NFI>,
530 <&pericfg CLK_PERI_NFI_PAD>;
531 clock-names = "nfi_clk", "pad_clk";
532 status = "disabled";
533 ecc-engine = <&bch>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 };
537
538 bch: ecc@1100e000 {
539 compatible = "mediatek,mt7623-ecc",
540 "mediatek,mt2701-ecc";
541 reg = <0 0x1100e000 0 0x1000>;
542 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
543 clocks = <&pericfg CLK_PERI_NFI_ECC>;
544 clock-names = "nfiecc_clk";
545 status = "disabled";
546 };
547
548 nor_flash: spi@11014000 {
549 compatible = "mediatek,mt7623-nor",
550 "mediatek,mt8173-nor";
551 reg = <0 0x11014000 0 0x1000>;
552 clocks = <&pericfg CLK_PERI_FLASH>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
554 clock-names = "spi", "sf";
555 #address-cells = <1>;
556 #size-cells = <0>;
557 status = "disabled";
558 };
559
560 spi1: spi@11016000 {
561 compatible = "mediatek,mt7623-spi",
562 "mediatek,mt2701-spi";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 reg = <0 0x11016000 0 0x100>;
566 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
567 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
568 <&topckgen CLK_TOP_SPI1_SEL>,
569 <&pericfg CLK_PERI_SPI1>;
570 clock-names = "parent-clk", "sel-clk", "spi-clk";
571 status = "disabled";
572 };
573
574 spi2: spi@11017000 {
575 compatible = "mediatek,mt7623-spi",
576 "mediatek,mt2701-spi";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <0 0x11017000 0 0x1000>;
580 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
581 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
582 <&topckgen CLK_TOP_SPI2_SEL>,
583 <&pericfg CLK_PERI_SPI2>;
584 clock-names = "parent-clk", "sel-clk", "spi-clk";
585 status = "disabled";
586 };
587
588 usb0: usb@11200000 {
589 compatible = "mediatek,mt7623-musb",
590 "mediatek,mtk-musb";
591 reg = <0 0x11200000 0 0x1000>;
592 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
593 interrupt-names = "mc";
594 phys = <&u2port2 PHY_TYPE_USB2>;
595 dr_mode = "otg";
596 clocks = <&pericfg CLK_PERI_USB0>,
597 <&pericfg CLK_PERI_USB0_MCU>,
598 <&pericfg CLK_PERI_USB_SLV>;
599 clock-names = "main","mcu","univpll";
600 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
601 status = "disabled";
602 };
603
604 u2phy1: t-phy@11210000 {
605 compatible = "mediatek,mt7623-tphy",
606 "mediatek,generic-tphy-v1";
607 reg = <0 0x11210000 0 0x0800>;
608 #address-cells = <2>;
609 #size-cells = <2>;
610 ranges;
611 status = "disabled";
612
613 u2port2: usb-phy@11210800 {
614 reg = <0 0x11210800 0 0x0100>;
615 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
616 clock-names = "ref";
617 #phy-cells = <1>;
618 };
619 };
620
621 audsys: clock-controller@11220000 {
622 compatible = "mediatek,mt7623-audsys",
623 "mediatek,mt2701-audsys",
624 "syscon";
625 reg = <0 0x11220000 0 0x2000>;
626 #clock-cells = <1>;
627
628 afe: audio-controller {
629 compatible = "mediatek,mt7623-audio",
630 "mediatek,mt2701-audio";
631 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
632 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
633 interrupt-names = "afe", "asys";
634 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
635
636 clocks = <&infracfg CLK_INFRA_AUDIO>,
637 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
638 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
639 <&topckgen CLK_TOP_AUD_48K_TIMING>,
640 <&topckgen CLK_TOP_AUD_44K_TIMING>,
641 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
642 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
643 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
644 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
645 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
646 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
647 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
648 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
649 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
650 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
651 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
652 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
653 <&audsys CLK_AUD_I2SO1>,
654 <&audsys CLK_AUD_I2SO2>,
655 <&audsys CLK_AUD_I2SO3>,
656 <&audsys CLK_AUD_I2SO4>,
657 <&audsys CLK_AUD_I2SIN1>,
658 <&audsys CLK_AUD_I2SIN2>,
659 <&audsys CLK_AUD_I2SIN3>,
660 <&audsys CLK_AUD_I2SIN4>,
661 <&audsys CLK_AUD_ASRCO1>,
662 <&audsys CLK_AUD_ASRCO2>,
663 <&audsys CLK_AUD_ASRCO3>,
664 <&audsys CLK_AUD_ASRCO4>,
665 <&audsys CLK_AUD_AFE>,
666 <&audsys CLK_AUD_AFE_CONN>,
667 <&audsys CLK_AUD_A1SYS>,
668 <&audsys CLK_AUD_A2SYS>,
669 <&audsys CLK_AUD_AFE_MRGIF>;
670
671 clock-names = "infra_sys_audio_clk",
672 "top_audio_mux1_sel",
673 "top_audio_mux2_sel",
674 "top_audio_a1sys_hp",
675 "top_audio_a2sys_hp",
676 "i2s0_src_sel",
677 "i2s1_src_sel",
678 "i2s2_src_sel",
679 "i2s3_src_sel",
680 "i2s0_src_div",
681 "i2s1_src_div",
682 "i2s2_src_div",
683 "i2s3_src_div",
684 "i2s0_mclk_en",
685 "i2s1_mclk_en",
686 "i2s2_mclk_en",
687 "i2s3_mclk_en",
688 "i2so0_hop_ck",
689 "i2so1_hop_ck",
690 "i2so2_hop_ck",
691 "i2so3_hop_ck",
692 "i2si0_hop_ck",
693 "i2si1_hop_ck",
694 "i2si2_hop_ck",
695 "i2si3_hop_ck",
696 "asrc0_out_ck",
697 "asrc1_out_ck",
698 "asrc2_out_ck",
699 "asrc3_out_ck",
700 "audio_afe_pd",
701 "audio_afe_conn_pd",
702 "audio_a1sys_pd",
703 "audio_a2sys_pd",
704 "audio_mrgif_pd";
705
706 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
707 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
708 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
709 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
710 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
711 <&topckgen CLK_TOP_AUD2PLL_90M>;
712 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
713 };
714 };
715
716 mmc0: mmc@11230000 {
717 compatible = "mediatek,mt7623-mmc",
718 "mediatek,mt2701-mmc";
719 reg = <0 0x11230000 0 0x1000>;
720 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
721 clocks = <&pericfg CLK_PERI_MSDC30_0>,
722 <&topckgen CLK_TOP_MSDC30_0_SEL>;
723 clock-names = "source", "hclk";
724 status = "disabled";
725 };
726
727 mmc1: mmc@11240000 {
728 compatible = "mediatek,mt7623-mmc",
729 "mediatek,mt2701-mmc";
730 reg = <0 0x11240000 0 0x1000>;
731 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
732 clocks = <&pericfg CLK_PERI_MSDC30_1>,
733 <&topckgen CLK_TOP_MSDC30_1_SEL>;
734 clock-names = "source", "hclk";
735 status = "disabled";
736 };
737
738 vdecsys: syscon@16000000 {
739 compatible = "mediatek,mt7623-vdecsys",
740 "mediatek,mt2701-vdecsys",
741 "syscon";
742 reg = <0 0x16000000 0 0x1000>;
743 #clock-cells = <1>;
744 };
745
746 hifsys: syscon@1a000000 {
747 compatible = "mediatek,mt7623-hifsys",
748 "mediatek,mt2701-hifsys",
749 "syscon";
750 reg = <0 0x1a000000 0 0x1000>;
751 #clock-cells = <1>;
752 #reset-cells = <1>;
753 };
754
755 pcie: pcie@1a140000 {
756 compatible = "mediatek,mt7623-pcie";
757 device_type = "pci";
758 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
759 <0 0x1a142000 0 0x1000>, /* Port0 registers */
760 <0 0x1a143000 0 0x1000>, /* Port1 registers */
761 <0 0x1a144000 0 0x1000>; /* Port2 registers */
762 reg-names = "subsys", "port0", "port1", "port2";
763 #address-cells = <3>;
764 #size-cells = <2>;
765 #interrupt-cells = <1>;
766 interrupt-map-mask = <0xf800 0 0 0>;
767 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
768 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
769 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
770 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
771 <&hifsys CLK_HIFSYS_PCIE0>,
772 <&hifsys CLK_HIFSYS_PCIE1>,
773 <&hifsys CLK_HIFSYS_PCIE2>;
774 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
775 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
776 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
777 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
778 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
779 phys = <&pcie0_port PHY_TYPE_PCIE>,
780 <&pcie1_port PHY_TYPE_PCIE>,
781 <&u3port1 PHY_TYPE_PCIE>;
782 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
783 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
784 bus-range = <0x00 0xff>;
785 status = "disabled";
786 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
787 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
788
789 pcie@0,0 {
790 reg = <0x0000 0 0 0 0>;
791 #address-cells = <3>;
792 #size-cells = <2>;
793 #interrupt-cells = <1>;
794 interrupt-map-mask = <0 0 0 0>;
795 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
796 ranges;
797 status = "disabled";
798 };
799
800 pcie@1,0 {
801 reg = <0x0800 0 0 0 0>;
802 #address-cells = <3>;
803 #size-cells = <2>;
804 #interrupt-cells = <1>;
805 interrupt-map-mask = <0 0 0 0>;
806 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
807 ranges;
808 status = "disabled";
809 };
810
811 pcie@2,0 {
812 reg = <0x1000 0 0 0 0>;
813 #address-cells = <3>;
814 #size-cells = <2>;
815 #interrupt-cells = <1>;
816 interrupt-map-mask = <0 0 0 0>;
817 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
818 ranges;
819 status = "disabled";
820 };
821 };
822
823 pcie0_phy: t-phy@1a149000 {
824 compatible = "mediatek,mt7623-tphy",
825 "mediatek,generic-tphy-v1";
826 reg = <0 0x1a149000 0 0x0700>;
827 #address-cells = <2>;
828 #size-cells = <2>;
829 ranges;
830 status = "disabled";
831
832 pcie0_port: pcie-phy@1a149900 {
833 reg = <0 0x1a149900 0 0x0700>;
834 clocks = <&clk26m>;
835 clock-names = "ref";
836 #phy-cells = <1>;
837 status = "okay";
838 };
839 };
840
841 pcie1_phy: t-phy@1a14a000 {
842 compatible = "mediatek,mt7623-tphy",
843 "mediatek,generic-tphy-v1";
844 reg = <0 0x1a14a000 0 0x0700>;
845 #address-cells = <2>;
846 #size-cells = <2>;
847 ranges;
848 status = "disabled";
849
850 pcie1_port: pcie-phy@1a14a900 {
851 reg = <0 0x1a14a900 0 0x0700>;
852 clocks = <&clk26m>;
853 clock-names = "ref";
854 #phy-cells = <1>;
855 status = "okay";
856 };
857 };
858
859 usb1: usb@1a1c0000 {
860 compatible = "mediatek,mt7623-xhci",
861 "mediatek,mtk-xhci";
862 reg = <0 0x1a1c0000 0 0x1000>,
863 <0 0x1a1c4700 0 0x0100>;
864 reg-names = "mac", "ippc";
865 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
866 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
867 <&topckgen CLK_TOP_ETHIF_SEL>;
868 clock-names = "sys_ck", "ref_ck";
869 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
870 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
871 status = "disabled";
872 };
873
874 u3phy1: t-phy@1a1c4000 {
875 compatible = "mediatek,mt7623-tphy",
876 "mediatek,generic-tphy-v1";
877 reg = <0 0x1a1c4000 0 0x0700>;
878 #address-cells = <2>;
879 #size-cells = <2>;
880 ranges;
881 status = "disabled";
882
883 u2port0: usb-phy@1a1c4800 {
884 reg = <0 0x1a1c4800 0 0x0100>;
885 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
886 clock-names = "ref";
887 #phy-cells = <1>;
888 status = "okay";
889 };
890
891 u3port0: usb-phy@1a1c4900 {
892 reg = <0 0x1a1c4900 0 0x0700>;
893 clocks = <&clk26m>;
894 clock-names = "ref";
895 #phy-cells = <1>;
896 status = "okay";
897 };
898 };
899
900 usb2: usb@1a240000 {
901 compatible = "mediatek,mt7623-xhci",
902 "mediatek,mtk-xhci";
903 reg = <0 0x1a240000 0 0x1000>,
904 <0 0x1a244700 0 0x0100>;
905 reg-names = "mac", "ippc";
906 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
907 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
908 <&topckgen CLK_TOP_ETHIF_SEL>;
909 clock-names = "sys_ck", "ref_ck";
910 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
911 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
912 status = "disabled";
913 };
914
915 u3phy2: t-phy@1a244000 {
916 compatible = "mediatek,mt7623-tphy",
917 "mediatek,generic-tphy-v1";
918 reg = <0 0x1a244000 0 0x0700>;
919 #address-cells = <2>;
920 #size-cells = <2>;
921 ranges;
922 status = "disabled";
923
924 u2port1: usb-phy@1a244800 {
925 reg = <0 0x1a244800 0 0x0100>;
926 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
927 clock-names = "ref";
928 #phy-cells = <1>;
929 status = "okay";
930 };
931
932 u3port1: usb-phy@1a244900 {
933 reg = <0 0x1a244900 0 0x0700>;
934 clocks = <&clk26m>;
935 clock-names = "ref";
936 #phy-cells = <1>;
937 status = "okay";
938 };
939 };
940
941 ethsys: syscon@1b000000 {
942 compatible = "mediatek,mt7623-ethsys",
943 "mediatek,mt2701-ethsys",
944 "syscon";
945 reg = <0 0x1b000000 0 0x1000>;
946 #clock-cells = <1>;
947 #reset-cells = <1>;
948 };
949
950 hsdma: dma-controller@1b007000 {
951 compatible = "mediatek,mt7623-hsdma";
952 reg = <0 0x1b007000 0 0x1000>;
953 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
954 clocks = <ðsys CLK_ETHSYS_HSDMA>;
955 clock-names = "hsdma";
956 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
957 #dma-cells = <1>;
958 };
959
960 eth: ethernet@1b100000 {
961 compatible = "mediatek,mt7623-eth",
962 "mediatek,mt2701-eth",
963 "syscon";
964 reg = <0 0x1b100000 0 0x20000>;
965 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
966 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
967 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
968 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
969 <ðsys CLK_ETHSYS_ESW>,
970 <ðsys CLK_ETHSYS_GP1>,
971 <ðsys CLK_ETHSYS_GP2>,
972 <&apmixedsys CLK_APMIXED_TRGPLL>;
973 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
974 resets = <ðsys MT2701_ETHSYS_FE_RST>,
975 <ðsys MT2701_ETHSYS_GMAC_RST>,
976 <ðsys MT2701_ETHSYS_PPE_RST>;
977 reset-names = "fe", "gmac", "ppe";
978 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
979 mediatek,ethsys = <ðsys>;
980 mediatek,pctl = <&syscfg_pctl_a>;
981 #address-cells = <1>;
982 #size-cells = <0>;
983 status = "disabled";
984 };
985
986 crypto: crypto@1b240000 {
987 compatible = "mediatek,eip97-crypto";
988 reg = <0 0x1b240000 0 0x20000>;
989 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
990 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
991 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
992 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
993 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
994 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
995 clock-names = "cryp";
996 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
997 status = "disabled";
998 };
999
1000 bdpsys: syscon@1c000000 {
1001 compatible = "mediatek,mt7623-bdpsys",
1002 "mediatek,mt2701-bdpsys",
1003 "syscon";
1004 reg = <0 0x1c000000 0 0x1000>;
1005 #clock-cells = <1>;
1006 };
1007};
1008
1009&pio {
1010 cir_pins_a:cir-default {
1011 pins-cir {
1012 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1013 bias-disable;
1014 };
1015 };
1016
1017 i2c0_pins_a: i2c0-default {
1018 pins-i2c0 {
1019 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1020 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1021 bias-disable;
1022 };
1023 };
1024
1025 i2c1_pins_a: i2c1-default {
1026 pin-i2c1 {
1027 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1028 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1029 bias-disable;
1030 };
1031 };
1032
1033 i2c1_pins_b: i2c1-alt {
1034 pin-i2c1 {
1035 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1036 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1037 bias-disable;
1038 };
1039 };
1040
1041 i2c2_pins_a: i2c2-default {
1042 pin-i2c2 {
1043 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1044 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1045 bias-disable;
1046 };
1047 };
1048
1049 i2c2_pins_b: i2c2-alt {
1050 pin-i2c2 {
1051 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1052 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1053 bias-disable;
1054 };
1055 };
1056
1057 i2s0_pins_a: i2s0-default {
1058 pin-i2s0 {
1059 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1060 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1061 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1062 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1063 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1064 drive-strength = <MTK_DRIVE_12mA>;
1065 bias-pull-down;
1066 };
1067 };
1068
1069 i2s1_pins_a: i2s1-default {
1070 pin-i2s1 {
1071 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1072 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1073 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1074 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1075 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1076 drive-strength = <MTK_DRIVE_12mA>;
1077 bias-pull-down;
1078 };
1079 };
1080
1081 key_pins_a: keys-alt {
1082 pins-keys {
1083 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1084 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1085 input-enable;
1086 };
1087 };
1088
1089 led_pins_a: leds-alt {
1090 pins-leds {
1091 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1092 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1093 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1094 };
1095 };
1096
1097 mmc0_pins_default: mmc0default {
1098 pins-cmd-dat {
1099 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1100 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1101 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1102 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1103 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1104 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1105 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1106 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1107 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1108 input-enable;
1109 bias-pull-up;
1110 };
1111
1112 pins-clk {
1113 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1114 bias-pull-down;
1115 };
1116
1117 pins-rst {
1118 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1119 bias-pull-up;
1120 };
1121 };
1122
1123 mmc0_pins_uhs: mmc0 {
1124 pins-cmd-dat {
1125 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1126 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1127 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1128 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1129 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1130 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1131 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1132 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1133 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1134 input-enable;
1135 drive-strength = <MTK_DRIVE_2mA>;
1136 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1137 };
1138
1139 pins-clk {
1140 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1141 drive-strength = <MTK_DRIVE_2mA>;
1142 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1143 };
1144
1145 pins-rst {
1146 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1147 bias-pull-up;
1148 };
1149 };
1150
1151 mmc1_pins_default: mmc1default {
1152 pins-cmd-dat {
1153 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1154 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1155 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1156 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1157 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1158 input-enable;
1159 drive-strength = <MTK_DRIVE_4mA>;
1160 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1161 };
1162
1163 pins-clk {
1164 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1165 bias-pull-down;
1166 drive-strength = <MTK_DRIVE_4mA>;
1167 };
1168
1169 pins-wp {
1170 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1171 input-enable;
1172 bias-pull-up;
1173 };
1174
1175 pins-insert {
1176 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1177 bias-pull-up;
1178 };
1179 };
1180
1181 mmc1_pins_uhs: mmc1 {
1182 pins-cmd-dat {
1183 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1184 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1185 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1186 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1187 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1188 input-enable;
1189 drive-strength = <MTK_DRIVE_4mA>;
1190 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1191 };
1192
1193 pins-clk {
1194 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1195 drive-strength = <MTK_DRIVE_4mA>;
1196 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1197 };
1198 };
1199
1200 nand_pins_default: nanddefault {
1201 pins-ale {
1202 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1203 drive-strength = <MTK_DRIVE_8mA>;
1204 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1205 };
1206
1207 pins-dat {
1208 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1209 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1210 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1211 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1212 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1213 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1214 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1215 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1216 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1217 input-enable;
1218 drive-strength = <MTK_DRIVE_8mA>;
1219 bias-pull-up;
1220 };
1221
1222 pins-we {
1223 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1224 drive-strength = <MTK_DRIVE_8mA>;
1225 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1226 };
1227 };
1228
1229 pcie_default: pcie_pin_default {
1230 pins_cmd_dat {
1231 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1232 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1233 bias-disable;
1234 };
1235 };
1236
1237 pwm_pins_a: pwm-default {
1238 pins-pwm {
1239 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1240 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1241 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1242 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1243 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1244 };
1245 };
1246
1247 spi0_pins_a: spi0-default {
1248 pins-spi {
1249 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1250 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1251 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1252 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1253 bias-disable;
1254 };
1255 };
1256
1257 spi1_pins_a: spi1-default {
1258 pins-spi {
1259 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1260 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1261 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1262 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1263 };
1264 };
1265
1266 spi2_pins_a: spi2-default {
1267 pins-spi {
1268 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1269 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1270 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1271 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1272 };
1273 };
1274
1275 uart0_pins_a: uart0-default {
1276 pins-dat {
1277 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1278 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1279 };
1280 };
1281
1282 uart1_pins_a: uart1-default {
1283 pins-dat {
1284 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1285 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1286 };
1287 };
1288
1289 uart2_pins_a: uart2-default {
1290 pins-dat {
1291 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1292 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1293 };
1294 };
1295
1296 uart2_pins_b: uart2-alt {
1297 pins-dat {
1298 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1299 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1300 };
1301 };
1302};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: John Crispin <john@phrozen.org>
5 * Sean Wang <sean.wang@mediatek.com>
6 * Ryder Lee <ryder.lee@mediatek.com>
7 *
8 */
9
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/clock/mt2701-clk.h>
13#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14#include <dt-bindings/power/mt2701-power.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17#include <dt-bindings/reset/mt2701-resets.h>
18#include <dt-bindings/thermal/thermal.h>
19
20/ {
21 compatible = "mediatek,mt7623";
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
29
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
33 };
34
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
38 };
39
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
43 };
44
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
48 };
49
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
53 };
54
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
58 };
59
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
63 };
64
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
68 };
69 };
70
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
75
76 cpu0: cpu@0 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <0x0>;
80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
81 <&apmixedsys CLK_APMIXED_MAINPLL>;
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
86 };
87
88 cpu1: cpu@1 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a7";
91 reg = <0x1>;
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
93 <&apmixedsys CLK_APMIXED_MAINPLL>;
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
98 };
99
100 cpu2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a7";
103 reg = <0x2>;
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
105 <&apmixedsys CLK_APMIXED_MAINPLL>;
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
110 };
111
112 cpu3: cpu@3 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a7";
115 reg = <0x3>;
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
117 <&apmixedsys CLK_APMIXED_MAINPLL>;
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
122 };
123 };
124
125 pmu {
126 compatible = "arm,cortex-a7-pmu";
127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
132 };
133
134 system_clk: dummy13m {
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
138 };
139
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
145 };
146
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
152 };
153
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
158
159 thermal-sensors = <&thermal 0>;
160
161 trips {
162 cpu_passive: cpu-passive {
163 temperature = <47000>;
164 hysteresis = <2000>;
165 type = "passive";
166 };
167
168 cpu_active: cpu-active {
169 temperature = <67000>;
170 hysteresis = <2000>;
171 type = "active";
172 };
173
174 cpu_hot: cpu-hot {
175 temperature = <87000>;
176 hysteresis = <2000>;
177 type = "hot";
178 };
179
180 cpu-crit {
181 temperature = <107000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186
187 cooling-maps {
188 map0 {
189 trip = <&cpu_passive>;
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
192 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 };
195
196 map1 {
197 trip = <&cpu_active>;
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202 };
203
204 map2 {
205 trip = <&cpu_hot>;
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 };
211 };
212 };
213 };
214
215 timer {
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
224 };
225
226 topckgen: syscon@10000000 {
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
229 "syscon";
230 reg = <0 0x10000000 0 0x1000>;
231 #clock-cells = <1>;
232 };
233
234 infracfg: syscon@10001000 {
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
237 "syscon";
238 reg = <0 0x10001000 0 0x1000>;
239 #clock-cells = <1>;
240 #reset-cells = <1>;
241 };
242
243 pericfg: syscon@10003000 {
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
246 "syscon";
247 reg = <0 0x10003000 0 0x1000>;
248 #clock-cells = <1>;
249 #reset-cells = <1>;
250 };
251
252 pio: pinctrl@10005000 {
253 compatible = "mediatek,mt7623-pinctrl";
254 reg = <0 0x1000b000 0 0x1000>;
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 pins-are-numbered;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 interrupt-parent = <&gic>;
261 #interrupt-cells = <2>;
262 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
264 };
265
266 syscfg_pctl_a: syscfg@10005000 {
267 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
268 reg = <0 0x10005000 0 0x1000>;
269 };
270
271 scpsys: power-controller@10006000 {
272 compatible = "mediatek,mt7623-scpsys",
273 "mediatek,mt2701-scpsys",
274 "syscon";
275 #power-domain-cells = <1>;
276 reg = <0 0x10006000 0 0x1000>;
277 infracfg = <&infracfg>;
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
281 clock-names = "mm", "mfg", "ethif";
282 };
283
284 watchdog: watchdog@10007000 {
285 compatible = "mediatek,mt7623-wdt",
286 "mediatek,mt6589-wdt";
287 reg = <0 0x10007000 0 0x100>;
288 };
289
290 timer: timer@10008000 {
291 compatible = "mediatek,mt7623-timer",
292 "mediatek,mt6577-timer";
293 reg = <0 0x10008000 0 0x80>;
294 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
295 clocks = <&system_clk>, <&rtc32k>;
296 clock-names = "system-clk", "rtc-clk";
297 };
298
299 pwrap: pwrap@1000d000 {
300 compatible = "mediatek,mt7623-pwrap",
301 "mediatek,mt2701-pwrap";
302 reg = <0 0x1000d000 0 0x1000>;
303 reg-names = "pwrap";
304 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
306 reset-names = "pwrap";
307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
308 <&infracfg CLK_INFRA_PMICWRAP>;
309 clock-names = "spi", "wrap";
310 };
311
312 cir: cir@10013000 {
313 compatible = "mediatek,mt7623-cir";
314 reg = <0 0x10013000 0 0x1000>;
315 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
316 clocks = <&infracfg CLK_INFRA_IRRX>;
317 clock-names = "clk";
318 status = "disabled";
319 };
320
321 sysirq: interrupt-controller@10200100 {
322 compatible = "mediatek,mt7623-sysirq",
323 "mediatek,mt6577-sysirq";
324 interrupt-controller;
325 #interrupt-cells = <3>;
326 interrupt-parent = <&gic>;
327 reg = <0 0x10200100 0 0x1c>;
328 };
329
330 efuse: efuse@10206000 {
331 compatible = "mediatek,mt7623-efuse",
332 "mediatek,mt8173-efuse";
333 reg = <0 0x10206000 0 0x1000>;
334 #address-cells = <1>;
335 #size-cells = <1>;
336 thermal_calibration_data: calib@424 {
337 reg = <0x424 0xc>;
338 };
339 };
340
341 apmixedsys: syscon@10209000 {
342 compatible = "mediatek,mt7623-apmixedsys",
343 "mediatek,mt2701-apmixedsys",
344 "syscon";
345 reg = <0 0x10209000 0 0x1000>;
346 #clock-cells = <1>;
347 };
348
349 rng: rng@1020f000 {
350 compatible = "mediatek,mt7623-rng";
351 reg = <0 0x1020f000 0 0x1000>;
352 clocks = <&infracfg CLK_INFRA_TRNG>;
353 clock-names = "rng";
354 };
355
356 gic: interrupt-controller@10211000 {
357 compatible = "arm,cortex-a7-gic";
358 interrupt-controller;
359 #interrupt-cells = <3>;
360 interrupt-parent = <&gic>;
361 reg = <0 0x10211000 0 0x1000>,
362 <0 0x10212000 0 0x2000>,
363 <0 0x10214000 0 0x2000>,
364 <0 0x10216000 0 0x2000>;
365 };
366
367 auxadc: adc@11001000 {
368 compatible = "mediatek,mt7623-auxadc",
369 "mediatek,mt2701-auxadc";
370 reg = <0 0x11001000 0 0x1000>;
371 clocks = <&pericfg CLK_PERI_AUXADC>;
372 clock-names = "main";
373 #io-channel-cells = <1>;
374 };
375
376 uart0: serial@11002000 {
377 compatible = "mediatek,mt7623-uart",
378 "mediatek,mt6577-uart";
379 reg = <0 0x11002000 0 0x400>;
380 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
381 clocks = <&pericfg CLK_PERI_UART0_SEL>,
382 <&pericfg CLK_PERI_UART0>;
383 clock-names = "baud", "bus";
384 status = "disabled";
385 };
386
387 uart1: serial@11003000 {
388 compatible = "mediatek,mt7623-uart",
389 "mediatek,mt6577-uart";
390 reg = <0 0x11003000 0 0x400>;
391 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
392 clocks = <&pericfg CLK_PERI_UART1_SEL>,
393 <&pericfg CLK_PERI_UART1>;
394 clock-names = "baud", "bus";
395 status = "disabled";
396 };
397
398 uart2: serial@11004000 {
399 compatible = "mediatek,mt7623-uart",
400 "mediatek,mt6577-uart";
401 reg = <0 0x11004000 0 0x400>;
402 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
403 clocks = <&pericfg CLK_PERI_UART2_SEL>,
404 <&pericfg CLK_PERI_UART2>;
405 clock-names = "baud", "bus";
406 status = "disabled";
407 };
408
409 uart3: serial@11005000 {
410 compatible = "mediatek,mt7623-uart",
411 "mediatek,mt6577-uart";
412 reg = <0 0x11005000 0 0x400>;
413 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
414 clocks = <&pericfg CLK_PERI_UART3_SEL>,
415 <&pericfg CLK_PERI_UART3>;
416 clock-names = "baud", "bus";
417 status = "disabled";
418 };
419
420 pwm: pwm@11006000 {
421 compatible = "mediatek,mt7623-pwm";
422 reg = <0 0x11006000 0 0x1000>;
423 #pwm-cells = <2>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
425 <&pericfg CLK_PERI_PWM>,
426 <&pericfg CLK_PERI_PWM1>,
427 <&pericfg CLK_PERI_PWM2>,
428 <&pericfg CLK_PERI_PWM3>,
429 <&pericfg CLK_PERI_PWM4>,
430 <&pericfg CLK_PERI_PWM5>;
431 clock-names = "top", "main", "pwm1", "pwm2",
432 "pwm3", "pwm4", "pwm5";
433 status = "disabled";
434 };
435
436 i2c0: i2c@11007000 {
437 compatible = "mediatek,mt7623-i2c",
438 "mediatek,mt6577-i2c";
439 reg = <0 0x11007000 0 0x70>,
440 <0 0x11000200 0 0x80>;
441 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
442 clock-div = <16>;
443 clocks = <&pericfg CLK_PERI_I2C0>,
444 <&pericfg CLK_PERI_AP_DMA>;
445 clock-names = "main", "dma";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
450
451 i2c1: i2c@11008000 {
452 compatible = "mediatek,mt7623-i2c",
453 "mediatek,mt6577-i2c";
454 reg = <0 0x11008000 0 0x70>,
455 <0 0x11000280 0 0x80>;
456 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
457 clock-div = <16>;
458 clocks = <&pericfg CLK_PERI_I2C1>,
459 <&pericfg CLK_PERI_AP_DMA>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 status = "disabled";
464 };
465
466 i2c2: i2c@11009000 {
467 compatible = "mediatek,mt7623-i2c",
468 "mediatek,mt6577-i2c";
469 reg = <0 0x11009000 0 0x70>,
470 <0 0x11000300 0 0x80>;
471 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
472 clock-div = <16>;
473 clocks = <&pericfg CLK_PERI_I2C2>,
474 <&pericfg CLK_PERI_AP_DMA>;
475 clock-names = "main", "dma";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480
481 spi0: spi@1100a000 {
482 compatible = "mediatek,mt7623-spi",
483 "mediatek,mt2701-spi";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 reg = <0 0x1100a000 0 0x100>;
487 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
490 <&pericfg CLK_PERI_SPI0>;
491 clock-names = "parent-clk", "sel-clk", "spi-clk";
492 status = "disabled";
493 };
494
495 thermal: thermal@1100b000 {
496 #thermal-sensor-cells = <1>;
497 compatible = "mediatek,mt7623-thermal",
498 "mediatek,mt2701-thermal";
499 reg = <0 0x1100b000 0 0x1000>;
500 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
501 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
502 clock-names = "therm", "auxadc";
503 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
504 reset-names = "therm";
505 mediatek,auxadc = <&auxadc>;
506 mediatek,apmixedsys = <&apmixedsys>;
507 nvmem-cells = <&thermal_calibration_data>;
508 nvmem-cell-names = "calibration-data";
509 };
510
511 btif: serial@1100c000 {
512 compatible = "mediatek,mt7623-btif",
513 "mediatek,mtk-btif";
514 reg = <0 0x1100c000 0 0x1000>;
515 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
516 clocks = <&pericfg CLK_PERI_BTIF>;
517 clock-names = "main";
518 reg-shift = <2>;
519 reg-io-width = <4>;
520 status = "disabled";
521 };
522
523 nandc: nfi@1100d000 {
524 compatible = "mediatek,mt7623-nfc",
525 "mediatek,mt2701-nfc";
526 reg = <0 0x1100d000 0 0x1000>;
527 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
528 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
529 clocks = <&pericfg CLK_PERI_NFI>,
530 <&pericfg CLK_PERI_NFI_PAD>;
531 clock-names = "nfi_clk", "pad_clk";
532 status = "disabled";
533 ecc-engine = <&bch>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 };
537
538 bch: ecc@1100e000 {
539 compatible = "mediatek,mt7623-ecc",
540 "mediatek,mt2701-ecc";
541 reg = <0 0x1100e000 0 0x1000>;
542 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
543 clocks = <&pericfg CLK_PERI_NFI_ECC>;
544 clock-names = "nfiecc_clk";
545 status = "disabled";
546 };
547
548 nor_flash: spi@11014000 {
549 compatible = "mediatek,mt7623-nor",
550 "mediatek,mt8173-nor";
551 reg = <0 0x11014000 0 0x1000>;
552 clocks = <&pericfg CLK_PERI_FLASH>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
554 clock-names = "spi", "sf";
555 #address-cells = <1>;
556 #size-cells = <0>;
557 status = "disabled";
558 };
559
560 spi1: spi@11016000 {
561 compatible = "mediatek,mt7623-spi",
562 "mediatek,mt2701-spi";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 reg = <0 0x11016000 0 0x100>;
566 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
567 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
568 <&topckgen CLK_TOP_SPI1_SEL>,
569 <&pericfg CLK_PERI_SPI1>;
570 clock-names = "parent-clk", "sel-clk", "spi-clk";
571 status = "disabled";
572 };
573
574 spi2: spi@11017000 {
575 compatible = "mediatek,mt7623-spi",
576 "mediatek,mt2701-spi";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <0 0x11017000 0 0x1000>;
580 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
581 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
582 <&topckgen CLK_TOP_SPI2_SEL>,
583 <&pericfg CLK_PERI_SPI2>;
584 clock-names = "parent-clk", "sel-clk", "spi-clk";
585 status = "disabled";
586 };
587
588 audsys: clock-controller@11220000 {
589 compatible = "mediatek,mt7623-audsys",
590 "mediatek,mt2701-audsys",
591 "syscon";
592 reg = <0 0x11220000 0 0x2000>;
593 #clock-cells = <1>;
594
595 afe: audio-controller {
596 compatible = "mediatek,mt7623-audio",
597 "mediatek,mt2701-audio";
598 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
599 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
600 interrupt-names = "afe", "asys";
601 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
602
603 clocks = <&infracfg CLK_INFRA_AUDIO>,
604 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
605 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
606 <&topckgen CLK_TOP_AUD_48K_TIMING>,
607 <&topckgen CLK_TOP_AUD_44K_TIMING>,
608 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
609 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
610 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
611 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
612 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
613 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
614 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
615 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
616 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
617 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
618 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
619 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
620 <&audsys CLK_AUD_I2SO1>,
621 <&audsys CLK_AUD_I2SO2>,
622 <&audsys CLK_AUD_I2SO3>,
623 <&audsys CLK_AUD_I2SO4>,
624 <&audsys CLK_AUD_I2SIN1>,
625 <&audsys CLK_AUD_I2SIN2>,
626 <&audsys CLK_AUD_I2SIN3>,
627 <&audsys CLK_AUD_I2SIN4>,
628 <&audsys CLK_AUD_ASRCO1>,
629 <&audsys CLK_AUD_ASRCO2>,
630 <&audsys CLK_AUD_ASRCO3>,
631 <&audsys CLK_AUD_ASRCO4>,
632 <&audsys CLK_AUD_AFE>,
633 <&audsys CLK_AUD_AFE_CONN>,
634 <&audsys CLK_AUD_A1SYS>,
635 <&audsys CLK_AUD_A2SYS>,
636 <&audsys CLK_AUD_AFE_MRGIF>;
637
638 clock-names = "infra_sys_audio_clk",
639 "top_audio_mux1_sel",
640 "top_audio_mux2_sel",
641 "top_audio_a1sys_hp",
642 "top_audio_a2sys_hp",
643 "i2s0_src_sel",
644 "i2s1_src_sel",
645 "i2s2_src_sel",
646 "i2s3_src_sel",
647 "i2s0_src_div",
648 "i2s1_src_div",
649 "i2s2_src_div",
650 "i2s3_src_div",
651 "i2s0_mclk_en",
652 "i2s1_mclk_en",
653 "i2s2_mclk_en",
654 "i2s3_mclk_en",
655 "i2so0_hop_ck",
656 "i2so1_hop_ck",
657 "i2so2_hop_ck",
658 "i2so3_hop_ck",
659 "i2si0_hop_ck",
660 "i2si1_hop_ck",
661 "i2si2_hop_ck",
662 "i2si3_hop_ck",
663 "asrc0_out_ck",
664 "asrc1_out_ck",
665 "asrc2_out_ck",
666 "asrc3_out_ck",
667 "audio_afe_pd",
668 "audio_afe_conn_pd",
669 "audio_a1sys_pd",
670 "audio_a2sys_pd",
671 "audio_mrgif_pd";
672
673 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
674 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
675 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
676 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
677 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
678 <&topckgen CLK_TOP_AUD2PLL_90M>;
679 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
680 };
681 };
682
683 mmc0: mmc@11230000 {
684 compatible = "mediatek,mt7623-mmc",
685 "mediatek,mt2701-mmc";
686 reg = <0 0x11230000 0 0x1000>;
687 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
688 clocks = <&pericfg CLK_PERI_MSDC30_0>,
689 <&topckgen CLK_TOP_MSDC30_0_SEL>;
690 clock-names = "source", "hclk";
691 status = "disabled";
692 };
693
694 mmc1: mmc@11240000 {
695 compatible = "mediatek,mt7623-mmc",
696 "mediatek,mt2701-mmc";
697 reg = <0 0x11240000 0 0x1000>;
698 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
699 clocks = <&pericfg CLK_PERI_MSDC30_1>,
700 <&topckgen CLK_TOP_MSDC30_1_SEL>;
701 clock-names = "source", "hclk";
702 status = "disabled";
703 };
704
705 vdecsys: syscon@16000000 {
706 compatible = "mediatek,mt7623-vdecsys",
707 "mediatek,mt2701-vdecsys",
708 "syscon";
709 reg = <0 0x16000000 0 0x1000>;
710 #clock-cells = <1>;
711 };
712
713 hifsys: syscon@1a000000 {
714 compatible = "mediatek,mt7623-hifsys",
715 "mediatek,mt2701-hifsys",
716 "syscon";
717 reg = <0 0x1a000000 0 0x1000>;
718 #clock-cells = <1>;
719 #reset-cells = <1>;
720 };
721
722 pcie: pcie@1a140000 {
723 compatible = "mediatek,mt7623-pcie";
724 device_type = "pci";
725 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
726 <0 0x1a142000 0 0x1000>, /* Port0 registers */
727 <0 0x1a143000 0 0x1000>, /* Port1 registers */
728 <0 0x1a144000 0 0x1000>; /* Port2 registers */
729 reg-names = "subsys", "port0", "port1", "port2";
730 #address-cells = <3>;
731 #size-cells = <2>;
732 #interrupt-cells = <1>;
733 interrupt-map-mask = <0xf800 0 0 0>;
734 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
735 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
736 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
737 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
738 <&hifsys CLK_HIFSYS_PCIE0>,
739 <&hifsys CLK_HIFSYS_PCIE1>,
740 <&hifsys CLK_HIFSYS_PCIE2>;
741 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
742 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
743 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
744 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
745 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
746 phys = <&pcie0_port PHY_TYPE_PCIE>,
747 <&pcie1_port PHY_TYPE_PCIE>,
748 <&u3port1 PHY_TYPE_PCIE>;
749 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
750 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
751 bus-range = <0x00 0xff>;
752 status = "disabled";
753 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
754 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
755
756 pcie@0,0 {
757 reg = <0x0000 0 0 0 0>;
758 #address-cells = <3>;
759 #size-cells = <2>;
760 #interrupt-cells = <1>;
761 interrupt-map-mask = <0 0 0 0>;
762 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
763 ranges;
764 status = "disabled";
765 };
766
767 pcie@1,0 {
768 reg = <0x0800 0 0 0 0>;
769 #address-cells = <3>;
770 #size-cells = <2>;
771 #interrupt-cells = <1>;
772 interrupt-map-mask = <0 0 0 0>;
773 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
774 ranges;
775 status = "disabled";
776 };
777
778 pcie@2,0 {
779 reg = <0x1000 0 0 0 0>;
780 #address-cells = <3>;
781 #size-cells = <2>;
782 #interrupt-cells = <1>;
783 interrupt-map-mask = <0 0 0 0>;
784 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
785 ranges;
786 status = "disabled";
787 };
788 };
789
790 pcie0_phy: t-phy@1a149000 {
791 compatible = "mediatek,mt7623-tphy",
792 "mediatek,generic-tphy-v1";
793 reg = <0 0x1a149000 0 0x0700>;
794 #address-cells = <2>;
795 #size-cells = <2>;
796 ranges;
797 status = "disabled";
798
799 pcie0_port: pcie-phy@1a149900 {
800 reg = <0 0x1a149900 0 0x0700>;
801 clocks = <&clk26m>;
802 clock-names = "ref";
803 #phy-cells = <1>;
804 status = "okay";
805 };
806 };
807
808 pcie1_phy: t-phy@1a14a000 {
809 compatible = "mediatek,mt7623-tphy",
810 "mediatek,generic-tphy-v1";
811 reg = <0 0x1a14a000 0 0x0700>;
812 #address-cells = <2>;
813 #size-cells = <2>;
814 ranges;
815 status = "disabled";
816
817 pcie1_port: pcie-phy@1a14a900 {
818 reg = <0 0x1a14a900 0 0x0700>;
819 clocks = <&clk26m>;
820 clock-names = "ref";
821 #phy-cells = <1>;
822 status = "okay";
823 };
824 };
825
826 usb1: usb@1a1c0000 {
827 compatible = "mediatek,mt7623-xhci",
828 "mediatek,mtk-xhci";
829 reg = <0 0x1a1c0000 0 0x1000>,
830 <0 0x1a1c4700 0 0x0100>;
831 reg-names = "mac", "ippc";
832 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
833 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
834 <&topckgen CLK_TOP_ETHIF_SEL>;
835 clock-names = "sys_ck", "ref_ck";
836 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
837 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
838 status = "disabled";
839 };
840
841 u3phy1: t-phy@1a1c4000 {
842 compatible = "mediatek,mt7623-tphy",
843 "mediatek,generic-tphy-v1";
844 reg = <0 0x1a1c4000 0 0x0700>;
845 #address-cells = <2>;
846 #size-cells = <2>;
847 ranges;
848 status = "disabled";
849
850 u2port0: usb-phy@1a1c4800 {
851 reg = <0 0x1a1c4800 0 0x0100>;
852 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
853 clock-names = "ref";
854 #phy-cells = <1>;
855 status = "okay";
856 };
857
858 u3port0: usb-phy@1a1c4900 {
859 reg = <0 0x1a1c4900 0 0x0700>;
860 clocks = <&clk26m>;
861 clock-names = "ref";
862 #phy-cells = <1>;
863 status = "okay";
864 };
865 };
866
867 usb2: usb@1a240000 {
868 compatible = "mediatek,mt7623-xhci",
869 "mediatek,mtk-xhci";
870 reg = <0 0x1a240000 0 0x1000>,
871 <0 0x1a244700 0 0x0100>;
872 reg-names = "mac", "ippc";
873 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
874 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
875 <&topckgen CLK_TOP_ETHIF_SEL>;
876 clock-names = "sys_ck", "ref_ck";
877 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
878 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
879 status = "disabled";
880 };
881
882 u3phy2: t-phy@1a244000 {
883 compatible = "mediatek,mt7623-tphy",
884 "mediatek,generic-tphy-v1";
885 reg = <0 0x1a244000 0 0x0700>;
886 #address-cells = <2>;
887 #size-cells = <2>;
888 ranges;
889 status = "disabled";
890
891 u2port1: usb-phy@1a244800 {
892 reg = <0 0x1a244800 0 0x0100>;
893 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
894 clock-names = "ref";
895 #phy-cells = <1>;
896 status = "okay";
897 };
898
899 u3port1: usb-phy@1a244900 {
900 reg = <0 0x1a244900 0 0x0700>;
901 clocks = <&clk26m>;
902 clock-names = "ref";
903 #phy-cells = <1>;
904 status = "okay";
905 };
906 };
907
908 ethsys: syscon@1b000000 {
909 compatible = "mediatek,mt7623-ethsys",
910 "mediatek,mt2701-ethsys",
911 "syscon";
912 reg = <0 0x1b000000 0 0x1000>;
913 #clock-cells = <1>;
914 #reset-cells = <1>;
915 };
916
917 hsdma: dma-controller@1b007000 {
918 compatible = "mediatek,mt7623-hsdma";
919 reg = <0 0x1b007000 0 0x1000>;
920 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
921 clocks = <ðsys CLK_ETHSYS_HSDMA>;
922 clock-names = "hsdma";
923 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
924 #dma-cells = <1>;
925 };
926
927 eth: ethernet@1b100000 {
928 compatible = "mediatek,mt7623-eth",
929 "mediatek,mt2701-eth",
930 "syscon";
931 reg = <0 0x1b100000 0 0x20000>;
932 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
933 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
934 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
935 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
936 <ðsys CLK_ETHSYS_ESW>,
937 <ðsys CLK_ETHSYS_GP1>,
938 <ðsys CLK_ETHSYS_GP2>,
939 <&apmixedsys CLK_APMIXED_TRGPLL>;
940 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
941 resets = <ðsys MT2701_ETHSYS_FE_RST>,
942 <ðsys MT2701_ETHSYS_GMAC_RST>,
943 <ðsys MT2701_ETHSYS_PPE_RST>;
944 reset-names = "fe", "gmac", "ppe";
945 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
946 mediatek,ethsys = <ðsys>;
947 mediatek,pctl = <&syscfg_pctl_a>;
948 #address-cells = <1>;
949 #size-cells = <0>;
950 status = "disabled";
951 };
952
953 crypto: crypto@1b240000 {
954 compatible = "mediatek,eip97-crypto";
955 reg = <0 0x1b240000 0 0x20000>;
956 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
957 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
958 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
959 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
960 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
961 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
962 clock-names = "cryp";
963 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
964 status = "disabled";
965 };
966
967 bdpsys: syscon@1c000000 {
968 compatible = "mediatek,mt7623-bdpsys",
969 "mediatek,mt2701-bdpsys",
970 "syscon";
971 reg = <0 0x1c000000 0 0x1000>;
972 #clock-cells = <1>;
973 };
974};
975
976&pio {
977 cir_pins_a:cir-default {
978 pins-cir {
979 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
980 bias-disable;
981 };
982 };
983
984 i2c0_pins_a: i2c0-default {
985 pins-i2c0 {
986 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
987 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
988 bias-disable;
989 };
990 };
991
992 i2c1_pins_a: i2c1-default {
993 pin-i2c1 {
994 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
995 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
996 bias-disable;
997 };
998 };
999
1000 i2c1_pins_b: i2c1-alt {
1001 pin-i2c1 {
1002 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1003 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1004 bias-disable;
1005 };
1006 };
1007
1008 i2c2_pins_a: i2c2-default {
1009 pin-i2c2 {
1010 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1011 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1012 bias-disable;
1013 };
1014 };
1015
1016 i2c2_pins_b: i2c2-alt {
1017 pin-i2c2 {
1018 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1019 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1020 bias-disable;
1021 };
1022 };
1023
1024 i2s0_pins_a: i2s0-default {
1025 pin-i2s0 {
1026 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1027 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1028 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1029 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1030 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1031 drive-strength = <MTK_DRIVE_12mA>;
1032 bias-pull-down;
1033 };
1034 };
1035
1036 i2s1_pins_a: i2s1-default {
1037 pin-i2s1 {
1038 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1039 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1040 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1041 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1042 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1043 drive-strength = <MTK_DRIVE_12mA>;
1044 bias-pull-down;
1045 };
1046 };
1047
1048 key_pins_a: keys-alt {
1049 pins-keys {
1050 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1051 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1052 input-enable;
1053 };
1054 };
1055
1056 led_pins_a: leds-alt {
1057 pins-leds {
1058 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1059 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1060 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1061 };
1062 };
1063
1064 mmc0_pins_default: mmc0default {
1065 pins-cmd-dat {
1066 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1067 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1068 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1069 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1070 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1071 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1072 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1073 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1074 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1075 input-enable;
1076 bias-pull-up;
1077 };
1078
1079 pins-clk {
1080 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1081 bias-pull-down;
1082 };
1083
1084 pins-rst {
1085 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1086 bias-pull-up;
1087 };
1088 };
1089
1090 mmc0_pins_uhs: mmc0 {
1091 pins-cmd-dat {
1092 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1093 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1094 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1095 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1096 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1097 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1098 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1099 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1100 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1101 input-enable;
1102 drive-strength = <MTK_DRIVE_2mA>;
1103 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1104 };
1105
1106 pins-clk {
1107 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1108 drive-strength = <MTK_DRIVE_2mA>;
1109 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1110 };
1111
1112 pins-rst {
1113 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1114 bias-pull-up;
1115 };
1116 };
1117
1118 mmc1_pins_default: mmc1default {
1119 pins-cmd-dat {
1120 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1121 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1122 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1123 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1124 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1125 input-enable;
1126 drive-strength = <MTK_DRIVE_4mA>;
1127 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1128 };
1129
1130 pins-clk {
1131 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1132 bias-pull-down;
1133 drive-strength = <MTK_DRIVE_4mA>;
1134 };
1135
1136 pins-wp {
1137 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1138 input-enable;
1139 bias-pull-up;
1140 };
1141
1142 pins-insert {
1143 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1144 bias-pull-up;
1145 };
1146 };
1147
1148 mmc1_pins_uhs: mmc1 {
1149 pins-cmd-dat {
1150 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1151 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1152 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1153 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1154 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1155 input-enable;
1156 drive-strength = <MTK_DRIVE_4mA>;
1157 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1158 };
1159
1160 pins-clk {
1161 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1162 drive-strength = <MTK_DRIVE_4mA>;
1163 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1164 };
1165 };
1166
1167 nand_pins_default: nanddefault {
1168 pins-ale {
1169 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1170 drive-strength = <MTK_DRIVE_8mA>;
1171 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1172 };
1173
1174 pins-dat {
1175 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1176 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1177 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1178 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1179 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1180 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1181 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1182 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1183 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1184 input-enable;
1185 drive-strength = <MTK_DRIVE_8mA>;
1186 bias-pull-up;
1187 };
1188
1189 pins-we {
1190 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1191 drive-strength = <MTK_DRIVE_8mA>;
1192 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1193 };
1194 };
1195
1196 pcie_default: pcie_pin_default {
1197 pins_cmd_dat {
1198 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1199 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1200 bias-disable;
1201 };
1202 };
1203
1204 pwm_pins_a: pwm-default {
1205 pins-pwm {
1206 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1207 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1208 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1209 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1210 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1211 };
1212 };
1213
1214 spi0_pins_a: spi0-default {
1215 pins-spi {
1216 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1217 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1218 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1219 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1220 bias-disable;
1221 };
1222 };
1223
1224 spi1_pins_a: spi1-default {
1225 pins-spi {
1226 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1227 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1228 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1229 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1230 };
1231 };
1232
1233 spi2_pins_a: spi2-default {
1234 pins-spi {
1235 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1236 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1237 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1238 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1239 };
1240 };
1241
1242 uart0_pins_a: uart0-default {
1243 pins-dat {
1244 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1245 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1246 };
1247 };
1248
1249 uart1_pins_a: uart1-default {
1250 pins-dat {
1251 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1252 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1253 };
1254 };
1255
1256 uart2_pins_a: uart2-default {
1257 pins-dat {
1258 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1259 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1260 };
1261 };
1262
1263 uart2_pins_b: uart2-alt {
1264 pins-dat {
1265 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1266 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1267 };
1268 };
1269};