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1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 */
9
10/dts-v1/;
11
12#include "imx7d-tqma7.dtsi"
13#include "imx7-mba7.dtsi"
14
15/ {
16 model = "TQ-Systems TQMa7D board on MBa7 carrier board";
17 compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
18};
19
20&fec2 {
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet2>;
23 phy-mode = "rgmii-id";
24 phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
25 phy-reset-duration = <1>;
26 phy-supply = <®_fec2_pwdn>;
27 phy-handle = <ðphy2_0>;
28 fsl,magic-packet;
29 status = "okay";
30
31 mdio {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 ethphy2_0: ethernet-phy@0 {
36 compatible = "ethernet-phy-ieee802.3-c22";
37 reg = <0>;
38 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
39 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
40 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
41 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
42 };
43 };
44};
45
46&iomuxc {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_hog_mba7_1>;
49
50 pinctrl_enet2: enet2grp {
51 fsl,pins = <
52 MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
53 MX7D_PAD_SD2_WP__ENET2_MDC 0x00
54 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
55 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
56 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
57 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
58 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
59 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
60 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
61 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
62 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
63 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
64 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
65 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
66 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
67 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
68 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
69 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
70 >;
71 };
72
73 pinctrl_pcie: pciegrp {
74 fsl,pins = <
75 /* #pcie_wake */
76 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
77 /* #pcie_rst */
78 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
79 /* #pcie_dis */
80 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
81 >;
82 };
83};
84
85&iomuxc_lpsr {
86 pinctrl_usbotg2: usbotg2grp {
87 fsl,pins = <
88 MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
89 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
90 >;
91 };
92};
93
94&pcie {
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pcie>;
97 /* 1.5V logically from 3.3V */
98 /* probe deferral not supported */
99 /* pcie-bus-supply = <®_mpcie_1v5>; */
100 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
101 status = "okay";
102};
103
104&usbotg2 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_usbotg2>;
107 vbus-supply = <®_usb_otg2_vbus>;
108 srp-disable;
109 hnp-disable;
110 adp-disable;
111 dr_mode = "host";
112 status = "okay";
113};
1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 */
9
10/dts-v1/;
11
12#include "imx7d-tqma7.dtsi"
13#include "imx7-mba7.dtsi"
14
15/ {
16 model = "TQ Systems TQMa7D board on MBa7 carrier board";
17 compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
18};
19
20&fec2 {
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet2>;
23 phy-mode = "rgmii-id";
24 phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
25 phy-reset-duration = <1>;
26 phy-reset-delay = <1>;
27 phy-supply = <®_fec2_pwdn>;
28 phy-handle = <ðphy2_0>;
29 fsl,magic-packet;
30 status = "okay";
31
32 mdio {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 ethphy2_0: ethernet-phy@0 {
37 compatible = "ethernet-phy-ieee802.3-c22";
38 reg = <0>;
39 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
40 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
41 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
42 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
43 };
44 };
45};
46
47&iomuxc {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog_mba7_1>;
50
51 pinctrl_enet2: enet2grp {
52 fsl,pins = <
53 MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
54 MX7D_PAD_SD2_WP__ENET2_MDC 0x00
55 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
56 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
57 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
58 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
59 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
60 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
61 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
62 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
63 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
64 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
65 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
66 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
67 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
68 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
69 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
70 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
71 >;
72 };
73
74 pinctrl_pcie: pciegrp {
75 fsl,pins = <
76 /* #pcie_wake */
77 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
78 /* #pcie_rst */
79 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
80 /* #pcie_dis */
81 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
82 >;
83 };
84};
85
86&iomuxc_lpsr {
87 pinctrl_usbotg2: usbotg2grp {
88 fsl,pins = <
89 MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
90 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
91 >;
92 };
93};
94
95&pcie {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_pcie>;
98 /* 1.5V logically from 3.3V */
99 /* probe deferral not supported */
100 /* pcie-bus-supply = <®_mpcie_1v5>; */
101 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
102 status = "okay";
103};
104
105&usbotg2 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_usbotg2>;
108 vbus-supply = <®_usb_otg2_vbus>;
109 srp-disable;
110 hnp-disable;
111 adp-disable;
112 dr_mode = "host";
113 status = "okay";
114};