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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 /*
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
17 */
18 chosen {};
19
20 aliases {
21 ethernet0 = &fec;
22 can0 = &can1;
23 can1 = &can2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 ipu0 = &ipu1;
35 mmc0 = &usdhc1;
36 mmc1 = &usdhc2;
37 mmc2 = &usdhc3;
38 mmc3 = &usdhc4;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 spi0 = &ecspi1;
45 spi1 = &ecspi2;
46 spi2 = &ecspi3;
47 spi3 = &ecspi4;
48 usb0 = &usbotg;
49 usb1 = &usbh1;
50 usb2 = &usbh2;
51 usb3 = &usbh3;
52 usbphy0 = &usbphy1;
53 usbphy1 = &usbphy2;
54 };
55
56 clocks {
57 ckil {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 ckih1 {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 osc {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
73 };
74 };
75
76 ldb: ldb {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
80 gpr = <&gpr>;
81 status = "disabled";
82
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0>;
87 status = "disabled";
88
89 port@0 {
90 reg = <0>;
91
92 lvds0_mux_0: endpoint {
93 remote-endpoint = <&ipu1_di0_lvds0>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 lvds0_mux_1: endpoint {
101 remote-endpoint = <&ipu1_di1_lvds0>;
102 };
103 };
104 };
105
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 reg = <1>;
110 status = "disabled";
111
112 port@0 {
113 reg = <0>;
114
115 lvds1_mux_0: endpoint {
116 remote-endpoint = <&ipu1_di0_lvds1>;
117 };
118 };
119
120 port@1 {
121 reg = <1>;
122
123 lvds1_mux_1: endpoint {
124 remote-endpoint = <&ipu1_di1_lvds1>;
125 };
126 };
127 };
128 };
129
130 pmu: pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
134 };
135
136 usbphynop1: usbphynop1 {
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
139 };
140
141 usbphynop2: usbphynop2 {
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
144 };
145
146 soc: soc {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
151 ranges;
152
153 dma_apbh: dma-apbh@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
161 #dma-cells = <1>;
162 dma-channels = <4>;
163 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
164 };
165
166 gpmi: nand-controller@112000 {
167 compatible = "fsl,imx6q-gpmi-nand";
168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
169 reg-names = "gpmi-nand", "bch";
170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "bch";
172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
173 <&clks IMX6QDL_CLK_GPMI_APB>,
174 <&clks IMX6QDL_CLK_GPMI_BCH>,
175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
176 <&clks IMX6QDL_CLK_PER1_BCH>;
177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
178 "gpmi_bch_apb", "per1_bch";
179 dmas = <&dma_apbh 0>;
180 dma-names = "rx-tx";
181 status = "disabled";
182 };
183
184 hdmi: hdmi@120000 {
185 reg = <0x00120000 0x9000>;
186 interrupts = <0 115 0x04>;
187 gpr = <&gpr>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
190 clock-names = "iahb", "isfr";
191 status = "disabled";
192
193 ports {
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 port@0 {
198 reg = <0>;
199
200 hdmi_mux_0: endpoint {
201 remote-endpoint = <&ipu1_di0_hdmi>;
202 };
203 };
204
205 port@1 {
206 reg = <1>;
207
208 hdmi_mux_1: endpoint {
209 remote-endpoint = <&ipu1_di1_hdmi>;
210 };
211 };
212 };
213 };
214
215 gpu_3d: gpu@130000 {
216 compatible = "vivante,gc";
217 reg = <0x00130000 0x4000>;
218 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
220 <&clks IMX6QDL_CLK_GPU3D_CORE>,
221 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
222 clock-names = "bus", "core", "shader";
223 power-domains = <&pd_pu>;
224 #cooling-cells = <2>;
225 };
226
227 gpu_2d: gpu@134000 {
228 compatible = "vivante,gc";
229 reg = <0x00134000 0x4000>;
230 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
232 <&clks IMX6QDL_CLK_GPU2D_CORE>;
233 clock-names = "bus", "core";
234 power-domains = <&pd_pu>;
235 #cooling-cells = <2>;
236 };
237
238 timer@a00600 {
239 compatible = "arm,cortex-a9-twd-timer";
240 reg = <0x00a00600 0x20>;
241 interrupts = <1 13 0xf01>;
242 interrupt-parent = <&intc>;
243 clocks = <&clks IMX6QDL_CLK_TWD>;
244 };
245
246 intc: interrupt-controller@a01000 {
247 compatible = "arm,cortex-a9-gic";
248 #interrupt-cells = <3>;
249 interrupt-controller;
250 reg = <0x00a01000 0x1000>,
251 <0x00a00100 0x100>;
252 interrupt-parent = <&intc>;
253 };
254
255 L2: cache-controller@a02000 {
256 compatible = "arm,pl310-cache";
257 reg = <0x00a02000 0x1000>;
258 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
259 cache-unified;
260 cache-level = <2>;
261 arm,tag-latency = <4 2 3>;
262 arm,data-latency = <4 2 3>;
263 arm,shared-override;
264 };
265
266 pcie: pcie@1ffc000 {
267 compatible = "fsl,imx6q-pcie";
268 reg = <0x01ffc000 0x04000>,
269 <0x01f00000 0x80000>;
270 reg-names = "dbi", "config";
271 #address-cells = <3>;
272 #size-cells = <2>;
273 device_type = "pci";
274 bus-range = <0x00 0xff>;
275 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
276 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
277 num-lanes = <1>;
278 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "msi";
280 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0x7>;
282 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
285 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
287 <&clks IMX6QDL_CLK_LVDS1_GATE>,
288 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
289 clock-names = "pcie", "pcie_bus", "pcie_phy";
290 status = "disabled";
291 };
292
293 aips1: bus@2000000 { /* AIPS1 */
294 compatible = "fsl,aips-bus", "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x02000000 0x100000>;
298 ranges;
299
300 spba-bus@2000000 {
301 compatible = "fsl,spba-bus", "simple-bus";
302 #address-cells = <1>;
303 #size-cells = <1>;
304 reg = <0x02000000 0x40000>;
305 ranges;
306
307 spdif: spdif@2004000 {
308 compatible = "fsl,imx35-spdif";
309 reg = <0x02004000 0x4000>;
310 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
311 dmas = <&sdma 14 18 0>,
312 <&sdma 15 18 0>;
313 dma-names = "rx", "tx";
314 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
315 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
316 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
317 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
318 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
319 clock-names = "core", "rxtx0",
320 "rxtx1", "rxtx2",
321 "rxtx3", "rxtx4",
322 "rxtx5", "rxtx6",
323 "rxtx7", "spba";
324 status = "disabled";
325 };
326
327 ecspi1: spi@2008000 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
331 reg = <0x02008000 0x4000>;
332 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
334 <&clks IMX6QDL_CLK_ECSPI1>;
335 clock-names = "ipg", "per";
336 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 ecspi2: spi@200c000 {
342 #address-cells = <1>;
343 #size-cells = <0>;
344 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
345 reg = <0x0200c000 0x4000>;
346 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
348 <&clks IMX6QDL_CLK_ECSPI2>;
349 clock-names = "ipg", "per";
350 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
355 ecspi3: spi@2010000 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
359 reg = <0x02010000 0x4000>;
360 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
362 <&clks IMX6QDL_CLK_ECSPI3>;
363 clock-names = "ipg", "per";
364 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
365 dma-names = "rx", "tx";
366 status = "disabled";
367 };
368
369 ecspi4: spi@2014000 {
370 #address-cells = <1>;
371 #size-cells = <0>;
372 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
373 reg = <0x02014000 0x4000>;
374 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
376 <&clks IMX6QDL_CLK_ECSPI4>;
377 clock-names = "ipg", "per";
378 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
379 dma-names = "rx", "tx";
380 status = "disabled";
381 };
382
383 uart1: serial@2020000 {
384 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
385 reg = <0x02020000 0x4000>;
386 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
388 <&clks IMX6QDL_CLK_UART_SERIAL>;
389 clock-names = "ipg", "per";
390 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
391 dma-names = "rx", "tx";
392 status = "disabled";
393 };
394
395 esai: esai@2024000 {
396 #sound-dai-cells = <0>;
397 compatible = "fsl,imx35-esai";
398 reg = <0x02024000 0x4000>;
399 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
401 <&clks IMX6QDL_CLK_ESAI_MEM>,
402 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
403 <&clks IMX6QDL_CLK_ESAI_IPG>,
404 <&clks IMX6QDL_CLK_SPBA>;
405 clock-names = "core", "mem", "extal", "fsys", "spba";
406 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
407 dma-names = "rx", "tx";
408 status = "disabled";
409 };
410
411 ssi1: ssi@2028000 {
412 #sound-dai-cells = <0>;
413 compatible = "fsl,imx6q-ssi",
414 "fsl,imx51-ssi";
415 reg = <0x02028000 0x4000>;
416 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
418 <&clks IMX6QDL_CLK_SSI1>;
419 clock-names = "ipg", "baud";
420 dmas = <&sdma 37 1 0>,
421 <&sdma 38 1 0>;
422 dma-names = "rx", "tx";
423 fsl,fifo-depth = <15>;
424 status = "disabled";
425 };
426
427 ssi2: ssi@202c000 {
428 #sound-dai-cells = <0>;
429 compatible = "fsl,imx6q-ssi",
430 "fsl,imx51-ssi";
431 reg = <0x0202c000 0x4000>;
432 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
434 <&clks IMX6QDL_CLK_SSI2>;
435 clock-names = "ipg", "baud";
436 dmas = <&sdma 41 1 0>,
437 <&sdma 42 1 0>;
438 dma-names = "rx", "tx";
439 fsl,fifo-depth = <15>;
440 status = "disabled";
441 };
442
443 ssi3: ssi@2030000 {
444 #sound-dai-cells = <0>;
445 compatible = "fsl,imx6q-ssi",
446 "fsl,imx51-ssi";
447 reg = <0x02030000 0x4000>;
448 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
450 <&clks IMX6QDL_CLK_SSI3>;
451 clock-names = "ipg", "baud";
452 dmas = <&sdma 45 1 0>,
453 <&sdma 46 1 0>;
454 dma-names = "rx", "tx";
455 fsl,fifo-depth = <15>;
456 status = "disabled";
457 };
458
459 asrc: asrc@2034000 {
460 compatible = "fsl,imx53-asrc";
461 reg = <0x02034000 0x4000>;
462 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
464 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
468 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
469 <&clks IMX6QDL_CLK_SPBA>;
470 clock-names = "mem", "ipg", "asrck_0",
471 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
472 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
473 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
474 "asrck_d", "asrck_e", "asrck_f", "spba";
475 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
476 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
477 dma-names = "rxa", "rxb", "rxc",
478 "txa", "txb", "txc";
479 fsl,asrc-rate = <48000>;
480 fsl,asrc-width = <16>;
481 status = "okay";
482 };
483
484 spba-bus@203c000 {
485 reg = <0x0203c000 0x4000>;
486 };
487 };
488
489 vpu: vpu@2040000 {
490 compatible = "cnm,coda960";
491 reg = <0x02040000 0x3c000>;
492 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
493 <0 3 IRQ_TYPE_LEVEL_HIGH>;
494 interrupt-names = "bit", "jpeg";
495 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
496 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
497 clock-names = "per", "ahb";
498 power-domains = <&pd_pu>;
499 resets = <&src 1>;
500 iram = <&ocram>;
501 };
502
503 aipstz@207c000 { /* AIPSTZ1 */
504 reg = <0x0207c000 0x4000>;
505 };
506
507 pwm1: pwm@2080000 {
508 #pwm-cells = <3>;
509 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
510 reg = <0x02080000 0x4000>;
511 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clks IMX6QDL_CLK_IPG>,
513 <&clks IMX6QDL_CLK_PWM1>;
514 clock-names = "ipg", "per";
515 status = "disabled";
516 };
517
518 pwm2: pwm@2084000 {
519 #pwm-cells = <3>;
520 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
521 reg = <0x02084000 0x4000>;
522 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clks IMX6QDL_CLK_IPG>,
524 <&clks IMX6QDL_CLK_PWM2>;
525 clock-names = "ipg", "per";
526 status = "disabled";
527 };
528
529 pwm3: pwm@2088000 {
530 #pwm-cells = <3>;
531 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
532 reg = <0x02088000 0x4000>;
533 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clks IMX6QDL_CLK_IPG>,
535 <&clks IMX6QDL_CLK_PWM3>;
536 clock-names = "ipg", "per";
537 status = "disabled";
538 };
539
540 pwm4: pwm@208c000 {
541 #pwm-cells = <3>;
542 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
543 reg = <0x0208c000 0x4000>;
544 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clks IMX6QDL_CLK_IPG>,
546 <&clks IMX6QDL_CLK_PWM4>;
547 clock-names = "ipg", "per";
548 status = "disabled";
549 };
550
551 can1: can@2090000 {
552 compatible = "fsl,imx6q-flexcan";
553 reg = <0x02090000 0x4000>;
554 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
556 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
557 clock-names = "ipg", "per";
558 fsl,stop-mode = <&gpr 0x34 28>;
559 status = "disabled";
560 };
561
562 can2: can@2094000 {
563 compatible = "fsl,imx6q-flexcan";
564 reg = <0x02094000 0x4000>;
565 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
567 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
568 clock-names = "ipg", "per";
569 fsl,stop-mode = <&gpr 0x34 29>;
570 status = "disabled";
571 };
572
573 gpt: timer@2098000 {
574 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
575 reg = <0x02098000 0x4000>;
576 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
578 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
579 <&clks IMX6QDL_CLK_GPT_3M>;
580 clock-names = "ipg", "per", "osc_per";
581 };
582
583 gpio1: gpio@209c000 {
584 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
585 reg = <0x0209c000 0x4000>;
586 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
587 <0 67 IRQ_TYPE_LEVEL_HIGH>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
592 };
593
594 gpio2: gpio@20a0000 {
595 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
596 reg = <0x020a0000 0x4000>;
597 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
598 <0 69 IRQ_TYPE_LEVEL_HIGH>;
599 gpio-controller;
600 #gpio-cells = <2>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 };
604
605 gpio3: gpio@20a4000 {
606 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
607 reg = <0x020a4000 0x4000>;
608 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
609 <0 71 IRQ_TYPE_LEVEL_HIGH>;
610 gpio-controller;
611 #gpio-cells = <2>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
614 };
615
616 gpio4: gpio@20a8000 {
617 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
618 reg = <0x020a8000 0x4000>;
619 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
620 <0 73 IRQ_TYPE_LEVEL_HIGH>;
621 gpio-controller;
622 #gpio-cells = <2>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 };
626
627 gpio5: gpio@20ac000 {
628 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
629 reg = <0x020ac000 0x4000>;
630 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
631 <0 75 IRQ_TYPE_LEVEL_HIGH>;
632 gpio-controller;
633 #gpio-cells = <2>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
636 };
637
638 gpio6: gpio@20b0000 {
639 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
640 reg = <0x020b0000 0x4000>;
641 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
642 <0 77 IRQ_TYPE_LEVEL_HIGH>;
643 gpio-controller;
644 #gpio-cells = <2>;
645 interrupt-controller;
646 #interrupt-cells = <2>;
647 };
648
649 gpio7: gpio@20b4000 {
650 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
651 reg = <0x020b4000 0x4000>;
652 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
653 <0 79 IRQ_TYPE_LEVEL_HIGH>;
654 gpio-controller;
655 #gpio-cells = <2>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
658 };
659
660 kpp: keypad@20b8000 {
661 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
662 reg = <0x020b8000 0x4000>;
663 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks IMX6QDL_CLK_IPG>;
665 status = "disabled";
666 };
667
668 wdog1: watchdog@20bc000 {
669 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
670 reg = <0x020bc000 0x4000>;
671 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clks IMX6QDL_CLK_IPG>;
673 };
674
675 wdog2: watchdog@20c0000 {
676 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
677 reg = <0x020c0000 0x4000>;
678 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX6QDL_CLK_IPG>;
680 status = "disabled";
681 };
682
683 clks: clock-controller@20c4000 {
684 compatible = "fsl,imx6q-ccm";
685 reg = <0x020c4000 0x4000>;
686 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
687 <0 88 IRQ_TYPE_LEVEL_HIGH>;
688 #clock-cells = <1>;
689 };
690
691 anatop: anatop@20c8000 {
692 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
693 reg = <0x020c8000 0x1000>;
694 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
695 <0 54 IRQ_TYPE_LEVEL_HIGH>,
696 <0 127 IRQ_TYPE_LEVEL_HIGH>;
697
698 reg_vdd1p1: regulator-1p1 {
699 compatible = "fsl,anatop-regulator";
700 regulator-name = "vdd1p1";
701 regulator-min-microvolt = <1000000>;
702 regulator-max-microvolt = <1200000>;
703 regulator-always-on;
704 anatop-reg-offset = <0x110>;
705 anatop-vol-bit-shift = <8>;
706 anatop-vol-bit-width = <5>;
707 anatop-min-bit-val = <4>;
708 anatop-min-voltage = <800000>;
709 anatop-max-voltage = <1375000>;
710 anatop-enable-bit = <0>;
711 };
712
713 reg_vdd3p0: regulator-3p0 {
714 compatible = "fsl,anatop-regulator";
715 regulator-name = "vdd3p0";
716 regulator-min-microvolt = <2800000>;
717 regulator-max-microvolt = <3150000>;
718 regulator-always-on;
719 anatop-reg-offset = <0x120>;
720 anatop-vol-bit-shift = <8>;
721 anatop-vol-bit-width = <5>;
722 anatop-min-bit-val = <0>;
723 anatop-min-voltage = <2625000>;
724 anatop-max-voltage = <3400000>;
725 anatop-enable-bit = <0>;
726 };
727
728 reg_vdd2p5: regulator-2p5 {
729 compatible = "fsl,anatop-regulator";
730 regulator-name = "vdd2p5";
731 regulator-min-microvolt = <2250000>;
732 regulator-max-microvolt = <2750000>;
733 regulator-always-on;
734 anatop-reg-offset = <0x130>;
735 anatop-vol-bit-shift = <8>;
736 anatop-vol-bit-width = <5>;
737 anatop-min-bit-val = <0>;
738 anatop-min-voltage = <2100000>;
739 anatop-max-voltage = <2875000>;
740 anatop-enable-bit = <0>;
741 };
742
743 reg_arm: regulator-vddcore {
744 compatible = "fsl,anatop-regulator";
745 regulator-name = "vddarm";
746 regulator-min-microvolt = <725000>;
747 regulator-max-microvolt = <1450000>;
748 regulator-always-on;
749 anatop-reg-offset = <0x140>;
750 anatop-vol-bit-shift = <0>;
751 anatop-vol-bit-width = <5>;
752 anatop-delay-reg-offset = <0x170>;
753 anatop-delay-bit-shift = <24>;
754 anatop-delay-bit-width = <2>;
755 anatop-min-bit-val = <1>;
756 anatop-min-voltage = <725000>;
757 anatop-max-voltage = <1450000>;
758 };
759
760 reg_pu: regulator-vddpu {
761 compatible = "fsl,anatop-regulator";
762 regulator-name = "vddpu";
763 regulator-min-microvolt = <725000>;
764 regulator-max-microvolt = <1450000>;
765 regulator-enable-ramp-delay = <380>;
766 anatop-reg-offset = <0x140>;
767 anatop-vol-bit-shift = <9>;
768 anatop-vol-bit-width = <5>;
769 anatop-delay-reg-offset = <0x170>;
770 anatop-delay-bit-shift = <26>;
771 anatop-delay-bit-width = <2>;
772 anatop-min-bit-val = <1>;
773 anatop-min-voltage = <725000>;
774 anatop-max-voltage = <1450000>;
775 };
776
777 reg_soc: regulator-vddsoc {
778 compatible = "fsl,anatop-regulator";
779 regulator-name = "vddsoc";
780 regulator-min-microvolt = <725000>;
781 regulator-max-microvolt = <1450000>;
782 regulator-always-on;
783 anatop-reg-offset = <0x140>;
784 anatop-vol-bit-shift = <18>;
785 anatop-vol-bit-width = <5>;
786 anatop-delay-reg-offset = <0x170>;
787 anatop-delay-bit-shift = <28>;
788 anatop-delay-bit-width = <2>;
789 anatop-min-bit-val = <1>;
790 anatop-min-voltage = <725000>;
791 anatop-max-voltage = <1450000>;
792 };
793
794 tempmon: tempmon {
795 compatible = "fsl,imx6q-tempmon";
796 interrupt-parent = <&gpc>;
797 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
798 fsl,tempmon = <&anatop>;
799 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
800 nvmem-cell-names = "calib", "temp_grade";
801 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
802 #thermal-sensor-cells = <0>;
803 };
804 };
805
806 usbphy1: usbphy@20c9000 {
807 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
808 reg = <0x020c9000 0x1000>;
809 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
811 fsl,anatop = <&anatop>;
812 };
813
814 usbphy2: usbphy@20ca000 {
815 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
816 reg = <0x020ca000 0x1000>;
817 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
819 fsl,anatop = <&anatop>;
820 };
821
822 snvs: snvs@20cc000 {
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 reg = <0x020cc000 0x4000>;
825
826 snvs_rtc: snvs-rtc-lp {
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
828 regmap = <&snvs>;
829 offset = <0x34>;
830 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
831 <0 20 IRQ_TYPE_LEVEL_HIGH>;
832 };
833
834 snvs_poweroff: snvs-poweroff {
835 compatible = "syscon-poweroff";
836 regmap = <&snvs>;
837 offset = <0x38>;
838 value = <0x60>;
839 mask = <0x60>;
840 status = "disabled";
841 };
842
843 snvs_pwrkey: snvs-powerkey {
844 compatible = "fsl,sec-v4.0-pwrkey";
845 regmap = <&snvs>;
846 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
847 linux,keycode = <KEY_POWER>;
848 wakeup-source;
849 status = "disabled";
850 };
851
852 snvs_lpgpr: snvs-lpgpr {
853 compatible = "fsl,imx6q-snvs-lpgpr";
854 };
855 };
856
857 epit1: epit@20d0000 { /* EPIT1 */
858 reg = <0x020d0000 0x4000>;
859 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
860 };
861
862 epit2: epit@20d4000 { /* EPIT2 */
863 reg = <0x020d4000 0x4000>;
864 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
865 };
866
867 src: reset-controller@20d8000 {
868 compatible = "fsl,imx6q-src", "fsl,imx51-src";
869 reg = <0x020d8000 0x4000>;
870 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
871 <0 96 IRQ_TYPE_LEVEL_HIGH>;
872 #reset-cells = <1>;
873 };
874
875 gpc: gpc@20dc000 {
876 compatible = "fsl,imx6q-gpc";
877 reg = <0x020dc000 0x4000>;
878 interrupt-controller;
879 #interrupt-cells = <3>;
880 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
881 interrupt-parent = <&intc>;
882 clocks = <&clks IMX6QDL_CLK_IPG>;
883 clock-names = "ipg";
884
885 pgc {
886 #address-cells = <1>;
887 #size-cells = <0>;
888
889 power-domain@0 {
890 reg = <0>;
891 #power-domain-cells = <0>;
892 };
893 pd_pu: power-domain@1 {
894 reg = <1>;
895 #power-domain-cells = <0>;
896 power-supply = <®_pu>;
897 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
898 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
899 <&clks IMX6QDL_CLK_GPU2D_CORE>,
900 <&clks IMX6QDL_CLK_GPU2D_AXI>,
901 <&clks IMX6QDL_CLK_OPENVG_AXI>,
902 <&clks IMX6QDL_CLK_VPU_AXI>;
903 };
904 };
905 };
906
907 gpr: iomuxc-gpr@20e0000 {
908 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
909 reg = <0x20e0000 0x38>;
910
911 mux: mux-controller {
912 compatible = "mmio-mux";
913 #mux-control-cells = <1>;
914 };
915 };
916
917 iomuxc: pinctrl@20e0000 {
918 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
919 reg = <0x20e0000 0x4000>;
920 };
921
922 dcic1: dcic@20e4000 {
923 reg = <0x020e4000 0x4000>;
924 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
925 };
926
927 dcic2: dcic@20e8000 {
928 reg = <0x020e8000 0x4000>;
929 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
930 };
931
932 sdma: dma-controller@20ec000 {
933 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
934 reg = <0x020ec000 0x4000>;
935 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6QDL_CLK_IPG>,
937 <&clks IMX6QDL_CLK_SDMA>;
938 clock-names = "ipg", "ahb";
939 #dma-cells = <3>;
940 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
941 };
942 };
943
944 aips2: bus@2100000 { /* AIPS2 */
945 compatible = "fsl,aips-bus", "simple-bus";
946 #address-cells = <1>;
947 #size-cells = <1>;
948 reg = <0x02100000 0x100000>;
949 ranges;
950
951 crypto: crypto@2100000 {
952 compatible = "fsl,sec-v4.0";
953 #address-cells = <1>;
954 #size-cells = <1>;
955 reg = <0x2100000 0x10000>;
956 ranges = <0 0x2100000 0x10000>;
957 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
958 <&clks IMX6QDL_CLK_CAAM_ACLK>,
959 <&clks IMX6QDL_CLK_CAAM_IPG>,
960 <&clks IMX6QDL_CLK_EIM_SLOW>;
961 clock-names = "mem", "aclk", "ipg", "emi_slow";
962
963 sec_jr0: jr@1000 {
964 compatible = "fsl,sec-v4.0-job-ring";
965 reg = <0x1000 0x1000>;
966 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
967 };
968
969 sec_jr1: jr@2000 {
970 compatible = "fsl,sec-v4.0-job-ring";
971 reg = <0x2000 0x1000>;
972 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
973 };
974 };
975
976 aipstz@217c000 { /* AIPSTZ2 */
977 reg = <0x0217c000 0x4000>;
978 };
979
980 usbotg: usb@2184000 {
981 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
982 reg = <0x02184000 0x200>;
983 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX6QDL_CLK_USBOH3>;
985 fsl,usbphy = <&usbphy1>;
986 fsl,usbmisc = <&usbmisc 0>;
987 ahb-burst-config = <0x0>;
988 tx-burst-size-dword = <0x10>;
989 rx-burst-size-dword = <0x10>;
990 status = "disabled";
991 };
992
993 usbh1: usb@2184200 {
994 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
995 reg = <0x02184200 0x200>;
996 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clks IMX6QDL_CLK_USBOH3>;
998 fsl,usbphy = <&usbphy2>;
999 fsl,usbmisc = <&usbmisc 1>;
1000 dr_mode = "host";
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1004 status = "disabled";
1005 };
1006
1007 usbh2: usb@2184400 {
1008 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1009 reg = <0x02184400 0x200>;
1010 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1012 fsl,usbphy = <&usbphynop1>;
1013 phy_type = "hsic";
1014 fsl,usbmisc = <&usbmisc 2>;
1015 dr_mode = "host";
1016 ahb-burst-config = <0x0>;
1017 tx-burst-size-dword = <0x10>;
1018 rx-burst-size-dword = <0x10>;
1019 status = "disabled";
1020 };
1021
1022 usbh3: usb@2184600 {
1023 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1024 reg = <0x02184600 0x200>;
1025 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1027 fsl,usbphy = <&usbphynop2>;
1028 phy_type = "hsic";
1029 fsl,usbmisc = <&usbmisc 3>;
1030 dr_mode = "host";
1031 ahb-burst-config = <0x0>;
1032 tx-burst-size-dword = <0x10>;
1033 rx-burst-size-dword = <0x10>;
1034 status = "disabled";
1035 };
1036
1037 usbmisc: usbmisc@2184800 {
1038 #index-cells = <1>;
1039 compatible = "fsl,imx6q-usbmisc";
1040 reg = <0x02184800 0x200>;
1041 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1042 };
1043
1044 fec: ethernet@2188000 {
1045 compatible = "fsl,imx6q-fec";
1046 reg = <0x02188000 0x4000>;
1047 interrupt-names = "int0", "pps";
1048 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1049 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6QDL_CLK_ENET>,
1051 <&clks IMX6QDL_CLK_ENET>,
1052 <&clks IMX6QDL_CLK_ENET_REF>,
1053 <&clks IMX6QDL_CLK_ENET_REF>;
1054 clock-names = "ipg", "ahb", "ptp", "enet_out";
1055 fsl,stop-mode = <&gpr 0x34 27>;
1056 status = "disabled";
1057 };
1058
1059 mlb@218c000 {
1060 reg = <0x0218c000 0x4000>;
1061 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1064 };
1065
1066 usdhc1: mmc@2190000 {
1067 compatible = "fsl,imx6q-usdhc";
1068 reg = <0x02190000 0x4000>;
1069 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1071 <&clks IMX6QDL_CLK_USDHC1>,
1072 <&clks IMX6QDL_CLK_USDHC1>;
1073 clock-names = "ipg", "ahb", "per";
1074 bus-width = <4>;
1075 status = "disabled";
1076 };
1077
1078 usdhc2: mmc@2194000 {
1079 compatible = "fsl,imx6q-usdhc";
1080 reg = <0x02194000 0x4000>;
1081 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1083 <&clks IMX6QDL_CLK_USDHC2>,
1084 <&clks IMX6QDL_CLK_USDHC2>;
1085 clock-names = "ipg", "ahb", "per";
1086 bus-width = <4>;
1087 status = "disabled";
1088 };
1089
1090 usdhc3: mmc@2198000 {
1091 compatible = "fsl,imx6q-usdhc";
1092 reg = <0x02198000 0x4000>;
1093 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1095 <&clks IMX6QDL_CLK_USDHC3>,
1096 <&clks IMX6QDL_CLK_USDHC3>;
1097 clock-names = "ipg", "ahb", "per";
1098 bus-width = <4>;
1099 status = "disabled";
1100 };
1101
1102 usdhc4: mmc@219c000 {
1103 compatible = "fsl,imx6q-usdhc";
1104 reg = <0x0219c000 0x4000>;
1105 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1107 <&clks IMX6QDL_CLK_USDHC4>,
1108 <&clks IMX6QDL_CLK_USDHC4>;
1109 clock-names = "ipg", "ahb", "per";
1110 bus-width = <4>;
1111 status = "disabled";
1112 };
1113
1114 i2c1: i2c@21a0000 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1118 reg = <0x021a0000 0x4000>;
1119 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6QDL_CLK_I2C1>;
1121 status = "disabled";
1122 };
1123
1124 i2c2: i2c@21a4000 {
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1128 reg = <0x021a4000 0x4000>;
1129 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&clks IMX6QDL_CLK_I2C2>;
1131 status = "disabled";
1132 };
1133
1134 i2c3: i2c@21a8000 {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1138 reg = <0x021a8000 0x4000>;
1139 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX6QDL_CLK_I2C3>;
1141 status = "disabled";
1142 };
1143
1144 romcp@21ac000 {
1145 reg = <0x021ac000 0x4000>;
1146 };
1147
1148 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b0000 0x4000>;
1151 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1152 };
1153
1154 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1155 compatible = "fsl,imx6q-mmdc";
1156 reg = <0x021b4000 0x4000>;
1157 status = "disabled";
1158 };
1159
1160 weim: weim@21b8000 {
1161 #address-cells = <2>;
1162 #size-cells = <1>;
1163 compatible = "fsl,imx6q-weim";
1164 reg = <0x021b8000 0x4000>;
1165 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1167 fsl,weim-cs-gpr = <&gpr>;
1168 status = "disabled";
1169 };
1170
1171 ocotp: efuse@21bc000 {
1172 compatible = "fsl,imx6q-ocotp", "syscon";
1173 reg = <0x021bc000 0x4000>;
1174 clocks = <&clks IMX6QDL_CLK_IIM>;
1175 #address-cells = <1>;
1176 #size-cells = <1>;
1177
1178 cpu_speed_grade: speed-grade@10 {
1179 reg = <0x10 4>;
1180 };
1181
1182 tempmon_calib: calib@38 {
1183 reg = <0x38 4>;
1184 };
1185
1186 tempmon_temp_grade: temp-grade@20 {
1187 reg = <0x20 4>;
1188 };
1189 };
1190
1191 tzasc@21d0000 { /* TZASC1 */
1192 reg = <0x021d0000 0x4000>;
1193 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1194 };
1195
1196 tzasc@21d4000 { /* TZASC2 */
1197 reg = <0x021d4000 0x4000>;
1198 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1199 };
1200
1201 audmux: audmux@21d8000 {
1202 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1203 reg = <0x021d8000 0x4000>;
1204 status = "disabled";
1205 };
1206
1207 mipi_csi: mipi@21dc000 {
1208 compatible = "fsl,imx6-mipi-csi2";
1209 reg = <0x021dc000 0x4000>;
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 interrupts = <0 100 0x04>, <0 101 0x04>;
1213 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1214 <&clks IMX6QDL_CLK_VIDEO_27M>,
1215 <&clks IMX6QDL_CLK_EIM_PODF>;
1216 clock-names = "dphy", "ref", "pix";
1217 status = "disabled";
1218 };
1219
1220 mipi_dsi: mipi@21e0000 {
1221 reg = <0x021e0000 0x4000>;
1222 status = "disabled";
1223
1224 ports {
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227
1228 port@0 {
1229 reg = <0>;
1230
1231 mipi_mux_0: endpoint {
1232 remote-endpoint = <&ipu1_di0_mipi>;
1233 };
1234 };
1235
1236 port@1 {
1237 reg = <1>;
1238
1239 mipi_mux_1: endpoint {
1240 remote-endpoint = <&ipu1_di1_mipi>;
1241 };
1242 };
1243 };
1244 };
1245
1246 vdoa@21e4000 {
1247 compatible = "fsl,imx6q-vdoa";
1248 reg = <0x021e4000 0x4000>;
1249 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&clks IMX6QDL_CLK_VDOA>;
1251 };
1252
1253 uart2: serial@21e8000 {
1254 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1255 reg = <0x021e8000 0x4000>;
1256 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1258 <&clks IMX6QDL_CLK_UART_SERIAL>;
1259 clock-names = "ipg", "per";
1260 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1261 dma-names = "rx", "tx";
1262 status = "disabled";
1263 };
1264
1265 uart3: serial@21ec000 {
1266 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1267 reg = <0x021ec000 0x4000>;
1268 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1270 <&clks IMX6QDL_CLK_UART_SERIAL>;
1271 clock-names = "ipg", "per";
1272 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1273 dma-names = "rx", "tx";
1274 status = "disabled";
1275 };
1276
1277 uart4: serial@21f0000 {
1278 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1279 reg = <0x021f0000 0x4000>;
1280 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1282 <&clks IMX6QDL_CLK_UART_SERIAL>;
1283 clock-names = "ipg", "per";
1284 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1285 dma-names = "rx", "tx";
1286 status = "disabled";
1287 };
1288
1289 uart5: serial@21f4000 {
1290 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1291 reg = <0x021f4000 0x4000>;
1292 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1294 <&clks IMX6QDL_CLK_UART_SERIAL>;
1295 clock-names = "ipg", "per";
1296 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1297 dma-names = "rx", "tx";
1298 status = "disabled";
1299 };
1300 };
1301
1302 ipu1: ipu@2400000 {
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 compatible = "fsl,imx6q-ipu";
1306 reg = <0x02400000 0x400000>;
1307 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1308 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&clks IMX6QDL_CLK_IPU1>,
1310 <&clks IMX6QDL_CLK_IPU1_DI0>,
1311 <&clks IMX6QDL_CLK_IPU1_DI1>;
1312 clock-names = "bus", "di0", "di1";
1313 resets = <&src 2>;
1314
1315 ipu1_csi0: port@0 {
1316 reg = <0>;
1317
1318 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1319 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1320 };
1321 };
1322
1323 ipu1_csi1: port@1 {
1324 reg = <1>;
1325 };
1326
1327 ipu1_di0: port@2 {
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330 reg = <2>;
1331
1332 ipu1_di0_disp0: endpoint@0 {
1333 reg = <0>;
1334 };
1335
1336 ipu1_di0_hdmi: endpoint@1 {
1337 reg = <1>;
1338 remote-endpoint = <&hdmi_mux_0>;
1339 };
1340
1341 ipu1_di0_mipi: endpoint@2 {
1342 reg = <2>;
1343 remote-endpoint = <&mipi_mux_0>;
1344 };
1345
1346 ipu1_di0_lvds0: endpoint@3 {
1347 reg = <3>;
1348 remote-endpoint = <&lvds0_mux_0>;
1349 };
1350
1351 ipu1_di0_lvds1: endpoint@4 {
1352 reg = <4>;
1353 remote-endpoint = <&lvds1_mux_0>;
1354 };
1355 };
1356
1357 ipu1_di1: port@3 {
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360 reg = <3>;
1361
1362 ipu1_di1_disp1: endpoint@0 {
1363 reg = <0>;
1364 };
1365
1366 ipu1_di1_hdmi: endpoint@1 {
1367 reg = <1>;
1368 remote-endpoint = <&hdmi_mux_1>;
1369 };
1370
1371 ipu1_di1_mipi: endpoint@2 {
1372 reg = <2>;
1373 remote-endpoint = <&mipi_mux_1>;
1374 };
1375
1376 ipu1_di1_lvds0: endpoint@3 {
1377 reg = <3>;
1378 remote-endpoint = <&lvds0_mux_1>;
1379 };
1380
1381 ipu1_di1_lvds1: endpoint@4 {
1382 reg = <4>;
1383 remote-endpoint = <&lvds1_mux_1>;
1384 };
1385 };
1386 };
1387 };
1388};
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 /*
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
17 */
18 chosen {};
19
20 aliases {
21 ethernet0 = &fec;
22 can0 = &can1;
23 can1 = &can2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 ipu0 = &ipu1;
35 mmc0 = &usdhc1;
36 mmc1 = &usdhc2;
37 mmc2 = &usdhc3;
38 mmc3 = &usdhc4;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 spi0 = &ecspi1;
45 spi1 = &ecspi2;
46 spi2 = &ecspi3;
47 spi3 = &ecspi4;
48 usb0 = &usbotg;
49 usb1 = &usbh1;
50 usb2 = &usbh2;
51 usb3 = &usbh3;
52 usbphy0 = &usbphy1;
53 usbphy1 = &usbphy2;
54 };
55
56 clocks {
57 ckil {
58 compatible = "fsl,imx-ckil", "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 ckih1 {
64 compatible = "fsl,imx-ckih1", "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 osc {
70 compatible = "fsl,imx-osc", "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
73 };
74 };
75
76 ldb: ldb {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
80 gpr = <&gpr>;
81 status = "disabled";
82
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0>;
87 status = "disabled";
88
89 port@0 {
90 reg = <0>;
91
92 lvds0_mux_0: endpoint {
93 remote-endpoint = <&ipu1_di0_lvds0>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 lvds0_mux_1: endpoint {
101 remote-endpoint = <&ipu1_di1_lvds0>;
102 };
103 };
104 };
105
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 reg = <1>;
110 status = "disabled";
111
112 port@0 {
113 reg = <0>;
114
115 lvds1_mux_0: endpoint {
116 remote-endpoint = <&ipu1_di0_lvds1>;
117 };
118 };
119
120 port@1 {
121 reg = <1>;
122
123 lvds1_mux_1: endpoint {
124 remote-endpoint = <&ipu1_di1_lvds1>;
125 };
126 };
127 };
128 };
129
130 pmu: pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
134 };
135
136 usbphynop1: usbphynop1 {
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
139 };
140
141 usbphynop2: usbphynop2 {
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
144 };
145
146 soc {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
151 ranges;
152
153 dma_apbh: dma-apbh@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
161 #dma-cells = <1>;
162 dma-channels = <4>;
163 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
164 };
165
166 gpmi: nand-controller@112000 {
167 compatible = "fsl,imx6q-gpmi-nand";
168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
169 reg-names = "gpmi-nand", "bch";
170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "bch";
172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
173 <&clks IMX6QDL_CLK_GPMI_APB>,
174 <&clks IMX6QDL_CLK_GPMI_BCH>,
175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
176 <&clks IMX6QDL_CLK_PER1_BCH>;
177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
178 "gpmi_bch_apb", "per1_bch";
179 dmas = <&dma_apbh 0>;
180 dma-names = "rx-tx";
181 status = "disabled";
182 };
183
184 hdmi: hdmi@120000 {
185 reg = <0x00120000 0x9000>;
186 interrupts = <0 115 0x04>;
187 gpr = <&gpr>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
190 clock-names = "iahb", "isfr";
191 status = "disabled";
192
193 ports {
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 port@0 {
198 reg = <0>;
199
200 hdmi_mux_0: endpoint {
201 remote-endpoint = <&ipu1_di0_hdmi>;
202 };
203 };
204
205 port@1 {
206 reg = <1>;
207
208 hdmi_mux_1: endpoint {
209 remote-endpoint = <&ipu1_di1_hdmi>;
210 };
211 };
212 };
213 };
214
215 gpu_3d: gpu@130000 {
216 compatible = "vivante,gc";
217 reg = <0x00130000 0x4000>;
218 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
220 <&clks IMX6QDL_CLK_GPU3D_CORE>,
221 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
222 clock-names = "bus", "core", "shader";
223 power-domains = <&pd_pu>;
224 #cooling-cells = <2>;
225 };
226
227 gpu_2d: gpu@134000 {
228 compatible = "vivante,gc";
229 reg = <0x00134000 0x4000>;
230 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
232 <&clks IMX6QDL_CLK_GPU2D_CORE>;
233 clock-names = "bus", "core";
234 power-domains = <&pd_pu>;
235 #cooling-cells = <2>;
236 };
237
238 timer@a00600 {
239 compatible = "arm,cortex-a9-twd-timer";
240 reg = <0x00a00600 0x20>;
241 interrupts = <1 13 0xf01>;
242 interrupt-parent = <&intc>;
243 clocks = <&clks IMX6QDL_CLK_TWD>;
244 };
245
246 intc: interrupt-controller@a01000 {
247 compatible = "arm,cortex-a9-gic";
248 #interrupt-cells = <3>;
249 interrupt-controller;
250 reg = <0x00a01000 0x1000>,
251 <0x00a00100 0x100>;
252 interrupt-parent = <&intc>;
253 };
254
255 L2: cache-controller@a02000 {
256 compatible = "arm,pl310-cache";
257 reg = <0x00a02000 0x1000>;
258 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
259 cache-unified;
260 cache-level = <2>;
261 arm,tag-latency = <4 2 3>;
262 arm,data-latency = <4 2 3>;
263 arm,shared-override;
264 };
265
266 pcie: pcie@1ffc000 {
267 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
268 reg = <0x01ffc000 0x04000>,
269 <0x01f00000 0x80000>;
270 reg-names = "dbi", "config";
271 #address-cells = <3>;
272 #size-cells = <2>;
273 device_type = "pci";
274 bus-range = <0x00 0xff>;
275 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
276 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
277 num-lanes = <1>;
278 num-viewport = <4>;
279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "msi";
281 #interrupt-cells = <1>;
282 interrupt-map-mask = <0 0 0 0x7>;
283 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
285 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
286 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
288 <&clks IMX6QDL_CLK_LVDS1_GATE>,
289 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
290 clock-names = "pcie", "pcie_bus", "pcie_phy";
291 status = "disabled";
292 };
293
294 bus@2000000 { /* AIPS1 */
295 compatible = "fsl,aips-bus", "simple-bus";
296 #address-cells = <1>;
297 #size-cells = <1>;
298 reg = <0x02000000 0x100000>;
299 ranges;
300
301 spba-bus@2000000 {
302 compatible = "fsl,spba-bus", "simple-bus";
303 #address-cells = <1>;
304 #size-cells = <1>;
305 reg = <0x02000000 0x40000>;
306 ranges;
307
308 spdif: spdif@2004000 {
309 compatible = "fsl,imx35-spdif";
310 reg = <0x02004000 0x4000>;
311 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
312 dmas = <&sdma 14 18 0>,
313 <&sdma 15 18 0>;
314 dma-names = "rx", "tx";
315 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
316 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
317 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
318 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
319 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
320 clock-names = "core", "rxtx0",
321 "rxtx1", "rxtx2",
322 "rxtx3", "rxtx4",
323 "rxtx5", "rxtx6",
324 "rxtx7", "spba";
325 status = "disabled";
326 };
327
328 ecspi1: spi@2008000 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
332 reg = <0x02008000 0x4000>;
333 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
335 <&clks IMX6QDL_CLK_ECSPI1>;
336 clock-names = "ipg", "per";
337 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
338 dma-names = "rx", "tx";
339 status = "disabled";
340 };
341
342 ecspi2: spi@200c000 {
343 #address-cells = <1>;
344 #size-cells = <0>;
345 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
346 reg = <0x0200c000 0x4000>;
347 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
349 <&clks IMX6QDL_CLK_ECSPI2>;
350 clock-names = "ipg", "per";
351 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
352 dma-names = "rx", "tx";
353 status = "disabled";
354 };
355
356 ecspi3: spi@2010000 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
360 reg = <0x02010000 0x4000>;
361 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
363 <&clks IMX6QDL_CLK_ECSPI3>;
364 clock-names = "ipg", "per";
365 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
366 dma-names = "rx", "tx";
367 status = "disabled";
368 };
369
370 ecspi4: spi@2014000 {
371 #address-cells = <1>;
372 #size-cells = <0>;
373 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
374 reg = <0x02014000 0x4000>;
375 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
377 <&clks IMX6QDL_CLK_ECSPI4>;
378 clock-names = "ipg", "per";
379 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
380 dma-names = "rx", "tx";
381 status = "disabled";
382 };
383
384 uart1: serial@2020000 {
385 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
386 reg = <0x02020000 0x4000>;
387 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
389 <&clks IMX6QDL_CLK_UART_SERIAL>;
390 clock-names = "ipg", "per";
391 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
392 dma-names = "rx", "tx";
393 status = "disabled";
394 };
395
396 esai: esai@2024000 {
397 #sound-dai-cells = <0>;
398 compatible = "fsl,imx35-esai";
399 reg = <0x02024000 0x4000>;
400 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
402 <&clks IMX6QDL_CLK_ESAI_MEM>,
403 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
404 <&clks IMX6QDL_CLK_ESAI_IPG>,
405 <&clks IMX6QDL_CLK_SPBA>;
406 clock-names = "core", "mem", "extal", "fsys", "spba";
407 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
408 dma-names = "rx", "tx";
409 status = "disabled";
410 };
411
412 ssi1: ssi@2028000 {
413 #sound-dai-cells = <0>;
414 compatible = "fsl,imx6q-ssi",
415 "fsl,imx51-ssi";
416 reg = <0x02028000 0x4000>;
417 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
419 <&clks IMX6QDL_CLK_SSI1>;
420 clock-names = "ipg", "baud";
421 dmas = <&sdma 37 1 0>,
422 <&sdma 38 1 0>;
423 dma-names = "rx", "tx";
424 fsl,fifo-depth = <15>;
425 status = "disabled";
426 };
427
428 ssi2: ssi@202c000 {
429 #sound-dai-cells = <0>;
430 compatible = "fsl,imx6q-ssi",
431 "fsl,imx51-ssi";
432 reg = <0x0202c000 0x4000>;
433 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
435 <&clks IMX6QDL_CLK_SSI2>;
436 clock-names = "ipg", "baud";
437 dmas = <&sdma 41 1 0>,
438 <&sdma 42 1 0>;
439 dma-names = "rx", "tx";
440 fsl,fifo-depth = <15>;
441 status = "disabled";
442 };
443
444 ssi3: ssi@2030000 {
445 #sound-dai-cells = <0>;
446 compatible = "fsl,imx6q-ssi",
447 "fsl,imx51-ssi";
448 reg = <0x02030000 0x4000>;
449 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
451 <&clks IMX6QDL_CLK_SSI3>;
452 clock-names = "ipg", "baud";
453 dmas = <&sdma 45 1 0>,
454 <&sdma 46 1 0>;
455 dma-names = "rx", "tx";
456 fsl,fifo-depth = <15>;
457 status = "disabled";
458 };
459
460 asrc: asrc@2034000 {
461 compatible = "fsl,imx53-asrc";
462 reg = <0x02034000 0x4000>;
463 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
465 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
468 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
469 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
470 <&clks IMX6QDL_CLK_SPBA>;
471 clock-names = "mem", "ipg", "asrck_0",
472 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
473 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
474 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
475 "asrck_d", "asrck_e", "asrck_f", "spba";
476 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
477 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
478 dma-names = "rxa", "rxb", "rxc",
479 "txa", "txb", "txc";
480 fsl,asrc-rate = <48000>;
481 fsl,asrc-width = <16>;
482 status = "okay";
483 };
484
485 spba@203c000 {
486 reg = <0x0203c000 0x4000>;
487 };
488 };
489
490 vpu: vpu@2040000 {
491 compatible = "cnm,coda960";
492 reg = <0x02040000 0x3c000>;
493 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
494 <0 3 IRQ_TYPE_LEVEL_HIGH>;
495 interrupt-names = "bit", "jpeg";
496 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
497 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
498 clock-names = "per", "ahb";
499 power-domains = <&pd_pu>;
500 resets = <&src 1>;
501 iram = <&ocram>;
502 };
503
504 aipstz@207c000 { /* AIPSTZ1 */
505 reg = <0x0207c000 0x4000>;
506 };
507
508 pwm1: pwm@2080000 {
509 #pwm-cells = <3>;
510 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
511 reg = <0x02080000 0x4000>;
512 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clks IMX6QDL_CLK_IPG>,
514 <&clks IMX6QDL_CLK_PWM1>;
515 clock-names = "ipg", "per";
516 status = "disabled";
517 };
518
519 pwm2: pwm@2084000 {
520 #pwm-cells = <3>;
521 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
522 reg = <0x02084000 0x4000>;
523 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&clks IMX6QDL_CLK_IPG>,
525 <&clks IMX6QDL_CLK_PWM2>;
526 clock-names = "ipg", "per";
527 status = "disabled";
528 };
529
530 pwm3: pwm@2088000 {
531 #pwm-cells = <3>;
532 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
533 reg = <0x02088000 0x4000>;
534 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clks IMX6QDL_CLK_IPG>,
536 <&clks IMX6QDL_CLK_PWM3>;
537 clock-names = "ipg", "per";
538 status = "disabled";
539 };
540
541 pwm4: pwm@208c000 {
542 #pwm-cells = <3>;
543 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
544 reg = <0x0208c000 0x4000>;
545 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clks IMX6QDL_CLK_IPG>,
547 <&clks IMX6QDL_CLK_PWM4>;
548 clock-names = "ipg", "per";
549 status = "disabled";
550 };
551
552 can1: can@2090000 {
553 compatible = "fsl,imx6q-flexcan";
554 reg = <0x02090000 0x4000>;
555 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
557 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
558 clock-names = "ipg", "per";
559 fsl,stop-mode = <&gpr 0x34 28>;
560 status = "disabled";
561 };
562
563 can2: can@2094000 {
564 compatible = "fsl,imx6q-flexcan";
565 reg = <0x02094000 0x4000>;
566 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
568 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
569 clock-names = "ipg", "per";
570 fsl,stop-mode = <&gpr 0x34 29>;
571 status = "disabled";
572 };
573
574 gpt: timer@2098000 {
575 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
576 reg = <0x02098000 0x4000>;
577 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
579 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
580 <&clks IMX6QDL_CLK_GPT_3M>;
581 clock-names = "ipg", "per", "osc_per";
582 };
583
584 gpio1: gpio@209c000 {
585 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
586 reg = <0x0209c000 0x4000>;
587 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
588 <0 67 IRQ_TYPE_LEVEL_HIGH>;
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 };
594
595 gpio2: gpio@20a0000 {
596 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
597 reg = <0x020a0000 0x4000>;
598 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
599 <0 69 IRQ_TYPE_LEVEL_HIGH>;
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
604 };
605
606 gpio3: gpio@20a4000 {
607 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
608 reg = <0x020a4000 0x4000>;
609 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
610 <0 71 IRQ_TYPE_LEVEL_HIGH>;
611 gpio-controller;
612 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 };
616
617 gpio4: gpio@20a8000 {
618 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
619 reg = <0x020a8000 0x4000>;
620 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
621 <0 73 IRQ_TYPE_LEVEL_HIGH>;
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-controller;
625 #interrupt-cells = <2>;
626 };
627
628 gpio5: gpio@20ac000 {
629 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
630 reg = <0x020ac000 0x4000>;
631 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
632 <0 75 IRQ_TYPE_LEVEL_HIGH>;
633 gpio-controller;
634 #gpio-cells = <2>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 };
638
639 gpio6: gpio@20b0000 {
640 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
641 reg = <0x020b0000 0x4000>;
642 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
643 <0 77 IRQ_TYPE_LEVEL_HIGH>;
644 gpio-controller;
645 #gpio-cells = <2>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 };
649
650 gpio7: gpio@20b4000 {
651 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
652 reg = <0x020b4000 0x4000>;
653 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
654 <0 79 IRQ_TYPE_LEVEL_HIGH>;
655 gpio-controller;
656 #gpio-cells = <2>;
657 interrupt-controller;
658 #interrupt-cells = <2>;
659 };
660
661 kpp: keypad@20b8000 {
662 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
663 reg = <0x020b8000 0x4000>;
664 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clks IMX6QDL_CLK_IPG>;
666 status = "disabled";
667 };
668
669 wdog1: watchdog@20bc000 {
670 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
671 reg = <0x020bc000 0x4000>;
672 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6QDL_CLK_IPG>;
674 };
675
676 wdog2: watchdog@20c0000 {
677 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
678 reg = <0x020c0000 0x4000>;
679 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clks IMX6QDL_CLK_IPG>;
681 status = "disabled";
682 };
683
684 clks: clock-controller@20c4000 {
685 compatible = "fsl,imx6q-ccm";
686 reg = <0x020c4000 0x4000>;
687 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
688 <0 88 IRQ_TYPE_LEVEL_HIGH>;
689 #clock-cells = <1>;
690 };
691
692 anatop: anatop@20c8000 {
693 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
694 reg = <0x020c8000 0x1000>;
695 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
696 <0 54 IRQ_TYPE_LEVEL_HIGH>,
697 <0 127 IRQ_TYPE_LEVEL_HIGH>;
698
699 reg_vdd1p1: regulator-1p1 {
700 compatible = "fsl,anatop-regulator";
701 regulator-name = "vdd1p1";
702 regulator-min-microvolt = <1000000>;
703 regulator-max-microvolt = <1200000>;
704 regulator-always-on;
705 anatop-reg-offset = <0x110>;
706 anatop-vol-bit-shift = <8>;
707 anatop-vol-bit-width = <5>;
708 anatop-min-bit-val = <4>;
709 anatop-min-voltage = <800000>;
710 anatop-max-voltage = <1375000>;
711 anatop-enable-bit = <0>;
712 };
713
714 reg_vdd3p0: regulator-3p0 {
715 compatible = "fsl,anatop-regulator";
716 regulator-name = "vdd3p0";
717 regulator-min-microvolt = <2800000>;
718 regulator-max-microvolt = <3150000>;
719 regulator-always-on;
720 anatop-reg-offset = <0x120>;
721 anatop-vol-bit-shift = <8>;
722 anatop-vol-bit-width = <5>;
723 anatop-min-bit-val = <0>;
724 anatop-min-voltage = <2625000>;
725 anatop-max-voltage = <3400000>;
726 anatop-enable-bit = <0>;
727 };
728
729 reg_vdd2p5: regulator-2p5 {
730 compatible = "fsl,anatop-regulator";
731 regulator-name = "vdd2p5";
732 regulator-min-microvolt = <2250000>;
733 regulator-max-microvolt = <2750000>;
734 regulator-always-on;
735 anatop-reg-offset = <0x130>;
736 anatop-vol-bit-shift = <8>;
737 anatop-vol-bit-width = <5>;
738 anatop-min-bit-val = <0>;
739 anatop-min-voltage = <2100000>;
740 anatop-max-voltage = <2875000>;
741 anatop-enable-bit = <0>;
742 };
743
744 reg_arm: regulator-vddcore {
745 compatible = "fsl,anatop-regulator";
746 regulator-name = "vddarm";
747 regulator-min-microvolt = <725000>;
748 regulator-max-microvolt = <1450000>;
749 regulator-always-on;
750 anatop-reg-offset = <0x140>;
751 anatop-vol-bit-shift = <0>;
752 anatop-vol-bit-width = <5>;
753 anatop-delay-reg-offset = <0x170>;
754 anatop-delay-bit-shift = <24>;
755 anatop-delay-bit-width = <2>;
756 anatop-min-bit-val = <1>;
757 anatop-min-voltage = <725000>;
758 anatop-max-voltage = <1450000>;
759 };
760
761 reg_pu: regulator-vddpu {
762 compatible = "fsl,anatop-regulator";
763 regulator-name = "vddpu";
764 regulator-min-microvolt = <725000>;
765 regulator-max-microvolt = <1450000>;
766 regulator-enable-ramp-delay = <150>;
767 anatop-reg-offset = <0x140>;
768 anatop-vol-bit-shift = <9>;
769 anatop-vol-bit-width = <5>;
770 anatop-delay-reg-offset = <0x170>;
771 anatop-delay-bit-shift = <26>;
772 anatop-delay-bit-width = <2>;
773 anatop-min-bit-val = <1>;
774 anatop-min-voltage = <725000>;
775 anatop-max-voltage = <1450000>;
776 };
777
778 reg_soc: regulator-vddsoc {
779 compatible = "fsl,anatop-regulator";
780 regulator-name = "vddsoc";
781 regulator-min-microvolt = <725000>;
782 regulator-max-microvolt = <1450000>;
783 regulator-always-on;
784 anatop-reg-offset = <0x140>;
785 anatop-vol-bit-shift = <18>;
786 anatop-vol-bit-width = <5>;
787 anatop-delay-reg-offset = <0x170>;
788 anatop-delay-bit-shift = <28>;
789 anatop-delay-bit-width = <2>;
790 anatop-min-bit-val = <1>;
791 anatop-min-voltage = <725000>;
792 anatop-max-voltage = <1450000>;
793 };
794
795 tempmon: tempmon {
796 compatible = "fsl,imx6q-tempmon";
797 interrupt-parent = <&gpc>;
798 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
799 fsl,tempmon = <&anatop>;
800 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
801 nvmem-cell-names = "calib", "temp_grade";
802 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
803 #thermal-sensor-cells = <0>;
804 };
805 };
806
807 usbphy1: usbphy@20c9000 {
808 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
809 reg = <0x020c9000 0x1000>;
810 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
812 fsl,anatop = <&anatop>;
813 };
814
815 usbphy2: usbphy@20ca000 {
816 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
817 reg = <0x020ca000 0x1000>;
818 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
820 fsl,anatop = <&anatop>;
821 };
822
823 snvs: snvs@20cc000 {
824 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
825 reg = <0x020cc000 0x4000>;
826
827 snvs_rtc: snvs-rtc-lp {
828 compatible = "fsl,sec-v4.0-mon-rtc-lp";
829 regmap = <&snvs>;
830 offset = <0x34>;
831 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
832 <0 20 IRQ_TYPE_LEVEL_HIGH>;
833 };
834
835 snvs_poweroff: snvs-poweroff {
836 compatible = "syscon-poweroff";
837 regmap = <&snvs>;
838 offset = <0x38>;
839 value = <0x60>;
840 mask = <0x60>;
841 status = "disabled";
842 };
843
844 snvs_pwrkey: snvs-powerkey {
845 compatible = "fsl,sec-v4.0-pwrkey";
846 regmap = <&snvs>;
847 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
848 linux,keycode = <KEY_POWER>;
849 wakeup-source;
850 status = "disabled";
851 };
852
853 snvs_lpgpr: snvs-lpgpr {
854 compatible = "fsl,imx6q-snvs-lpgpr";
855 };
856 };
857
858 epit1: epit@20d0000 { /* EPIT1 */
859 reg = <0x020d0000 0x4000>;
860 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
861 };
862
863 epit2: epit@20d4000 { /* EPIT2 */
864 reg = <0x020d4000 0x4000>;
865 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
866 };
867
868 src: reset-controller@20d8000 {
869 compatible = "fsl,imx6q-src", "fsl,imx51-src";
870 reg = <0x020d8000 0x4000>;
871 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
872 <0 96 IRQ_TYPE_LEVEL_HIGH>;
873 #reset-cells = <1>;
874 };
875
876 gpc: gpc@20dc000 {
877 compatible = "fsl,imx6q-gpc";
878 reg = <0x020dc000 0x4000>;
879 interrupt-controller;
880 #interrupt-cells = <3>;
881 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
882 interrupt-parent = <&intc>;
883 clocks = <&clks IMX6QDL_CLK_IPG>;
884 clock-names = "ipg";
885
886 pgc {
887 #address-cells = <1>;
888 #size-cells = <0>;
889
890 power-domain@0 {
891 reg = <0>;
892 #power-domain-cells = <0>;
893 };
894 pd_pu: power-domain@1 {
895 reg = <1>;
896 #power-domain-cells = <0>;
897 power-supply = <®_pu>;
898 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
899 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
900 <&clks IMX6QDL_CLK_GPU2D_CORE>,
901 <&clks IMX6QDL_CLK_GPU2D_AXI>,
902 <&clks IMX6QDL_CLK_OPENVG_AXI>,
903 <&clks IMX6QDL_CLK_VPU_AXI>;
904 };
905 };
906 };
907
908 gpr: iomuxc-gpr@20e0000 {
909 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
910 reg = <0x20e0000 0x38>;
911
912 mux: mux-controller {
913 compatible = "mmio-mux";
914 #mux-control-cells = <1>;
915 };
916 };
917
918 iomuxc: pinctrl@20e0000 {
919 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
920 reg = <0x20e0000 0x4000>;
921 };
922
923 dcic1: dcic@20e4000 {
924 reg = <0x020e4000 0x4000>;
925 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
926 };
927
928 dcic2: dcic@20e8000 {
929 reg = <0x020e8000 0x4000>;
930 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
931 };
932
933 sdma: sdma@20ec000 {
934 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
935 reg = <0x020ec000 0x4000>;
936 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clks IMX6QDL_CLK_IPG>,
938 <&clks IMX6QDL_CLK_SDMA>;
939 clock-names = "ipg", "ahb";
940 #dma-cells = <3>;
941 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
942 };
943 };
944
945 bus@2100000 { /* AIPS2 */
946 compatible = "fsl,aips-bus", "simple-bus";
947 #address-cells = <1>;
948 #size-cells = <1>;
949 reg = <0x02100000 0x100000>;
950 ranges;
951
952 crypto: crypto@2100000 {
953 compatible = "fsl,sec-v4.0";
954 #address-cells = <1>;
955 #size-cells = <1>;
956 reg = <0x2100000 0x10000>;
957 ranges = <0 0x2100000 0x10000>;
958 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
959 <&clks IMX6QDL_CLK_CAAM_ACLK>,
960 <&clks IMX6QDL_CLK_CAAM_IPG>,
961 <&clks IMX6QDL_CLK_EIM_SLOW>;
962 clock-names = "mem", "aclk", "ipg", "emi_slow";
963
964 sec_jr0: jr@1000 {
965 compatible = "fsl,sec-v4.0-job-ring";
966 reg = <0x1000 0x1000>;
967 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
968 };
969
970 sec_jr1: jr@2000 {
971 compatible = "fsl,sec-v4.0-job-ring";
972 reg = <0x2000 0x1000>;
973 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
974 };
975 };
976
977 aipstz@217c000 { /* AIPSTZ2 */
978 reg = <0x0217c000 0x4000>;
979 };
980
981 usbotg: usb@2184000 {
982 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
983 reg = <0x02184000 0x200>;
984 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&clks IMX6QDL_CLK_USBOH3>;
986 fsl,usbphy = <&usbphy1>;
987 fsl,usbmisc = <&usbmisc 0>;
988 ahb-burst-config = <0x0>;
989 tx-burst-size-dword = <0x10>;
990 rx-burst-size-dword = <0x10>;
991 status = "disabled";
992 };
993
994 usbh1: usb@2184200 {
995 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
996 reg = <0x02184200 0x200>;
997 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6QDL_CLK_USBOH3>;
999 fsl,usbphy = <&usbphy2>;
1000 fsl,usbmisc = <&usbmisc 1>;
1001 dr_mode = "host";
1002 ahb-burst-config = <0x0>;
1003 tx-burst-size-dword = <0x10>;
1004 rx-burst-size-dword = <0x10>;
1005 status = "disabled";
1006 };
1007
1008 usbh2: usb@2184400 {
1009 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1010 reg = <0x02184400 0x200>;
1011 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1013 fsl,usbphy = <&usbphynop1>;
1014 phy_type = "hsic";
1015 fsl,usbmisc = <&usbmisc 2>;
1016 dr_mode = "host";
1017 ahb-burst-config = <0x0>;
1018 tx-burst-size-dword = <0x10>;
1019 rx-burst-size-dword = <0x10>;
1020 status = "disabled";
1021 };
1022
1023 usbh3: usb@2184600 {
1024 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1025 reg = <0x02184600 0x200>;
1026 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1028 fsl,usbphy = <&usbphynop2>;
1029 phy_type = "hsic";
1030 fsl,usbmisc = <&usbmisc 3>;
1031 dr_mode = "host";
1032 ahb-burst-config = <0x0>;
1033 tx-burst-size-dword = <0x10>;
1034 rx-burst-size-dword = <0x10>;
1035 status = "disabled";
1036 };
1037
1038 usbmisc: usbmisc@2184800 {
1039 #index-cells = <1>;
1040 compatible = "fsl,imx6q-usbmisc";
1041 reg = <0x02184800 0x200>;
1042 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1043 };
1044
1045 fec: ethernet@2188000 {
1046 compatible = "fsl,imx6q-fec";
1047 reg = <0x02188000 0x4000>;
1048 interrupt-names = "int0", "pps";
1049 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1050 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&clks IMX6QDL_CLK_ENET>,
1052 <&clks IMX6QDL_CLK_ENET>,
1053 <&clks IMX6QDL_CLK_ENET_REF>,
1054 <&clks IMX6QDL_CLK_ENET_REF>;
1055 clock-names = "ipg", "ahb", "ptp", "enet_out";
1056 fsl,stop-mode = <&gpr 0x34 27>;
1057 status = "disabled";
1058 };
1059
1060 mlb@218c000 {
1061 reg = <0x0218c000 0x4000>;
1062 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1064 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1065 };
1066
1067 usdhc1: mmc@2190000 {
1068 compatible = "fsl,imx6q-usdhc";
1069 reg = <0x02190000 0x4000>;
1070 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1072 <&clks IMX6QDL_CLK_USDHC1>,
1073 <&clks IMX6QDL_CLK_USDHC1>;
1074 clock-names = "ipg", "ahb", "per";
1075 bus-width = <4>;
1076 status = "disabled";
1077 };
1078
1079 usdhc2: mmc@2194000 {
1080 compatible = "fsl,imx6q-usdhc";
1081 reg = <0x02194000 0x4000>;
1082 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1084 <&clks IMX6QDL_CLK_USDHC2>,
1085 <&clks IMX6QDL_CLK_USDHC2>;
1086 clock-names = "ipg", "ahb", "per";
1087 bus-width = <4>;
1088 status = "disabled";
1089 };
1090
1091 usdhc3: mmc@2198000 {
1092 compatible = "fsl,imx6q-usdhc";
1093 reg = <0x02198000 0x4000>;
1094 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1096 <&clks IMX6QDL_CLK_USDHC3>,
1097 <&clks IMX6QDL_CLK_USDHC3>;
1098 clock-names = "ipg", "ahb", "per";
1099 bus-width = <4>;
1100 status = "disabled";
1101 };
1102
1103 usdhc4: mmc@219c000 {
1104 compatible = "fsl,imx6q-usdhc";
1105 reg = <0x0219c000 0x4000>;
1106 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1108 <&clks IMX6QDL_CLK_USDHC4>,
1109 <&clks IMX6QDL_CLK_USDHC4>;
1110 clock-names = "ipg", "ahb", "per";
1111 bus-width = <4>;
1112 status = "disabled";
1113 };
1114
1115 i2c1: i2c@21a0000 {
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1119 reg = <0x021a0000 0x4000>;
1120 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clks IMX6QDL_CLK_I2C1>;
1122 status = "disabled";
1123 };
1124
1125 i2c2: i2c@21a4000 {
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1129 reg = <0x021a4000 0x4000>;
1130 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&clks IMX6QDL_CLK_I2C2>;
1132 status = "disabled";
1133 };
1134
1135 i2c3: i2c@21a8000 {
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1139 reg = <0x021a8000 0x4000>;
1140 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&clks IMX6QDL_CLK_I2C3>;
1142 status = "disabled";
1143 };
1144
1145 romcp@21ac000 {
1146 reg = <0x021ac000 0x4000>;
1147 };
1148
1149 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1150 compatible = "fsl,imx6q-mmdc";
1151 reg = <0x021b0000 0x4000>;
1152 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1153 };
1154
1155 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1156 compatible = "fsl,imx6q-mmdc";
1157 reg = <0x021b4000 0x4000>;
1158 status = "disabled";
1159 };
1160
1161 weim: weim@21b8000 {
1162 #address-cells = <2>;
1163 #size-cells = <1>;
1164 compatible = "fsl,imx6q-weim";
1165 reg = <0x021b8000 0x4000>;
1166 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1167 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1168 fsl,weim-cs-gpr = <&gpr>;
1169 status = "disabled";
1170 };
1171
1172 ocotp: efuse@21bc000 {
1173 compatible = "fsl,imx6q-ocotp", "syscon";
1174 reg = <0x021bc000 0x4000>;
1175 clocks = <&clks IMX6QDL_CLK_IIM>;
1176 #address-cells = <1>;
1177 #size-cells = <1>;
1178
1179 cpu_speed_grade: speed-grade@10 {
1180 reg = <0x10 4>;
1181 };
1182
1183 tempmon_calib: calib@38 {
1184 reg = <0x38 4>;
1185 };
1186
1187 tempmon_temp_grade: temp-grade@20 {
1188 reg = <0x20 4>;
1189 };
1190 };
1191
1192 tzasc@21d0000 { /* TZASC1 */
1193 reg = <0x021d0000 0x4000>;
1194 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1195 };
1196
1197 tzasc@21d4000 { /* TZASC2 */
1198 reg = <0x021d4000 0x4000>;
1199 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1200 };
1201
1202 audmux: audmux@21d8000 {
1203 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1204 reg = <0x021d8000 0x4000>;
1205 status = "disabled";
1206 };
1207
1208 mipi_csi: mipi@21dc000 {
1209 compatible = "fsl,imx6-mipi-csi2";
1210 reg = <0x021dc000 0x4000>;
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 interrupts = <0 100 0x04>, <0 101 0x04>;
1214 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1215 <&clks IMX6QDL_CLK_VIDEO_27M>,
1216 <&clks IMX6QDL_CLK_EIM_PODF>;
1217 clock-names = "dphy", "ref", "pix";
1218 status = "disabled";
1219 };
1220
1221 mipi_dsi: mipi@21e0000 {
1222 reg = <0x021e0000 0x4000>;
1223 status = "disabled";
1224
1225 ports {
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1228
1229 port@0 {
1230 reg = <0>;
1231
1232 mipi_mux_0: endpoint {
1233 remote-endpoint = <&ipu1_di0_mipi>;
1234 };
1235 };
1236
1237 port@1 {
1238 reg = <1>;
1239
1240 mipi_mux_1: endpoint {
1241 remote-endpoint = <&ipu1_di1_mipi>;
1242 };
1243 };
1244 };
1245 };
1246
1247 vdoa@21e4000 {
1248 compatible = "fsl,imx6q-vdoa";
1249 reg = <0x021e4000 0x4000>;
1250 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&clks IMX6QDL_CLK_VDOA>;
1252 };
1253
1254 uart2: serial@21e8000 {
1255 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1256 reg = <0x021e8000 0x4000>;
1257 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1259 <&clks IMX6QDL_CLK_UART_SERIAL>;
1260 clock-names = "ipg", "per";
1261 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1262 dma-names = "rx", "tx";
1263 status = "disabled";
1264 };
1265
1266 uart3: serial@21ec000 {
1267 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1268 reg = <0x021ec000 0x4000>;
1269 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1271 <&clks IMX6QDL_CLK_UART_SERIAL>;
1272 clock-names = "ipg", "per";
1273 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1274 dma-names = "rx", "tx";
1275 status = "disabled";
1276 };
1277
1278 uart4: serial@21f0000 {
1279 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1280 reg = <0x021f0000 0x4000>;
1281 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1283 <&clks IMX6QDL_CLK_UART_SERIAL>;
1284 clock-names = "ipg", "per";
1285 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1286 dma-names = "rx", "tx";
1287 status = "disabled";
1288 };
1289
1290 uart5: serial@21f4000 {
1291 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1292 reg = <0x021f4000 0x4000>;
1293 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1295 <&clks IMX6QDL_CLK_UART_SERIAL>;
1296 clock-names = "ipg", "per";
1297 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1298 dma-names = "rx", "tx";
1299 status = "disabled";
1300 };
1301 };
1302
1303 ipu1: ipu@2400000 {
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306 compatible = "fsl,imx6q-ipu";
1307 reg = <0x02400000 0x400000>;
1308 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1309 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&clks IMX6QDL_CLK_IPU1>,
1311 <&clks IMX6QDL_CLK_IPU1_DI0>,
1312 <&clks IMX6QDL_CLK_IPU1_DI1>;
1313 clock-names = "bus", "di0", "di1";
1314 resets = <&src 2>;
1315
1316 ipu1_csi0: port@0 {
1317 reg = <0>;
1318
1319 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1320 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1321 };
1322 };
1323
1324 ipu1_csi1: port@1 {
1325 reg = <1>;
1326 };
1327
1328 ipu1_di0: port@2 {
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1331 reg = <2>;
1332
1333 ipu1_di0_disp0: endpoint@0 {
1334 reg = <0>;
1335 };
1336
1337 ipu1_di0_hdmi: endpoint@1 {
1338 reg = <1>;
1339 remote-endpoint = <&hdmi_mux_0>;
1340 };
1341
1342 ipu1_di0_mipi: endpoint@2 {
1343 reg = <2>;
1344 remote-endpoint = <&mipi_mux_0>;
1345 };
1346
1347 ipu1_di0_lvds0: endpoint@3 {
1348 reg = <3>;
1349 remote-endpoint = <&lvds0_mux_0>;
1350 };
1351
1352 ipu1_di0_lvds1: endpoint@4 {
1353 reg = <4>;
1354 remote-endpoint = <&lvds1_mux_0>;
1355 };
1356 };
1357
1358 ipu1_di1: port@3 {
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1361 reg = <3>;
1362
1363 ipu1_di1_disp1: endpoint@0 {
1364 reg = <0>;
1365 };
1366
1367 ipu1_di1_hdmi: endpoint@1 {
1368 reg = <1>;
1369 remote-endpoint = <&hdmi_mux_1>;
1370 };
1371
1372 ipu1_di1_mipi: endpoint@2 {
1373 reg = <2>;
1374 remote-endpoint = <&mipi_mux_1>;
1375 };
1376
1377 ipu1_di1_lvds0: endpoint@3 {
1378 reg = <3>;
1379 remote-endpoint = <&lvds0_mux_1>;
1380 };
1381
1382 ipu1_di1_lvds1: endpoint@4 {
1383 reg = <4>;
1384 remote-endpoint = <&lvds1_mux_1>;
1385 };
1386 };
1387 };
1388 };
1389};