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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2014-2022 Toradex
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pwm/pwm.h>
10
11/ {
12 model = "Toradex Colibri iMX6DL/S Module";
13 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
14
15 backlight: backlight {
16 compatible = "pwm-backlight";
17 brightness-levels = <0 45 63 88 119 158 203 255>;
18 default-brightness-level = <4>;
19 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_bl_on>;
22 power-supply = <®_module_3v3>;
23 pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>;
24 status = "disabled";
25 };
26
27 extcon_usbc_det: usbc-det {
28 compatible = "linux,extcon-usb-gpio";
29 id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_usbc_det>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_keys>;
38
39 wakeup {
40 debounce-interval = <10>;
41 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
42 label = "Wake-Up";
43 linux,code = <KEY_WAKEUP>;
44 wakeup-source;
45 };
46 };
47
48 lcd_display: disp0 {
49 compatible = "fsl,imx-parallel-display";
50 interface-pix-fmt = "bgr666";
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
53 status = "disabled";
54
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 port@0 {
59 reg = <0>;
60
61 lcd_display_in: endpoint {
62 remote-endpoint = <&ipu1_di0_disp0>;
63 };
64 };
65
66 port@1 {
67 reg = <1>;
68
69 lcd_display_out: endpoint {
70 remote-endpoint = <&lcd_panel_in>;
71 };
72 };
73 };
74
75 /* Will be filled by the bootloader */
76 memory@10000000 {
77 device_type = "memory";
78 reg = <0x10000000 0>;
79 };
80
81 panel_dpi: panel-dpi {
82 /*
83 * edt,et057090dhu: EDT 5.7" LCD TFT
84 * edt,et070080dh6: EDT 7.0" LCD TFT
85 */
86 compatible = "edt,et057090dhu";
87 backlight = <&backlight>;
88 status = "disabled";
89
90 port {
91 lcd_panel_in: endpoint {
92 remote-endpoint = <&lcd_display_out>;
93 };
94 };
95 };
96
97 reg_module_3v3: regulator-module-3v3 {
98 compatible = "regulator-fixed";
99 regulator-name = "+V3.3";
100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <3300000>;
102 regulator-always-on;
103 };
104
105 reg_module_3v3_audio: regulator-module-3v3-audio {
106 compatible = "regulator-fixed";
107 regulator-name = "+V3.3_AUDIO";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 regulator-always-on;
111 };
112
113 reg_usb_host_vbus: regulator-usb-host-vbus {
114 compatible = "regulator-fixed";
115 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
118 regulator-max-microvolt = <5000000>;
119 regulator-min-microvolt = <5000000>;
120 regulator-name = "usb_host_vbus";
121 status = "disabled";
122 };
123
124 sound {
125 compatible = "fsl,imx-audio-sgtl5000";
126 audio-codec = <&codec>;
127 audio-routing =
128 "Headphone Jack", "HP_OUT",
129 "LINE_IN", "Line In Jack",
130 "MIC_IN", "Mic Jack",
131 "Mic Jack", "Mic Bias";
132 model = "imx6dl-colibri-sgtl5000";
133 mux-int-port = <1>;
134 mux-ext-port = <5>;
135 ssi-controller = <&ssi1>;
136 };
137
138 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
139 sound_spdif: sound-spdif {
140 compatible = "fsl,imx-audio-spdif";
141 spdif-controller = <&spdif>;
142 spdif-in;
143 spdif-out;
144 model = "imx-spdif";
145 status = "disabled";
146 };
147};
148
149&audmux {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
152 status = "okay";
153};
154
155/* Optional on SODIMM 55/63 */
156&can1 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_flexcan1>;
159 status = "disabled";
160};
161
162/* Optional on SODIMM 178/188 */
163&can2 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_flexcan2>;
166 status = "disabled";
167};
168
169&clks {
170 fsl,pmic-stby-poweroff;
171};
172
173/* Colibri SSP */
174&ecspi4 {
175 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_ecspi4>;
178 status = "disabled";
179};
180
181&fec {
182 phy-mode = "rmii";
183 phy-handle = <ðphy>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_enet>;
186 status = "okay";
187
188 mdio {
189 #address-cells = <1>;
190 #size-cells = <0>;
191
192 ethphy: ethernet-phy@0 {
193 reg = <0>;
194 micrel,led-mode = <0>;
195 };
196 };
197};
198
199&gpio1 {
200 gpio-line-names = "",
201 "SODIMM_67",
202 "SODIMM_180",
203 "SODIMM_196",
204 "SODIMM_174",
205 "SODIMM_176",
206 "SODIMM_194",
207 "SODIMM_55",
208 "SODIMM_63",
209 "SODIMM_28",
210 "SODIMM_93",
211 "SODIMM_69",
212 "SODIMM_99",
213 "SODIMM_130",
214 "SODIMM_106",
215 "SODIMM_98",
216 "SODIMM_192",
217 "SODIMM_49",
218 "SODIMM_190",
219 "SODIMM_51",
220 "SODIMM_47",
221 "SODIMM_53",
222 "",
223 "SODIMM_22";
224};
225
226&gpio2 {
227 gpio-line-names = "SODIMM_132",
228 "SODIMM_134",
229 "SODIMM_135",
230 "SODIMM_133",
231 "SODIMM_102",
232 "SODIMM_43",
233 "SODIMM_127",
234 "SODIMM_37",
235 "SODIMM_104",
236 "SODIMM_59",
237 "SODIMM_30",
238 "SODIMM_100",
239 "SODIMM_38",
240 "SODIMM_34",
241 "SODIMM_32",
242 "SODIMM_36",
243 "SODIMM_59",
244 "SODIMM_67",
245 "SODIMM_97",
246 "SODIMM_79",
247 "SODIMM_103",
248 "SODIMM_101",
249 "SODIMM_45",
250 "SODIMM_105",
251 "SODIMM_107",
252 "SODIMM_91",
253 "SODIMM_89",
254 "SODIMM_150",
255 "SODIMM_126",
256 "SODIMM_128",
257 "",
258 "SODIMM_94";
259};
260
261&gpio3 {
262 gpio-line-names = "SODIMM_111",
263 "SODIMM_113",
264 "SODIMM_115",
265 "SODIMM_117",
266 "SODIMM_119",
267 "SODIMM_121",
268 "SODIMM_123",
269 "SODIMM_125",
270 "SODIMM_110",
271 "SODIMM_112",
272 "SODIMM_114",
273 "SODIMM_116",
274 "SODIMM_118",
275 "SODIMM_120",
276 "SODIMM_122",
277 "SODIMM_124",
278 "",
279 "SODIMM_96",
280 "SODIMM_77",
281 "SODIMM_25",
282 "SODIMM_27",
283 "SODIMM_88",
284 "SODIMM_90",
285 "SODIMM_31",
286 "SODIMM_23",
287 "SODIMM_29",
288 "SODIMM_71",
289 "SODIMM_73",
290 "SODIMM_92",
291 "SODIMM_81",
292 "SODIMM_131",
293 "SODIMM_129";
294};
295
296&gpio4 {
297 gpio-line-names = "",
298 "",
299 "",
300 "",
301 "",
302 "SODIMM_168",
303 "",
304 "",
305 "",
306 "",
307 "SODIMM_184",
308 "SODIMM_186",
309 "HDMI_15",
310 "HDMI_16",
311 "SODIMM_178",
312 "SODIMM_188",
313 "SODIMM_56",
314 "SODIMM_44",
315 "SODIMM_68",
316 "SODIMM_82",
317 "SODIMM_24",
318 "SODIMM_76",
319 "SODIMM_70",
320 "SODIMM_60",
321 "SODIMM_58",
322 "SODIMM_78",
323 "SODIMM_72",
324 "SODIMM_80",
325 "SODIMM_46",
326 "SODIMM_62",
327 "SODIMM_48",
328 "SODIMM_74";
329};
330
331&gpio5 {
332 gpio-line-names = "SODIMM_95",
333 "",
334 "SODIMM_86",
335 "",
336 "SODIMM_65",
337 "SODIMM_50",
338 "SODIMM_52",
339 "SODIMM_54",
340 "SODIMM_66",
341 "SODIMM_64",
342 "SODIMM_57",
343 "SODIMM_61",
344 "SODIMM_136",
345 "SODIMM_138",
346 "SODIMM_140",
347 "SODIMM_142",
348 "SODIMM_144",
349 "SODIMM_146",
350 "SODIMM_172",
351 "SODIMM_170",
352 "SODIMM_149",
353 "SODIMM_151",
354 "SODIMM_153",
355 "SODIMM_155",
356 "SODIMM_157",
357 "SODIMM_159",
358 "SODIMM_161",
359 "SODIMM_163",
360 "SODIMM_33",
361 "SODIMM_35",
362 "SODIMM_165",
363 "SODIMM_167";
364};
365
366&gpio6 {
367 gpio-line-names = "SODIMM_169",
368 "SODIMM_171",
369 "SODIMM_173",
370 "SODIMM_175",
371 "SODIMM_177",
372 "SODIMM_179",
373 "SODIMM_85",
374 "SODIMM_166",
375 "SODIMM_160",
376 "SODIMM_162",
377 "SODIMM_158",
378 "SODIMM_164",
379 "",
380 "",
381 "SODIMM_156",
382 "SODIMM_75",
383 "SODIMM_154",
384 "",
385 "",
386 "",
387 "",
388 "",
389 "",
390 "",
391 "",
392 "",
393 "",
394 "",
395 "",
396 "",
397 "",
398 "SODIMM_152";
399};
400
401&gpio7 {
402 gpio-line-names = "",
403 "",
404 "",
405 "",
406 "",
407 "",
408 "",
409 "",
410 "",
411 "SODIMM_19",
412 "SODIMM_21",
413 "",
414 "SODIMM_137";
415};
416
417&hdmi {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_hdmi_ddc>;
420 status = "disabled";
421};
422
423/*
424 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
425 * touch screen controller
426 */
427&i2c2 {
428 clock-frequency = <100000>;
429 pinctrl-names = "default", "gpio";
430 pinctrl-0 = <&pinctrl_i2c2>;
431 pinctrl-1 = <&pinctrl_i2c2_gpio>;
432 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
433 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
434 status = "okay";
435
436 pmic: pmic@8 {
437 compatible = "fsl,pfuze100";
438 fsl,pmic-stby-poweroff;
439 reg = <0x08>;
440
441 regulators {
442 sw1a_reg: sw1ab {
443 regulator-always-on;
444 regulator-boot-on;
445 regulator-max-microvolt = <1875000>;
446 regulator-min-microvolt = <300000>;
447 regulator-ramp-delay = <6250>;
448 };
449
450 sw1c_reg: sw1c {
451 regulator-always-on;
452 regulator-boot-on;
453 regulator-max-microvolt = <1875000>;
454 regulator-min-microvolt = <300000>;
455 regulator-ramp-delay = <6250>;
456 };
457
458 sw3a_reg: sw3a {
459 regulator-always-on;
460 regulator-boot-on;
461 regulator-max-microvolt = <1975000>;
462 regulator-min-microvolt = <400000>;
463 };
464
465 swbst_reg: swbst {
466 regulator-always-on;
467 regulator-boot-on;
468 regulator-max-microvolt = <5150000>;
469 regulator-min-microvolt = <5000000>;
470 };
471
472 snvs_reg: vsnvs {
473 regulator-always-on;
474 regulator-boot-on;
475 regulator-max-microvolt = <3000000>;
476 regulator-min-microvolt = <1000000>;
477 };
478
479 vref_reg: vrefddr {
480 regulator-always-on;
481 regulator-boot-on;
482 };
483
484 /* vgen1: unused */
485
486 vgen2_reg: vgen2 {
487 regulator-always-on;
488 regulator-boot-on;
489 regulator-max-microvolt = <1550000>;
490 regulator-min-microvolt = <800000>;
491 };
492
493 /*
494 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
495 * the i.MX 6 NVCC_SD1.
496 */
497 vgen3_reg: vgen3 {
498 regulator-always-on;
499 regulator-boot-on;
500 regulator-max-microvolt = <3300000>;
501 regulator-min-microvolt = <1800000>;
502 };
503
504 vgen4_reg: vgen4 {
505 regulator-always-on;
506 regulator-boot-on;
507 regulator-max-microvolt = <1800000>;
508 regulator-min-microvolt = <1800000>;
509 };
510
511 vgen5_reg: vgen5 {
512 regulator-always-on;
513 regulator-boot-on;
514 regulator-max-microvolt = <3300000>;
515 regulator-min-microvolt = <1800000>;
516 };
517
518 vgen6_reg: vgen6 {
519 regulator-always-on;
520 regulator-boot-on;
521 regulator-max-microvolt = <3300000>;
522 regulator-min-microvolt = <1800000>;
523 };
524 };
525 };
526
527 codec: sgtl5000@a {
528 compatible = "fsl,sgtl5000";
529 clocks = <&clks IMX6QDL_CLK_CKO>;
530 lrclk-strength = <3>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_sgtl5000>;
533 reg = <0x0a>;
534 #sound-dai-cells = <0>;
535 VDDA-supply = <®_module_3v3_audio>;
536 VDDIO-supply = <®_module_3v3>;
537 VDDD-supply = <&vgen4_reg>;
538 };
539
540 /* STMPE811 touch screen controller */
541 stmpe811@41 {
542 compatible = "st,stmpe811";
543 blocks = <0x5>;
544 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
545 interrupt-parent = <&gpio6>;
546 interrupt-controller;
547 id = <0>;
548 irq-trigger = <0x1>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_touch_int>;
551 reg = <0x41>;
552 /* 3.25 MHz ADC clock speed */
553 st,adc-freq = <1>;
554 /* 12-bit ADC */
555 st,mod-12b = <1>;
556 /* internal ADC reference */
557 st,ref-sel = <0>;
558 /* ADC converstion time: 80 clocks */
559 st,sample-time = <4>;
560
561 stmpe_ts: stmpe_touchscreen {
562 compatible = "st,stmpe-ts";
563 /* 8 sample average control */
564 st,ave-ctrl = <3>;
565 /* 7 length fractional part in z */
566 st,fraction-z = <7>;
567 /*
568 * 50 mA typical 80 mA max touchscreen drivers
569 * current limit value
570 */
571 st,i-drive = <1>;
572 /* 1 ms panel driver settling time */
573 st,settling = <3>;
574 /* 5 ms touch detect interrupt delay */
575 st,touch-det-delay = <5>;
576 status = "disabled";
577 };
578
579 stmpe_adc: stmpe_adc {
580 compatible = "st,stmpe-adc";
581 /* forbid to use ADC channels 3-0 (touch) */
582 st,norequest-mask = <0x0F>;
583 };
584 };
585};
586
587/*
588 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
589 */
590&i2c3 {
591 clock-frequency = <100000>;
592 pinctrl-names = "default", "gpio";
593 pinctrl-0 = <&pinctrl_i2c3>;
594 pinctrl-1 = <&pinctrl_i2c3_gpio>;
595 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
596 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
597 status = "disabled";
598
599 atmel_mxt_ts: touchscreen@4a {
600 compatible = "atmel,maxtouch";
601 interrupt-parent = <&gpio2>;
602 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_atmel_conn>;
605 reg = <0x4a>;
606 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */
607 status = "disabled";
608 };
609};
610
611&ipu1_di0_disp0 {
612 remote-endpoint = <&lcd_display_in>;
613};
614
615/* Colibri PWM<B> */
616&pwm1 {
617 pinctrl-names = "default";
618 pinctrl-0 = <&pinctrl_pwm1>;
619 status = "disabled";
620};
621
622/* Colibri PWM<D> */
623&pwm2 {
624 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_pwm2>;
626 status = "disabled";
627};
628
629/* Colibri PWM<A> */
630&pwm3 {
631 pinctrl-names = "default";
632 pinctrl-0 = <&pinctrl_pwm3>;
633 status = "disabled";
634};
635
636/* Colibri PWM<C> */
637&pwm4 {
638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_pwm4>;
640 status = "disabled";
641};
642
643/* Optional S/PDIF out on SODIMM 137 */
644&spdif {
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_spdif>;
647 status = "disabled";
648};
649
650&ssi1 {
651 status = "okay";
652};
653
654/* Colibri UART_A */
655&uart1 {
656 fsl,dte-mode;
657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
659 uart-has-rtscts;
660 status = "disabled";
661};
662
663/* Colibri UART_B */
664&uart2 {
665 fsl,dte-mode;
666 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_uart2_dte>;
668 uart-has-rtscts;
669 status = "disabled";
670};
671
672/* Colibri UART_C */
673&uart3 {
674 fsl,dte-mode;
675 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_uart3_dte>;
677 status = "disabled";
678};
679
680/* Colibri USBH */
681&usbh1 {
682 vbus-supply = <®_usb_host_vbus>;
683};
684
685/* Colibri USBC */
686&usbotg {
687 disable-over-current;
688 dr_mode = "otg";
689 extcon = <0>, <&extcon_usbc_det>;
690 status = "disabled";
691};
692
693/* Colibri MMC */
694&usdhc1 {
695 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
696 bus-width = <4>;
697 no-1-8-v;
698 disable-wp;
699 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
700 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
701 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
702 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
703 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>;
704 vmmc-supply = <®_module_3v3>;
705 vqmmc-supply = <&vgen3_reg>;
706 status = "disabled";
707};
708
709/* eMMC */
710&usdhc3 {
711 bus-width = <8>;
712 no-1-8-v;
713 non-removable;
714 pinctrl-names = "default";
715 pinctrl-0 = <&pinctrl_usdhc3>;
716 vqmmc-supply = <®_module_3v3>;
717 status = "okay";
718};
719
720&weim {
721 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
723 &pinctrl_weim_cs1 &pinctrl_weim_cs2
724 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
725 #address-cells = <2>;
726 #size-cells = <1>;
727 status = "disabled";
728};
729
730&iomuxc {
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_usbh_oc_1>;
733
734 /* Atmel MXT touchsceen + Capacitive Touch Adapter */
735 /* NOTE: This pin group conflicts with pin groups
736 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously.
737 */
738 pinctrl_atmel_adap: atmeladaptergrp {
739 fsl,pins = <
740 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */
741 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */
742 >;
743 };
744
745 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
746 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and
747 * pinctrl_weim_cs2. Don't use them simultaneously.
748 */
749 pinctrl_atmel_conn: atmelconnectorgrp {
750 fsl,pins = <
751 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */
752 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */
753 >;
754 };
755
756 pinctrl_audmux: audmuxgrp {
757 fsl,pins = <
758 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
759 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
760 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
761 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
762 >;
763 };
764
765 pinctrl_cam_mclk: cammclkgrp {
766 fsl,pins = <
767 /* Parallel Camera CAM sys_mclk */
768 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
769 >;
770 };
771
772 /* CSI pins used as GPIOs */
773 pinctrl_csi_gpio_1: csigpio1grp {
774 fsl,pins = <
775 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0
776 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
777 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
778 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
779 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
780 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
781 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
782 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
783 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0
784 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
785 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
786 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
787 >;
788 };
789
790 pinctrl_csi_gpio_2: csigpio2grp {
791 fsl,pins = <
792 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
793 >;
794 };
795
796 pinctrl_ecspi4: ecspi4grp {
797 fsl,pins = <
798 /* SPI CS */
799 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
800 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
801 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
802 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
803 >;
804 };
805
806 pinctrl_enet: enetgrp {
807 fsl,pins = <
808 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
809 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
810 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
811 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
812 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
813 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
814 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
815 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
816 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
817 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
818 >;
819 };
820
821 pinctrl_flexcan1: flexcan1grp {
822 fsl,pins = <
823 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
824 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
825 >;
826 };
827
828 pinctrl_flexcan2: flexcan2grp {
829 fsl,pins = <
830 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
831 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
832 >;
833 };
834
835 pinctrl_gpio_1: gpio1grp {
836 fsl,pins = <
837 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
838 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
839 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
840 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
841 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
842 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
843 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
844 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
845 >;
846 };
847 pinctrl_gpio_2: gpio2grp {
848 fsl,pins = <
849 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
850 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
851 >;
852 };
853
854 pinctrl_gpio_bl_on: gpioblongrp {
855 fsl,pins = <
856 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
857 >;
858 };
859
860 pinctrl_gpio_keys: gpiokeysgrp {
861 fsl,pins = <
862 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
863 >;
864 };
865
866 pinctrl_hdmi_ddc: hdmiddcgrp {
867 fsl,pins = <
868 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
869 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
870 >;
871 };
872
873 pinctrl_i2c2: i2c2grp {
874 fsl,pins = <
875 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
876 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
877 >;
878 };
879
880 pinctrl_i2c2_gpio: i2c2gpiogrp {
881 fsl,pins = <
882 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
883 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
884 >;
885 };
886
887 pinctrl_i2c3: i2c3grp {
888 fsl,pins = <
889 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
890 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
891 >;
892 };
893
894 pinctrl_i2c3_gpio: i2c3gpiogrp {
895 fsl,pins = <
896 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
897 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
898 >;
899 };
900
901 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
902 fsl,pins = <
903 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
904 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
905 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
906 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
907 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
908 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
909 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
910 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
911 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
912 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
913 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
914 /* Disable PWM pins on camera interface */
915 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
916 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
917 >;
918 };
919
920 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
921 fsl,pins = <
922 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
923 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
924 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
925 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
926 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
927 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
928 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
929 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
930 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
931 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
932 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
933 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
934 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
935 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
936 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
937 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
938 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
939 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
940 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
941 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
942 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
943 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
944 >;
945 };
946
947 pinctrl_lvds_transceiver: lvdstxgrp {
948 fsl,pins = <
949 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */
950 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */
951 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */
952 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */
953 >;
954 };
955
956 pinctrl_mic_gnd: micgndgrp {
957 fsl,pins = <
958 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
959 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
960 >;
961 };
962
963 pinctrl_mmc_cd: mmccdgrp {
964 fsl,pins = <
965 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
966 >;
967 };
968
969 pinctrl_mmc_cd_sleep: mmccdslpgrp {
970 fsl,pins = <
971 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0
972 >;
973 };
974
975 pinctrl_pwm1: pwm1grp {
976 fsl,pins = <
977 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
978 >;
979 };
980
981 pinctrl_pwm2: pwm2grp {
982 fsl,pins = <
983 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
984 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
985 >;
986 };
987
988 pinctrl_pwm3: pwm3grp {
989 fsl,pins = <
990 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
991 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
992 >;
993 };
994
995 pinctrl_pwm4: pwm4grp {
996 fsl,pins = <
997 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
998 >;
999 };
1000
1001 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
1002 fsl,pins = <
1003 /* SODIMM 129 / USBH_PEN */
1004 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
1005 >;
1006 };
1007
1008 pinctrl_sgtl5000: sgtl5000grp {
1009 fsl,pins = <
1010 /* SGTL5000 sys_mclk */
1011 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
1012 >;
1013 };
1014
1015 pinctrl_spdif: spdifgrp {
1016 fsl,pins = <
1017 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1018 >;
1019 };
1020
1021 pinctrl_touch_int: gpiotouchintgrp {
1022 fsl,pins = <
1023 /* STMPE811 interrupt */
1024 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
1025 >;
1026 };
1027
1028 pinctrl_uart1_dce: uart1dcegrp {
1029 fsl,pins = <
1030 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1031 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1032 >;
1033 };
1034
1035 /* DTE mode */
1036 pinctrl_uart1_dte: uart1dtegrp {
1037 fsl,pins = <
1038 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
1039 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
1040 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
1041 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
1042 >;
1043 };
1044
1045 /* Additional DTR, DSR, DCD */
1046 pinctrl_uart1_ctrl: uart1ctrlgrp {
1047 fsl,pins = <
1048 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
1049 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
1050 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
1051 >;
1052 };
1053
1054 pinctrl_uart2_dte: uart2dtegrp {
1055 fsl,pins = <
1056 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
1057 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
1058 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
1059 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
1060 >;
1061 };
1062
1063 pinctrl_uart3_dte: uart3dtegrp {
1064 fsl,pins = <
1065 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
1066 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
1067 >;
1068 };
1069
1070 pinctrl_usbc_det: usbcdetgrp {
1071 fsl,pins = <
1072 /* SODIMM 137 / USBC_DET */
1073 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
1074 /* USBC_DET_OVERWRITE */
1075 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
1076 /* USBC_DET_EN */
1077 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
1078 >;
1079 };
1080
1081 pinctrl_usbc_id_1: usbcid1grp {
1082 fsl,pins = <
1083 /* USBC_ID */
1084 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
1085 >;
1086 };
1087
1088 pinctrl_usbh_oc_1: usbhoc1grp {
1089 fsl,pins = <
1090 /* USBH_OC */
1091 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
1092 >;
1093 };
1094
1095 pinctrl_usdhc1: usdhc1grp {
1096 fsl,pins = <
1097 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
1098 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
1099 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
1100 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
1101 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
1102 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
1103 >;
1104 };
1105
1106 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1107 fsl,pins = <
1108 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
1109 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
1110 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
1111 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
1112 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
1113 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
1114 >;
1115 };
1116
1117 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1118 fsl,pins = <
1119 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
1120 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
1121 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
1122 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
1123 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
1124 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
1125 >;
1126 };
1127
1128 /* avoid backfeeding with removed card power */
1129 pinctrl_usdhc1_sleep: usdhc1sleepgrp {
1130 fsl,pins = <
1131 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
1132 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
1133 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
1134 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
1135 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
1136 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
1137 >;
1138 };
1139
1140 pinctrl_usdhc3: usdhc3grp {
1141 fsl,pins = <
1142 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1143 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1144 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1145 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1146 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1147 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1148 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1149 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1150 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1151 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1152 /* eMMC reset */
1153 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
1154 >;
1155 };
1156
1157 pinctrl_weim_cs0: weimcs0grp {
1158 fsl,pins = <
1159 /* nEXT_CS0 */
1160 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1161 >;
1162 };
1163
1164 pinctrl_weim_cs1: weimcs1grp {
1165 fsl,pins = <
1166 /* nEXT_CS1 */
1167 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
1168 >;
1169 };
1170
1171 pinctrl_weim_cs2: weimcs2grp {
1172 fsl,pins = <
1173 /* nEXT_CS2 */
1174 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
1175 >;
1176 };
1177
1178 /* ADDRESS[16:18] [25] used as GPIO */
1179 pinctrl_weim_gpio_1: weimgpio1grp {
1180 fsl,pins = <
1181 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
1182 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
1183 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
1184 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
1185 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
1186 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
1187 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1188 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
1189 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
1190 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
1191 >;
1192 };
1193
1194 /* ADDRESS[19:24] used as GPIO */
1195 pinctrl_weim_gpio_2: weimgpio2grp {
1196 fsl,pins = <
1197 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
1198 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
1199 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
1200 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
1201 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
1202 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
1203 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1204 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
1205 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
1206 >;
1207 };
1208
1209 /* DATA[16:31] used as GPIO */
1210 pinctrl_weim_gpio_3: weimgpio3grp {
1211 fsl,pins = <
1212 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
1213 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
1214 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
1215 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
1216 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
1217 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
1218 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
1219 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
1220 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
1221 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
1222 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
1223 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
1224 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
1225 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
1226 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
1227 >;
1228 };
1229
1230 /* DQM[0:3] used as GPIO */
1231 pinctrl_weim_gpio_4: weimgpio4grp {
1232 fsl,pins = <
1233 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
1234 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
1235 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
1236 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
1237 >;
1238 };
1239
1240 /* RDY used as GPIO */
1241 pinctrl_weim_gpio_5: weimgpio5grp {
1242 fsl,pins = <
1243 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
1244 >;
1245 };
1246
1247 /* ADDRESS[16] DATA[30] used as GPIO */
1248 pinctrl_weim_gpio_6: weimgpio6grp {
1249 fsl,pins = <
1250 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
1251 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
1252 >;
1253 };
1254
1255 pinctrl_weim_npwe: weimnpwegrp {
1256 fsl,pins = <
1257 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
1258 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
1259 >;
1260 };
1261
1262 pinctrl_weim_sram: weimsramgrp {
1263 fsl,pins = <
1264 /* Data */
1265 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
1266 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
1267 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
1268 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
1269 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
1270 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
1271 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
1272 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
1273 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
1274 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
1275 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
1276 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
1277 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
1278 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
1279 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
1280 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
1281 /* Address */
1282 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1283 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1284 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1285 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1286 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1287 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1288 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1289 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1290 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1291 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1292 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1293 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1294 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1295 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1296 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1297 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1298 /* Ctrl */
1299 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1300 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1301 >;
1302 };
1303
1304 pinctrl_weim_rdnwr: weimrdnwrgrp {
1305 fsl,pins = <
1306 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
1307 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
1308 >;
1309 };
1310};
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2014-2020 Toradex
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 model = "Toradex Colibri iMX6DL/S Module";
12 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
13
14 backlight: backlight {
15 compatible = "pwm-backlight";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_bl_on>;
18 pwms = <&pwm3 0 5000000>;
19 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
20 status = "disabled";
21 };
22
23 reg_module_3v3: regulator-module-3v3 {
24 compatible = "regulator-fixed";
25 regulator-name = "+V3.3";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 regulator-always-on;
29 };
30
31 reg_module_3v3_audio: regulator-module-3v3-audio {
32 compatible = "regulator-fixed";
33 regulator-name = "+V3.3_AUDIO";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 regulator-always-on;
37 };
38
39 reg_usb_host_vbus: regulator-usb-host-vbus {
40 compatible = "regulator-fixed";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
43 regulator-name = "usb_host_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
47 status = "disabled";
48 };
49
50 sound {
51 compatible = "fsl,imx-audio-sgtl5000";
52 model = "imx6dl-colibri-sgtl5000";
53 ssi-controller = <&ssi1>;
54 audio-codec = <&codec>;
55 audio-routing =
56 "Headphone Jack", "HP_OUT",
57 "LINE_IN", "Line In Jack",
58 "MIC_IN", "Mic Jack",
59 "Mic Jack", "Mic Bias";
60 mux-int-port = <1>;
61 mux-ext-port = <5>;
62 };
63
64 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
65 sound_spdif: sound-spdif {
66 compatible = "fsl,imx-audio-spdif";
67 model = "imx-spdif";
68 spdif-controller = <&spdif>;
69 spdif-in;
70 spdif-out;
71 status = "disabled";
72 };
73};
74
75&audmux {
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
78 status = "okay";
79};
80
81/* Optional on SODIMM 55/63 */
82&can1 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_flexcan1>;
85 status = "disabled";
86};
87
88/* Optional on SODIMM 178/188 */
89&can2 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_flexcan2>;
92 status = "disabled";
93};
94
95/* Colibri SSP */
96&ecspi4 {
97 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_ecspi4>;
100 status = "disabled";
101};
102
103&fec {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_enet>;
106 phy-mode = "rmii";
107 phy-handle = <ðphy>;
108 status = "okay";
109
110 mdio {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 ethphy: ethernet-phy@0 {
115 reg = <0>;
116 micrel,led-mode = <0>;
117 };
118 };
119};
120
121&hdmi {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_hdmi_ddc>;
124 status = "disabled";
125};
126
127/*
128 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
129 * touch screen controller
130 */
131&i2c2 {
132 clock-frequency = <100000>;
133 pinctrl-names = "default", "gpio";
134 pinctrl-0 = <&pinctrl_i2c2>;
135 pinctrl-0 = <&pinctrl_i2c2_gpio>;
136 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
137 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
138 status = "okay";
139
140 pmic: pfuze100@8 {
141 compatible = "fsl,pfuze100";
142 reg = <0x08>;
143
144 regulators {
145 sw1a_reg: sw1ab {
146 regulator-min-microvolt = <300000>;
147 regulator-max-microvolt = <1875000>;
148 regulator-boot-on;
149 regulator-always-on;
150 regulator-ramp-delay = <6250>;
151 };
152
153 sw1c_reg: sw1c {
154 regulator-min-microvolt = <300000>;
155 regulator-max-microvolt = <1875000>;
156 regulator-boot-on;
157 regulator-always-on;
158 regulator-ramp-delay = <6250>;
159 };
160
161 sw3a_reg: sw3a {
162 regulator-min-microvolt = <400000>;
163 regulator-max-microvolt = <1975000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 swbst_reg: swbst {
169 regulator-min-microvolt = <5000000>;
170 regulator-max-microvolt = <5150000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174
175 snvs_reg: vsnvs {
176 regulator-min-microvolt = <1000000>;
177 regulator-max-microvolt = <3000000>;
178 regulator-boot-on;
179 regulator-always-on;
180 };
181
182 vref_reg: vrefddr {
183 regulator-boot-on;
184 regulator-always-on;
185 };
186
187 /* vgen1: unused */
188
189 vgen2_reg: vgen2 {
190 regulator-min-microvolt = <800000>;
191 regulator-max-microvolt = <1550000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 /*
197 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
198 * the i.MX 6 NVCC_SD1.
199 */
200 vgen3_reg: vgen3 {
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3300000>;
203 regulator-boot-on;
204 regulator-always-on;
205 };
206
207 vgen4_reg: vgen4 {
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 vgen5_reg: vgen5 {
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <3300000>;
217 regulator-boot-on;
218 regulator-always-on;
219 };
220
221 vgen6_reg: vgen6 {
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <3300000>;
224 regulator-boot-on;
225 regulator-always-on;
226 };
227 };
228 };
229
230 codec: sgtl5000@a {
231 compatible = "fsl,sgtl5000";
232 reg = <0x0a>;
233 clocks = <&clks IMX6QDL_CLK_CKO>;
234 VDDA-supply = <®_module_3v3_audio>;
235 VDDIO-supply = <®_module_3v3>;
236 VDDD-supply = <&vgen4_reg>;
237 lrclk-strength = <3>;
238 };
239
240 /* STMPE811 touch screen controller */
241 stmpe811@41 {
242 compatible = "st,stmpe811";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_touch_int>;
245 reg = <0x41>;
246 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-parent = <&gpio6>;
248 interrupt-controller;
249 id = <0>;
250 blocks = <0x5>;
251 irq-trigger = <0x1>;
252 /* 3.25 MHz ADC clock speed */
253 st,adc-freq = <1>;
254 /* 12-bit ADC */
255 st,mod-12b = <1>;
256 /* internal ADC reference */
257 st,ref-sel = <0>;
258 /* ADC converstion time: 80 clocks */
259 st,sample-time = <4>;
260
261 stmpe_touchscreen {
262 compatible = "st,stmpe-ts";
263 /* 8 sample average control */
264 st,ave-ctrl = <3>;
265 /* 7 length fractional part in z */
266 st,fraction-z = <7>;
267 /*
268 * 50 mA typical 80 mA max touchscreen drivers
269 * current limit value
270 */
271 st,i-drive = <1>;
272 /* 1 ms panel driver settling time */
273 st,settling = <3>;
274 /* 5 ms touch detect interrupt delay */
275 st,touch-det-delay = <5>;
276 };
277
278 stmpe_adc {
279 compatible = "st,stmpe-adc";
280 /* forbid to use ADC channels 3-0 (touch) */
281 st,norequest-mask = <0x0F>;
282 };
283 };
284};
285
286/*
287 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
288 */
289&i2c3 {
290 clock-frequency = <100000>;
291 pinctrl-names = "default", "gpio";
292 pinctrl-0 = <&pinctrl_i2c3>;
293 pinctrl-1 = <&pinctrl_i2c3_gpio>;
294 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
295 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
296 status = "disabled";
297};
298
299/* Colibri PWM<B> */
300&pwm1 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_pwm1>;
303 status = "disabled";
304};
305
306/* Colibri PWM<D> */
307&pwm2 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_pwm2>;
310 status = "disabled";
311};
312
313/* Colibri PWM<A> */
314&pwm3 {
315 #pwm-cells = <2>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_pwm3>;
318 status = "disabled";
319};
320
321/* Colibri PWM<C> */
322&pwm4 {
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_pwm4>;
325 status = "disabled";
326};
327
328/* Optional S/PDIF out on SODIMM 137 */
329&spdif {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_spdif>;
332 status = "disabled";
333};
334
335&ssi1 {
336 status = "okay";
337};
338
339/* Colibri UART_A */
340&uart1 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
343 fsl,dte-mode;
344 uart-has-rtscts;
345 status = "disabled";
346};
347
348/* Colibri UART_B */
349&uart2 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_uart2_dte>;
352 fsl,dte-mode;
353 uart-has-rtscts;
354 status = "disabled";
355};
356
357/* Colibri UART_C */
358&uart3 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_uart3_dte>;
361 fsl,dte-mode;
362 status = "disabled";
363};
364
365&usbotg {
366 disable-over-current;
367 dr_mode = "peripheral";
368 status = "disabled";
369};
370
371/* Colibri MMC */
372&usdhc1 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
375 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
376 disable-wp;
377 vqmmc-supply = <®_module_3v3>;
378 bus-width = <4>;
379 no-1-8-v;
380 status = "disabled";
381};
382
383/* eMMC */
384&usdhc3 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_usdhc3>;
387 vqmmc-supply = <®_module_3v3>;
388 bus-width = <8>;
389 no-1-8-v;
390 non-removable;
391 status = "okay";
392};
393
394&weim {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
397 &pinctrl_weim_cs1 &pinctrl_weim_cs2
398 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
399 #address-cells = <2>;
400 #size-cells = <1>;
401 status = "disabled";
402};
403
404&iomuxc {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_usbh_oc_1>;
407
408 pinctrl_audmux: audmuxgrp {
409 fsl,pins = <
410 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
411 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
412 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
413 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
414 /* SGTL5000 sys_mclk */
415 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
416 >;
417 };
418
419 pinctrl_cam_mclk: cammclkgrp {
420 fsl,pins = <
421 /* Parallel Camera CAM sys_mclk */
422 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
423 >;
424 };
425
426 pinctrl_ecspi4: ecspi4grp {
427 fsl,pins = <
428 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
429 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
430 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
431 /* SPI CS */
432 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
433 >;
434 };
435
436 pinctrl_enet: enetgrp {
437 fsl,pins = <
438 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
439 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
440 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
441 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
442 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
443 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
444 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
445 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
446 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
447 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
448 >;
449 };
450
451 pinctrl_flexcan1: flexcan1grp {
452 fsl,pins = <
453 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
454 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
455 >;
456 };
457
458 pinctrl_flexcan2: flexcan2grp {
459 fsl,pins = <
460 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
461 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
462 >;
463 };
464
465 pinctrl_gpio_bl_on: gpioblon {
466 fsl,pins = <
467 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
468 >;
469 };
470
471 pinctrl_gpio_keys: gpiokeys {
472 fsl,pins = <
473 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
474 >;
475 };
476
477 pinctrl_hdmi_ddc: hdmiddcgrp {
478 fsl,pins = <
479 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
480 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
481 >;
482 };
483
484 pinctrl_i2c2: i2c2grp {
485 fsl,pins = <
486 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
487 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
488 >;
489 };
490
491 pinctrl_i2c2_gpio: i2c2grp {
492 fsl,pins = <
493 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
494 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
495 >;
496 };
497
498 pinctrl_i2c3: i2c3grp {
499 fsl,pins = <
500 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
501 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
502 >;
503 };
504
505 pinctrl_i2c3_gpio: i2c3gpiogrp {
506 fsl,pins = <
507 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
508 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
509 >;
510 };
511
512 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
513 fsl,pins = <
514 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
515 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
516 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
517 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
518 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
519 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
520 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
521 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
522 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
523 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
524 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
525 /* Disable PWM pins on camera interface */
526 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
527 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
528 >;
529 };
530
531 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
532 fsl,pins = <
533 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
534 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
535 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
536 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
537 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
538 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
539 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
540 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
541 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
542 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
543 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
544 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
545 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
546 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
547 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
548 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
549 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
550 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
551 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
552 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
553 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
554 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
555 >;
556 };
557
558 pinctrl_mic_gnd: gpiomicgnd {
559 fsl,pins = <
560 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
561 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
562 >;
563 };
564
565 pinctrl_mmc_cd: gpiommccd {
566 fsl,pins = <
567 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
568 >;
569 };
570
571 pinctrl_pwm1: pwm1grp {
572 fsl,pins = <
573 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
574 >;
575 };
576
577 pinctrl_pwm2: pwm2grp {
578 fsl,pins = <
579 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
580 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
581 >;
582 };
583
584 pinctrl_pwm3: pwm3grp {
585 fsl,pins = <
586 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
587 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
588 >;
589 };
590
591 pinctrl_pwm4: pwm4grp {
592 fsl,pins = <
593 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
594 >;
595 };
596
597 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
598 fsl,pins = <
599 /* USBH_EN */
600 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
601 >;
602 };
603
604 pinctrl_usbh_oc_1: usbhoc1grp {
605 fsl,pins = <
606 /* USBH_OC */
607 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
608 >;
609 };
610
611 pinctrl_spdif: spdifgrp {
612 fsl,pins = <
613 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
614 >;
615 };
616
617 pinctrl_touch_int: gpiotouchintgrp {
618 fsl,pins = <
619 /* STMPE811 interrupt */
620 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
621 >;
622 };
623
624 pinctrl_uart1_dce: uart1dcegrp {
625 fsl,pins = <
626 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
627 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
628 >;
629 };
630
631 /* DTE mode */
632 pinctrl_uart1_dte: uart1dtegrp {
633 fsl,pins = <
634 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
635 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
636 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
637 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
638 >;
639 };
640
641 /* Additional DTR, DSR, DCD */
642 pinctrl_uart1_ctrl: uart1ctrlgrp {
643 fsl,pins = <
644 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
645 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
646 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
647 >;
648 };
649
650 pinctrl_uart2_dte: uart2dtegrp {
651 fsl,pins = <
652 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
653 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
654 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
655 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
656 >;
657 };
658
659 pinctrl_uart3_dte: uart3dtegrp {
660 fsl,pins = <
661 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
662 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
663 >;
664 };
665
666 pinctrl_usbc_det: usbcdetgrp {
667 fsl,pins = <
668 /* USBC_DET */
669 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
670 /* USBC_DET_EN */
671 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
672 /* USBC_DET_OVERWRITE */
673 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
674 >;
675 };
676
677 pinctrl_usbc_id_1: usbc_id-1 {
678 fsl,pins = <
679 /* USBC_ID */
680 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
681 >;
682 };
683
684 pinctrl_usdhc1: usdhc1grp {
685 fsl,pins = <
686 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
687 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
688 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
689 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
690 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
691 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
692 >;
693 };
694
695 pinctrl_usdhc3: usdhc3grp {
696 fsl,pins = <
697 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
698 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
699 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
700 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
701 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
702 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
703 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
704 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
705 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
706 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
707 /* eMMC reset */
708 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
709 >;
710 };
711
712 pinctrl_weim_cs0: weimcs0grp {
713 fsl,pins = <
714 /* nEXT_CS0 */
715 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
716 >;
717 };
718
719 pinctrl_weim_cs1: weimcs1grp {
720 fsl,pins = <
721 /* nEXT_CS1 */
722 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
723 >;
724 };
725
726 pinctrl_weim_cs2: weimcs2grp {
727 fsl,pins = <
728 /* nEXT_CS2 */
729 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
730 >;
731 };
732
733 pinctrl_weim_sram: weimsramgrp {
734 fsl,pins = <
735 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
736 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
737 /* Data */
738 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
739 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
740 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
741 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
742 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
743 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
744 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
745 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
746 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
747 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
748 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
749 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
750 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
751 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
752 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
753 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
754 /* Address */
755 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
756 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
757 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
758 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
759 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
760 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
761 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
762 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
763 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
764 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
765 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
766 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
767 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
768 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
769 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
770 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
771 >;
772 };
773
774 pinctrl_weim_rdnwr: weimrdnwr {
775 fsl,pins = <
776 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
777 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
778 >;
779 };
780
781 pinctrl_weim_npwe: weimnpwe {
782 fsl,pins = <
783 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
784 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
785 >;
786 };
787
788 /* ADDRESS[16:18] [25] used as GPIO */
789 pinctrl_weim_gpio_1: weimgpio-1 {
790 fsl,pins = <
791 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
792 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
793 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
794 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
795 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
796 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
797 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
798 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
799 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
800 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
801 >;
802 };
803
804 /* ADDRESS[19:24] used as GPIO */
805 pinctrl_weim_gpio_2: weimgpio-2 {
806 fsl,pins = <
807 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
808 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
809 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
810 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
811 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
812 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
813 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
814 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
815 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
816 >;
817 };
818
819 /* DATA[16:31] used as GPIO */
820 pinctrl_weim_gpio_3: weimgpio-3 {
821 fsl,pins = <
822 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
823 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
824 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
825 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
826 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
827 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
828 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
829 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
830 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
831 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
832 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
833 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
834 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
835 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
836 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
837 >;
838 };
839
840 /* DQM[0:3] used as GPIO */
841 pinctrl_weim_gpio_4: weimgpio-4 {
842 fsl,pins = <
843 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
844 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
845 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
846 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
847 >;
848 };
849
850 /* RDY used as GPIO */
851 pinctrl_weim_gpio_5: weimgpio-5 {
852 fsl,pins = <
853 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
854 >;
855 };
856
857 /* ADDRESS[16] DATA[30] used as GPIO */
858 pinctrl_weim_gpio_6: weimgpio-6 {
859 fsl,pins = <
860 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
861 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
862 >;
863 };
864};