1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * MMC IOdelay values for TI's DRA7xx SoCs.
 4 * Copyright (C) 2018 Texas Instruments
 5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 6 */
 7
 8&dra7_pmx_core {
 9	mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
10		pinctrl-single,pins = <
11			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
12			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
13			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
14			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
15			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
16			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
17		>;
18	};
19};

 1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * MMC IOdelay values for TI's DRA7xx SoCs.
 4 * Copyright (C) 2018 Texas Instruments
 5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 6 */
 7
 8&dra7_pmx_core {
 9	mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
10		pinctrl-single,pins = <
11			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
12			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
13			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
14			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
15			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
16			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
17		>;
18	};
19};