1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 Broadcom Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/arm-gic.h>
  7#include <dt-bindings/interrupt-controller/irq.h>
  8
  9/ {
 10	compatible = "brcm,bcm63148", "brcm,bcmbca";
 11	#address-cells = <1>;
 12	#size-cells = <1>;
 13
 14	interrupt-parent = <&gic>;
 15
 16	cpus {
 17		#address-cells = <1>;
 18		#size-cells = <0>;
 19
 20		B15_0: cpu@0 {
 21			device_type = "cpu";
 22			compatible = "brcm,brahma-b15";
 23			reg = <0x0>;
 24			next-level-cache = <&L2_0>;
 25			enable-method = "psci";
 26		};
 27
 28		B15_1: cpu@1 {
 29			device_type = "cpu";
 30			compatible = "brcm,brahma-b15";
 31			reg = <0x1>;
 32			next-level-cache = <&L2_0>;
 33			enable-method = "psci";
 34		};
 35
 36		L2_0: l2-cache0 {
 37			compatible = "cache";
 38			cache-level = <2>;
 39		};
 40	};
 41
 42	timer {
 43		compatible = "arm,armv7-timer";
 44		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 45			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 46			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 47			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 48	};
 49
 50	pmu: pmu {
 51		compatible = "arm,cortex-a15-pmu";
 52		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 53			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 54		interrupt-affinity = <&B15_0>, <&B15_1>;
 55	};
 56
 57	clocks: clocks {
 58		periph_clk: periph-clk {
 59			compatible = "fixed-clock";
 60			#clock-cells = <0>;
 61			clock-frequency = <50000000>;
 62		};
 63	};
 64
 65	psci {
 66		compatible = "arm,psci-0.2";
 67		method = "smc";
 68	};
 69
 70	axi@80030000 {
 71		compatible = "simple-bus";
 72		#address-cells = <1>;
 73		#size-cells = <1>;
 74		ranges = <0 0x80030000 0x8000>;
 75
 76		gic: interrupt-controller@1000 {
 77			compatible = "arm,cortex-a15-gic";
 78			#interrupt-cells = <3>;
 79			interrupt-controller;
 80			reg = <0x1000 0x1000>,
 81				<0x2000 0x2000>,
 82				<0x4000 0x2000>,
 83				<0x6000 0x2000>;
 84			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 85					IRQ_TYPE_LEVEL_HIGH)>;
 86		};
 87	};
 88
 89	bus@ff800000 {
 90		compatible = "simple-bus";
 91		#address-cells = <1>;
 92		#size-cells = <1>;
 93		ranges = <0 0xfffe8000 0x8000>;
 94
 95		uart0: serial@600 {
 96			compatible = "brcm,bcm6345-uart";
 97			reg = <0x600 0x20>;
 98			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 99			clocks = <&periph_clk>;
100			clock-names = "refclk";
101			status = "disabled";
102		};
103	};
104};