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1// SPDX-License-Identifier: GPL-2.0+
2// Cadence XSPI flash controller driver
3// Copyright (C) 2020-21 Cadence
4
5#include <linux/completion.h>
6#include <linux/delay.h>
7#include <linux/err.h>
8#include <linux/errno.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/spi-mem.h>
20#include <linux/bitfield.h>
21#include <linux/limits.h>
22#include <linux/log2.h>
23
24#define CDNS_XSPI_MAGIC_NUM_VALUE 0x6522
25#define CDNS_XSPI_MAX_BANKS 8
26#define CDNS_XSPI_NAME "cadence-xspi"
27
28/*
29 * Note: below are additional auxiliary registers to
30 * configure XSPI controller pin-strap settings
31 */
32
33/* PHY DQ timing register */
34#define CDNS_XSPI_CCP_PHY_DQ_TIMING 0x0000
35
36/* PHY DQS timing register */
37#define CDNS_XSPI_CCP_PHY_DQS_TIMING 0x0004
38
39/* PHY gate loopback control register */
40#define CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL 0x0008
41
42/* PHY DLL slave control register */
43#define CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL 0x0010
44
45/* DLL PHY control register */
46#define CDNS_XSPI_DLL_PHY_CTRL 0x1034
47
48/* Command registers */
49#define CDNS_XSPI_CMD_REG_0 0x0000
50#define CDNS_XSPI_CMD_REG_1 0x0004
51#define CDNS_XSPI_CMD_REG_2 0x0008
52#define CDNS_XSPI_CMD_REG_3 0x000C
53#define CDNS_XSPI_CMD_REG_4 0x0010
54#define CDNS_XSPI_CMD_REG_5 0x0014
55
56/* Command status registers */
57#define CDNS_XSPI_CMD_STATUS_REG 0x0044
58
59/* Controller status register */
60#define CDNS_XSPI_CTRL_STATUS_REG 0x0100
61#define CDNS_XSPI_INIT_COMPLETED BIT(16)
62#define CDNS_XSPI_INIT_LEGACY BIT(9)
63#define CDNS_XSPI_INIT_FAIL BIT(8)
64#define CDNS_XSPI_CTRL_BUSY BIT(7)
65
66/* Controller interrupt status register */
67#define CDNS_XSPI_INTR_STATUS_REG 0x0110
68#define CDNS_XSPI_STIG_DONE BIT(23)
69#define CDNS_XSPI_SDMA_ERROR BIT(22)
70#define CDNS_XSPI_SDMA_TRIGGER BIT(21)
71#define CDNS_XSPI_CMD_IGNRD_EN BIT(20)
72#define CDNS_XSPI_DDMA_TERR_EN BIT(18)
73#define CDNS_XSPI_CDMA_TREE_EN BIT(17)
74#define CDNS_XSPI_CTRL_IDLE_EN BIT(16)
75
76#define CDNS_XSPI_TRD_COMP_INTR_STATUS 0x0120
77#define CDNS_XSPI_TRD_ERR_INTR_STATUS 0x0130
78#define CDNS_XSPI_TRD_ERR_INTR_EN 0x0134
79
80/* Controller interrupt enable register */
81#define CDNS_XSPI_INTR_ENABLE_REG 0x0114
82#define CDNS_XSPI_INTR_EN BIT(31)
83#define CDNS_XSPI_STIG_DONE_EN BIT(23)
84#define CDNS_XSPI_SDMA_ERROR_EN BIT(22)
85#define CDNS_XSPI_SDMA_TRIGGER_EN BIT(21)
86
87#define CDNS_XSPI_INTR_MASK (CDNS_XSPI_INTR_EN | \
88 CDNS_XSPI_STIG_DONE_EN | \
89 CDNS_XSPI_SDMA_ERROR_EN | \
90 CDNS_XSPI_SDMA_TRIGGER_EN)
91
92/* Controller config register */
93#define CDNS_XSPI_CTRL_CONFIG_REG 0x0230
94#define CDNS_XSPI_CTRL_WORK_MODE GENMASK(6, 5)
95
96#define CDNS_XSPI_WORK_MODE_DIRECT 0
97#define CDNS_XSPI_WORK_MODE_STIG 1
98#define CDNS_XSPI_WORK_MODE_ACMD 3
99
100/* SDMA trigger transaction registers */
101#define CDNS_XSPI_SDMA_SIZE_REG 0x0240
102#define CDNS_XSPI_SDMA_TRD_INFO_REG 0x0244
103#define CDNS_XSPI_SDMA_DIR BIT(8)
104
105/* Controller features register */
106#define CDNS_XSPI_CTRL_FEATURES_REG 0x0F04
107#define CDNS_XSPI_NUM_BANKS GENMASK(25, 24)
108#define CDNS_XSPI_DMA_DATA_WIDTH BIT(21)
109#define CDNS_XSPI_NUM_THREADS GENMASK(3, 0)
110
111/* Controller version register */
112#define CDNS_XSPI_CTRL_VERSION_REG 0x0F00
113#define CDNS_XSPI_MAGIC_NUM GENMASK(31, 16)
114#define CDNS_XSPI_CTRL_REV GENMASK(7, 0)
115
116/* STIG Profile 1.0 instruction fields (split into registers) */
117#define CDNS_XSPI_CMD_INSTR_TYPE GENMASK(6, 0)
118#define CDNS_XSPI_CMD_P1_R1_ADDR0 GENMASK(31, 24)
119#define CDNS_XSPI_CMD_P1_R2_ADDR1 GENMASK(7, 0)
120#define CDNS_XSPI_CMD_P1_R2_ADDR2 GENMASK(15, 8)
121#define CDNS_XSPI_CMD_P1_R2_ADDR3 GENMASK(23, 16)
122#define CDNS_XSPI_CMD_P1_R2_ADDR4 GENMASK(31, 24)
123#define CDNS_XSPI_CMD_P1_R3_ADDR5 GENMASK(7, 0)
124#define CDNS_XSPI_CMD_P1_R3_CMD GENMASK(23, 16)
125#define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES GENMASK(30, 28)
126#define CDNS_XSPI_CMD_P1_R4_ADDR_IOS GENMASK(1, 0)
127#define CDNS_XSPI_CMD_P1_R4_CMD_IOS GENMASK(9, 8)
128#define CDNS_XSPI_CMD_P1_R4_BANK GENMASK(14, 12)
129
130/* STIG data sequence instruction fields (split into registers) */
131#define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L GENMASK(31, 16)
132#define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H GENMASK(15, 0)
133#define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY GENMASK(25, 20)
134#define CDNS_XSPI_CMD_DSEQ_R4_BANK GENMASK(14, 12)
135#define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS GENMASK(9, 8)
136#define CDNS_XSPI_CMD_DSEQ_R4_DIR BIT(4)
137
138/* STIG command status fields */
139#define CDNS_XSPI_CMD_STATUS_COMPLETED BIT(15)
140#define CDNS_XSPI_CMD_STATUS_FAILED BIT(14)
141#define CDNS_XSPI_CMD_STATUS_DQS_ERROR BIT(3)
142#define CDNS_XSPI_CMD_STATUS_CRC_ERROR BIT(2)
143#define CDNS_XSPI_CMD_STATUS_BUS_ERROR BIT(1)
144#define CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR BIT(0)
145
146#define CDNS_XSPI_STIG_DONE_FLAG BIT(0)
147#define CDNS_XSPI_TRD_STATUS 0x0104
148
149/* Helper macros for filling command registers */
150#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \
151 FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \
152 CDNS_XSPI_STIG_INSTR_TYPE_1 : CDNS_XSPI_STIG_INSTR_TYPE_0) | \
153 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
154
155#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op) ( \
156 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
157 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \
158 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
159 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF))
160
161#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op) ( \
162 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \
163 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \
164 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes))
165
166#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \
167 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_ADDR_IOS, ilog2((op)->addr.buswidth)) | \
168 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_CMD_IOS, ilog2((op)->cmd.buswidth)) | \
169 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_BANK, chipsel))
170
171#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op) \
172 FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ)
173
174#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \
175 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF)
176
177#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \
178 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \
179 ((op)->data.nbytes >> 16) & 0xffff) | \
180 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \
181 (op)->dummy.buswidth != 0 ? \
182 (((op)->dummy.nbytes * 8) / (op)->dummy.buswidth) : \
183 0))
184
185#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \
186 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \
187 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS, \
188 ilog2((op)->data.buswidth)) | \
189 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DIR, \
190 ((op)->data.dir == SPI_MEM_DATA_IN) ? \
191 CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
192
193enum cdns_xspi_stig_instr_type {
194 CDNS_XSPI_STIG_INSTR_TYPE_0,
195 CDNS_XSPI_STIG_INSTR_TYPE_1,
196 CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ = 127,
197};
198
199enum cdns_xspi_sdma_dir {
200 CDNS_XSPI_SDMA_DIR_READ,
201 CDNS_XSPI_SDMA_DIR_WRITE,
202};
203
204enum cdns_xspi_stig_cmd_dir {
205 CDNS_XSPI_STIG_CMD_DIR_READ,
206 CDNS_XSPI_STIG_CMD_DIR_WRITE,
207};
208
209struct cdns_xspi_dev {
210 struct platform_device *pdev;
211 struct device *dev;
212
213 void __iomem *iobase;
214 void __iomem *auxbase;
215 void __iomem *sdmabase;
216
217 int irq;
218 int cur_cs;
219 unsigned int sdmasize;
220
221 struct completion cmd_complete;
222 struct completion auto_cmd_complete;
223 struct completion sdma_complete;
224 bool sdma_error;
225
226 void *in_buffer;
227 const void *out_buffer;
228
229 u8 hw_num_banks;
230};
231
232static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
233{
234 u32 ctrl_stat;
235
236 return readl_relaxed_poll_timeout(cdns_xspi->iobase +
237 CDNS_XSPI_CTRL_STATUS_REG,
238 ctrl_stat,
239 ((ctrl_stat &
240 CDNS_XSPI_CTRL_BUSY) == 0),
241 100, 1000);
242}
243
244static void cdns_xspi_trigger_command(struct cdns_xspi_dev *cdns_xspi,
245 u32 cmd_regs[6])
246{
247 writel(cmd_regs[5], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_5);
248 writel(cmd_regs[4], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_4);
249 writel(cmd_regs[3], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_3);
250 writel(cmd_regs[2], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_2);
251 writel(cmd_regs[1], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_1);
252 writel(cmd_regs[0], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_0);
253}
254
255static int cdns_xspi_check_command_status(struct cdns_xspi_dev *cdns_xspi)
256{
257 int ret = 0;
258 u32 cmd_status = readl(cdns_xspi->iobase + CDNS_XSPI_CMD_STATUS_REG);
259
260 if (cmd_status & CDNS_XSPI_CMD_STATUS_COMPLETED) {
261 if ((cmd_status & CDNS_XSPI_CMD_STATUS_FAILED) != 0) {
262 if (cmd_status & CDNS_XSPI_CMD_STATUS_DQS_ERROR) {
263 dev_err(cdns_xspi->dev,
264 "Incorrect DQS pulses detected\n");
265 ret = -EPROTO;
266 }
267 if (cmd_status & CDNS_XSPI_CMD_STATUS_CRC_ERROR) {
268 dev_err(cdns_xspi->dev,
269 "CRC error received\n");
270 ret = -EPROTO;
271 }
272 if (cmd_status & CDNS_XSPI_CMD_STATUS_BUS_ERROR) {
273 dev_err(cdns_xspi->dev,
274 "Error resp on system DMA interface\n");
275 ret = -EPROTO;
276 }
277 if (cmd_status & CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR) {
278 dev_err(cdns_xspi->dev,
279 "Invalid command sequence detected\n");
280 ret = -EPROTO;
281 }
282 }
283 } else {
284 dev_err(cdns_xspi->dev, "Fatal err - command not completed\n");
285 ret = -EPROTO;
286 }
287
288 return ret;
289}
290
291static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
292 bool enabled)
293{
294 u32 intr_enable;
295
296 intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
297 if (enabled)
298 intr_enable |= CDNS_XSPI_INTR_MASK;
299 else
300 intr_enable &= ~CDNS_XSPI_INTR_MASK;
301 writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
302}
303
304static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
305{
306 u32 ctrl_ver;
307 u32 ctrl_features;
308 u16 hw_magic_num;
309
310 ctrl_ver = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_VERSION_REG);
311 hw_magic_num = FIELD_GET(CDNS_XSPI_MAGIC_NUM, ctrl_ver);
312 if (hw_magic_num != CDNS_XSPI_MAGIC_NUM_VALUE) {
313 dev_err(cdns_xspi->dev,
314 "Incorrect XSPI magic number: %x, expected: %x\n",
315 hw_magic_num, CDNS_XSPI_MAGIC_NUM_VALUE);
316 return -EIO;
317 }
318
319 ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
320 cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
321 cdns_xspi_set_interrupts(cdns_xspi, false);
322
323 return 0;
324}
325
326static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
327{
328 u32 sdma_size, sdma_trd_info;
329 u8 sdma_dir;
330
331 sdma_size = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG);
332 sdma_trd_info = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG);
333 sdma_dir = FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info);
334
335 switch (sdma_dir) {
336 case CDNS_XSPI_SDMA_DIR_READ:
337 ioread8_rep(cdns_xspi->sdmabase,
338 cdns_xspi->in_buffer, sdma_size);
339 break;
340
341 case CDNS_XSPI_SDMA_DIR_WRITE:
342 iowrite8_rep(cdns_xspi->sdmabase,
343 cdns_xspi->out_buffer, sdma_size);
344 break;
345 }
346}
347
348static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi,
349 const struct spi_mem_op *op,
350 bool data_phase)
351{
352 u32 cmd_regs[6];
353 u32 cmd_status;
354 int ret;
355
356 ret = cdns_xspi_wait_for_controller_idle(cdns_xspi);
357 if (ret < 0)
358 return -EIO;
359
360 writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
361 cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
362
363 cdns_xspi_set_interrupts(cdns_xspi, true);
364 cdns_xspi->sdma_error = false;
365
366 memset(cmd_regs, 0, sizeof(cmd_regs));
367 cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase);
368 cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op);
369 cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op);
370 cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op,
371 cdns_xspi->cur_cs);
372
373 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
374
375 if (data_phase) {
376 cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG;
377 cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op);
378 cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op);
379 cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op);
380 cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op,
381 cdns_xspi->cur_cs);
382
383 cdns_xspi->in_buffer = op->data.buf.in;
384 cdns_xspi->out_buffer = op->data.buf.out;
385
386 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
387
388 wait_for_completion(&cdns_xspi->sdma_complete);
389 if (cdns_xspi->sdma_error) {
390 cdns_xspi_set_interrupts(cdns_xspi, false);
391 return -EIO;
392 }
393 cdns_xspi_sdma_handle(cdns_xspi);
394 }
395
396 wait_for_completion(&cdns_xspi->cmd_complete);
397 cdns_xspi_set_interrupts(cdns_xspi, false);
398
399 cmd_status = cdns_xspi_check_command_status(cdns_xspi);
400 if (cmd_status)
401 return -EPROTO;
402
403 return 0;
404}
405
406static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
407 struct spi_mem *mem,
408 const struct spi_mem_op *op)
409{
410 enum spi_mem_data_dir dir = op->data.dir;
411
412 if (cdns_xspi->cur_cs != mem->spi->chip_select)
413 cdns_xspi->cur_cs = mem->spi->chip_select;
414
415 return cdns_xspi_send_stig_command(cdns_xspi, op,
416 (dir != SPI_MEM_NO_DATA));
417}
418
419static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
420 const struct spi_mem_op *op)
421{
422 struct cdns_xspi_dev *cdns_xspi =
423 spi_master_get_devdata(mem->spi->master);
424 int ret = 0;
425
426 ret = cdns_xspi_mem_op(cdns_xspi, mem, op);
427
428 return ret;
429}
430
431static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
432{
433 struct cdns_xspi_dev *cdns_xspi =
434 spi_master_get_devdata(mem->spi->master);
435
436 op->data.nbytes = clamp_val(op->data.nbytes, 0, cdns_xspi->sdmasize);
437
438 return 0;
439}
440
441static const struct spi_controller_mem_ops cadence_xspi_mem_ops = {
442 .exec_op = cdns_xspi_mem_op_execute,
443 .adjust_op_size = cdns_xspi_adjust_mem_op_size,
444};
445
446static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
447{
448 struct cdns_xspi_dev *cdns_xspi = dev;
449 u32 irq_status;
450 irqreturn_t result = IRQ_NONE;
451
452 irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
453 writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
454
455 if (irq_status &
456 (CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER |
457 CDNS_XSPI_STIG_DONE)) {
458 if (irq_status & CDNS_XSPI_SDMA_ERROR) {
459 dev_err(cdns_xspi->dev,
460 "Slave DMA transaction error\n");
461 cdns_xspi->sdma_error = true;
462 complete(&cdns_xspi->sdma_complete);
463 }
464
465 if (irq_status & CDNS_XSPI_SDMA_TRIGGER)
466 complete(&cdns_xspi->sdma_complete);
467
468 if (irq_status & CDNS_XSPI_STIG_DONE)
469 complete(&cdns_xspi->cmd_complete);
470
471 result = IRQ_HANDLED;
472 }
473
474 irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS);
475 if (irq_status) {
476 writel(irq_status,
477 cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS);
478
479 complete(&cdns_xspi->auto_cmd_complete);
480
481 result = IRQ_HANDLED;
482 }
483
484 return result;
485}
486
487static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
488{
489 struct device_node *node_prop = pdev->dev.of_node;
490 struct device_node *node_child;
491 unsigned int cs;
492
493 for_each_child_of_node(node_prop, node_child) {
494 if (!of_device_is_available(node_child))
495 continue;
496
497 if (of_property_read_u32(node_child, "reg", &cs)) {
498 dev_err(&pdev->dev, "Couldn't get memory chip select\n");
499 of_node_put(node_child);
500 return -ENXIO;
501 } else if (cs >= CDNS_XSPI_MAX_BANKS) {
502 dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
503 of_node_put(node_child);
504 return -ENXIO;
505 }
506 }
507
508 return 0;
509}
510
511static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
512{
513 struct device *dev = cdns_xspi->dev;
514
515 dev_info(dev, "PHY configuration\n");
516 dev_info(dev, " * xspi_dll_phy_ctrl: %08x\n",
517 readl(cdns_xspi->iobase + CDNS_XSPI_DLL_PHY_CTRL));
518 dev_info(dev, " * phy_dq_timing: %08x\n",
519 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQ_TIMING));
520 dev_info(dev, " * phy_dqs_timing: %08x\n",
521 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQS_TIMING));
522 dev_info(dev, " * phy_gate_loopback_ctrl: %08x\n",
523 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL));
524 dev_info(dev, " * phy_dll_slave_ctrl: %08x\n",
525 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL));
526}
527
528static int cdns_xspi_probe(struct platform_device *pdev)
529{
530 struct device *dev = &pdev->dev;
531 struct spi_master *master = NULL;
532 struct cdns_xspi_dev *cdns_xspi = NULL;
533 struct resource *res;
534 int ret;
535
536 master = devm_spi_alloc_master(dev, sizeof(*cdns_xspi));
537 if (!master)
538 return -ENOMEM;
539
540 master->mode_bits = SPI_3WIRE | SPI_TX_DUAL | SPI_TX_QUAD |
541 SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
542 SPI_MODE_0 | SPI_MODE_3;
543
544 master->mem_ops = &cadence_xspi_mem_ops;
545 master->dev.of_node = pdev->dev.of_node;
546 master->bus_num = -1;
547
548 platform_set_drvdata(pdev, master);
549
550 cdns_xspi = spi_master_get_devdata(master);
551 cdns_xspi->pdev = pdev;
552 cdns_xspi->dev = &pdev->dev;
553 cdns_xspi->cur_cs = 0;
554
555 init_completion(&cdns_xspi->cmd_complete);
556 init_completion(&cdns_xspi->auto_cmd_complete);
557 init_completion(&cdns_xspi->sdma_complete);
558
559 ret = cdns_xspi_of_get_plat_data(pdev);
560 if (ret)
561 return -ENODEV;
562
563 cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io");
564 if (IS_ERR(cdns_xspi->iobase)) {
565 dev_err(dev, "Failed to remap controller base address\n");
566 return PTR_ERR(cdns_xspi->iobase);
567 }
568
569 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
570 cdns_xspi->sdmabase = devm_ioremap_resource(dev, res);
571 if (IS_ERR(cdns_xspi->sdmabase))
572 return PTR_ERR(cdns_xspi->sdmabase);
573 cdns_xspi->sdmasize = resource_size(res);
574
575 cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux");
576 if (IS_ERR(cdns_xspi->auxbase)) {
577 dev_err(dev, "Failed to remap AUX address\n");
578 return PTR_ERR(cdns_xspi->auxbase);
579 }
580
581 cdns_xspi->irq = platform_get_irq(pdev, 0);
582 if (cdns_xspi->irq < 0)
583 return -ENXIO;
584
585 ret = devm_request_irq(dev, cdns_xspi->irq, cdns_xspi_irq_handler,
586 IRQF_SHARED, pdev->name, cdns_xspi);
587 if (ret) {
588 dev_err(dev, "Failed to request IRQ: %d\n", cdns_xspi->irq);
589 return ret;
590 }
591
592 cdns_xspi_print_phy_config(cdns_xspi);
593
594 ret = cdns_xspi_controller_init(cdns_xspi);
595 if (ret) {
596 dev_err(dev, "Failed to initialize controller\n");
597 return ret;
598 }
599
600 master->num_chipselect = 1 << cdns_xspi->hw_num_banks;
601
602 ret = devm_spi_register_master(dev, master);
603 if (ret) {
604 dev_err(dev, "Failed to register SPI master\n");
605 return ret;
606 }
607
608 dev_info(dev, "Successfully registered SPI master\n");
609
610 return 0;
611}
612
613static const struct of_device_id cdns_xspi_of_match[] = {
614 {
615 .compatible = "cdns,xspi-nor",
616 },
617 { /* end of table */}
618};
619MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
620
621static struct platform_driver cdns_xspi_platform_driver = {
622 .probe = cdns_xspi_probe,
623 .remove = NULL,
624 .driver = {
625 .name = CDNS_XSPI_NAME,
626 .of_match_table = cdns_xspi_of_match,
627 },
628};
629
630module_platform_driver(cdns_xspi_platform_driver);
631
632MODULE_DESCRIPTION("Cadence XSPI Controller Driver");
633MODULE_LICENSE("GPL v2");
634MODULE_ALIAS("platform:" CDNS_XSPI_NAME);
635MODULE_AUTHOR("Konrad Kociolek <konrad@cadence.com>");
636MODULE_AUTHOR("Jayshri Pawar <jpawar@cadence.com>");
637MODULE_AUTHOR("Parshuram Thombare <pthombar@cadence.com>");