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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include "phy-mtk-mipi-dsi.h"
7
8inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
9{
10 return container_of(hw, struct mtk_mipi_tx, pll_hw);
11}
12
13int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
14 unsigned long parent_rate)
15{
16 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
17
18 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
19
20 mipi_tx->data_rate = rate;
21
22 return 0;
23}
24
25unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
26 unsigned long parent_rate)
27{
28 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
29
30 return mipi_tx->data_rate;
31}
32
33static int mtk_mipi_tx_power_on(struct phy *phy)
34{
35 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
36 int ret;
37
38 /* Power up core and enable PLL */
39 ret = clk_prepare_enable(mipi_tx->pll);
40 if (ret < 0)
41 return ret;
42
43 /* Enable DSI Lane LDO outputs, disable pad tie low */
44 mipi_tx->driver_data->mipi_tx_enable_signal(phy);
45 return 0;
46}
47
48static int mtk_mipi_tx_power_off(struct phy *phy)
49{
50 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
51
52 /* Enable pad tie low, disable DSI Lane LDO outputs */
53 mipi_tx->driver_data->mipi_tx_disable_signal(phy);
54
55 /* Disable PLL and power down core */
56 clk_disable_unprepare(mipi_tx->pll);
57
58 return 0;
59}
60
61static const struct phy_ops mtk_mipi_tx_ops = {
62 .power_on = mtk_mipi_tx_power_on,
63 .power_off = mtk_mipi_tx_power_off,
64 .owner = THIS_MODULE,
65};
66
67static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
68{
69 struct nvmem_cell *cell;
70 size_t len;
71 u32 *buf;
72
73 cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
74 if (IS_ERR(cell)) {
75 dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
76 return;
77 }
78 buf = (u32 *)nvmem_cell_read(cell, &len);
79 nvmem_cell_put(cell);
80
81 if (IS_ERR(buf)) {
82 dev_info(mipi_tx->dev, "can't get data, ignore it\n");
83 return;
84 }
85
86 if (len < 3 * sizeof(u32)) {
87 dev_info(mipi_tx->dev, "invalid calibration data\n");
88 kfree(buf);
89 return;
90 }
91
92 mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
93 (buf[0] >> 11 & 0x1f);
94 mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
95 (buf[0] >> 1 & 0x1f);
96 mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
97 (buf[1] >> 22 & 0x1f);
98 mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
99 (buf[1] >> 12 & 0x1f);
100 mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
101 (buf[1] >> 2 & 0x1f);
102 kfree(buf);
103}
104
105static int mtk_mipi_tx_probe(struct platform_device *pdev)
106{
107 struct device *dev = &pdev->dev;
108 struct mtk_mipi_tx *mipi_tx;
109 const char *ref_clk_name;
110 struct clk *ref_clk;
111 struct clk_init_data clk_init = {
112 .num_parents = 1,
113 .parent_names = (const char * const *)&ref_clk_name,
114 .flags = CLK_SET_RATE_GATE,
115 };
116 struct phy *phy;
117 struct phy_provider *phy_provider;
118 int ret;
119
120 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
121 if (!mipi_tx)
122 return -ENOMEM;
123
124 mipi_tx->driver_data = of_device_get_match_data(dev);
125 if (!mipi_tx->driver_data)
126 return -ENODEV;
127
128 mipi_tx->regs = devm_platform_ioremap_resource(pdev, 0);
129 if (IS_ERR(mipi_tx->regs))
130 return PTR_ERR(mipi_tx->regs);
131
132 ref_clk = devm_clk_get(dev, NULL);
133 if (IS_ERR(ref_clk))
134 return dev_err_probe(dev, PTR_ERR(ref_clk),
135 "Failed to get reference clock\n");
136
137 ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
138 &mipi_tx->mipitx_drive);
139 /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
140 if (ret < 0)
141 mipi_tx->mipitx_drive = 4600;
142
143 /* check the mipitx_drive valid */
144 if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
145 dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
146 mipi_tx->mipitx_drive);
147 mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
148 6000);
149 }
150
151 ref_clk_name = __clk_get_name(ref_clk);
152
153 ret = of_property_read_string(dev->of_node, "clock-output-names",
154 &clk_init.name);
155 if (ret < 0)
156 return dev_err_probe(dev, ret, "Failed to read clock-output-names\n");
157
158 clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
159
160 mipi_tx->pll_hw.init = &clk_init;
161 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
162 if (IS_ERR(mipi_tx->pll))
163 return dev_err_probe(dev, PTR_ERR(mipi_tx->pll), "Failed to register PLL\n");
164
165 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
166 if (IS_ERR(phy))
167 return dev_err_probe(dev, PTR_ERR(phy), "Failed to create MIPI D-PHY\n");
168
169 phy_set_drvdata(phy, mipi_tx);
170
171 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
172 if (IS_ERR(phy_provider))
173 return PTR_ERR(phy_provider);
174
175 mipi_tx->dev = dev;
176
177 mtk_mipi_tx_get_calibration_datal(mipi_tx);
178
179 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
180 mipi_tx->pll);
181}
182
183static int mtk_mipi_tx_remove(struct platform_device *pdev)
184{
185 of_clk_del_provider(pdev->dev.of_node);
186 return 0;
187}
188
189static const struct of_device_id mtk_mipi_tx_match[] = {
190 { .compatible = "mediatek,mt2701-mipi-tx",
191 .data = &mt2701_mipitx_data },
192 { .compatible = "mediatek,mt8173-mipi-tx",
193 .data = &mt8173_mipitx_data },
194 { .compatible = "mediatek,mt8183-mipi-tx",
195 .data = &mt8183_mipitx_data },
196 { },
197};
198MODULE_DEVICE_TABLE(of, mtk_mipi_tx_match);
199
200static struct platform_driver mtk_mipi_tx_driver = {
201 .probe = mtk_mipi_tx_probe,
202 .remove = mtk_mipi_tx_remove,
203 .driver = {
204 .name = "mediatek-mipi-tx",
205 .of_match_table = mtk_mipi_tx_match,
206 },
207};
208module_platform_driver(mtk_mipi_tx_driver);
209
210MODULE_DESCRIPTION("MediaTek MIPI TX Driver");
211MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include "phy-mtk-mipi-dsi.h"
7
8inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
9{
10 return container_of(hw, struct mtk_mipi_tx, pll_hw);
11}
12
13void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
14 u32 bits)
15{
16 u32 temp = readl(mipi_tx->regs + offset);
17
18 writel(temp & ~bits, mipi_tx->regs + offset);
19}
20
21void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
22 u32 bits)
23{
24 u32 temp = readl(mipi_tx->regs + offset);
25
26 writel(temp | bits, mipi_tx->regs + offset);
27}
28
29void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
30 u32 mask, u32 data)
31{
32 u32 temp = readl(mipi_tx->regs + offset);
33
34 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
35}
36
37int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
38 unsigned long parent_rate)
39{
40 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
41
42 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
43
44 mipi_tx->data_rate = rate;
45
46 return 0;
47}
48
49unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
50 unsigned long parent_rate)
51{
52 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
53
54 return mipi_tx->data_rate;
55}
56
57static int mtk_mipi_tx_power_on(struct phy *phy)
58{
59 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
60 int ret;
61
62 /* Power up core and enable PLL */
63 ret = clk_prepare_enable(mipi_tx->pll);
64 if (ret < 0)
65 return ret;
66
67 /* Enable DSI Lane LDO outputs, disable pad tie low */
68 mipi_tx->driver_data->mipi_tx_enable_signal(phy);
69 return 0;
70}
71
72static int mtk_mipi_tx_power_off(struct phy *phy)
73{
74 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
75
76 /* Enable pad tie low, disable DSI Lane LDO outputs */
77 mipi_tx->driver_data->mipi_tx_disable_signal(phy);
78
79 /* Disable PLL and power down core */
80 clk_disable_unprepare(mipi_tx->pll);
81
82 return 0;
83}
84
85static const struct phy_ops mtk_mipi_tx_ops = {
86 .power_on = mtk_mipi_tx_power_on,
87 .power_off = mtk_mipi_tx_power_off,
88 .owner = THIS_MODULE,
89};
90
91static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
92{
93 struct nvmem_cell *cell;
94 size_t len;
95 u32 *buf;
96
97 cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
98 if (IS_ERR(cell)) {
99 dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
100 return;
101 }
102 buf = (u32 *)nvmem_cell_read(cell, &len);
103 nvmem_cell_put(cell);
104
105 if (IS_ERR(buf)) {
106 dev_info(mipi_tx->dev, "can't get data, ignore it\n");
107 return;
108 }
109
110 if (len < 3 * sizeof(u32)) {
111 dev_info(mipi_tx->dev, "invalid calibration data\n");
112 kfree(buf);
113 return;
114 }
115
116 mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
117 (buf[0] >> 11 & 0x1f);
118 mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
119 (buf[0] >> 1 & 0x1f);
120 mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
121 (buf[1] >> 22 & 0x1f);
122 mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
123 (buf[1] >> 12 & 0x1f);
124 mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
125 (buf[1] >> 2 & 0x1f);
126 kfree(buf);
127}
128
129static int mtk_mipi_tx_probe(struct platform_device *pdev)
130{
131 struct device *dev = &pdev->dev;
132 struct mtk_mipi_tx *mipi_tx;
133 struct resource *mem;
134 const char *ref_clk_name;
135 struct clk *ref_clk;
136 struct clk_init_data clk_init = {
137 .num_parents = 1,
138 .parent_names = (const char * const *)&ref_clk_name,
139 .flags = CLK_SET_RATE_GATE,
140 };
141 struct phy *phy;
142 struct phy_provider *phy_provider;
143 int ret;
144
145 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
146 if (!mipi_tx)
147 return -ENOMEM;
148
149 mipi_tx->driver_data = of_device_get_match_data(dev);
150
151 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
152 mipi_tx->regs = devm_ioremap_resource(dev, mem);
153 if (IS_ERR(mipi_tx->regs)) {
154 return PTR_ERR(mipi_tx->regs);
155 }
156
157 ref_clk = devm_clk_get(dev, NULL);
158 if (IS_ERR(ref_clk)) {
159 ret = PTR_ERR(ref_clk);
160 dev_err(dev, "Failed to get reference clock: %d\n", ret);
161 return ret;
162 }
163
164 ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
165 &mipi_tx->mipitx_drive);
166 /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
167 if (ret < 0)
168 mipi_tx->mipitx_drive = 4600;
169
170 /* check the mipitx_drive valid */
171 if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
172 dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
173 mipi_tx->mipitx_drive);
174 mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
175 6000);
176 }
177
178 ref_clk_name = __clk_get_name(ref_clk);
179
180 ret = of_property_read_string(dev->of_node, "clock-output-names",
181 &clk_init.name);
182 if (ret < 0) {
183 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
184 return ret;
185 }
186
187 clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
188
189 mipi_tx->pll_hw.init = &clk_init;
190 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
191 if (IS_ERR(mipi_tx->pll)) {
192 ret = PTR_ERR(mipi_tx->pll);
193 dev_err(dev, "Failed to register PLL: %d\n", ret);
194 return ret;
195 }
196
197 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
198 if (IS_ERR(phy)) {
199 ret = PTR_ERR(phy);
200 dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
201 return ret;
202 }
203 phy_set_drvdata(phy, mipi_tx);
204
205 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
206 if (IS_ERR(phy_provider)) {
207 ret = PTR_ERR(phy_provider);
208 return ret;
209 }
210
211 mipi_tx->dev = dev;
212
213 mtk_mipi_tx_get_calibration_datal(mipi_tx);
214
215 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
216 mipi_tx->pll);
217}
218
219static int mtk_mipi_tx_remove(struct platform_device *pdev)
220{
221 of_clk_del_provider(pdev->dev.of_node);
222 return 0;
223}
224
225static const struct of_device_id mtk_mipi_tx_match[] = {
226 { .compatible = "mediatek,mt2701-mipi-tx",
227 .data = &mt2701_mipitx_data },
228 { .compatible = "mediatek,mt8173-mipi-tx",
229 .data = &mt8173_mipitx_data },
230 { .compatible = "mediatek,mt8183-mipi-tx",
231 .data = &mt8183_mipitx_data },
232 { },
233};
234MODULE_DEVICE_TABLE(of, mtk_mipi_tx_match);
235
236static struct platform_driver mtk_mipi_tx_driver = {
237 .probe = mtk_mipi_tx_probe,
238 .remove = mtk_mipi_tx_remove,
239 .driver = {
240 .name = "mediatek-mipi-tx",
241 .of_match_table = mtk_mipi_tx_match,
242 },
243};
244module_platform_driver(mtk_mipi_tx_driver);
245
246MODULE_DESCRIPTION("MediaTek MIPI TX Driver");
247MODULE_LICENSE("GPL v2");