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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/iopoll.h>
24#include <linux/msi.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_platform.h>
28#include <linux/pci.h>
29#include <linux/phy/phy.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32
33#include "pcie-rcar.h"
34
35struct rcar_msi {
36 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
37 struct irq_domain *domain;
38 struct mutex map_lock;
39 spinlock_t mask_lock;
40 int irq1;
41 int irq2;
42};
43
44#ifdef CONFIG_ARM
45/*
46 * Here we keep a static copy of the remapped PCIe controller address.
47 * This is only used on aarch32 systems, all of which have one single
48 * PCIe controller, to provide quick access to the PCIe controller in
49 * the L1 link state fixup function, called from the ARM fault handler.
50 */
51static void __iomem *pcie_base;
52/*
53 * Static copy of PCIe device pointer, so we can check whether the
54 * device is runtime suspended or not.
55 */
56static struct device *pcie_dev;
57#endif
58
59/* Structure representing the PCIe interface */
60struct rcar_pcie_host {
61 struct rcar_pcie pcie;
62 struct phy *phy;
63 struct clk *bus_clk;
64 struct rcar_msi msi;
65 int (*phy_init_fn)(struct rcar_pcie_host *host);
66};
67
68static DEFINE_SPINLOCK(pmsr_lock);
69
70static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
71{
72 unsigned long flags;
73 u32 pmsr, val;
74 int ret = 0;
75
76 spin_lock_irqsave(&pmsr_lock, flags);
77
78 if (!pcie_base || pm_runtime_suspended(pcie_dev)) {
79 ret = -EINVAL;
80 goto unlock_exit;
81 }
82
83 pmsr = readl(pcie_base + PMSR);
84
85 /*
86 * Test if the PCIe controller received PM_ENTER_L1 DLLP and
87 * the PCIe controller is not in L1 link state. If true, apply
88 * fix, which will put the controller into L1 link state, from
89 * which it can return to L0s/L0 on its own.
90 */
91 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
92 writel(L1IATN, pcie_base + PMCTLR);
93 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
94 val & L1FAEG, 10, 1000);
95 WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
96 writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
97 }
98
99unlock_exit:
100 spin_unlock_irqrestore(&pmsr_lock, flags);
101 return ret;
102}
103
104static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
105{
106 return container_of(msi, struct rcar_pcie_host, msi);
107}
108
109static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
110{
111 unsigned int shift = BITS_PER_BYTE * (where & 3);
112 u32 val = rcar_pci_read_reg(pcie, where & ~3);
113
114 return val >> shift;
115}
116
117#ifdef CONFIG_ARM
118#define __rcar_pci_rw_reg_workaround(instr) \
119 " .arch armv7-a\n" \
120 "1: " instr " %1, [%2]\n" \
121 "2: isb\n" \
122 "3: .pushsection .text.fixup,\"ax\"\n" \
123 " .align 2\n" \
124 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \
125 " b 3b\n" \
126 " .popsection\n" \
127 " .pushsection __ex_table,\"a\"\n" \
128 " .align 3\n" \
129 " .long 1b, 4b\n" \
130 " .long 2b, 4b\n" \
131 " .popsection\n"
132#endif
133
134static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val,
135 unsigned int reg)
136{
137 int error = PCIBIOS_SUCCESSFUL;
138#ifdef CONFIG_ARM
139 asm volatile(
140 __rcar_pci_rw_reg_workaround("str")
141 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory");
142#else
143 rcar_pci_write_reg(pcie, val, reg);
144#endif
145 return error;
146}
147
148static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val,
149 unsigned int reg)
150{
151 int error = PCIBIOS_SUCCESSFUL;
152#ifdef CONFIG_ARM
153 asm volatile(
154 __rcar_pci_rw_reg_workaround("ldr")
155 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory");
156
157 if (error != PCIBIOS_SUCCESSFUL)
158 PCI_SET_ERROR_RESPONSE(val);
159#else
160 *val = rcar_pci_read_reg(pcie, reg);
161#endif
162 return error;
163}
164
165/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
166static int rcar_pcie_config_access(struct rcar_pcie_host *host,
167 unsigned char access_type, struct pci_bus *bus,
168 unsigned int devfn, int where, u32 *data)
169{
170 struct rcar_pcie *pcie = &host->pcie;
171 unsigned int dev, func, reg, index;
172 int ret;
173
174 /* Wake the bus up in case it is in L1 state. */
175 ret = rcar_pcie_wakeup(pcie->dev, pcie->base);
176 if (ret) {
177 PCI_SET_ERROR_RESPONSE(data);
178 return PCIBIOS_SET_FAILED;
179 }
180
181 dev = PCI_SLOT(devfn);
182 func = PCI_FUNC(devfn);
183 reg = where & ~3;
184 index = reg / 4;
185
186 /*
187 * While each channel has its own memory-mapped extended config
188 * space, it's generally only accessible when in endpoint mode.
189 * When in root complex mode, the controller is unable to target
190 * itself with either type 0 or type 1 accesses, and indeed, any
191 * controller initiated target transfer to its own config space
192 * result in a completer abort.
193 *
194 * Each channel effectively only supports a single device, but as
195 * the same channel <-> device access works for any PCI_SLOT()
196 * value, we cheat a bit here and bind the controller's config
197 * space to devfn 0 in order to enable self-enumeration. In this
198 * case the regular ECAR/ECDR path is sidelined and the mangled
199 * config access itself is initiated as an internal bus transaction.
200 */
201 if (pci_is_root_bus(bus)) {
202 if (dev != 0)
203 return PCIBIOS_DEVICE_NOT_FOUND;
204
205 if (access_type == RCAR_PCI_ACCESS_READ)
206 *data = rcar_pci_read_reg(pcie, PCICONF(index));
207 else
208 rcar_pci_write_reg(pcie, *data, PCICONF(index));
209
210 return PCIBIOS_SUCCESSFUL;
211 }
212
213 /* Clear errors */
214 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
215
216 /* Set the PIO address */
217 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
218 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
219
220 /* Enable the configuration access */
221 if (pci_is_root_bus(bus->parent))
222 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
223 else
224 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
225
226 /* Check for errors */
227 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
228 return PCIBIOS_DEVICE_NOT_FOUND;
229
230 /* Check for master and target aborts */
231 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
232 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
233 return PCIBIOS_DEVICE_NOT_FOUND;
234
235 if (access_type == RCAR_PCI_ACCESS_READ)
236 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR);
237 else
238 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR);
239
240 /* Disable the configuration access */
241 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
242
243 return ret;
244}
245
246static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
247 int where, int size, u32 *val)
248{
249 struct rcar_pcie_host *host = bus->sysdata;
250 int ret;
251
252 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
253 bus, devfn, where, val);
254 if (ret != PCIBIOS_SUCCESSFUL)
255 return ret;
256
257 if (size == 1)
258 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
259 else if (size == 2)
260 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
261
262 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
263 bus->number, devfn, where, size, *val);
264
265 return ret;
266}
267
268/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
269static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
270 int where, int size, u32 val)
271{
272 struct rcar_pcie_host *host = bus->sysdata;
273 unsigned int shift;
274 u32 data;
275 int ret;
276
277 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
278 bus, devfn, where, &data);
279 if (ret != PCIBIOS_SUCCESSFUL)
280 return ret;
281
282 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
283 bus->number, devfn, where, size, val);
284
285 if (size == 1) {
286 shift = BITS_PER_BYTE * (where & 3);
287 data &= ~(0xff << shift);
288 data |= ((val & 0xff) << shift);
289 } else if (size == 2) {
290 shift = BITS_PER_BYTE * (where & 2);
291 data &= ~(0xffff << shift);
292 data |= ((val & 0xffff) << shift);
293 } else
294 data = val;
295
296 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE,
297 bus, devfn, where, &data);
298
299 return ret;
300}
301
302static struct pci_ops rcar_pcie_ops = {
303 .read = rcar_pcie_read_conf,
304 .write = rcar_pcie_write_conf,
305};
306
307static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
308{
309 struct device *dev = pcie->dev;
310 unsigned int timeout = 1000;
311 u32 macsr;
312
313 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
314 return;
315
316 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
317 dev_err(dev, "Speed change already in progress\n");
318 return;
319 }
320
321 macsr = rcar_pci_read_reg(pcie, MACSR);
322 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
323 goto done;
324
325 /* Set target link speed to 5.0 GT/s */
326 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
327 PCI_EXP_LNKSTA_CLS_5_0GB);
328
329 /* Set speed change reason as intentional factor */
330 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
331
332 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
333 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
334 rcar_pci_write_reg(pcie, macsr, MACSR);
335
336 /* Start link speed change */
337 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
338
339 while (timeout--) {
340 macsr = rcar_pci_read_reg(pcie, MACSR);
341 if (macsr & SPCHGFIN) {
342 /* Clear the interrupt bits */
343 rcar_pci_write_reg(pcie, macsr, MACSR);
344
345 if (macsr & SPCHGFAIL)
346 dev_err(dev, "Speed change failed\n");
347
348 goto done;
349 }
350
351 msleep(1);
352 }
353
354 dev_err(dev, "Speed change timed out\n");
355
356done:
357 dev_info(dev, "Current link speed is %s GT/s\n",
358 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
359}
360
361static void rcar_pcie_hw_enable(struct rcar_pcie_host *host)
362{
363 struct rcar_pcie *pcie = &host->pcie;
364 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
365 struct resource_entry *win;
366 LIST_HEAD(res);
367 int i = 0;
368
369 /* Try setting 5 GT/s link speed */
370 rcar_pcie_force_speedup(pcie);
371
372 /* Setup PCI resources */
373 resource_list_for_each_entry(win, &bridge->windows) {
374 struct resource *res = win->res;
375
376 if (!res->flags)
377 continue;
378
379 switch (resource_type(res)) {
380 case IORESOURCE_IO:
381 case IORESOURCE_MEM:
382 rcar_pcie_set_outbound(pcie, i, win);
383 i++;
384 break;
385 }
386 }
387}
388
389static int rcar_pcie_enable(struct rcar_pcie_host *host)
390{
391 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
392
393 rcar_pcie_hw_enable(host);
394
395 pci_add_flags(PCI_REASSIGN_ALL_BUS);
396
397 bridge->sysdata = host;
398 bridge->ops = &rcar_pcie_ops;
399
400 return pci_host_probe(bridge);
401}
402
403static int phy_wait_for_ack(struct rcar_pcie *pcie)
404{
405 struct device *dev = pcie->dev;
406 unsigned int timeout = 100;
407
408 while (timeout--) {
409 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
410 return 0;
411
412 udelay(100);
413 }
414
415 dev_err(dev, "Access to PCIe phy timed out\n");
416
417 return -ETIMEDOUT;
418}
419
420static void phy_write_reg(struct rcar_pcie *pcie,
421 unsigned int rate, u32 addr,
422 unsigned int lane, u32 data)
423{
424 u32 phyaddr;
425
426 phyaddr = WRITE_CMD |
427 ((rate & 1) << RATE_POS) |
428 ((lane & 0xf) << LANE_POS) |
429 ((addr & 0xff) << ADR_POS);
430
431 /* Set write data */
432 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
433 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
434
435 /* Ignore errors as they will be dealt with if the data link is down */
436 phy_wait_for_ack(pcie);
437
438 /* Clear command */
439 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
440 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
441
442 /* Ignore errors as they will be dealt with if the data link is down */
443 phy_wait_for_ack(pcie);
444}
445
446static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
447{
448 int err;
449
450 /* Begin initialization */
451 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
452
453 /* Set mode */
454 rcar_pci_write_reg(pcie, 1, PCIEMSR);
455
456 err = rcar_pcie_wait_for_phyrdy(pcie);
457 if (err)
458 return err;
459
460 /*
461 * Initial header for port config space is type 1, set the device
462 * class to match. Hardware takes care of propagating the IDSETR
463 * settings, so there is no need to bother with a quirk.
464 */
465 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1);
466
467 /*
468 * Setup Secondary Bus Number & Subordinate Bus Number, even though
469 * they aren't used, to avoid bridge being detected as broken.
470 */
471 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
472 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
473
474 /* Initialize default capabilities. */
475 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
476 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
477 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
478 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
479 PCI_HEADER_TYPE_BRIDGE);
480
481 /* Enable data link layer active state reporting */
482 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
483 PCI_EXP_LNKCAP_DLLLARC);
484
485 /* Write out the physical slot number = 0 */
486 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
487
488 /* Set the completion timer timeout to the maximum 50ms. */
489 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
490
491 /* Terminate list of capabilities (Next Capability Offset=0) */
492 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
493
494 /* Enable MSI */
495 if (IS_ENABLED(CONFIG_PCI_MSI))
496 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
497
498 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
499
500 /* Finish initialization - establish a PCI Express link */
501 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
502
503 /* This will timeout if we don't have a link. */
504 err = rcar_pcie_wait_for_dl(pcie);
505 if (err)
506 return err;
507
508 /* Enable INTx interrupts */
509 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
510
511 wmb();
512
513 return 0;
514}
515
516static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host)
517{
518 struct rcar_pcie *pcie = &host->pcie;
519
520 /* Initialize the phy */
521 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
522 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
523 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
524 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
525 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
526 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
527 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
528 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
529 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
530 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
531 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
532 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
533
534 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
535 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
536 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
537
538 return 0;
539}
540
541static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host)
542{
543 struct rcar_pcie *pcie = &host->pcie;
544
545 /*
546 * These settings come from the R-Car Series, 2nd Generation User's
547 * Manual, section 50.3.1 (2) Initialization of the physical layer.
548 */
549 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
550 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
551 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
552 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
553
554 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
555 /* The following value is for DC connection, no termination resistor */
556 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
557 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
558 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
559
560 return 0;
561}
562
563static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
564{
565 int err;
566
567 err = phy_init(host->phy);
568 if (err)
569 return err;
570
571 err = phy_power_on(host->phy);
572 if (err)
573 phy_exit(host->phy);
574
575 return err;
576}
577
578static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
579{
580 struct rcar_pcie_host *host = data;
581 struct rcar_pcie *pcie = &host->pcie;
582 struct rcar_msi *msi = &host->msi;
583 struct device *dev = pcie->dev;
584 unsigned long reg;
585
586 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
587
588 /* MSI & INTx share an interrupt - we only handle MSI here */
589 if (!reg)
590 return IRQ_NONE;
591
592 while (reg) {
593 unsigned int index = find_first_bit(®, 32);
594 int ret;
595
596 ret = generic_handle_domain_irq(msi->domain->parent, index);
597 if (ret) {
598 /* Unknown MSI, just clear it */
599 dev_dbg(dev, "unexpected MSI\n");
600 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
601 }
602
603 /* see if there's any more pending in this vector */
604 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
605 }
606
607 return IRQ_HANDLED;
608}
609
610static void rcar_msi_top_irq_ack(struct irq_data *d)
611{
612 irq_chip_ack_parent(d);
613}
614
615static void rcar_msi_top_irq_mask(struct irq_data *d)
616{
617 pci_msi_mask_irq(d);
618 irq_chip_mask_parent(d);
619}
620
621static void rcar_msi_top_irq_unmask(struct irq_data *d)
622{
623 pci_msi_unmask_irq(d);
624 irq_chip_unmask_parent(d);
625}
626
627static struct irq_chip rcar_msi_top_chip = {
628 .name = "PCIe MSI",
629 .irq_ack = rcar_msi_top_irq_ack,
630 .irq_mask = rcar_msi_top_irq_mask,
631 .irq_unmask = rcar_msi_top_irq_unmask,
632};
633
634static void rcar_msi_irq_ack(struct irq_data *d)
635{
636 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
637 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
638
639 /* clear the interrupt */
640 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
641}
642
643static void rcar_msi_irq_mask(struct irq_data *d)
644{
645 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
646 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
647 unsigned long flags;
648 u32 value;
649
650 spin_lock_irqsave(&msi->mask_lock, flags);
651 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
652 value &= ~BIT(d->hwirq);
653 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
654 spin_unlock_irqrestore(&msi->mask_lock, flags);
655}
656
657static void rcar_msi_irq_unmask(struct irq_data *d)
658{
659 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
660 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
661 unsigned long flags;
662 u32 value;
663
664 spin_lock_irqsave(&msi->mask_lock, flags);
665 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
666 value |= BIT(d->hwirq);
667 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
668 spin_unlock_irqrestore(&msi->mask_lock, flags);
669}
670
671static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
672{
673 return -EINVAL;
674}
675
676static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
677{
678 struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
679 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
680
681 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
682 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
683 msg->data = data->hwirq;
684}
685
686static struct irq_chip rcar_msi_bottom_chip = {
687 .name = "Rcar MSI",
688 .irq_ack = rcar_msi_irq_ack,
689 .irq_mask = rcar_msi_irq_mask,
690 .irq_unmask = rcar_msi_irq_unmask,
691 .irq_set_affinity = rcar_msi_set_affinity,
692 .irq_compose_msi_msg = rcar_compose_msi_msg,
693};
694
695static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
696 unsigned int nr_irqs, void *args)
697{
698 struct rcar_msi *msi = domain->host_data;
699 unsigned int i;
700 int hwirq;
701
702 mutex_lock(&msi->map_lock);
703
704 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
705
706 mutex_unlock(&msi->map_lock);
707
708 if (hwirq < 0)
709 return -ENOSPC;
710
711 for (i = 0; i < nr_irqs; i++)
712 irq_domain_set_info(domain, virq + i, hwirq + i,
713 &rcar_msi_bottom_chip, domain->host_data,
714 handle_edge_irq, NULL, NULL);
715
716 return 0;
717}
718
719static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
720 unsigned int nr_irqs)
721{
722 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
723 struct rcar_msi *msi = domain->host_data;
724
725 mutex_lock(&msi->map_lock);
726
727 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
728
729 mutex_unlock(&msi->map_lock);
730}
731
732static const struct irq_domain_ops rcar_msi_domain_ops = {
733 .alloc = rcar_msi_domain_alloc,
734 .free = rcar_msi_domain_free,
735};
736
737static struct msi_domain_info rcar_msi_info = {
738 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
739 MSI_FLAG_MULTI_PCI_MSI),
740 .chip = &rcar_msi_top_chip,
741};
742
743static int rcar_allocate_domains(struct rcar_msi *msi)
744{
745 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
746 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
747 struct irq_domain *parent;
748
749 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
750 &rcar_msi_domain_ops, msi);
751 if (!parent) {
752 dev_err(pcie->dev, "failed to create IRQ domain\n");
753 return -ENOMEM;
754 }
755 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
756
757 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
758 if (!msi->domain) {
759 dev_err(pcie->dev, "failed to create MSI domain\n");
760 irq_domain_remove(parent);
761 return -ENOMEM;
762 }
763
764 return 0;
765}
766
767static void rcar_free_domains(struct rcar_msi *msi)
768{
769 struct irq_domain *parent = msi->domain->parent;
770
771 irq_domain_remove(msi->domain);
772 irq_domain_remove(parent);
773}
774
775static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
776{
777 struct rcar_pcie *pcie = &host->pcie;
778 struct device *dev = pcie->dev;
779 struct rcar_msi *msi = &host->msi;
780 struct resource res;
781 int err;
782
783 mutex_init(&msi->map_lock);
784 spin_lock_init(&msi->mask_lock);
785
786 err = of_address_to_resource(dev->of_node, 0, &res);
787 if (err)
788 return err;
789
790 err = rcar_allocate_domains(msi);
791 if (err)
792 return err;
793
794 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
795 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
796 IRQF_SHARED | IRQF_NO_THREAD,
797 rcar_msi_bottom_chip.name, host);
798 if (err < 0) {
799 dev_err(dev, "failed to request IRQ: %d\n", err);
800 goto err;
801 }
802
803 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
804 IRQF_SHARED | IRQF_NO_THREAD,
805 rcar_msi_bottom_chip.name, host);
806 if (err < 0) {
807 dev_err(dev, "failed to request IRQ: %d\n", err);
808 goto err;
809 }
810
811 /* disable all MSIs */
812 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
813
814 /*
815 * Setup MSI data target using RC base address address, which
816 * is guaranteed to be in the low 32bit range on any RCar HW.
817 */
818 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
819 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
820
821 return 0;
822
823err:
824 rcar_free_domains(msi);
825 return err;
826}
827
828static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
829{
830 struct rcar_pcie *pcie = &host->pcie;
831
832 /* Disable all MSI interrupts */
833 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
834
835 /* Disable address decoding of the MSI interrupt, MSIFE */
836 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
837
838 rcar_free_domains(&host->msi);
839}
840
841static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
842{
843 struct rcar_pcie *pcie = &host->pcie;
844 struct device *dev = pcie->dev;
845 struct resource res;
846 int err, i;
847
848 host->phy = devm_phy_optional_get(dev, "pcie");
849 if (IS_ERR(host->phy))
850 return PTR_ERR(host->phy);
851
852 err = of_address_to_resource(dev->of_node, 0, &res);
853 if (err)
854 return err;
855
856 pcie->base = devm_ioremap_resource(dev, &res);
857 if (IS_ERR(pcie->base))
858 return PTR_ERR(pcie->base);
859
860 host->bus_clk = devm_clk_get(dev, "pcie_bus");
861 if (IS_ERR(host->bus_clk)) {
862 dev_err(dev, "cannot get pcie bus clock\n");
863 return PTR_ERR(host->bus_clk);
864 }
865
866 i = irq_of_parse_and_map(dev->of_node, 0);
867 if (!i) {
868 dev_err(dev, "cannot get platform resources for msi interrupt\n");
869 err = -ENOENT;
870 goto err_irq1;
871 }
872 host->msi.irq1 = i;
873
874 i = irq_of_parse_and_map(dev->of_node, 1);
875 if (!i) {
876 dev_err(dev, "cannot get platform resources for msi interrupt\n");
877 err = -ENOENT;
878 goto err_irq2;
879 }
880 host->msi.irq2 = i;
881
882#ifdef CONFIG_ARM
883 /* Cache static copy for L1 link state fixup hook on aarch32 */
884 pcie_base = pcie->base;
885 pcie_dev = pcie->dev;
886#endif
887
888 return 0;
889
890err_irq2:
891 irq_dispose_mapping(host->msi.irq1);
892err_irq1:
893 return err;
894}
895
896static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
897 struct resource_entry *entry,
898 int *index)
899{
900 u64 restype = entry->res->flags;
901 u64 cpu_addr = entry->res->start;
902 u64 cpu_end = entry->res->end;
903 u64 pci_addr = entry->res->start - entry->offset;
904 u32 flags = LAM_64BIT | LAR_ENABLE;
905 u64 mask;
906 u64 size = resource_size(entry->res);
907 int idx = *index;
908
909 if (restype & IORESOURCE_PREFETCH)
910 flags |= LAM_PREFETCH;
911
912 while (cpu_addr < cpu_end) {
913 if (idx >= MAX_NR_INBOUND_MAPS - 1) {
914 dev_err(pcie->dev, "Failed to map inbound regions!\n");
915 return -EINVAL;
916 }
917 /*
918 * If the size of the range is larger than the alignment of
919 * the start address, we have to use multiple entries to
920 * perform the mapping.
921 */
922 if (cpu_addr > 0) {
923 unsigned long nr_zeros = __ffs64(cpu_addr);
924 u64 alignment = 1ULL << nr_zeros;
925
926 size = min(size, alignment);
927 }
928 /* Hardware supports max 4GiB inbound region */
929 size = min(size, 1ULL << 32);
930
931 mask = roundup_pow_of_two(size) - 1;
932 mask &= ~0xf;
933
934 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
935 lower_32_bits(mask) | flags, idx, true);
936
937 pci_addr += size;
938 cpu_addr += size;
939 idx += 2;
940 }
941 *index = idx;
942
943 return 0;
944}
945
946static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host)
947{
948 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
949 struct resource_entry *entry;
950 int index = 0, err = 0;
951
952 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
953 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
954 if (err)
955 break;
956 }
957
958 return err;
959}
960
961static const struct of_device_id rcar_pcie_of_match[] = {
962 { .compatible = "renesas,pcie-r8a7779",
963 .data = rcar_pcie_phy_init_h1 },
964 { .compatible = "renesas,pcie-r8a7790",
965 .data = rcar_pcie_phy_init_gen2 },
966 { .compatible = "renesas,pcie-r8a7791",
967 .data = rcar_pcie_phy_init_gen2 },
968 { .compatible = "renesas,pcie-rcar-gen2",
969 .data = rcar_pcie_phy_init_gen2 },
970 { .compatible = "renesas,pcie-r8a7795",
971 .data = rcar_pcie_phy_init_gen3 },
972 { .compatible = "renesas,pcie-rcar-gen3",
973 .data = rcar_pcie_phy_init_gen3 },
974 {},
975};
976
977static int rcar_pcie_probe(struct platform_device *pdev)
978{
979 struct device *dev = &pdev->dev;
980 struct rcar_pcie_host *host;
981 struct rcar_pcie *pcie;
982 u32 data;
983 int err;
984 struct pci_host_bridge *bridge;
985
986 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
987 if (!bridge)
988 return -ENOMEM;
989
990 host = pci_host_bridge_priv(bridge);
991 pcie = &host->pcie;
992 pcie->dev = dev;
993 platform_set_drvdata(pdev, host);
994
995 pm_runtime_enable(pcie->dev);
996 err = pm_runtime_get_sync(pcie->dev);
997 if (err < 0) {
998 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
999 goto err_pm_put;
1000 }
1001
1002 err = rcar_pcie_get_resources(host);
1003 if (err < 0) {
1004 dev_err(dev, "failed to request resources: %d\n", err);
1005 goto err_pm_put;
1006 }
1007
1008 err = clk_prepare_enable(host->bus_clk);
1009 if (err) {
1010 dev_err(dev, "failed to enable bus clock: %d\n", err);
1011 goto err_unmap_msi_irqs;
1012 }
1013
1014 err = rcar_pcie_parse_map_dma_ranges(host);
1015 if (err)
1016 goto err_clk_disable;
1017
1018 host->phy_init_fn = of_device_get_match_data(dev);
1019 err = host->phy_init_fn(host);
1020 if (err) {
1021 dev_err(dev, "failed to init PCIe PHY\n");
1022 goto err_clk_disable;
1023 }
1024
1025 /* Failure to get a link might just be that no cards are inserted */
1026 if (rcar_pcie_hw_init(pcie)) {
1027 dev_info(dev, "PCIe link down\n");
1028 err = -ENODEV;
1029 goto err_phy_shutdown;
1030 }
1031
1032 data = rcar_pci_read_reg(pcie, MACSR);
1033 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1034
1035 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1036 err = rcar_pcie_enable_msi(host);
1037 if (err < 0) {
1038 dev_err(dev,
1039 "failed to enable MSI support: %d\n",
1040 err);
1041 goto err_phy_shutdown;
1042 }
1043 }
1044
1045 err = rcar_pcie_enable(host);
1046 if (err)
1047 goto err_msi_teardown;
1048
1049 return 0;
1050
1051err_msi_teardown:
1052 if (IS_ENABLED(CONFIG_PCI_MSI))
1053 rcar_pcie_teardown_msi(host);
1054
1055err_phy_shutdown:
1056 if (host->phy) {
1057 phy_power_off(host->phy);
1058 phy_exit(host->phy);
1059 }
1060
1061err_clk_disable:
1062 clk_disable_unprepare(host->bus_clk);
1063
1064err_unmap_msi_irqs:
1065 irq_dispose_mapping(host->msi.irq2);
1066 irq_dispose_mapping(host->msi.irq1);
1067
1068err_pm_put:
1069 pm_runtime_put(dev);
1070 pm_runtime_disable(dev);
1071
1072 return err;
1073}
1074
1075static int rcar_pcie_resume(struct device *dev)
1076{
1077 struct rcar_pcie_host *host = dev_get_drvdata(dev);
1078 struct rcar_pcie *pcie = &host->pcie;
1079 unsigned int data;
1080 int err;
1081
1082 err = rcar_pcie_parse_map_dma_ranges(host);
1083 if (err)
1084 return 0;
1085
1086 /* Failure to get a link might just be that no cards are inserted */
1087 err = host->phy_init_fn(host);
1088 if (err) {
1089 dev_info(dev, "PCIe link down\n");
1090 return 0;
1091 }
1092
1093 data = rcar_pci_read_reg(pcie, MACSR);
1094 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1095
1096 /* Enable MSI */
1097 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1098 struct resource res;
1099 u32 val;
1100
1101 of_address_to_resource(dev->of_node, 0, &res);
1102 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
1103 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
1104
1105 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
1106 rcar_pci_write_reg(pcie, val, PCIEMSIIER);
1107 }
1108
1109 rcar_pcie_hw_enable(host);
1110
1111 return 0;
1112}
1113
1114static int rcar_pcie_resume_noirq(struct device *dev)
1115{
1116 struct rcar_pcie_host *host = dev_get_drvdata(dev);
1117 struct rcar_pcie *pcie = &host->pcie;
1118
1119 if (rcar_pci_read_reg(pcie, PMSR) &&
1120 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1121 return 0;
1122
1123 /* Re-establish the PCIe link */
1124 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1125 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1126 return rcar_pcie_wait_for_dl(pcie);
1127}
1128
1129static const struct dev_pm_ops rcar_pcie_pm_ops = {
1130 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume)
1131 .resume_noirq = rcar_pcie_resume_noirq,
1132};
1133
1134static struct platform_driver rcar_pcie_driver = {
1135 .driver = {
1136 .name = "rcar-pcie",
1137 .of_match_table = rcar_pcie_of_match,
1138 .pm = &rcar_pcie_pm_ops,
1139 .suppress_bind_attrs = true,
1140 },
1141 .probe = rcar_pcie_probe,
1142};
1143
1144#ifdef CONFIG_ARM
1145static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
1146 unsigned int fsr, struct pt_regs *regs)
1147{
1148 return !fixup_exception(regs);
1149}
1150
1151static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = {
1152 { .compatible = "renesas,pcie-r8a7779" },
1153 { .compatible = "renesas,pcie-r8a7790" },
1154 { .compatible = "renesas,pcie-r8a7791" },
1155 { .compatible = "renesas,pcie-rcar-gen2" },
1156 {},
1157};
1158
1159static int __init rcar_pcie_init(void)
1160{
1161 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) {
1162#ifdef CONFIG_ARM_LPAE
1163 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1164 "asynchronous external abort");
1165#else
1166 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1167 "imprecise external abort");
1168#endif
1169 }
1170
1171 return platform_driver_register(&rcar_pcie_driver);
1172}
1173device_initcall(rcar_pcie_init);
1174#else
1175builtin_platform_driver(rcar_pcie_driver);
1176#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/msi.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/of_platform.h>
27#include <linux/pci.h>
28#include <linux/phy/phy.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/slab.h>
32
33#include "pcie-rcar.h"
34
35struct rcar_msi {
36 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
37 struct irq_domain *domain;
38 struct mutex map_lock;
39 spinlock_t mask_lock;
40 int irq1;
41 int irq2;
42};
43
44/* Structure representing the PCIe interface */
45struct rcar_pcie_host {
46 struct rcar_pcie pcie;
47 struct phy *phy;
48 struct clk *bus_clk;
49 struct rcar_msi msi;
50 int (*phy_init_fn)(struct rcar_pcie_host *host);
51};
52
53static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
54{
55 return container_of(msi, struct rcar_pcie_host, msi);
56}
57
58static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
59{
60 unsigned int shift = BITS_PER_BYTE * (where & 3);
61 u32 val = rcar_pci_read_reg(pcie, where & ~3);
62
63 return val >> shift;
64}
65
66/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
67static int rcar_pcie_config_access(struct rcar_pcie_host *host,
68 unsigned char access_type, struct pci_bus *bus,
69 unsigned int devfn, int where, u32 *data)
70{
71 struct rcar_pcie *pcie = &host->pcie;
72 unsigned int dev, func, reg, index;
73
74 dev = PCI_SLOT(devfn);
75 func = PCI_FUNC(devfn);
76 reg = where & ~3;
77 index = reg / 4;
78
79 /*
80 * While each channel has its own memory-mapped extended config
81 * space, it's generally only accessible when in endpoint mode.
82 * When in root complex mode, the controller is unable to target
83 * itself with either type 0 or type 1 accesses, and indeed, any
84 * controller initiated target transfer to its own config space
85 * result in a completer abort.
86 *
87 * Each channel effectively only supports a single device, but as
88 * the same channel <-> device access works for any PCI_SLOT()
89 * value, we cheat a bit here and bind the controller's config
90 * space to devfn 0 in order to enable self-enumeration. In this
91 * case the regular ECAR/ECDR path is sidelined and the mangled
92 * config access itself is initiated as an internal bus transaction.
93 */
94 if (pci_is_root_bus(bus)) {
95 if (dev != 0)
96 return PCIBIOS_DEVICE_NOT_FOUND;
97
98 if (access_type == RCAR_PCI_ACCESS_READ)
99 *data = rcar_pci_read_reg(pcie, PCICONF(index));
100 else
101 rcar_pci_write_reg(pcie, *data, PCICONF(index));
102
103 return PCIBIOS_SUCCESSFUL;
104 }
105
106 /* Clear errors */
107 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
108
109 /* Set the PIO address */
110 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
111 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
112
113 /* Enable the configuration access */
114 if (pci_is_root_bus(bus->parent))
115 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
116 else
117 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
118
119 /* Check for errors */
120 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
121 return PCIBIOS_DEVICE_NOT_FOUND;
122
123 /* Check for master and target aborts */
124 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
125 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
126 return PCIBIOS_DEVICE_NOT_FOUND;
127
128 if (access_type == RCAR_PCI_ACCESS_READ)
129 *data = rcar_pci_read_reg(pcie, PCIECDR);
130 else
131 rcar_pci_write_reg(pcie, *data, PCIECDR);
132
133 /* Disable the configuration access */
134 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
135
136 return PCIBIOS_SUCCESSFUL;
137}
138
139static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
140 int where, int size, u32 *val)
141{
142 struct rcar_pcie_host *host = bus->sysdata;
143 int ret;
144
145 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
146 bus, devfn, where, val);
147 if (ret != PCIBIOS_SUCCESSFUL) {
148 *val = 0xffffffff;
149 return ret;
150 }
151
152 if (size == 1)
153 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
154 else if (size == 2)
155 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
156
157 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
158 bus->number, devfn, where, size, *val);
159
160 return ret;
161}
162
163/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
164static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
165 int where, int size, u32 val)
166{
167 struct rcar_pcie_host *host = bus->sysdata;
168 unsigned int shift;
169 u32 data;
170 int ret;
171
172 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
173 bus, devfn, where, &data);
174 if (ret != PCIBIOS_SUCCESSFUL)
175 return ret;
176
177 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
178 bus->number, devfn, where, size, val);
179
180 if (size == 1) {
181 shift = BITS_PER_BYTE * (where & 3);
182 data &= ~(0xff << shift);
183 data |= ((val & 0xff) << shift);
184 } else if (size == 2) {
185 shift = BITS_PER_BYTE * (where & 2);
186 data &= ~(0xffff << shift);
187 data |= ((val & 0xffff) << shift);
188 } else
189 data = val;
190
191 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE,
192 bus, devfn, where, &data);
193
194 return ret;
195}
196
197static struct pci_ops rcar_pcie_ops = {
198 .read = rcar_pcie_read_conf,
199 .write = rcar_pcie_write_conf,
200};
201
202static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
203{
204 struct device *dev = pcie->dev;
205 unsigned int timeout = 1000;
206 u32 macsr;
207
208 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
209 return;
210
211 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
212 dev_err(dev, "Speed change already in progress\n");
213 return;
214 }
215
216 macsr = rcar_pci_read_reg(pcie, MACSR);
217 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
218 goto done;
219
220 /* Set target link speed to 5.0 GT/s */
221 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
222 PCI_EXP_LNKSTA_CLS_5_0GB);
223
224 /* Set speed change reason as intentional factor */
225 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
226
227 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
228 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
229 rcar_pci_write_reg(pcie, macsr, MACSR);
230
231 /* Start link speed change */
232 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
233
234 while (timeout--) {
235 macsr = rcar_pci_read_reg(pcie, MACSR);
236 if (macsr & SPCHGFIN) {
237 /* Clear the interrupt bits */
238 rcar_pci_write_reg(pcie, macsr, MACSR);
239
240 if (macsr & SPCHGFAIL)
241 dev_err(dev, "Speed change failed\n");
242
243 goto done;
244 }
245
246 msleep(1);
247 }
248
249 dev_err(dev, "Speed change timed out\n");
250
251done:
252 dev_info(dev, "Current link speed is %s GT/s\n",
253 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
254}
255
256static void rcar_pcie_hw_enable(struct rcar_pcie_host *host)
257{
258 struct rcar_pcie *pcie = &host->pcie;
259 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
260 struct resource_entry *win;
261 LIST_HEAD(res);
262 int i = 0;
263
264 /* Try setting 5 GT/s link speed */
265 rcar_pcie_force_speedup(pcie);
266
267 /* Setup PCI resources */
268 resource_list_for_each_entry(win, &bridge->windows) {
269 struct resource *res = win->res;
270
271 if (!res->flags)
272 continue;
273
274 switch (resource_type(res)) {
275 case IORESOURCE_IO:
276 case IORESOURCE_MEM:
277 rcar_pcie_set_outbound(pcie, i, win);
278 i++;
279 break;
280 }
281 }
282}
283
284static int rcar_pcie_enable(struct rcar_pcie_host *host)
285{
286 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
287
288 rcar_pcie_hw_enable(host);
289
290 pci_add_flags(PCI_REASSIGN_ALL_BUS);
291
292 bridge->sysdata = host;
293 bridge->ops = &rcar_pcie_ops;
294
295 return pci_host_probe(bridge);
296}
297
298static int phy_wait_for_ack(struct rcar_pcie *pcie)
299{
300 struct device *dev = pcie->dev;
301 unsigned int timeout = 100;
302
303 while (timeout--) {
304 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
305 return 0;
306
307 udelay(100);
308 }
309
310 dev_err(dev, "Access to PCIe phy timed out\n");
311
312 return -ETIMEDOUT;
313}
314
315static void phy_write_reg(struct rcar_pcie *pcie,
316 unsigned int rate, u32 addr,
317 unsigned int lane, u32 data)
318{
319 u32 phyaddr;
320
321 phyaddr = WRITE_CMD |
322 ((rate & 1) << RATE_POS) |
323 ((lane & 0xf) << LANE_POS) |
324 ((addr & 0xff) << ADR_POS);
325
326 /* Set write data */
327 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
328 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
329
330 /* Ignore errors as they will be dealt with if the data link is down */
331 phy_wait_for_ack(pcie);
332
333 /* Clear command */
334 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
335 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
336
337 /* Ignore errors as they will be dealt with if the data link is down */
338 phy_wait_for_ack(pcie);
339}
340
341static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
342{
343 int err;
344
345 /* Begin initialization */
346 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
347
348 /* Set mode */
349 rcar_pci_write_reg(pcie, 1, PCIEMSR);
350
351 err = rcar_pcie_wait_for_phyrdy(pcie);
352 if (err)
353 return err;
354
355 /*
356 * Initial header for port config space is type 1, set the device
357 * class to match. Hardware takes care of propagating the IDSETR
358 * settings, so there is no need to bother with a quirk.
359 */
360 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
361
362 /*
363 * Setup Secondary Bus Number & Subordinate Bus Number, even though
364 * they aren't used, to avoid bridge being detected as broken.
365 */
366 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
367 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
368
369 /* Initialize default capabilities. */
370 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
371 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
372 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
373 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
374 PCI_HEADER_TYPE_BRIDGE);
375
376 /* Enable data link layer active state reporting */
377 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
378 PCI_EXP_LNKCAP_DLLLARC);
379
380 /* Write out the physical slot number = 0 */
381 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
382
383 /* Set the completion timer timeout to the maximum 50ms. */
384 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
385
386 /* Terminate list of capabilities (Next Capability Offset=0) */
387 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
388
389 /* Enable MSI */
390 if (IS_ENABLED(CONFIG_PCI_MSI))
391 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
392
393 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
394
395 /* Finish initialization - establish a PCI Express link */
396 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
397
398 /* This will timeout if we don't have a link. */
399 err = rcar_pcie_wait_for_dl(pcie);
400 if (err)
401 return err;
402
403 /* Enable INTx interrupts */
404 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
405
406 wmb();
407
408 return 0;
409}
410
411static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host)
412{
413 struct rcar_pcie *pcie = &host->pcie;
414
415 /* Initialize the phy */
416 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
417 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
418 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
419 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
420 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
421 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
422 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
423 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
424 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
425 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
426 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
427 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
428
429 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
430 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
431 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
432
433 return 0;
434}
435
436static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host)
437{
438 struct rcar_pcie *pcie = &host->pcie;
439
440 /*
441 * These settings come from the R-Car Series, 2nd Generation User's
442 * Manual, section 50.3.1 (2) Initialization of the physical layer.
443 */
444 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
445 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
446 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
447 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
448
449 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
450 /* The following value is for DC connection, no termination resistor */
451 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
452 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
453 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
454
455 return 0;
456}
457
458static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
459{
460 int err;
461
462 err = phy_init(host->phy);
463 if (err)
464 return err;
465
466 err = phy_power_on(host->phy);
467 if (err)
468 phy_exit(host->phy);
469
470 return err;
471}
472
473static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
474{
475 struct rcar_pcie_host *host = data;
476 struct rcar_pcie *pcie = &host->pcie;
477 struct rcar_msi *msi = &host->msi;
478 struct device *dev = pcie->dev;
479 unsigned long reg;
480
481 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
482
483 /* MSI & INTx share an interrupt - we only handle MSI here */
484 if (!reg)
485 return IRQ_NONE;
486
487 while (reg) {
488 unsigned int index = find_first_bit(®, 32);
489 unsigned int msi_irq;
490
491 msi_irq = irq_find_mapping(msi->domain->parent, index);
492 if (msi_irq) {
493 generic_handle_irq(msi_irq);
494 } else {
495 /* Unknown MSI, just clear it */
496 dev_dbg(dev, "unexpected MSI\n");
497 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
498 }
499
500 /* see if there's any more pending in this vector */
501 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
502 }
503
504 return IRQ_HANDLED;
505}
506
507static void rcar_msi_top_irq_ack(struct irq_data *d)
508{
509 irq_chip_ack_parent(d);
510}
511
512static void rcar_msi_top_irq_mask(struct irq_data *d)
513{
514 pci_msi_mask_irq(d);
515 irq_chip_mask_parent(d);
516}
517
518static void rcar_msi_top_irq_unmask(struct irq_data *d)
519{
520 pci_msi_unmask_irq(d);
521 irq_chip_unmask_parent(d);
522}
523
524static struct irq_chip rcar_msi_top_chip = {
525 .name = "PCIe MSI",
526 .irq_ack = rcar_msi_top_irq_ack,
527 .irq_mask = rcar_msi_top_irq_mask,
528 .irq_unmask = rcar_msi_top_irq_unmask,
529};
530
531static void rcar_msi_irq_ack(struct irq_data *d)
532{
533 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
534 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
535
536 /* clear the interrupt */
537 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
538}
539
540static void rcar_msi_irq_mask(struct irq_data *d)
541{
542 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
543 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
544 unsigned long flags;
545 u32 value;
546
547 spin_lock_irqsave(&msi->mask_lock, flags);
548 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
549 value &= ~BIT(d->hwirq);
550 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
551 spin_unlock_irqrestore(&msi->mask_lock, flags);
552}
553
554static void rcar_msi_irq_unmask(struct irq_data *d)
555{
556 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
557 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
558 unsigned long flags;
559 u32 value;
560
561 spin_lock_irqsave(&msi->mask_lock, flags);
562 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
563 value |= BIT(d->hwirq);
564 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
565 spin_unlock_irqrestore(&msi->mask_lock, flags);
566}
567
568static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
569{
570 return -EINVAL;
571}
572
573static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
574{
575 struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
576 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
577
578 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
579 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
580 msg->data = data->hwirq;
581}
582
583static struct irq_chip rcar_msi_bottom_chip = {
584 .name = "Rcar MSI",
585 .irq_ack = rcar_msi_irq_ack,
586 .irq_mask = rcar_msi_irq_mask,
587 .irq_unmask = rcar_msi_irq_unmask,
588 .irq_set_affinity = rcar_msi_set_affinity,
589 .irq_compose_msi_msg = rcar_compose_msi_msg,
590};
591
592static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
593 unsigned int nr_irqs, void *args)
594{
595 struct rcar_msi *msi = domain->host_data;
596 unsigned int i;
597 int hwirq;
598
599 mutex_lock(&msi->map_lock);
600
601 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
602
603 mutex_unlock(&msi->map_lock);
604
605 if (hwirq < 0)
606 return -ENOSPC;
607
608 for (i = 0; i < nr_irqs; i++)
609 irq_domain_set_info(domain, virq + i, hwirq + i,
610 &rcar_msi_bottom_chip, domain->host_data,
611 handle_edge_irq, NULL, NULL);
612
613 return 0;
614}
615
616static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
617 unsigned int nr_irqs)
618{
619 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
620 struct rcar_msi *msi = domain->host_data;
621
622 mutex_lock(&msi->map_lock);
623
624 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
625
626 mutex_unlock(&msi->map_lock);
627}
628
629static const struct irq_domain_ops rcar_msi_domain_ops = {
630 .alloc = rcar_msi_domain_alloc,
631 .free = rcar_msi_domain_free,
632};
633
634static struct msi_domain_info rcar_msi_info = {
635 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
636 MSI_FLAG_MULTI_PCI_MSI),
637 .chip = &rcar_msi_top_chip,
638};
639
640static int rcar_allocate_domains(struct rcar_msi *msi)
641{
642 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
643 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
644 struct irq_domain *parent;
645
646 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
647 &rcar_msi_domain_ops, msi);
648 if (!parent) {
649 dev_err(pcie->dev, "failed to create IRQ domain\n");
650 return -ENOMEM;
651 }
652 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
653
654 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
655 if (!msi->domain) {
656 dev_err(pcie->dev, "failed to create MSI domain\n");
657 irq_domain_remove(parent);
658 return -ENOMEM;
659 }
660
661 return 0;
662}
663
664static void rcar_free_domains(struct rcar_msi *msi)
665{
666 struct irq_domain *parent = msi->domain->parent;
667
668 irq_domain_remove(msi->domain);
669 irq_domain_remove(parent);
670}
671
672static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
673{
674 struct rcar_pcie *pcie = &host->pcie;
675 struct device *dev = pcie->dev;
676 struct rcar_msi *msi = &host->msi;
677 struct resource res;
678 int err;
679
680 mutex_init(&msi->map_lock);
681 spin_lock_init(&msi->mask_lock);
682
683 err = of_address_to_resource(dev->of_node, 0, &res);
684 if (err)
685 return err;
686
687 err = rcar_allocate_domains(msi);
688 if (err)
689 return err;
690
691 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
692 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
693 IRQF_SHARED | IRQF_NO_THREAD,
694 rcar_msi_bottom_chip.name, host);
695 if (err < 0) {
696 dev_err(dev, "failed to request IRQ: %d\n", err);
697 goto err;
698 }
699
700 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
701 IRQF_SHARED | IRQF_NO_THREAD,
702 rcar_msi_bottom_chip.name, host);
703 if (err < 0) {
704 dev_err(dev, "failed to request IRQ: %d\n", err);
705 goto err;
706 }
707
708 /* disable all MSIs */
709 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
710
711 /*
712 * Setup MSI data target using RC base address address, which
713 * is guaranteed to be in the low 32bit range on any RCar HW.
714 */
715 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
716 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
717
718 return 0;
719
720err:
721 rcar_free_domains(msi);
722 return err;
723}
724
725static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
726{
727 struct rcar_pcie *pcie = &host->pcie;
728
729 /* Disable all MSI interrupts */
730 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
731
732 /* Disable address decoding of the MSI interrupt, MSIFE */
733 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
734
735 rcar_free_domains(&host->msi);
736}
737
738static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
739{
740 struct rcar_pcie *pcie = &host->pcie;
741 struct device *dev = pcie->dev;
742 struct resource res;
743 int err, i;
744
745 host->phy = devm_phy_optional_get(dev, "pcie");
746 if (IS_ERR(host->phy))
747 return PTR_ERR(host->phy);
748
749 err = of_address_to_resource(dev->of_node, 0, &res);
750 if (err)
751 return err;
752
753 pcie->base = devm_ioremap_resource(dev, &res);
754 if (IS_ERR(pcie->base))
755 return PTR_ERR(pcie->base);
756
757 host->bus_clk = devm_clk_get(dev, "pcie_bus");
758 if (IS_ERR(host->bus_clk)) {
759 dev_err(dev, "cannot get pcie bus clock\n");
760 return PTR_ERR(host->bus_clk);
761 }
762
763 i = irq_of_parse_and_map(dev->of_node, 0);
764 if (!i) {
765 dev_err(dev, "cannot get platform resources for msi interrupt\n");
766 err = -ENOENT;
767 goto err_irq1;
768 }
769 host->msi.irq1 = i;
770
771 i = irq_of_parse_and_map(dev->of_node, 1);
772 if (!i) {
773 dev_err(dev, "cannot get platform resources for msi interrupt\n");
774 err = -ENOENT;
775 goto err_irq2;
776 }
777 host->msi.irq2 = i;
778
779 return 0;
780
781err_irq2:
782 irq_dispose_mapping(host->msi.irq1);
783err_irq1:
784 return err;
785}
786
787static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
788 struct resource_entry *entry,
789 int *index)
790{
791 u64 restype = entry->res->flags;
792 u64 cpu_addr = entry->res->start;
793 u64 cpu_end = entry->res->end;
794 u64 pci_addr = entry->res->start - entry->offset;
795 u32 flags = LAM_64BIT | LAR_ENABLE;
796 u64 mask;
797 u64 size = resource_size(entry->res);
798 int idx = *index;
799
800 if (restype & IORESOURCE_PREFETCH)
801 flags |= LAM_PREFETCH;
802
803 while (cpu_addr < cpu_end) {
804 if (idx >= MAX_NR_INBOUND_MAPS - 1) {
805 dev_err(pcie->dev, "Failed to map inbound regions!\n");
806 return -EINVAL;
807 }
808 /*
809 * If the size of the range is larger than the alignment of
810 * the start address, we have to use multiple entries to
811 * perform the mapping.
812 */
813 if (cpu_addr > 0) {
814 unsigned long nr_zeros = __ffs64(cpu_addr);
815 u64 alignment = 1ULL << nr_zeros;
816
817 size = min(size, alignment);
818 }
819 /* Hardware supports max 4GiB inbound region */
820 size = min(size, 1ULL << 32);
821
822 mask = roundup_pow_of_two(size) - 1;
823 mask &= ~0xf;
824
825 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
826 lower_32_bits(mask) | flags, idx, true);
827
828 pci_addr += size;
829 cpu_addr += size;
830 idx += 2;
831 }
832 *index = idx;
833
834 return 0;
835}
836
837static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host)
838{
839 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
840 struct resource_entry *entry;
841 int index = 0, err = 0;
842
843 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
844 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
845 if (err)
846 break;
847 }
848
849 return err;
850}
851
852static const struct of_device_id rcar_pcie_of_match[] = {
853 { .compatible = "renesas,pcie-r8a7779",
854 .data = rcar_pcie_phy_init_h1 },
855 { .compatible = "renesas,pcie-r8a7790",
856 .data = rcar_pcie_phy_init_gen2 },
857 { .compatible = "renesas,pcie-r8a7791",
858 .data = rcar_pcie_phy_init_gen2 },
859 { .compatible = "renesas,pcie-rcar-gen2",
860 .data = rcar_pcie_phy_init_gen2 },
861 { .compatible = "renesas,pcie-r8a7795",
862 .data = rcar_pcie_phy_init_gen3 },
863 { .compatible = "renesas,pcie-rcar-gen3",
864 .data = rcar_pcie_phy_init_gen3 },
865 {},
866};
867
868static int rcar_pcie_probe(struct platform_device *pdev)
869{
870 struct device *dev = &pdev->dev;
871 struct rcar_pcie_host *host;
872 struct rcar_pcie *pcie;
873 u32 data;
874 int err;
875 struct pci_host_bridge *bridge;
876
877 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
878 if (!bridge)
879 return -ENOMEM;
880
881 host = pci_host_bridge_priv(bridge);
882 pcie = &host->pcie;
883 pcie->dev = dev;
884 platform_set_drvdata(pdev, host);
885
886 pm_runtime_enable(pcie->dev);
887 err = pm_runtime_get_sync(pcie->dev);
888 if (err < 0) {
889 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
890 goto err_pm_put;
891 }
892
893 err = rcar_pcie_get_resources(host);
894 if (err < 0) {
895 dev_err(dev, "failed to request resources: %d\n", err);
896 goto err_pm_put;
897 }
898
899 err = clk_prepare_enable(host->bus_clk);
900 if (err) {
901 dev_err(dev, "failed to enable bus clock: %d\n", err);
902 goto err_unmap_msi_irqs;
903 }
904
905 err = rcar_pcie_parse_map_dma_ranges(host);
906 if (err)
907 goto err_clk_disable;
908
909 host->phy_init_fn = of_device_get_match_data(dev);
910 err = host->phy_init_fn(host);
911 if (err) {
912 dev_err(dev, "failed to init PCIe PHY\n");
913 goto err_clk_disable;
914 }
915
916 /* Failure to get a link might just be that no cards are inserted */
917 if (rcar_pcie_hw_init(pcie)) {
918 dev_info(dev, "PCIe link down\n");
919 err = -ENODEV;
920 goto err_phy_shutdown;
921 }
922
923 data = rcar_pci_read_reg(pcie, MACSR);
924 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
925
926 if (IS_ENABLED(CONFIG_PCI_MSI)) {
927 err = rcar_pcie_enable_msi(host);
928 if (err < 0) {
929 dev_err(dev,
930 "failed to enable MSI support: %d\n",
931 err);
932 goto err_phy_shutdown;
933 }
934 }
935
936 err = rcar_pcie_enable(host);
937 if (err)
938 goto err_msi_teardown;
939
940 return 0;
941
942err_msi_teardown:
943 if (IS_ENABLED(CONFIG_PCI_MSI))
944 rcar_pcie_teardown_msi(host);
945
946err_phy_shutdown:
947 if (host->phy) {
948 phy_power_off(host->phy);
949 phy_exit(host->phy);
950 }
951
952err_clk_disable:
953 clk_disable_unprepare(host->bus_clk);
954
955err_unmap_msi_irqs:
956 irq_dispose_mapping(host->msi.irq2);
957 irq_dispose_mapping(host->msi.irq1);
958
959err_pm_put:
960 pm_runtime_put(dev);
961 pm_runtime_disable(dev);
962
963 return err;
964}
965
966static int __maybe_unused rcar_pcie_resume(struct device *dev)
967{
968 struct rcar_pcie_host *host = dev_get_drvdata(dev);
969 struct rcar_pcie *pcie = &host->pcie;
970 unsigned int data;
971 int err;
972
973 err = rcar_pcie_parse_map_dma_ranges(host);
974 if (err)
975 return 0;
976
977 /* Failure to get a link might just be that no cards are inserted */
978 err = host->phy_init_fn(host);
979 if (err) {
980 dev_info(dev, "PCIe link down\n");
981 return 0;
982 }
983
984 data = rcar_pci_read_reg(pcie, MACSR);
985 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
986
987 /* Enable MSI */
988 if (IS_ENABLED(CONFIG_PCI_MSI)) {
989 struct resource res;
990 u32 val;
991
992 of_address_to_resource(dev->of_node, 0, &res);
993 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
994 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
995
996 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
997 rcar_pci_write_reg(pcie, val, PCIEMSIIER);
998 }
999
1000 rcar_pcie_hw_enable(host);
1001
1002 return 0;
1003}
1004
1005static int rcar_pcie_resume_noirq(struct device *dev)
1006{
1007 struct rcar_pcie_host *host = dev_get_drvdata(dev);
1008 struct rcar_pcie *pcie = &host->pcie;
1009
1010 if (rcar_pci_read_reg(pcie, PMSR) &&
1011 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1012 return 0;
1013
1014 /* Re-establish the PCIe link */
1015 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1016 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1017 return rcar_pcie_wait_for_dl(pcie);
1018}
1019
1020static const struct dev_pm_ops rcar_pcie_pm_ops = {
1021 SET_SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume)
1022 .resume_noirq = rcar_pcie_resume_noirq,
1023};
1024
1025static struct platform_driver rcar_pcie_driver = {
1026 .driver = {
1027 .name = "rcar-pcie",
1028 .of_match_table = rcar_pcie_of_match,
1029 .pm = &rcar_pcie_pm_ops,
1030 .suppress_bind_attrs = true,
1031 },
1032 .probe = rcar_pcie_probe,
1033};
1034builtin_platform_driver(rcar_pcie_driver);