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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2020 MediaTek Inc.
6 * Author: Jianjun Wang <jianjun.wang@mediatek.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/iopoll.h>
12#include <linux/irq.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/msi.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/pm_runtime.h>
23#include <linux/reset.h>
24
25#include "../pci.h"
26
27#define PCIE_SETTING_REG 0x80
28#define PCIE_PCI_IDS_1 0x9c
29#define PCI_CLASS(class) (class << 8)
30#define PCIE_RC_MODE BIT(0)
31
32#define PCIE_CFGNUM_REG 0x140
33#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
34#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
35#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))
36#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
37#define PCIE_CFG_OFFSET_ADDR 0x1000
38#define PCIE_CFG_HEADER(bus, devfn) \
39 (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
40
41#define PCIE_RST_CTRL_REG 0x148
42#define PCIE_MAC_RSTB BIT(0)
43#define PCIE_PHY_RSTB BIT(1)
44#define PCIE_BRG_RSTB BIT(2)
45#define PCIE_PE_RSTB BIT(3)
46
47#define PCIE_LTSSM_STATUS_REG 0x150
48#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
49#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
50#define PCIE_LTSSM_STATE_L2_IDLE 0x14
51
52#define PCIE_LINK_STATUS_REG 0x154
53#define PCIE_PORT_LINKUP BIT(8)
54
55#define PCIE_MSI_SET_NUM 8
56#define PCIE_MSI_IRQS_PER_SET 32
57#define PCIE_MSI_IRQS_NUM \
58 (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
59
60#define PCIE_INT_ENABLE_REG 0x180
61#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
62#define PCIE_MSI_SHIFT 8
63#define PCIE_INTX_SHIFT 24
64#define PCIE_INTX_ENABLE \
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
66
67#define PCIE_INT_STATUS_REG 0x184
68#define PCIE_MSI_SET_ENABLE_REG 0x190
69#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
70
71#define PCIE_MSI_SET_BASE_REG 0xc00
72#define PCIE_MSI_SET_OFFSET 0x10
73#define PCIE_MSI_SET_STATUS_OFFSET 0x04
74#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
75
76#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
77#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
78
79#define PCIE_ICMD_PM_REG 0x198
80#define PCIE_TURN_OFF_LINK BIT(4)
81
82#define PCIE_MISC_CTRL_REG 0x348
83#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
84
85#define PCIE_TRANS_TABLE_BASE_REG 0x800
86#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
87#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
88#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
89#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
90#define PCIE_ATR_TLB_SET_OFFSET 0x20
91
92#define PCIE_MAX_TRANS_TABLES 8
93#define PCIE_ATR_EN BIT(0)
94#define PCIE_ATR_SIZE(size) \
95 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
96#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
97#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
98#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
99#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
100#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
101#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
102
103/**
104 * struct mtk_msi_set - MSI information for each set
105 * @base: IO mapped register base
106 * @msg_addr: MSI message address
107 * @saved_irq_state: IRQ enable state saved at suspend time
108 */
109struct mtk_msi_set {
110 void __iomem *base;
111 phys_addr_t msg_addr;
112 u32 saved_irq_state;
113};
114
115/**
116 * struct mtk_gen3_pcie - PCIe port information
117 * @dev: pointer to PCIe device
118 * @base: IO mapped register base
119 * @reg_base: physical register base
120 * @mac_reset: MAC reset control
121 * @phy_reset: PHY reset control
122 * @phy: PHY controller block
123 * @clks: PCIe clocks
124 * @num_clks: PCIe clocks count for this port
125 * @irq: PCIe controller interrupt number
126 * @saved_irq_state: IRQ enable state saved at suspend time
127 * @irq_lock: lock protecting IRQ register access
128 * @intx_domain: legacy INTx IRQ domain
129 * @msi_domain: MSI IRQ domain
130 * @msi_bottom_domain: MSI IRQ bottom domain
131 * @msi_sets: MSI sets information
132 * @lock: lock protecting IRQ bit map
133 * @msi_irq_in_use: bit map for assigned MSI IRQ
134 */
135struct mtk_gen3_pcie {
136 struct device *dev;
137 void __iomem *base;
138 phys_addr_t reg_base;
139 struct reset_control *mac_reset;
140 struct reset_control *phy_reset;
141 struct phy *phy;
142 struct clk_bulk_data *clks;
143 int num_clks;
144
145 int irq;
146 u32 saved_irq_state;
147 raw_spinlock_t irq_lock;
148 struct irq_domain *intx_domain;
149 struct irq_domain *msi_domain;
150 struct irq_domain *msi_bottom_domain;
151 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
152 struct mutex lock;
153 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
154};
155
156/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
157static const char *const ltssm_str[] = {
158 "detect.quiet", /* 0x00 */
159 "detect.active", /* 0x01 */
160 "polling.active", /* 0x02 */
161 "polling.compliance", /* 0x03 */
162 "polling.configuration", /* 0x04 */
163 "config.linkwidthstart", /* 0x05 */
164 "config.linkwidthaccept", /* 0x06 */
165 "config.lanenumwait", /* 0x07 */
166 "config.lanenumaccept", /* 0x08 */
167 "config.complete", /* 0x09 */
168 "config.idle", /* 0x0A */
169 "recovery.receiverlock", /* 0x0B */
170 "recovery.equalization", /* 0x0C */
171 "recovery.speed", /* 0x0D */
172 "recovery.receiverconfig", /* 0x0E */
173 "recovery.idle", /* 0x0F */
174 "L0", /* 0x10 */
175 "L0s", /* 0x11 */
176 "L1.entry", /* 0x12 */
177 "L1.idle", /* 0x13 */
178 "L2.idle", /* 0x14 */
179 "L2.transmitwake", /* 0x15 */
180 "disable", /* 0x16 */
181 "loopback.entry", /* 0x17 */
182 "loopback.active", /* 0x18 */
183 "loopback.exit", /* 0x19 */
184 "hotreset", /* 0x1A */
185};
186
187/**
188 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
189 * @bus: PCI bus to query
190 * @devfn: device/function number
191 * @where: offset in config space
192 * @size: data size in TLP header
193 *
194 * Set byte enable field and device information in configuration TLP header.
195 */
196static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn,
197 int where, int size)
198{
199 struct mtk_gen3_pcie *pcie = bus->sysdata;
200 int bytes;
201 u32 val;
202
203 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);
204
205 val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) |
206 PCIE_CFG_HEADER(bus->number, devfn);
207
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
209}
210
211static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
212 int where)
213{
214 struct mtk_gen3_pcie *pcie = bus->sysdata;
215
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where;
217}
218
219static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
220 int where, int size, u32 *val)
221{
222 mtk_pcie_config_tlp_header(bus, devfn, where, size);
223
224 return pci_generic_config_read32(bus, devfn, where, size, val);
225}
226
227static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
228 int where, int size, u32 val)
229{
230 mtk_pcie_config_tlp_header(bus, devfn, where, size);
231
232 if (size <= 2)
233 val <<= (where & 0x3) * 8;
234
235 return pci_generic_config_write32(bus, devfn, where, 4, val);
236}
237
238static struct pci_ops mtk_pcie_ops = {
239 .map_bus = mtk_pcie_map_bus,
240 .read = mtk_pcie_config_read,
241 .write = mtk_pcie_config_write,
242};
243
244static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
245 resource_size_t cpu_addr,
246 resource_size_t pci_addr,
247 resource_size_t size,
248 unsigned long type, int num)
249{
250 void __iomem *table;
251 u32 val;
252
253 if (num >= PCIE_MAX_TRANS_TABLES) {
254 dev_err(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
255 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
256 return -ENODEV;
257 }
258
259 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG +
260 num * PCIE_ATR_TLB_SET_OFFSET;
261
262 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1),
263 table);
264 writel_relaxed(upper_32_bits(cpu_addr),
265 table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
266 writel_relaxed(lower_32_bits(pci_addr),
267 table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
268 writel_relaxed(upper_32_bits(pci_addr),
269 table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
270
271 if (type == IORESOURCE_IO)
272 val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
273 else
274 val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
275
276 writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
277
278 return 0;
279}
280
281static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
282{
283 int i;
284 u32 val;
285
286 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
287 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
288
289 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
290 i * PCIE_MSI_SET_OFFSET;
291 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +
292 i * PCIE_MSI_SET_OFFSET;
293
294 /* Configure the MSI capture address */
295 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
296 writel_relaxed(upper_32_bits(msi_set->msg_addr),
297 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +
298 i * PCIE_MSI_SET_ADDR_HI_OFFSET);
299 }
300
301 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);
302 val |= PCIE_MSI_SET_ENABLE;
303 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
304
305 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
306 val |= PCIE_MSI_ENABLE;
307 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
308}
309
310static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
311{
312 struct resource_entry *entry;
313 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
314 unsigned int table_index = 0;
315 int err;
316 u32 val;
317
318 /* Set as RC mode */
319 val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
320 val |= PCIE_RC_MODE;
321 writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
322
323 /* Set class code */
324 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
325 val &= ~GENMASK(31, 8);
326 val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL);
327 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
328
329 /* Mask all INTx interrupts */
330 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
331 val &= ~PCIE_INTX_ENABLE;
332 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
333
334 /* Disable DVFSRC voltage request */
335 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
336 val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
337 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
338
339 /* Assert all reset signals */
340 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
341 val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
342 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
343
344 /*
345 * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
346 * and 2.2.1 (Initial Power-Up (G3 to S0)).
347 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
348 * for the power and clock to become stable.
349 */
350 msleep(100);
351
352 /* De-assert reset signals */
353 val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
354 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
355
356 /* Check if the link is up or not */
357 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
358 !!(val & PCIE_PORT_LINKUP), 20,
359 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
360 if (err) {
361 const char *ltssm_state;
362 int ltssm_index;
363
364 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);
365 ltssm_index = PCIE_LTSSM_STATE(val);
366 ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ?
367 "Unknown state" : ltssm_str[ltssm_index];
368 dev_err(pcie->dev,
369 "PCIe link down, current LTSSM state: %s (%#x)\n",
370 ltssm_state, val);
371 return err;
372 }
373
374 mtk_pcie_enable_msi(pcie);
375
376 /* Set PCIe translation windows */
377 resource_list_for_each_entry(entry, &host->windows) {
378 struct resource *res = entry->res;
379 unsigned long type = resource_type(res);
380 resource_size_t cpu_addr;
381 resource_size_t pci_addr;
382 resource_size_t size;
383 const char *range_type;
384
385 if (type == IORESOURCE_IO) {
386 cpu_addr = pci_pio_to_address(res->start);
387 range_type = "IO";
388 } else if (type == IORESOURCE_MEM) {
389 cpu_addr = res->start;
390 range_type = "MEM";
391 } else {
392 continue;
393 }
394
395 pci_addr = res->start - entry->offset;
396 size = resource_size(res);
397 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,
398 type, table_index);
399 if (err)
400 return err;
401
402 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
403 range_type, table_index, (unsigned long long)cpu_addr,
404 (unsigned long long)pci_addr, (unsigned long long)size);
405
406 table_index++;
407 }
408
409 return 0;
410}
411
412static int mtk_pcie_set_affinity(struct irq_data *data,
413 const struct cpumask *mask, bool force)
414{
415 return -EINVAL;
416}
417
418static void mtk_pcie_msi_irq_mask(struct irq_data *data)
419{
420 pci_msi_mask_irq(data);
421 irq_chip_mask_parent(data);
422}
423
424static void mtk_pcie_msi_irq_unmask(struct irq_data *data)
425{
426 pci_msi_unmask_irq(data);
427 irq_chip_unmask_parent(data);
428}
429
430static struct irq_chip mtk_msi_irq_chip = {
431 .irq_ack = irq_chip_ack_parent,
432 .irq_mask = mtk_pcie_msi_irq_mask,
433 .irq_unmask = mtk_pcie_msi_irq_unmask,
434 .name = "MSI",
435};
436
437static struct msi_domain_info mtk_msi_domain_info = {
438 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
439 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
440 .chip = &mtk_msi_irq_chip,
441};
442
443static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
444{
445 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
446 struct mtk_gen3_pcie *pcie = data->domain->host_data;
447 unsigned long hwirq;
448
449 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
450
451 msg->address_hi = upper_32_bits(msi_set->msg_addr);
452 msg->address_lo = lower_32_bits(msi_set->msg_addr);
453 msg->data = hwirq;
454 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
455 hwirq, msg->address_hi, msg->address_lo, msg->data);
456}
457
458static void mtk_msi_bottom_irq_ack(struct irq_data *data)
459{
460 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
461 unsigned long hwirq;
462
463 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
464
465 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
466}
467
468static void mtk_msi_bottom_irq_mask(struct irq_data *data)
469{
470 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
471 struct mtk_gen3_pcie *pcie = data->domain->host_data;
472 unsigned long hwirq, flags;
473 u32 val;
474
475 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
476
477 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
478 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
479 val &= ~BIT(hwirq);
480 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
481 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
482}
483
484static void mtk_msi_bottom_irq_unmask(struct irq_data *data)
485{
486 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
487 struct mtk_gen3_pcie *pcie = data->domain->host_data;
488 unsigned long hwirq, flags;
489 u32 val;
490
491 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
492
493 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
494 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
495 val |= BIT(hwirq);
496 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
497 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
498}
499
500static struct irq_chip mtk_msi_bottom_irq_chip = {
501 .irq_ack = mtk_msi_bottom_irq_ack,
502 .irq_mask = mtk_msi_bottom_irq_mask,
503 .irq_unmask = mtk_msi_bottom_irq_unmask,
504 .irq_compose_msi_msg = mtk_compose_msi_msg,
505 .irq_set_affinity = mtk_pcie_set_affinity,
506 .name = "MSI",
507};
508
509static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
510 unsigned int virq, unsigned int nr_irqs,
511 void *arg)
512{
513 struct mtk_gen3_pcie *pcie = domain->host_data;
514 struct mtk_msi_set *msi_set;
515 int i, hwirq, set_idx;
516
517 mutex_lock(&pcie->lock);
518
519 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
520 order_base_2(nr_irqs));
521
522 mutex_unlock(&pcie->lock);
523
524 if (hwirq < 0)
525 return -ENOSPC;
526
527 set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
528 msi_set = &pcie->msi_sets[set_idx];
529
530 for (i = 0; i < nr_irqs; i++)
531 irq_domain_set_info(domain, virq + i, hwirq + i,
532 &mtk_msi_bottom_irq_chip, msi_set,
533 handle_edge_irq, NULL, NULL);
534
535 return 0;
536}
537
538static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
539 unsigned int virq, unsigned int nr_irqs)
540{
541 struct mtk_gen3_pcie *pcie = domain->host_data;
542 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
543
544 mutex_lock(&pcie->lock);
545
546 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq,
547 order_base_2(nr_irqs));
548
549 mutex_unlock(&pcie->lock);
550
551 irq_domain_free_irqs_common(domain, virq, nr_irqs);
552}
553
554static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {
555 .alloc = mtk_msi_bottom_domain_alloc,
556 .free = mtk_msi_bottom_domain_free,
557};
558
559static void mtk_intx_mask(struct irq_data *data)
560{
561 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
562 unsigned long flags;
563 u32 val;
564
565 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
566 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
567 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
568 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
569 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
570}
571
572static void mtk_intx_unmask(struct irq_data *data)
573{
574 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
575 unsigned long flags;
576 u32 val;
577
578 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
579 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
580 val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
581 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
582 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
583}
584
585/**
586 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
587 * @data: pointer to chip specific data
588 *
589 * As an emulated level IRQ, its interrupt status will remain
590 * until the corresponding de-assert message is received; hence that
591 * the status can only be cleared when the interrupt has been serviced.
592 */
593static void mtk_intx_eoi(struct irq_data *data)
594{
595 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
596 unsigned long hwirq;
597
598 hwirq = data->hwirq + PCIE_INTX_SHIFT;
599 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
600}
601
602static struct irq_chip mtk_intx_irq_chip = {
603 .irq_mask = mtk_intx_mask,
604 .irq_unmask = mtk_intx_unmask,
605 .irq_eoi = mtk_intx_eoi,
606 .irq_set_affinity = mtk_pcie_set_affinity,
607 .name = "INTx",
608};
609
610static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
611 irq_hw_number_t hwirq)
612{
613 irq_set_chip_data(irq, domain->host_data);
614 irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
615 handle_fasteoi_irq, "INTx");
616 return 0;
617}
618
619static const struct irq_domain_ops intx_domain_ops = {
620 .map = mtk_pcie_intx_map,
621};
622
623static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie)
624{
625 struct device *dev = pcie->dev;
626 struct device_node *intc_node, *node = dev->of_node;
627 int ret;
628
629 raw_spin_lock_init(&pcie->irq_lock);
630
631 /* Setup INTx */
632 intc_node = of_get_child_by_name(node, "interrupt-controller");
633 if (!intc_node) {
634 dev_err(dev, "missing interrupt-controller node\n");
635 return -ENODEV;
636 }
637
638 pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
639 &intx_domain_ops, pcie);
640 if (!pcie->intx_domain) {
641 dev_err(dev, "failed to create INTx IRQ domain\n");
642 ret = -ENODEV;
643 goto out_put_node;
644 }
645
646 /* Setup MSI */
647 mutex_init(&pcie->lock);
648
649 pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
650 &mtk_msi_bottom_domain_ops, pcie);
651 if (!pcie->msi_bottom_domain) {
652 dev_err(dev, "failed to create MSI bottom domain\n");
653 ret = -ENODEV;
654 goto err_msi_bottom_domain;
655 }
656
657 pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
658 &mtk_msi_domain_info,
659 pcie->msi_bottom_domain);
660 if (!pcie->msi_domain) {
661 dev_err(dev, "failed to create MSI domain\n");
662 ret = -ENODEV;
663 goto err_msi_domain;
664 }
665
666 of_node_put(intc_node);
667 return 0;
668
669err_msi_domain:
670 irq_domain_remove(pcie->msi_bottom_domain);
671err_msi_bottom_domain:
672 irq_domain_remove(pcie->intx_domain);
673out_put_node:
674 of_node_put(intc_node);
675 return ret;
676}
677
678static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie)
679{
680 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
681
682 if (pcie->intx_domain)
683 irq_domain_remove(pcie->intx_domain);
684
685 if (pcie->msi_domain)
686 irq_domain_remove(pcie->msi_domain);
687
688 if (pcie->msi_bottom_domain)
689 irq_domain_remove(pcie->msi_bottom_domain);
690
691 irq_dispose_mapping(pcie->irq);
692}
693
694static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx)
695{
696 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];
697 unsigned long msi_enable, msi_status;
698 irq_hw_number_t bit, hwirq;
699
700 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
701
702 do {
703 msi_status = readl_relaxed(msi_set->base +
704 PCIE_MSI_SET_STATUS_OFFSET);
705 msi_status &= msi_enable;
706 if (!msi_status)
707 break;
708
709 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
710 hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
711 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq);
712 }
713 } while (true);
714}
715
716static void mtk_pcie_irq_handler(struct irq_desc *desc)
717{
718 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc);
719 struct irq_chip *irqchip = irq_desc_get_chip(desc);
720 unsigned long status;
721 irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
722
723 chained_irq_enter(irqchip, desc);
724
725 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);
726 for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
727 PCIE_INTX_SHIFT)
728 generic_handle_domain_irq(pcie->intx_domain,
729 irq_bit - PCIE_INTX_SHIFT);
730
731 irq_bit = PCIE_MSI_SHIFT;
732 for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
733 PCIE_MSI_SHIFT) {
734 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT);
735
736 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
737 }
738
739 chained_irq_exit(irqchip, desc);
740}
741
742static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
743{
744 struct device *dev = pcie->dev;
745 struct platform_device *pdev = to_platform_device(dev);
746 int err;
747
748 err = mtk_pcie_init_irq_domains(pcie);
749 if (err)
750 return err;
751
752 pcie->irq = platform_get_irq(pdev, 0);
753 if (pcie->irq < 0)
754 return pcie->irq;
755
756 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie);
757
758 return 0;
759}
760
761static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
762{
763 struct device *dev = pcie->dev;
764 struct platform_device *pdev = to_platform_device(dev);
765 struct resource *regs;
766 int ret;
767
768 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
769 if (!regs)
770 return -EINVAL;
771 pcie->base = devm_ioremap_resource(dev, regs);
772 if (IS_ERR(pcie->base)) {
773 dev_err(dev, "failed to map register base\n");
774 return PTR_ERR(pcie->base);
775 }
776
777 pcie->reg_base = regs->start;
778
779 pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
780 if (IS_ERR(pcie->phy_reset)) {
781 ret = PTR_ERR(pcie->phy_reset);
782 if (ret != -EPROBE_DEFER)
783 dev_err(dev, "failed to get PHY reset\n");
784
785 return ret;
786 }
787
788 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
789 if (IS_ERR(pcie->mac_reset)) {
790 ret = PTR_ERR(pcie->mac_reset);
791 if (ret != -EPROBE_DEFER)
792 dev_err(dev, "failed to get MAC reset\n");
793
794 return ret;
795 }
796
797 pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
798 if (IS_ERR(pcie->phy)) {
799 ret = PTR_ERR(pcie->phy);
800 if (ret != -EPROBE_DEFER)
801 dev_err(dev, "failed to get PHY\n");
802
803 return ret;
804 }
805
806 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
807 if (pcie->num_clks < 0) {
808 dev_err(dev, "failed to get clocks\n");
809 return pcie->num_clks;
810 }
811
812 return 0;
813}
814
815static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
816{
817 struct device *dev = pcie->dev;
818 int err;
819
820 /* PHY power on and enable pipe clock */
821 reset_control_deassert(pcie->phy_reset);
822
823 err = phy_init(pcie->phy);
824 if (err) {
825 dev_err(dev, "failed to initialize PHY\n");
826 goto err_phy_init;
827 }
828
829 err = phy_power_on(pcie->phy);
830 if (err) {
831 dev_err(dev, "failed to power on PHY\n");
832 goto err_phy_on;
833 }
834
835 /* MAC power on and enable transaction layer clocks */
836 reset_control_deassert(pcie->mac_reset);
837
838 pm_runtime_enable(dev);
839 pm_runtime_get_sync(dev);
840
841 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
842 if (err) {
843 dev_err(dev, "failed to enable clocks\n");
844 goto err_clk_init;
845 }
846
847 return 0;
848
849err_clk_init:
850 pm_runtime_put_sync(dev);
851 pm_runtime_disable(dev);
852 reset_control_assert(pcie->mac_reset);
853 phy_power_off(pcie->phy);
854err_phy_on:
855 phy_exit(pcie->phy);
856err_phy_init:
857 reset_control_assert(pcie->phy_reset);
858
859 return err;
860}
861
862static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
863{
864 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
865
866 pm_runtime_put_sync(pcie->dev);
867 pm_runtime_disable(pcie->dev);
868 reset_control_assert(pcie->mac_reset);
869
870 phy_power_off(pcie->phy);
871 phy_exit(pcie->phy);
872 reset_control_assert(pcie->phy_reset);
873}
874
875static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
876{
877 int err;
878
879 err = mtk_pcie_parse_port(pcie);
880 if (err)
881 return err;
882
883 /*
884 * The controller may have been left out of reset by the bootloader
885 * so make sure that we get a clean start by asserting resets here.
886 */
887 reset_control_assert(pcie->phy_reset);
888 reset_control_assert(pcie->mac_reset);
889 usleep_range(10, 20);
890
891 /* Don't touch the hardware registers before power up */
892 err = mtk_pcie_power_up(pcie);
893 if (err)
894 return err;
895
896 /* Try link up */
897 err = mtk_pcie_startup_port(pcie);
898 if (err)
899 goto err_setup;
900
901 err = mtk_pcie_setup_irq(pcie);
902 if (err)
903 goto err_setup;
904
905 return 0;
906
907err_setup:
908 mtk_pcie_power_down(pcie);
909
910 return err;
911}
912
913static int mtk_pcie_probe(struct platform_device *pdev)
914{
915 struct device *dev = &pdev->dev;
916 struct mtk_gen3_pcie *pcie;
917 struct pci_host_bridge *host;
918 int err;
919
920 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
921 if (!host)
922 return -ENOMEM;
923
924 pcie = pci_host_bridge_priv(host);
925
926 pcie->dev = dev;
927 platform_set_drvdata(pdev, pcie);
928
929 err = mtk_pcie_setup(pcie);
930 if (err)
931 return err;
932
933 host->ops = &mtk_pcie_ops;
934 host->sysdata = pcie;
935
936 err = pci_host_probe(host);
937 if (err) {
938 mtk_pcie_irq_teardown(pcie);
939 mtk_pcie_power_down(pcie);
940 return err;
941 }
942
943 return 0;
944}
945
946static int mtk_pcie_remove(struct platform_device *pdev)
947{
948 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);
949 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
950
951 pci_lock_rescan_remove();
952 pci_stop_root_bus(host->bus);
953 pci_remove_root_bus(host->bus);
954 pci_unlock_rescan_remove();
955
956 mtk_pcie_irq_teardown(pcie);
957 mtk_pcie_power_down(pcie);
958
959 return 0;
960}
961
962static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)
963{
964 int i;
965
966 raw_spin_lock(&pcie->irq_lock);
967
968 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
969
970 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
971 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
972
973 msi_set->saved_irq_state = readl_relaxed(msi_set->base +
974 PCIE_MSI_SET_ENABLE_OFFSET);
975 }
976
977 raw_spin_unlock(&pcie->irq_lock);
978}
979
980static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie)
981{
982 int i;
983
984 raw_spin_lock(&pcie->irq_lock);
985
986 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
987
988 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
989 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
990
991 writel_relaxed(msi_set->saved_irq_state,
992 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
993 }
994
995 raw_spin_unlock(&pcie->irq_lock);
996}
997
998static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie)
999{
1000 u32 val;
1001
1002 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);
1003 val |= PCIE_TURN_OFF_LINK;
1004 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
1005
1006 /* Check the link is L2 */
1007 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,
1008 (PCIE_LTSSM_STATE(val) ==
1009 PCIE_LTSSM_STATE_L2_IDLE), 20,
1010 50 * USEC_PER_MSEC);
1011}
1012
1013static int mtk_pcie_suspend_noirq(struct device *dev)
1014{
1015 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1016 int err;
1017 u32 val;
1018
1019 /* Trigger link to L2 state */
1020 err = mtk_pcie_turn_off_link(pcie);
1021 if (err) {
1022 dev_err(pcie->dev, "cannot enter L2 state\n");
1023 return err;
1024 }
1025
1026 /* Pull down the PERST# pin */
1027 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
1028 val |= PCIE_PE_RSTB;
1029 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
1030
1031 dev_dbg(pcie->dev, "entered L2 states successfully");
1032
1033 mtk_pcie_irq_save(pcie);
1034 mtk_pcie_power_down(pcie);
1035
1036 return 0;
1037}
1038
1039static int mtk_pcie_resume_noirq(struct device *dev)
1040{
1041 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1042 int err;
1043
1044 err = mtk_pcie_power_up(pcie);
1045 if (err)
1046 return err;
1047
1048 err = mtk_pcie_startup_port(pcie);
1049 if (err) {
1050 mtk_pcie_power_down(pcie);
1051 return err;
1052 }
1053
1054 mtk_pcie_irq_restore(pcie);
1055
1056 return 0;
1057}
1058
1059static const struct dev_pm_ops mtk_pcie_pm_ops = {
1060 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1061 mtk_pcie_resume_noirq)
1062};
1063
1064static const struct of_device_id mtk_pcie_of_match[] = {
1065 { .compatible = "mediatek,mt8192-pcie" },
1066 {},
1067};
1068MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
1069
1070static struct platform_driver mtk_pcie_driver = {
1071 .probe = mtk_pcie_probe,
1072 .remove = mtk_pcie_remove,
1073 .driver = {
1074 .name = "mtk-pcie-gen3",
1075 .of_match_table = mtk_pcie_of_match,
1076 .pm = &mtk_pcie_pm_ops,
1077 },
1078};
1079
1080module_platform_driver(mtk_pcie_driver);
1081MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2020 MediaTek Inc.
6 * Author: Jianjun Wang <jianjun.wang@mediatek.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/iopoll.h>
12#include <linux/irq.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/msi.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/pm_runtime.h>
23#include <linux/reset.h>
24
25#include "../pci.h"
26
27#define PCIE_SETTING_REG 0x80
28#define PCIE_PCI_IDS_1 0x9c
29#define PCI_CLASS(class) (class << 8)
30#define PCIE_RC_MODE BIT(0)
31
32#define PCIE_CFGNUM_REG 0x140
33#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
34#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
35#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))
36#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
37#define PCIE_CFG_OFFSET_ADDR 0x1000
38#define PCIE_CFG_HEADER(bus, devfn) \
39 (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
40
41#define PCIE_RST_CTRL_REG 0x148
42#define PCIE_MAC_RSTB BIT(0)
43#define PCIE_PHY_RSTB BIT(1)
44#define PCIE_BRG_RSTB BIT(2)
45#define PCIE_PE_RSTB BIT(3)
46
47#define PCIE_LTSSM_STATUS_REG 0x150
48#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
49#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
50#define PCIE_LTSSM_STATE_L2_IDLE 0x14
51
52#define PCIE_LINK_STATUS_REG 0x154
53#define PCIE_PORT_LINKUP BIT(8)
54
55#define PCIE_MSI_SET_NUM 8
56#define PCIE_MSI_IRQS_PER_SET 32
57#define PCIE_MSI_IRQS_NUM \
58 (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
59
60#define PCIE_INT_ENABLE_REG 0x180
61#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
62#define PCIE_MSI_SHIFT 8
63#define PCIE_INTX_SHIFT 24
64#define PCIE_INTX_ENABLE \
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
66
67#define PCIE_INT_STATUS_REG 0x184
68#define PCIE_MSI_SET_ENABLE_REG 0x190
69#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
70
71#define PCIE_MSI_SET_BASE_REG 0xc00
72#define PCIE_MSI_SET_OFFSET 0x10
73#define PCIE_MSI_SET_STATUS_OFFSET 0x04
74#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
75
76#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
77#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
78
79#define PCIE_ICMD_PM_REG 0x198
80#define PCIE_TURN_OFF_LINK BIT(4)
81
82#define PCIE_TRANS_TABLE_BASE_REG 0x800
83#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
84#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
85#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
86#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
87#define PCIE_ATR_TLB_SET_OFFSET 0x20
88
89#define PCIE_MAX_TRANS_TABLES 8
90#define PCIE_ATR_EN BIT(0)
91#define PCIE_ATR_SIZE(size) \
92 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
93#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
94#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
95#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
96#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
97#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
98#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
99
100/**
101 * struct mtk_msi_set - MSI information for each set
102 * @base: IO mapped register base
103 * @msg_addr: MSI message address
104 * @saved_irq_state: IRQ enable state saved at suspend time
105 */
106struct mtk_msi_set {
107 void __iomem *base;
108 phys_addr_t msg_addr;
109 u32 saved_irq_state;
110};
111
112/**
113 * struct mtk_pcie_port - PCIe port information
114 * @dev: pointer to PCIe device
115 * @base: IO mapped register base
116 * @reg_base: physical register base
117 * @mac_reset: MAC reset control
118 * @phy_reset: PHY reset control
119 * @phy: PHY controller block
120 * @clks: PCIe clocks
121 * @num_clks: PCIe clocks count for this port
122 * @irq: PCIe controller interrupt number
123 * @saved_irq_state: IRQ enable state saved at suspend time
124 * @irq_lock: lock protecting IRQ register access
125 * @intx_domain: legacy INTx IRQ domain
126 * @msi_domain: MSI IRQ domain
127 * @msi_bottom_domain: MSI IRQ bottom domain
128 * @msi_sets: MSI sets information
129 * @lock: lock protecting IRQ bit map
130 * @msi_irq_in_use: bit map for assigned MSI IRQ
131 */
132struct mtk_pcie_port {
133 struct device *dev;
134 void __iomem *base;
135 phys_addr_t reg_base;
136 struct reset_control *mac_reset;
137 struct reset_control *phy_reset;
138 struct phy *phy;
139 struct clk_bulk_data *clks;
140 int num_clks;
141
142 int irq;
143 u32 saved_irq_state;
144 raw_spinlock_t irq_lock;
145 struct irq_domain *intx_domain;
146 struct irq_domain *msi_domain;
147 struct irq_domain *msi_bottom_domain;
148 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
149 struct mutex lock;
150 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
151};
152
153/**
154 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
155 * @bus: PCI bus to query
156 * @devfn: device/function number
157 * @where: offset in config space
158 * @size: data size in TLP header
159 *
160 * Set byte enable field and device information in configuration TLP header.
161 */
162static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn,
163 int where, int size)
164{
165 struct mtk_pcie_port *port = bus->sysdata;
166 int bytes;
167 u32 val;
168
169 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);
170
171 val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) |
172 PCIE_CFG_HEADER(bus->number, devfn);
173
174 writel_relaxed(val, port->base + PCIE_CFGNUM_REG);
175}
176
177static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
178 int where)
179{
180 struct mtk_pcie_port *port = bus->sysdata;
181
182 return port->base + PCIE_CFG_OFFSET_ADDR + where;
183}
184
185static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
186 int where, int size, u32 *val)
187{
188 mtk_pcie_config_tlp_header(bus, devfn, where, size);
189
190 return pci_generic_config_read32(bus, devfn, where, size, val);
191}
192
193static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
194 int where, int size, u32 val)
195{
196 mtk_pcie_config_tlp_header(bus, devfn, where, size);
197
198 if (size <= 2)
199 val <<= (where & 0x3) * 8;
200
201 return pci_generic_config_write32(bus, devfn, where, 4, val);
202}
203
204static struct pci_ops mtk_pcie_ops = {
205 .map_bus = mtk_pcie_map_bus,
206 .read = mtk_pcie_config_read,
207 .write = mtk_pcie_config_write,
208};
209
210static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,
211 resource_size_t cpu_addr,
212 resource_size_t pci_addr,
213 resource_size_t size,
214 unsigned long type, int num)
215{
216 void __iomem *table;
217 u32 val;
218
219 if (num >= PCIE_MAX_TRANS_TABLES) {
220 dev_err(port->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
221 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
222 return -ENODEV;
223 }
224
225 table = port->base + PCIE_TRANS_TABLE_BASE_REG +
226 num * PCIE_ATR_TLB_SET_OFFSET;
227
228 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1),
229 table);
230 writel_relaxed(upper_32_bits(cpu_addr),
231 table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
232 writel_relaxed(lower_32_bits(pci_addr),
233 table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
234 writel_relaxed(upper_32_bits(pci_addr),
235 table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
236
237 if (type == IORESOURCE_IO)
238 val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
239 else
240 val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
241
242 writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
243
244 return 0;
245}
246
247static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
248{
249 int i;
250 u32 val;
251
252 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
253 struct mtk_msi_set *msi_set = &port->msi_sets[i];
254
255 msi_set->base = port->base + PCIE_MSI_SET_BASE_REG +
256 i * PCIE_MSI_SET_OFFSET;
257 msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG +
258 i * PCIE_MSI_SET_OFFSET;
259
260 /* Configure the MSI capture address */
261 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
262 writel_relaxed(upper_32_bits(msi_set->msg_addr),
263 port->base + PCIE_MSI_SET_ADDR_HI_BASE +
264 i * PCIE_MSI_SET_ADDR_HI_OFFSET);
265 }
266
267 val = readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG);
268 val |= PCIE_MSI_SET_ENABLE;
269 writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG);
270
271 val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
272 val |= PCIE_MSI_ENABLE;
273 writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
274}
275
276static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
277{
278 struct resource_entry *entry;
279 struct pci_host_bridge *host = pci_host_bridge_from_priv(port);
280 unsigned int table_index = 0;
281 int err;
282 u32 val;
283
284 /* Set as RC mode */
285 val = readl_relaxed(port->base + PCIE_SETTING_REG);
286 val |= PCIE_RC_MODE;
287 writel_relaxed(val, port->base + PCIE_SETTING_REG);
288
289 /* Set class code */
290 val = readl_relaxed(port->base + PCIE_PCI_IDS_1);
291 val &= ~GENMASK(31, 8);
292 val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
293 writel_relaxed(val, port->base + PCIE_PCI_IDS_1);
294
295 /* Mask all INTx interrupts */
296 val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
297 val &= ~PCIE_INTX_ENABLE;
298 writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
299
300 /* Assert all reset signals */
301 val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
302 val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
303 writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
304
305 /*
306 * Described in PCIe CEM specification setctions 2.2 (PERST# Signal)
307 * and 2.2.1 (Initial Power-Up (G3 to S0)).
308 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
309 * for the power and clock to become stable.
310 */
311 msleep(100);
312
313 /* De-assert reset signals */
314 val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
315 writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
316
317 /* Check if the link is up or not */
318 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val,
319 !!(val & PCIE_PORT_LINKUP), 20,
320 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
321 if (err) {
322 val = readl_relaxed(port->base + PCIE_LTSSM_STATUS_REG);
323 dev_err(port->dev, "PCIe link down, ltssm reg val: %#x\n", val);
324 return err;
325 }
326
327 mtk_pcie_enable_msi(port);
328
329 /* Set PCIe translation windows */
330 resource_list_for_each_entry(entry, &host->windows) {
331 struct resource *res = entry->res;
332 unsigned long type = resource_type(res);
333 resource_size_t cpu_addr;
334 resource_size_t pci_addr;
335 resource_size_t size;
336 const char *range_type;
337
338 if (type == IORESOURCE_IO) {
339 cpu_addr = pci_pio_to_address(res->start);
340 range_type = "IO";
341 } else if (type == IORESOURCE_MEM) {
342 cpu_addr = res->start;
343 range_type = "MEM";
344 } else {
345 continue;
346 }
347
348 pci_addr = res->start - entry->offset;
349 size = resource_size(res);
350 err = mtk_pcie_set_trans_table(port, cpu_addr, pci_addr, size,
351 type, table_index);
352 if (err)
353 return err;
354
355 dev_dbg(port->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
356 range_type, table_index, (unsigned long long)cpu_addr,
357 (unsigned long long)pci_addr, (unsigned long long)size);
358
359 table_index++;
360 }
361
362 return 0;
363}
364
365static int mtk_pcie_set_affinity(struct irq_data *data,
366 const struct cpumask *mask, bool force)
367{
368 return -EINVAL;
369}
370
371static void mtk_pcie_msi_irq_mask(struct irq_data *data)
372{
373 pci_msi_mask_irq(data);
374 irq_chip_mask_parent(data);
375}
376
377static void mtk_pcie_msi_irq_unmask(struct irq_data *data)
378{
379 pci_msi_unmask_irq(data);
380 irq_chip_unmask_parent(data);
381}
382
383static struct irq_chip mtk_msi_irq_chip = {
384 .irq_ack = irq_chip_ack_parent,
385 .irq_mask = mtk_pcie_msi_irq_mask,
386 .irq_unmask = mtk_pcie_msi_irq_unmask,
387 .name = "MSI",
388};
389
390static struct msi_domain_info mtk_msi_domain_info = {
391 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
392 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
393 .chip = &mtk_msi_irq_chip,
394};
395
396static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
397{
398 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
399 struct mtk_pcie_port *port = data->domain->host_data;
400 unsigned long hwirq;
401
402 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
403
404 msg->address_hi = upper_32_bits(msi_set->msg_addr);
405 msg->address_lo = lower_32_bits(msi_set->msg_addr);
406 msg->data = hwirq;
407 dev_dbg(port->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
408 hwirq, msg->address_hi, msg->address_lo, msg->data);
409}
410
411static void mtk_msi_bottom_irq_ack(struct irq_data *data)
412{
413 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
414 unsigned long hwirq;
415
416 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
417
418 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
419}
420
421static void mtk_msi_bottom_irq_mask(struct irq_data *data)
422{
423 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
424 struct mtk_pcie_port *port = data->domain->host_data;
425 unsigned long hwirq, flags;
426 u32 val;
427
428 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
429
430 raw_spin_lock_irqsave(&port->irq_lock, flags);
431 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
432 val &= ~BIT(hwirq);
433 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
434 raw_spin_unlock_irqrestore(&port->irq_lock, flags);
435}
436
437static void mtk_msi_bottom_irq_unmask(struct irq_data *data)
438{
439 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
440 struct mtk_pcie_port *port = data->domain->host_data;
441 unsigned long hwirq, flags;
442 u32 val;
443
444 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
445
446 raw_spin_lock_irqsave(&port->irq_lock, flags);
447 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
448 val |= BIT(hwirq);
449 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
450 raw_spin_unlock_irqrestore(&port->irq_lock, flags);
451}
452
453static struct irq_chip mtk_msi_bottom_irq_chip = {
454 .irq_ack = mtk_msi_bottom_irq_ack,
455 .irq_mask = mtk_msi_bottom_irq_mask,
456 .irq_unmask = mtk_msi_bottom_irq_unmask,
457 .irq_compose_msi_msg = mtk_compose_msi_msg,
458 .irq_set_affinity = mtk_pcie_set_affinity,
459 .name = "MSI",
460};
461
462static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
463 unsigned int virq, unsigned int nr_irqs,
464 void *arg)
465{
466 struct mtk_pcie_port *port = domain->host_data;
467 struct mtk_msi_set *msi_set;
468 int i, hwirq, set_idx;
469
470 mutex_lock(&port->lock);
471
472 hwirq = bitmap_find_free_region(port->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
473 order_base_2(nr_irqs));
474
475 mutex_unlock(&port->lock);
476
477 if (hwirq < 0)
478 return -ENOSPC;
479
480 set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
481 msi_set = &port->msi_sets[set_idx];
482
483 for (i = 0; i < nr_irqs; i++)
484 irq_domain_set_info(domain, virq + i, hwirq + i,
485 &mtk_msi_bottom_irq_chip, msi_set,
486 handle_edge_irq, NULL, NULL);
487
488 return 0;
489}
490
491static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
492 unsigned int virq, unsigned int nr_irqs)
493{
494 struct mtk_pcie_port *port = domain->host_data;
495 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
496
497 mutex_lock(&port->lock);
498
499 bitmap_release_region(port->msi_irq_in_use, data->hwirq,
500 order_base_2(nr_irqs));
501
502 mutex_unlock(&port->lock);
503
504 irq_domain_free_irqs_common(domain, virq, nr_irqs);
505}
506
507static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {
508 .alloc = mtk_msi_bottom_domain_alloc,
509 .free = mtk_msi_bottom_domain_free,
510};
511
512static void mtk_intx_mask(struct irq_data *data)
513{
514 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
515 unsigned long flags;
516 u32 val;
517
518 raw_spin_lock_irqsave(&port->irq_lock, flags);
519 val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
520 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
521 writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
522 raw_spin_unlock_irqrestore(&port->irq_lock, flags);
523}
524
525static void mtk_intx_unmask(struct irq_data *data)
526{
527 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
528 unsigned long flags;
529 u32 val;
530
531 raw_spin_lock_irqsave(&port->irq_lock, flags);
532 val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
533 val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
534 writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
535 raw_spin_unlock_irqrestore(&port->irq_lock, flags);
536}
537
538/**
539 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
540 * @data: pointer to chip specific data
541 *
542 * As an emulated level IRQ, its interrupt status will remain
543 * until the corresponding de-assert message is received; hence that
544 * the status can only be cleared when the interrupt has been serviced.
545 */
546static void mtk_intx_eoi(struct irq_data *data)
547{
548 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
549 unsigned long hwirq;
550
551 hwirq = data->hwirq + PCIE_INTX_SHIFT;
552 writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
553}
554
555static struct irq_chip mtk_intx_irq_chip = {
556 .irq_mask = mtk_intx_mask,
557 .irq_unmask = mtk_intx_unmask,
558 .irq_eoi = mtk_intx_eoi,
559 .irq_set_affinity = mtk_pcie_set_affinity,
560 .name = "INTx",
561};
562
563static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
564 irq_hw_number_t hwirq)
565{
566 irq_set_chip_data(irq, domain->host_data);
567 irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
568 handle_fasteoi_irq, "INTx");
569 return 0;
570}
571
572static const struct irq_domain_ops intx_domain_ops = {
573 .map = mtk_pcie_intx_map,
574};
575
576static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)
577{
578 struct device *dev = port->dev;
579 struct device_node *intc_node, *node = dev->of_node;
580 int ret;
581
582 raw_spin_lock_init(&port->irq_lock);
583
584 /* Setup INTx */
585 intc_node = of_get_child_by_name(node, "interrupt-controller");
586 if (!intc_node) {
587 dev_err(dev, "missing interrupt-controller node\n");
588 return -ENODEV;
589 }
590
591 port->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
592 &intx_domain_ops, port);
593 if (!port->intx_domain) {
594 dev_err(dev, "failed to create INTx IRQ domain\n");
595 return -ENODEV;
596 }
597
598 /* Setup MSI */
599 mutex_init(&port->lock);
600
601 port->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
602 &mtk_msi_bottom_domain_ops, port);
603 if (!port->msi_bottom_domain) {
604 dev_err(dev, "failed to create MSI bottom domain\n");
605 ret = -ENODEV;
606 goto err_msi_bottom_domain;
607 }
608
609 port->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
610 &mtk_msi_domain_info,
611 port->msi_bottom_domain);
612 if (!port->msi_domain) {
613 dev_err(dev, "failed to create MSI domain\n");
614 ret = -ENODEV;
615 goto err_msi_domain;
616 }
617
618 return 0;
619
620err_msi_domain:
621 irq_domain_remove(port->msi_bottom_domain);
622err_msi_bottom_domain:
623 irq_domain_remove(port->intx_domain);
624
625 return ret;
626}
627
628static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port)
629{
630 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
631
632 if (port->intx_domain)
633 irq_domain_remove(port->intx_domain);
634
635 if (port->msi_domain)
636 irq_domain_remove(port->msi_domain);
637
638 if (port->msi_bottom_domain)
639 irq_domain_remove(port->msi_bottom_domain);
640
641 irq_dispose_mapping(port->irq);
642}
643
644static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx)
645{
646 struct mtk_msi_set *msi_set = &port->msi_sets[set_idx];
647 unsigned long msi_enable, msi_status;
648 unsigned int virq;
649 irq_hw_number_t bit, hwirq;
650
651 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
652
653 do {
654 msi_status = readl_relaxed(msi_set->base +
655 PCIE_MSI_SET_STATUS_OFFSET);
656 msi_status &= msi_enable;
657 if (!msi_status)
658 break;
659
660 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
661 hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
662 virq = irq_find_mapping(port->msi_bottom_domain, hwirq);
663 generic_handle_irq(virq);
664 }
665 } while (true);
666}
667
668static void mtk_pcie_irq_handler(struct irq_desc *desc)
669{
670 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
671 struct irq_chip *irqchip = irq_desc_get_chip(desc);
672 unsigned long status;
673 unsigned int virq;
674 irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
675
676 chained_irq_enter(irqchip, desc);
677
678 status = readl_relaxed(port->base + PCIE_INT_STATUS_REG);
679 for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
680 PCIE_INTX_SHIFT) {
681 virq = irq_find_mapping(port->intx_domain,
682 irq_bit - PCIE_INTX_SHIFT);
683 generic_handle_irq(virq);
684 }
685
686 irq_bit = PCIE_MSI_SHIFT;
687 for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
688 PCIE_MSI_SHIFT) {
689 mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT);
690
691 writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG);
692 }
693
694 chained_irq_exit(irqchip, desc);
695}
696
697static int mtk_pcie_setup_irq(struct mtk_pcie_port *port)
698{
699 struct device *dev = port->dev;
700 struct platform_device *pdev = to_platform_device(dev);
701 int err;
702
703 err = mtk_pcie_init_irq_domains(port);
704 if (err)
705 return err;
706
707 port->irq = platform_get_irq(pdev, 0);
708 if (port->irq < 0)
709 return port->irq;
710
711 irq_set_chained_handler_and_data(port->irq, mtk_pcie_irq_handler, port);
712
713 return 0;
714}
715
716static int mtk_pcie_parse_port(struct mtk_pcie_port *port)
717{
718 struct device *dev = port->dev;
719 struct platform_device *pdev = to_platform_device(dev);
720 struct resource *regs;
721 int ret;
722
723 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
724 if (!regs)
725 return -EINVAL;
726 port->base = devm_ioremap_resource(dev, regs);
727 if (IS_ERR(port->base)) {
728 dev_err(dev, "failed to map register base\n");
729 return PTR_ERR(port->base);
730 }
731
732 port->reg_base = regs->start;
733
734 port->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
735 if (IS_ERR(port->phy_reset)) {
736 ret = PTR_ERR(port->phy_reset);
737 if (ret != -EPROBE_DEFER)
738 dev_err(dev, "failed to get PHY reset\n");
739
740 return ret;
741 }
742
743 port->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
744 if (IS_ERR(port->mac_reset)) {
745 ret = PTR_ERR(port->mac_reset);
746 if (ret != -EPROBE_DEFER)
747 dev_err(dev, "failed to get MAC reset\n");
748
749 return ret;
750 }
751
752 port->phy = devm_phy_optional_get(dev, "pcie-phy");
753 if (IS_ERR(port->phy)) {
754 ret = PTR_ERR(port->phy);
755 if (ret != -EPROBE_DEFER)
756 dev_err(dev, "failed to get PHY\n");
757
758 return ret;
759 }
760
761 port->num_clks = devm_clk_bulk_get_all(dev, &port->clks);
762 if (port->num_clks < 0) {
763 dev_err(dev, "failed to get clocks\n");
764 return port->num_clks;
765 }
766
767 return 0;
768}
769
770static int mtk_pcie_power_up(struct mtk_pcie_port *port)
771{
772 struct device *dev = port->dev;
773 int err;
774
775 /* PHY power on and enable pipe clock */
776 reset_control_deassert(port->phy_reset);
777
778 err = phy_init(port->phy);
779 if (err) {
780 dev_err(dev, "failed to initialize PHY\n");
781 goto err_phy_init;
782 }
783
784 err = phy_power_on(port->phy);
785 if (err) {
786 dev_err(dev, "failed to power on PHY\n");
787 goto err_phy_on;
788 }
789
790 /* MAC power on and enable transaction layer clocks */
791 reset_control_deassert(port->mac_reset);
792
793 pm_runtime_enable(dev);
794 pm_runtime_get_sync(dev);
795
796 err = clk_bulk_prepare_enable(port->num_clks, port->clks);
797 if (err) {
798 dev_err(dev, "failed to enable clocks\n");
799 goto err_clk_init;
800 }
801
802 return 0;
803
804err_clk_init:
805 pm_runtime_put_sync(dev);
806 pm_runtime_disable(dev);
807 reset_control_assert(port->mac_reset);
808 phy_power_off(port->phy);
809err_phy_on:
810 phy_exit(port->phy);
811err_phy_init:
812 reset_control_assert(port->phy_reset);
813
814 return err;
815}
816
817static void mtk_pcie_power_down(struct mtk_pcie_port *port)
818{
819 clk_bulk_disable_unprepare(port->num_clks, port->clks);
820
821 pm_runtime_put_sync(port->dev);
822 pm_runtime_disable(port->dev);
823 reset_control_assert(port->mac_reset);
824
825 phy_power_off(port->phy);
826 phy_exit(port->phy);
827 reset_control_assert(port->phy_reset);
828}
829
830static int mtk_pcie_setup(struct mtk_pcie_port *port)
831{
832 int err;
833
834 err = mtk_pcie_parse_port(port);
835 if (err)
836 return err;
837
838 /* Don't touch the hardware registers before power up */
839 err = mtk_pcie_power_up(port);
840 if (err)
841 return err;
842
843 /* Try link up */
844 err = mtk_pcie_startup_port(port);
845 if (err)
846 goto err_setup;
847
848 err = mtk_pcie_setup_irq(port);
849 if (err)
850 goto err_setup;
851
852 return 0;
853
854err_setup:
855 mtk_pcie_power_down(port);
856
857 return err;
858}
859
860static int mtk_pcie_probe(struct platform_device *pdev)
861{
862 struct device *dev = &pdev->dev;
863 struct mtk_pcie_port *port;
864 struct pci_host_bridge *host;
865 int err;
866
867 host = devm_pci_alloc_host_bridge(dev, sizeof(*port));
868 if (!host)
869 return -ENOMEM;
870
871 port = pci_host_bridge_priv(host);
872
873 port->dev = dev;
874 platform_set_drvdata(pdev, port);
875
876 err = mtk_pcie_setup(port);
877 if (err)
878 return err;
879
880 host->ops = &mtk_pcie_ops;
881 host->sysdata = port;
882
883 err = pci_host_probe(host);
884 if (err) {
885 mtk_pcie_irq_teardown(port);
886 mtk_pcie_power_down(port);
887 return err;
888 }
889
890 return 0;
891}
892
893static int mtk_pcie_remove(struct platform_device *pdev)
894{
895 struct mtk_pcie_port *port = platform_get_drvdata(pdev);
896 struct pci_host_bridge *host = pci_host_bridge_from_priv(port);
897
898 pci_lock_rescan_remove();
899 pci_stop_root_bus(host->bus);
900 pci_remove_root_bus(host->bus);
901 pci_unlock_rescan_remove();
902
903 mtk_pcie_irq_teardown(port);
904 mtk_pcie_power_down(port);
905
906 return 0;
907}
908
909static void __maybe_unused mtk_pcie_irq_save(struct mtk_pcie_port *port)
910{
911 int i;
912
913 raw_spin_lock(&port->irq_lock);
914
915 port->saved_irq_state = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
916
917 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
918 struct mtk_msi_set *msi_set = &port->msi_sets[i];
919
920 msi_set->saved_irq_state = readl_relaxed(msi_set->base +
921 PCIE_MSI_SET_ENABLE_OFFSET);
922 }
923
924 raw_spin_unlock(&port->irq_lock);
925}
926
927static void __maybe_unused mtk_pcie_irq_restore(struct mtk_pcie_port *port)
928{
929 int i;
930
931 raw_spin_lock(&port->irq_lock);
932
933 writel_relaxed(port->saved_irq_state, port->base + PCIE_INT_ENABLE_REG);
934
935 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
936 struct mtk_msi_set *msi_set = &port->msi_sets[i];
937
938 writel_relaxed(msi_set->saved_irq_state,
939 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
940 }
941
942 raw_spin_unlock(&port->irq_lock);
943}
944
945static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
946{
947 u32 val;
948
949 val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
950 val |= PCIE_TURN_OFF_LINK;
951 writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
952
953 /* Check the link is L2 */
954 return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
955 (PCIE_LTSSM_STATE(val) ==
956 PCIE_LTSSM_STATE_L2_IDLE), 20,
957 50 * USEC_PER_MSEC);
958}
959
960static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
961{
962 struct mtk_pcie_port *port = dev_get_drvdata(dev);
963 int err;
964 u32 val;
965
966 /* Trigger link to L2 state */
967 err = mtk_pcie_turn_off_link(port);
968 if (err) {
969 dev_err(port->dev, "cannot enter L2 state\n");
970 return err;
971 }
972
973 /* Pull down the PERST# pin */
974 val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
975 val |= PCIE_PE_RSTB;
976 writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
977
978 dev_dbg(port->dev, "entered L2 states successfully");
979
980 mtk_pcie_irq_save(port);
981 mtk_pcie_power_down(port);
982
983 return 0;
984}
985
986static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
987{
988 struct mtk_pcie_port *port = dev_get_drvdata(dev);
989 int err;
990
991 err = mtk_pcie_power_up(port);
992 if (err)
993 return err;
994
995 err = mtk_pcie_startup_port(port);
996 if (err) {
997 mtk_pcie_power_down(port);
998 return err;
999 }
1000
1001 mtk_pcie_irq_restore(port);
1002
1003 return 0;
1004}
1005
1006static const struct dev_pm_ops mtk_pcie_pm_ops = {
1007 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1008 mtk_pcie_resume_noirq)
1009};
1010
1011static const struct of_device_id mtk_pcie_of_match[] = {
1012 { .compatible = "mediatek,mt8192-pcie" },
1013 {},
1014};
1015MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
1016
1017static struct platform_driver mtk_pcie_driver = {
1018 .probe = mtk_pcie_probe,
1019 .remove = mtk_pcie_remove,
1020 .driver = {
1021 .name = "mtk-pcie",
1022 .of_match_table = mtk_pcie_of_match,
1023 .pm = &mtk_pcie_pm_ops,
1024 },
1025};
1026
1027module_platform_driver(mtk_pcie_driver);
1028MODULE_LICENSE("GPL v2");