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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017 Cadence
3// Cadence PCIe endpoint controller driver.
4// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
5
6#include <linux/delay.h>
7#include <linux/kernel.h>
8#include <linux/of.h>
9#include <linux/pci-epc.h>
10#include <linux/platform_device.h>
11#include <linux/sizes.h>
12
13#include "pcie-cadence.h"
14
15#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
16#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
17#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
18
19static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn)
20{
21 u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
22 u32 first_vf_offset, stride;
23
24 if (vfn == 0)
25 return fn;
26
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET);
28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE);
29 fn = fn + first_vf_offset + ((vfn - 1) * stride);
30
31 return fn;
32}
33
34static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
35 struct pci_epf_header *hdr)
36{
37 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
38 u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
39 struct cdns_pcie *pcie = &ep->pcie;
40 u32 reg;
41
42 if (vfn > 1) {
43 dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n");
44 return -EINVAL;
45 } else if (vfn == 1) {
46 reg = cap + PCI_SRIOV_VF_DID;
47 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid);
48 return 0;
49 }
50
51 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
52 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
53 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
54 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
55 hdr->subclass_code | hdr->baseclass_code << 8);
56 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
57 hdr->cache_line_size);
58 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
59 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
60
61 /*
62 * Vendor ID can only be modified from function 0, all other functions
63 * use the same vendor ID as function 0.
64 */
65 if (fn == 0) {
66 /* Update the vendor IDs. */
67 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
68 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
69
70 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
71 }
72
73 return 0;
74}
75
76static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
77 struct pci_epf_bar *epf_bar)
78{
79 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
80 struct cdns_pcie_epf *epf = &ep->epf[fn];
81 struct cdns_pcie *pcie = &ep->pcie;
82 dma_addr_t bar_phys = epf_bar->phys_addr;
83 enum pci_barno bar = epf_bar->barno;
84 int flags = epf_bar->flags;
85 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
86 u64 sz;
87
88 /* BAR size is 2^(aperture + 7) */
89 sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
90 /*
91 * roundup_pow_of_two() returns an unsigned long, which is not suited
92 * for 64bit values.
93 */
94 sz = 1ULL << fls64(sz - 1);
95 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
96
97 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
98 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
99 } else {
100 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
101 bool is_64bits = sz > SZ_2G;
102
103 if (is_64bits && (bar & 1))
104 return -EINVAL;
105
106 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
107 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
108
109 if (is_64bits && is_prefetch)
110 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
111 else if (is_prefetch)
112 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
113 else if (is_64bits)
114 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
115 else
116 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
117 }
118
119 addr0 = lower_32_bits(bar_phys);
120 addr1 = upper_32_bits(bar_phys);
121
122 if (vfn == 1)
123 reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);
124 else
125 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);
126 b = (bar < BAR_4) ? bar : bar - BAR_4;
127
128 if (vfn == 0 || vfn == 1) {
129 cfg = cdns_pcie_readl(pcie, reg);
130 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
131 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
132 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
133 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
134 cdns_pcie_writel(pcie, reg, cfg);
135 }
136
137 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
138 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
139 addr0);
140 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
141 addr1);
142
143 if (vfn > 0)
144 epf = &epf->epf[vfn - 1];
145 epf->epf_bar[bar] = epf_bar;
146
147 return 0;
148}
149
150static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
151 struct pci_epf_bar *epf_bar)
152{
153 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
154 struct cdns_pcie_epf *epf = &ep->epf[fn];
155 struct cdns_pcie *pcie = &ep->pcie;
156 enum pci_barno bar = epf_bar->barno;
157 u32 reg, cfg, b, ctrl;
158
159 if (vfn == 1)
160 reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);
161 else
162 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);
163 b = (bar < BAR_4) ? bar : bar - BAR_4;
164
165 if (vfn == 0 || vfn == 1) {
166 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
167 cfg = cdns_pcie_readl(pcie, reg);
168 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
169 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
170 cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
171 cdns_pcie_writel(pcie, reg, cfg);
172 }
173
174 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
175 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
176 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
177
178 if (vfn > 0)
179 epf = &epf->epf[vfn - 1];
180 epf->epf_bar[bar] = NULL;
181}
182
183static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
184 phys_addr_t addr, u64 pci_addr, size_t size)
185{
186 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
187 struct cdns_pcie *pcie = &ep->pcie;
188 u32 r;
189
190 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
191 if (r >= ep->max_regions - 1) {
192 dev_err(&epc->dev, "no free outbound region\n");
193 return -EINVAL;
194 }
195
196 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
197 cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size);
198
199 set_bit(r, &ep->ob_region_map);
200 ep->ob_addr[r] = addr;
201
202 return 0;
203}
204
205static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
206 phys_addr_t addr)
207{
208 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
209 struct cdns_pcie *pcie = &ep->pcie;
210 u32 r;
211
212 for (r = 0; r < ep->max_regions - 1; r++)
213 if (ep->ob_addr[r] == addr)
214 break;
215
216 if (r == ep->max_regions - 1)
217 return;
218
219 cdns_pcie_reset_outbound_region(pcie, r);
220
221 ep->ob_addr[r] = 0;
222 clear_bit(r, &ep->ob_region_map);
223}
224
225static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc)
226{
227 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
228 struct cdns_pcie *pcie = &ep->pcie;
229 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
230 u16 flags;
231
232 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
233
234 /*
235 * Set the Multiple Message Capable bitfield into the Message Control
236 * register.
237 */
238 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
239 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
240 flags |= PCI_MSI_FLAGS_64BIT;
241 flags &= ~PCI_MSI_FLAGS_MASKBIT;
242 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
243
244 return 0;
245}
246
247static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
248{
249 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
250 struct cdns_pcie *pcie = &ep->pcie;
251 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
252 u16 flags, mme;
253
254 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
255
256 /* Validate that the MSI feature is actually enabled. */
257 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
258 if (!(flags & PCI_MSI_FLAGS_ENABLE))
259 return -EINVAL;
260
261 /*
262 * Get the Multiple Message Enable bitfield from the Message Control
263 * register.
264 */
265 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
266
267 return mme;
268}
269
270static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
271{
272 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
273 struct cdns_pcie *pcie = &ep->pcie;
274 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
275 u32 val, reg;
276
277 func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no);
278
279 reg = cap + PCI_MSIX_FLAGS;
280 val = cdns_pcie_ep_fn_readw(pcie, func_no, reg);
281 if (!(val & PCI_MSIX_FLAGS_ENABLE))
282 return -EINVAL;
283
284 val &= PCI_MSIX_FLAGS_QSIZE;
285
286 return val;
287}
288
289static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
290 u16 interrupts, enum pci_barno bir,
291 u32 offset)
292{
293 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
294 struct cdns_pcie *pcie = &ep->pcie;
295 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
296 u32 val, reg;
297
298 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
299
300 reg = cap + PCI_MSIX_FLAGS;
301 val = cdns_pcie_ep_fn_readw(pcie, fn, reg);
302 val &= ~PCI_MSIX_FLAGS_QSIZE;
303 val |= interrupts;
304 cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
305
306 /* Set MSIX BAR and offset */
307 reg = cap + PCI_MSIX_TABLE;
308 val = offset | bir;
309 cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
310
311 /* Set PBA BAR and offset. BAR must match MSIX BAR */
312 reg = cap + PCI_MSIX_PBA;
313 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
314 cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
315
316 return 0;
317}
318
319static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx,
320 bool is_asserted)
321{
322 struct cdns_pcie *pcie = &ep->pcie;
323 unsigned long flags;
324 u32 offset;
325 u16 status;
326 u8 msg_code;
327
328 intx &= 3;
329
330 /* Set the outbound region if needed. */
331 if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
332 ep->irq_pci_fn != fn)) {
333 /* First region was reserved for IRQ writes. */
334 cdns_pcie_set_outbound_region_for_normal_msg(pcie, 0, fn, 0,
335 ep->irq_phys_addr);
336 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
337 ep->irq_pci_fn = fn;
338 }
339
340 if (is_asserted) {
341 ep->irq_pending |= BIT(intx);
342 msg_code = MSG_CODE_ASSERT_INTA + intx;
343 } else {
344 ep->irq_pending &= ~BIT(intx);
345 msg_code = MSG_CODE_DEASSERT_INTA + intx;
346 }
347
348 spin_lock_irqsave(&ep->lock, flags);
349 status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
350 if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
351 status ^= PCI_STATUS_INTERRUPT;
352 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
353 }
354 spin_unlock_irqrestore(&ep->lock, flags);
355
356 offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
357 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
358 CDNS_PCIE_MSG_NO_DATA;
359 writel(0, ep->irq_cpu_addr + offset);
360}
361
362static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
363 u8 intx)
364{
365 u16 cmd;
366
367 cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
368 if (cmd & PCI_COMMAND_INTX_DISABLE)
369 return -EINVAL;
370
371 cdns_pcie_ep_assert_intx(ep, fn, intx, true);
372 /*
373 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
374 */
375 mdelay(1);
376 cdns_pcie_ep_assert_intx(ep, fn, intx, false);
377 return 0;
378}
379
380static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
381 u8 interrupt_num)
382{
383 struct cdns_pcie *pcie = &ep->pcie;
384 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
385 u16 flags, mme, data, data_mask;
386 u8 msi_count;
387 u64 pci_addr, pci_addr_mask = 0xff;
388
389 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
390
391 /* Check whether the MSI feature has been enabled by the PCI host. */
392 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
393 if (!(flags & PCI_MSI_FLAGS_ENABLE))
394 return -EINVAL;
395
396 /* Get the number of enabled MSIs */
397 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
398 msi_count = 1 << mme;
399 if (!interrupt_num || interrupt_num > msi_count)
400 return -EINVAL;
401
402 /* Compute the data value to be written. */
403 data_mask = msi_count - 1;
404 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
405 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
406
407 /* Get the PCI address where to write the data into. */
408 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
409 pci_addr <<= 32;
410 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
411 pci_addr &= GENMASK_ULL(63, 2);
412
413 /* Set the outbound region if needed. */
414 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
415 ep->irq_pci_fn != fn)) {
416 /* First region was reserved for IRQ writes. */
417 cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
418 false,
419 ep->irq_phys_addr,
420 pci_addr & ~pci_addr_mask,
421 pci_addr_mask + 1);
422 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
423 ep->irq_pci_fn = fn;
424 }
425 writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
426
427 return 0;
428}
429
430static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn,
431 phys_addr_t addr, u8 interrupt_num,
432 u32 entry_size, u32 *msi_data,
433 u32 *msi_addr_offset)
434{
435 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
436 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
437 struct cdns_pcie *pcie = &ep->pcie;
438 u64 pci_addr, pci_addr_mask = 0xff;
439 u16 flags, mme, data, data_mask;
440 u8 msi_count;
441 int ret;
442 int i;
443
444 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
445
446 /* Check whether the MSI feature has been enabled by the PCI host. */
447 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
448 if (!(flags & PCI_MSI_FLAGS_ENABLE))
449 return -EINVAL;
450
451 /* Get the number of enabled MSIs */
452 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
453 msi_count = 1 << mme;
454 if (!interrupt_num || interrupt_num > msi_count)
455 return -EINVAL;
456
457 /* Compute the data value to be written. */
458 data_mask = msi_count - 1;
459 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
460 data = data & ~data_mask;
461
462 /* Get the PCI address where to write the data into. */
463 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
464 pci_addr <<= 32;
465 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
466 pci_addr &= GENMASK_ULL(63, 2);
467
468 for (i = 0; i < interrupt_num; i++) {
469 ret = cdns_pcie_ep_map_addr(epc, fn, vfn, addr,
470 pci_addr & ~pci_addr_mask,
471 entry_size);
472 if (ret)
473 return ret;
474 addr = addr + entry_size;
475 }
476
477 *msi_data = data;
478 *msi_addr_offset = pci_addr & pci_addr_mask;
479
480 return 0;
481}
482
483static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
484 u16 interrupt_num)
485{
486 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
487 u32 tbl_offset, msg_data, reg;
488 struct cdns_pcie *pcie = &ep->pcie;
489 struct pci_epf_msix_tbl *msix_tbl;
490 struct cdns_pcie_epf *epf;
491 u64 pci_addr_mask = 0xff;
492 u64 msg_addr;
493 u16 flags;
494 u8 bir;
495
496 epf = &ep->epf[fn];
497 if (vfn > 0)
498 epf = &epf->epf[vfn - 1];
499
500 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
501
502 /* Check whether the MSI-X feature has been enabled by the PCI host. */
503 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS);
504 if (!(flags & PCI_MSIX_FLAGS_ENABLE))
505 return -EINVAL;
506
507 reg = cap + PCI_MSIX_TABLE;
508 tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg);
509 bir = tbl_offset & PCI_MSIX_TABLE_BIR;
510 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
511
512 msix_tbl = epf->epf_bar[bir]->addr + tbl_offset;
513 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
514 msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
515
516 /* Set the outbound region if needed. */
517 if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) ||
518 ep->irq_pci_fn != fn) {
519 /* First region was reserved for IRQ writes. */
520 cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
521 false,
522 ep->irq_phys_addr,
523 msg_addr & ~pci_addr_mask,
524 pci_addr_mask + 1);
525 ep->irq_pci_addr = (msg_addr & ~pci_addr_mask);
526 ep->irq_pci_fn = fn;
527 }
528 writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask));
529
530 return 0;
531}
532
533static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
534 enum pci_epc_irq_type type,
535 u16 interrupt_num)
536{
537 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
538 struct cdns_pcie *pcie = &ep->pcie;
539 struct device *dev = pcie->dev;
540
541 switch (type) {
542 case PCI_EPC_IRQ_LEGACY:
543 if (vfn > 0) {
544 dev_err(dev, "Cannot raise legacy interrupts for VF\n");
545 return -EINVAL;
546 }
547 return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);
548
549 case PCI_EPC_IRQ_MSI:
550 return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num);
551
552 case PCI_EPC_IRQ_MSIX:
553 return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num);
554
555 default:
556 break;
557 }
558
559 return -EINVAL;
560}
561
562static int cdns_pcie_ep_start(struct pci_epc *epc)
563{
564 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
565 struct cdns_pcie *pcie = &ep->pcie;
566 struct device *dev = pcie->dev;
567 int max_epfs = sizeof(epc->function_num_map) * 8;
568 int ret, value, epf;
569
570 /*
571 * BIT(0) is hardwired to 1, hence function 0 is always enabled
572 * and can't be disabled anyway.
573 */
574 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);
575
576 if (ep->quirk_disable_flr) {
577 for (epf = 0; epf < max_epfs; epf++) {
578 if (!(epc->function_num_map & BIT(epf)))
579 continue;
580
581 value = cdns_pcie_ep_fn_readl(pcie, epf,
582 CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
583 PCI_EXP_DEVCAP);
584 value &= ~PCI_EXP_DEVCAP_FLR;
585 cdns_pcie_ep_fn_writel(pcie, epf,
586 CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
587 PCI_EXP_DEVCAP, value);
588 }
589 }
590
591 ret = cdns_pcie_start_link(pcie);
592 if (ret) {
593 dev_err(dev, "Failed to start link\n");
594 return ret;
595 }
596
597 return 0;
598}
599
600static const struct pci_epc_features cdns_pcie_epc_vf_features = {
601 .linkup_notifier = false,
602 .msi_capable = true,
603 .msix_capable = true,
604 .align = 65536,
605};
606
607static const struct pci_epc_features cdns_pcie_epc_features = {
608 .linkup_notifier = false,
609 .msi_capable = true,
610 .msix_capable = true,
611 .align = 256,
612};
613
614static const struct pci_epc_features*
615cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
616{
617 if (!vfunc_no)
618 return &cdns_pcie_epc_features;
619
620 return &cdns_pcie_epc_vf_features;
621}
622
623static const struct pci_epc_ops cdns_pcie_epc_ops = {
624 .write_header = cdns_pcie_ep_write_header,
625 .set_bar = cdns_pcie_ep_set_bar,
626 .clear_bar = cdns_pcie_ep_clear_bar,
627 .map_addr = cdns_pcie_ep_map_addr,
628 .unmap_addr = cdns_pcie_ep_unmap_addr,
629 .set_msi = cdns_pcie_ep_set_msi,
630 .get_msi = cdns_pcie_ep_get_msi,
631 .set_msix = cdns_pcie_ep_set_msix,
632 .get_msix = cdns_pcie_ep_get_msix,
633 .raise_irq = cdns_pcie_ep_raise_irq,
634 .map_msi_irq = cdns_pcie_ep_map_msi_irq,
635 .start = cdns_pcie_ep_start,
636 .get_features = cdns_pcie_ep_get_features,
637};
638
639
640int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
641{
642 struct device *dev = ep->pcie.dev;
643 struct platform_device *pdev = to_platform_device(dev);
644 struct device_node *np = dev->of_node;
645 struct cdns_pcie *pcie = &ep->pcie;
646 struct cdns_pcie_epf *epf;
647 struct resource *res;
648 struct pci_epc *epc;
649 int ret;
650 int i;
651
652 pcie->is_rc = false;
653
654 pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
655 if (IS_ERR(pcie->reg_base)) {
656 dev_err(dev, "missing \"reg\"\n");
657 return PTR_ERR(pcie->reg_base);
658 }
659
660 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
661 if (!res) {
662 dev_err(dev, "missing \"mem\"\n");
663 return -EINVAL;
664 }
665 pcie->mem_res = res;
666
667 ep->max_regions = CDNS_PCIE_MAX_OB;
668 of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions);
669
670 ep->ob_addr = devm_kcalloc(dev,
671 ep->max_regions, sizeof(*ep->ob_addr),
672 GFP_KERNEL);
673 if (!ep->ob_addr)
674 return -ENOMEM;
675
676 /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
677 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
678
679 epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
680 if (IS_ERR(epc)) {
681 dev_err(dev, "failed to create epc device\n");
682 return PTR_ERR(epc);
683 }
684
685 epc_set_drvdata(epc, ep);
686
687 if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
688 epc->max_functions = 1;
689
690 ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf),
691 GFP_KERNEL);
692 if (!ep->epf)
693 return -ENOMEM;
694
695 epc->max_vfs = devm_kcalloc(dev, epc->max_functions,
696 sizeof(*epc->max_vfs), GFP_KERNEL);
697 if (!epc->max_vfs)
698 return -ENOMEM;
699
700 ret = of_property_read_u8_array(np, "max-virtual-functions",
701 epc->max_vfs, epc->max_functions);
702 if (ret == 0) {
703 for (i = 0; i < epc->max_functions; i++) {
704 epf = &ep->epf[i];
705 if (epc->max_vfs[i] == 0)
706 continue;
707 epf->epf = devm_kcalloc(dev, epc->max_vfs[i],
708 sizeof(*ep->epf), GFP_KERNEL);
709 if (!epf->epf)
710 return -ENOMEM;
711 }
712 }
713
714 ret = pci_epc_mem_init(epc, pcie->mem_res->start,
715 resource_size(pcie->mem_res), PAGE_SIZE);
716 if (ret < 0) {
717 dev_err(dev, "failed to initialize the memory space\n");
718 return ret;
719 }
720
721 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
722 SZ_128K);
723 if (!ep->irq_cpu_addr) {
724 dev_err(dev, "failed to reserve memory space for MSI\n");
725 ret = -ENOMEM;
726 goto free_epc_mem;
727 }
728 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
729 /* Reserve region 0 for IRQs */
730 set_bit(0, &ep->ob_region_map);
731
732 if (ep->quirk_detect_quiet_flag)
733 cdns_pcie_detect_quiet_min_delay_set(&ep->pcie);
734
735 spin_lock_init(&ep->lock);
736
737 return 0;
738
739 free_epc_mem:
740 pci_epc_mem_exit(epc);
741
742 return ret;
743}
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017 Cadence
3// Cadence PCIe endpoint controller driver.
4// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
5
6#include <linux/delay.h>
7#include <linux/kernel.h>
8#include <linux/of.h>
9#include <linux/pci-epc.h>
10#include <linux/platform_device.h>
11#include <linux/sizes.h>
12
13#include "pcie-cadence.h"
14
15#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
16#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
17#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
18
19static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
20 struct pci_epf_header *hdr)
21{
22 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
23 struct cdns_pcie *pcie = &ep->pcie;
24
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
28 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
29 hdr->subclass_code | hdr->baseclass_code << 8);
30 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
31 hdr->cache_line_size);
32 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
33 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
34
35 /*
36 * Vendor ID can only be modified from function 0, all other functions
37 * use the same vendor ID as function 0.
38 */
39 if (fn == 0) {
40 /* Update the vendor IDs. */
41 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
42 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
43
44 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
45 }
46
47 return 0;
48}
49
50static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
51 struct pci_epf_bar *epf_bar)
52{
53 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
54 struct cdns_pcie_epf *epf = &ep->epf[fn];
55 struct cdns_pcie *pcie = &ep->pcie;
56 dma_addr_t bar_phys = epf_bar->phys_addr;
57 enum pci_barno bar = epf_bar->barno;
58 int flags = epf_bar->flags;
59 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
60 u64 sz;
61
62 /* BAR size is 2^(aperture + 7) */
63 sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
64 /*
65 * roundup_pow_of_two() returns an unsigned long, which is not suited
66 * for 64bit values.
67 */
68 sz = 1ULL << fls64(sz - 1);
69 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
70
71 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
72 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
73 } else {
74 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
75 bool is_64bits = sz > SZ_2G;
76
77 if (is_64bits && (bar & 1))
78 return -EINVAL;
79
80 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
81 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
82
83 if (is_64bits && is_prefetch)
84 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
85 else if (is_prefetch)
86 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
87 else if (is_64bits)
88 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
89 else
90 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
91 }
92
93 addr0 = lower_32_bits(bar_phys);
94 addr1 = upper_32_bits(bar_phys);
95 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
96 addr0);
97 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
98 addr1);
99
100 if (bar < BAR_4) {
101 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
102 b = bar;
103 } else {
104 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
105 b = bar - BAR_4;
106 }
107
108 cfg = cdns_pcie_readl(pcie, reg);
109 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
110 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
111 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
112 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
113 cdns_pcie_writel(pcie, reg, cfg);
114
115 epf->epf_bar[bar] = epf_bar;
116
117 return 0;
118}
119
120static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
121 struct pci_epf_bar *epf_bar)
122{
123 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
124 struct cdns_pcie_epf *epf = &ep->epf[fn];
125 struct cdns_pcie *pcie = &ep->pcie;
126 enum pci_barno bar = epf_bar->barno;
127 u32 reg, cfg, b, ctrl;
128
129 if (bar < BAR_4) {
130 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
131 b = bar;
132 } else {
133 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
134 b = bar - BAR_4;
135 }
136
137 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
138 cfg = cdns_pcie_readl(pcie, reg);
139 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
140 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
141 cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
142 cdns_pcie_writel(pcie, reg, cfg);
143
144 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
145 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
146
147 epf->epf_bar[bar] = NULL;
148}
149
150static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
151 u64 pci_addr, size_t size)
152{
153 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
154 struct cdns_pcie *pcie = &ep->pcie;
155 u32 r;
156
157 r = find_first_zero_bit(&ep->ob_region_map,
158 sizeof(ep->ob_region_map) * BITS_PER_LONG);
159 if (r >= ep->max_regions - 1) {
160 dev_err(&epc->dev, "no free outbound region\n");
161 return -EINVAL;
162 }
163
164 cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size);
165
166 set_bit(r, &ep->ob_region_map);
167 ep->ob_addr[r] = addr;
168
169 return 0;
170}
171
172static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
173 phys_addr_t addr)
174{
175 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
176 struct cdns_pcie *pcie = &ep->pcie;
177 u32 r;
178
179 for (r = 0; r < ep->max_regions - 1; r++)
180 if (ep->ob_addr[r] == addr)
181 break;
182
183 if (r == ep->max_regions - 1)
184 return;
185
186 cdns_pcie_reset_outbound_region(pcie, r);
187
188 ep->ob_addr[r] = 0;
189 clear_bit(r, &ep->ob_region_map);
190}
191
192static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
193{
194 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
195 struct cdns_pcie *pcie = &ep->pcie;
196 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
197 u16 flags;
198
199 /*
200 * Set the Multiple Message Capable bitfield into the Message Control
201 * register.
202 */
203 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
204 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
205 flags |= PCI_MSI_FLAGS_64BIT;
206 flags &= ~PCI_MSI_FLAGS_MASKBIT;
207 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
208
209 return 0;
210}
211
212static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
213{
214 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
215 struct cdns_pcie *pcie = &ep->pcie;
216 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
217 u16 flags, mme;
218
219 /* Validate that the MSI feature is actually enabled. */
220 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
221 if (!(flags & PCI_MSI_FLAGS_ENABLE))
222 return -EINVAL;
223
224 /*
225 * Get the Multiple Message Enable bitfield from the Message Control
226 * register.
227 */
228 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
229
230 return mme;
231}
232
233static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
234{
235 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
236 struct cdns_pcie *pcie = &ep->pcie;
237 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
238 u32 val, reg;
239
240 reg = cap + PCI_MSIX_FLAGS;
241 val = cdns_pcie_ep_fn_readw(pcie, func_no, reg);
242 if (!(val & PCI_MSIX_FLAGS_ENABLE))
243 return -EINVAL;
244
245 val &= PCI_MSIX_FLAGS_QSIZE;
246
247 return val;
248}
249
250static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u16 interrupts,
251 enum pci_barno bir, u32 offset)
252{
253 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
254 struct cdns_pcie *pcie = &ep->pcie;
255 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
256 u32 val, reg;
257
258 reg = cap + PCI_MSIX_FLAGS;
259 val = cdns_pcie_ep_fn_readw(pcie, fn, reg);
260 val &= ~PCI_MSIX_FLAGS_QSIZE;
261 val |= interrupts;
262 cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
263
264 /* Set MSIX BAR and offset */
265 reg = cap + PCI_MSIX_TABLE;
266 val = offset | bir;
267 cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
268
269 /* Set PBA BAR and offset. BAR must match MSIX BAR */
270 reg = cap + PCI_MSIX_PBA;
271 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
272 cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
273
274 return 0;
275}
276
277static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
278 u8 intx, bool is_asserted)
279{
280 struct cdns_pcie *pcie = &ep->pcie;
281 unsigned long flags;
282 u32 offset;
283 u16 status;
284 u8 msg_code;
285
286 intx &= 3;
287
288 /* Set the outbound region if needed. */
289 if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
290 ep->irq_pci_fn != fn)) {
291 /* First region was reserved for IRQ writes. */
292 cdns_pcie_set_outbound_region_for_normal_msg(pcie, 0, fn, 0,
293 ep->irq_phys_addr);
294 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
295 ep->irq_pci_fn = fn;
296 }
297
298 if (is_asserted) {
299 ep->irq_pending |= BIT(intx);
300 msg_code = MSG_CODE_ASSERT_INTA + intx;
301 } else {
302 ep->irq_pending &= ~BIT(intx);
303 msg_code = MSG_CODE_DEASSERT_INTA + intx;
304 }
305
306 spin_lock_irqsave(&ep->lock, flags);
307 status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
308 if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
309 status ^= PCI_STATUS_INTERRUPT;
310 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
311 }
312 spin_unlock_irqrestore(&ep->lock, flags);
313
314 offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
315 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
316 CDNS_PCIE_MSG_NO_DATA;
317 writel(0, ep->irq_cpu_addr + offset);
318}
319
320static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
321{
322 u16 cmd;
323
324 cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
325 if (cmd & PCI_COMMAND_INTX_DISABLE)
326 return -EINVAL;
327
328 cdns_pcie_ep_assert_intx(ep, fn, intx, true);
329 /*
330 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
331 */
332 mdelay(1);
333 cdns_pcie_ep_assert_intx(ep, fn, intx, false);
334 return 0;
335}
336
337static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
338 u8 interrupt_num)
339{
340 struct cdns_pcie *pcie = &ep->pcie;
341 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
342 u16 flags, mme, data, data_mask;
343 u8 msi_count;
344 u64 pci_addr, pci_addr_mask = 0xff;
345
346 /* Check whether the MSI feature has been enabled by the PCI host. */
347 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
348 if (!(flags & PCI_MSI_FLAGS_ENABLE))
349 return -EINVAL;
350
351 /* Get the number of enabled MSIs */
352 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
353 msi_count = 1 << mme;
354 if (!interrupt_num || interrupt_num > msi_count)
355 return -EINVAL;
356
357 /* Compute the data value to be written. */
358 data_mask = msi_count - 1;
359 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
360 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
361
362 /* Get the PCI address where to write the data into. */
363 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
364 pci_addr <<= 32;
365 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
366 pci_addr &= GENMASK_ULL(63, 2);
367
368 /* Set the outbound region if needed. */
369 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
370 ep->irq_pci_fn != fn)) {
371 /* First region was reserved for IRQ writes. */
372 cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
373 false,
374 ep->irq_phys_addr,
375 pci_addr & ~pci_addr_mask,
376 pci_addr_mask + 1);
377 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
378 ep->irq_pci_fn = fn;
379 }
380 writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
381
382 return 0;
383}
384
385static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn,
386 phys_addr_t addr, u8 interrupt_num,
387 u32 entry_size, u32 *msi_data,
388 u32 *msi_addr_offset)
389{
390 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
391 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
392 struct cdns_pcie *pcie = &ep->pcie;
393 u64 pci_addr, pci_addr_mask = 0xff;
394 u16 flags, mme, data, data_mask;
395 u8 msi_count;
396 int ret;
397 int i;
398
399 /* Check whether the MSI feature has been enabled by the PCI host. */
400 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
401 if (!(flags & PCI_MSI_FLAGS_ENABLE))
402 return -EINVAL;
403
404 /* Get the number of enabled MSIs */
405 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
406 msi_count = 1 << mme;
407 if (!interrupt_num || interrupt_num > msi_count)
408 return -EINVAL;
409
410 /* Compute the data value to be written. */
411 data_mask = msi_count - 1;
412 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
413 data = data & ~data_mask;
414
415 /* Get the PCI address where to write the data into. */
416 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
417 pci_addr <<= 32;
418 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
419 pci_addr &= GENMASK_ULL(63, 2);
420
421 for (i = 0; i < interrupt_num; i++) {
422 ret = cdns_pcie_ep_map_addr(epc, fn, addr,
423 pci_addr & ~pci_addr_mask,
424 entry_size);
425 if (ret)
426 return ret;
427 addr = addr + entry_size;
428 }
429
430 *msi_data = data;
431 *msi_addr_offset = pci_addr & pci_addr_mask;
432
433 return 0;
434}
435
436static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn,
437 u16 interrupt_num)
438{
439 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
440 u32 tbl_offset, msg_data, reg;
441 struct cdns_pcie *pcie = &ep->pcie;
442 struct pci_epf_msix_tbl *msix_tbl;
443 struct cdns_pcie_epf *epf;
444 u64 pci_addr_mask = 0xff;
445 u64 msg_addr;
446 u16 flags;
447 u8 bir;
448
449 /* Check whether the MSI-X feature has been enabled by the PCI host. */
450 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS);
451 if (!(flags & PCI_MSIX_FLAGS_ENABLE))
452 return -EINVAL;
453
454 reg = cap + PCI_MSIX_TABLE;
455 tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg);
456 bir = tbl_offset & PCI_MSIX_TABLE_BIR;
457 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
458
459 epf = &ep->epf[fn];
460 msix_tbl = epf->epf_bar[bir]->addr + tbl_offset;
461 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
462 msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
463
464 /* Set the outbound region if needed. */
465 if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) ||
466 ep->irq_pci_fn != fn) {
467 /* First region was reserved for IRQ writes. */
468 cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
469 false,
470 ep->irq_phys_addr,
471 msg_addr & ~pci_addr_mask,
472 pci_addr_mask + 1);
473 ep->irq_pci_addr = (msg_addr & ~pci_addr_mask);
474 ep->irq_pci_fn = fn;
475 }
476 writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask));
477
478 return 0;
479}
480
481static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
482 enum pci_epc_irq_type type,
483 u16 interrupt_num)
484{
485 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
486
487 switch (type) {
488 case PCI_EPC_IRQ_LEGACY:
489 return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
490
491 case PCI_EPC_IRQ_MSI:
492 return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
493
494 case PCI_EPC_IRQ_MSIX:
495 return cdns_pcie_ep_send_msix_irq(ep, fn, interrupt_num);
496
497 default:
498 break;
499 }
500
501 return -EINVAL;
502}
503
504static int cdns_pcie_ep_start(struct pci_epc *epc)
505{
506 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
507 struct cdns_pcie *pcie = &ep->pcie;
508 struct device *dev = pcie->dev;
509 int ret;
510
511 /*
512 * BIT(0) is hardwired to 1, hence function 0 is always enabled
513 * and can't be disabled anyway.
514 */
515 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);
516
517 ret = cdns_pcie_start_link(pcie);
518 if (ret) {
519 dev_err(dev, "Failed to start link\n");
520 return ret;
521 }
522
523 return 0;
524}
525
526static const struct pci_epc_features cdns_pcie_epc_features = {
527 .linkup_notifier = false,
528 .msi_capable = true,
529 .msix_capable = true,
530 .align = 256,
531};
532
533static const struct pci_epc_features*
534cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
535{
536 return &cdns_pcie_epc_features;
537}
538
539static const struct pci_epc_ops cdns_pcie_epc_ops = {
540 .write_header = cdns_pcie_ep_write_header,
541 .set_bar = cdns_pcie_ep_set_bar,
542 .clear_bar = cdns_pcie_ep_clear_bar,
543 .map_addr = cdns_pcie_ep_map_addr,
544 .unmap_addr = cdns_pcie_ep_unmap_addr,
545 .set_msi = cdns_pcie_ep_set_msi,
546 .get_msi = cdns_pcie_ep_get_msi,
547 .set_msix = cdns_pcie_ep_set_msix,
548 .get_msix = cdns_pcie_ep_get_msix,
549 .raise_irq = cdns_pcie_ep_raise_irq,
550 .map_msi_irq = cdns_pcie_ep_map_msi_irq,
551 .start = cdns_pcie_ep_start,
552 .get_features = cdns_pcie_ep_get_features,
553};
554
555
556int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
557{
558 struct device *dev = ep->pcie.dev;
559 struct platform_device *pdev = to_platform_device(dev);
560 struct device_node *np = dev->of_node;
561 struct cdns_pcie *pcie = &ep->pcie;
562 struct resource *res;
563 struct pci_epc *epc;
564 int ret;
565
566 pcie->is_rc = false;
567
568 pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
569 if (IS_ERR(pcie->reg_base)) {
570 dev_err(dev, "missing \"reg\"\n");
571 return PTR_ERR(pcie->reg_base);
572 }
573
574 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
575 if (!res) {
576 dev_err(dev, "missing \"mem\"\n");
577 return -EINVAL;
578 }
579 pcie->mem_res = res;
580
581 ep->max_regions = CDNS_PCIE_MAX_OB;
582 of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions);
583
584 ep->ob_addr = devm_kcalloc(dev,
585 ep->max_regions, sizeof(*ep->ob_addr),
586 GFP_KERNEL);
587 if (!ep->ob_addr)
588 return -ENOMEM;
589
590 /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
591 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
592
593 epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
594 if (IS_ERR(epc)) {
595 dev_err(dev, "failed to create epc device\n");
596 return PTR_ERR(epc);
597 }
598
599 epc_set_drvdata(epc, ep);
600
601 if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
602 epc->max_functions = 1;
603
604 ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf),
605 GFP_KERNEL);
606 if (!ep->epf)
607 return -ENOMEM;
608
609 ret = pci_epc_mem_init(epc, pcie->mem_res->start,
610 resource_size(pcie->mem_res), PAGE_SIZE);
611 if (ret < 0) {
612 dev_err(dev, "failed to initialize the memory space\n");
613 return ret;
614 }
615
616 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
617 SZ_128K);
618 if (!ep->irq_cpu_addr) {
619 dev_err(dev, "failed to reserve memory space for MSI\n");
620 ret = -ENOMEM;
621 goto free_epc_mem;
622 }
623 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
624 /* Reserve region 0 for IRQs */
625 set_bit(0, &ep->ob_region_map);
626
627 if (ep->quirk_detect_quiet_flag)
628 cdns_pcie_detect_quiet_min_delay_set(&ep->pcie);
629
630 spin_lock_init(&ep->lock);
631
632 return 0;
633
634 free_epc_mem:
635 pci_epc_mem_exit(epc);
636
637 return ret;
638}