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1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 */
6
7#ifndef __SPARX5_MAIN_H__
8#define __SPARX5_MAIN_H__
9
10#include <linux/types.h>
11#include <linux/phy/phy.h>
12#include <linux/netdevice.h>
13#include <linux/phy.h>
14#include <linux/if_vlan.h>
15#include <linux/bitmap.h>
16#include <linux/phylink.h>
17#include <linux/net_tstamp.h>
18#include <linux/ptp_clock_kernel.h>
19#include <linux/hrtimer.h>
20#include <linux/debugfs.h>
21
22#include "sparx5_main_regs.h"
23
24/* Target chip type */
25enum spx5_target_chiptype {
26 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
27 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
28 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
29 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
30 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
31 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
32 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
33 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
34 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
35 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */
36};
37
38enum sparx5_port_max_tags {
39 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */
40 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */
41 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */
42};
43
44enum sparx5_vlan_port_type {
45 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */
46 SPX5_VLAN_PORT_TYPE_C, /* C-port */
47 SPX5_VLAN_PORT_TYPE_S, /* S-port */
48 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */
49};
50
51#define SPX5_PORTS 65
52#define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */
53#define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */
54#define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */
55#define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */
56#define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */
57#define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/
58#define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */
59
60#define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */
61#define PGID_UC_FLOOD (PGID_BASE + 0)
62#define PGID_MC_FLOOD (PGID_BASE + 1)
63#define PGID_IPV4_MC_DATA (PGID_BASE + 2)
64#define PGID_IPV4_MC_CTRL (PGID_BASE + 3)
65#define PGID_IPV6_MC_DATA (PGID_BASE + 4)
66#define PGID_IPV6_MC_CTRL (PGID_BASE + 5)
67#define PGID_BCAST (PGID_BASE + 6)
68#define PGID_CPU (PGID_BASE + 7)
69#define PGID_MCAST_START (PGID_BASE + 8)
70
71#define PGID_TABLE_SIZE 3290
72
73#define IFH_LEN 9 /* 36 bytes */
74#define NULL_VID 0
75#define SPX5_MACT_PULL_DELAY (2 * HZ)
76#define SPX5_STATS_CHECK_DELAY (1 * HZ)
77#define SPX5_PRIOS 8 /* Number of priority queues */
78#define SPX5_BUFFER_CELL_SZ 184 /* Cell size */
79#define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */
80
81#define XTR_QUEUE 0
82#define INJ_QUEUE 0
83
84#define FDMA_DCB_MAX 64
85#define FDMA_RX_DCB_MAX_DBS 15
86#define FDMA_TX_DCB_MAX_DBS 1
87
88#define SPARX5_PHC_COUNT 3
89#define SPARX5_PHC_PORT 0
90
91#define IFH_REW_OP_NOOP 0x0
92#define IFH_REW_OP_ONE_STEP_PTP 0x3
93#define IFH_REW_OP_TWO_STEP_PTP 0x4
94
95#define IFH_PDU_TYPE_NONE 0x0
96#define IFH_PDU_TYPE_PTP 0x5
97#define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6
98#define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7
99
100struct sparx5;
101
102struct sparx5_db_hw {
103 u64 dataptr;
104 u64 status;
105};
106
107struct sparx5_rx_dcb_hw {
108 u64 nextptr;
109 u64 info;
110 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS];
111};
112
113struct sparx5_tx_dcb_hw {
114 u64 nextptr;
115 u64 info;
116 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS];
117};
118
119/* Frame DMA receive state:
120 * For each DB, there is a SKB, and the skb data pointer is mapped in
121 * the DB. Once a frame is received the skb is given to the upper layers
122 * and a new skb is added to the dcb.
123 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused.
124 */
125struct sparx5_rx {
126 struct sparx5_rx_dcb_hw *dcb_entries;
127 struct sparx5_rx_dcb_hw *last_entry;
128 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS];
129 int db_index;
130 int dcb_index;
131 dma_addr_t dma;
132 struct napi_struct napi;
133 u32 channel_id;
134 struct net_device *ndev;
135 u64 packets;
136};
137
138/* Frame DMA transmit state:
139 * DCBs are chained using the DCBs nextptr field.
140 */
141struct sparx5_tx {
142 struct sparx5_tx_dcb_hw *curr_entry;
143 struct sparx5_tx_dcb_hw *first_entry;
144 struct list_head db_list;
145 dma_addr_t dma;
146 u32 channel_id;
147 u64 packets;
148 u64 dropped;
149};
150
151struct sparx5_port_config {
152 phy_interface_t portmode;
153 u32 bandwidth;
154 int speed;
155 int duplex;
156 enum phy_media media;
157 bool inband;
158 bool power_down;
159 bool autoneg;
160 bool serdes_reset;
161 u32 pause;
162 u32 pause_adv;
163 phy_interface_t phy_mode;
164 u32 sd_sgpio;
165};
166
167struct sparx5_port {
168 struct net_device *ndev;
169 struct sparx5 *sparx5;
170 struct device_node *of_node;
171 struct phy *serdes;
172 struct sparx5_port_config conf;
173 struct phylink_config phylink_config;
174 struct phylink *phylink;
175 struct phylink_pcs phylink_pcs;
176 u16 portno;
177 /* Ingress default VLAN (pvid) */
178 u16 pvid;
179 /* Egress default VLAN (vid) */
180 u16 vid;
181 bool signd_internal;
182 bool signd_active_high;
183 bool signd_enable;
184 bool flow_control;
185 enum sparx5_port_max_tags max_vlan_tags;
186 enum sparx5_vlan_port_type vlan_type;
187 u32 custom_etype;
188 bool vlan_aware;
189 struct hrtimer inj_timer;
190 /* ptp */
191 u8 ptp_cmd;
192 u16 ts_id;
193 struct sk_buff_head tx_skbs;
194 bool is_mrouter;
195};
196
197enum sparx5_core_clockfreq {
198 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */
199 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */
200 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */
201 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */
202};
203
204struct sparx5_phc {
205 struct ptp_clock *clock;
206 struct ptp_clock_info info;
207 struct hwtstamp_config hwtstamp_config;
208 struct sparx5 *sparx5;
209 u8 index;
210};
211
212struct sparx5_skb_cb {
213 u8 rew_op;
214 u8 pdu_type;
215 u8 pdu_w16_offset;
216 u16 ts_id;
217 unsigned long jiffies;
218};
219
220struct sparx5_mdb_entry {
221 struct list_head list;
222 DECLARE_BITMAP(port_mask, SPX5_PORTS);
223 unsigned char addr[ETH_ALEN];
224 bool cpu_copy;
225 u16 vid;
226 u16 pgid_idx;
227};
228
229#define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10)
230#define SPARX5_SKB_CB(skb) \
231 ((struct sparx5_skb_cb *)((skb)->cb))
232
233struct sparx5 {
234 struct platform_device *pdev;
235 struct device *dev;
236 u32 chip_id;
237 enum spx5_target_chiptype target_ct;
238 void __iomem *regs[NUM_TARGETS];
239 int port_count;
240 struct mutex lock; /* MAC reg lock */
241 /* port structures are in net device */
242 struct sparx5_port *ports[SPX5_PORTS];
243 enum sparx5_core_clockfreq coreclock;
244 /* Statistics */
245 u32 num_stats;
246 u32 num_ethtool_stats;
247 const char * const *stats_layout;
248 u64 *stats;
249 /* Workqueue for reading stats */
250 struct mutex queue_stats_lock;
251 struct delayed_work stats_work;
252 struct workqueue_struct *stats_queue;
253 /* Notifiers */
254 struct notifier_block netdevice_nb;
255 struct notifier_block switchdev_nb;
256 struct notifier_block switchdev_blocking_nb;
257 /* Switch state */
258 u8 base_mac[ETH_ALEN];
259 /* Associated bridge device (when bridged) */
260 struct net_device *hw_bridge_dev;
261 /* Bridged interfaces */
262 DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
263 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
264 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
265 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
266 /* SW MAC table */
267 struct list_head mact_entries;
268 /* mac table list (mact_entries) mutex */
269 struct mutex mact_lock;
270 /* SW MDB table */
271 struct list_head mdb_entries;
272 /* mdb list mutex */
273 struct mutex mdb_lock;
274 struct delayed_work mact_work;
275 struct workqueue_struct *mact_queue;
276 /* Board specifics */
277 bool sd_sgpio_remapping;
278 /* Register based inj/xtr */
279 int xtr_irq;
280 /* Frame DMA */
281 int fdma_irq;
282 struct sparx5_rx rx;
283 struct sparx5_tx tx;
284 /* PTP */
285 bool ptp;
286 struct sparx5_phc phc[SPARX5_PHC_COUNT];
287 spinlock_t ptp_clock_lock; /* lock for phc */
288 spinlock_t ptp_ts_id_lock; /* lock for ts_id */
289 struct mutex ptp_lock; /* lock for ptp interface state */
290 u16 ptp_skbs;
291 int ptp_irq;
292 /* VCAP */
293 struct vcap_control *vcap_ctrl;
294 /* PGID allocation map */
295 u8 pgid_map[PGID_TABLE_SIZE];
296 /* Common root for debugfs */
297 struct dentry *debugfs_root;
298};
299
300/* sparx5_switchdev.c */
301int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
302void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
303
304/* sparx5_packet.c */
305struct frame_info {
306 int src_port;
307 u32 timestamp;
308};
309
310void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
311void sparx5_ifh_parse(u32 *ifh, struct frame_info *info);
312irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
313netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
314int sparx5_manual_injection_mode(struct sparx5 *sparx5);
315void sparx5_port_inj_timer_setup(struct sparx5_port *port);
316
317/* sparx5_fdma.c */
318int sparx5_fdma_start(struct sparx5 *sparx5);
319int sparx5_fdma_stop(struct sparx5 *sparx5);
320int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb);
321irqreturn_t sparx5_fdma_handler(int irq, void *args);
322
323/* sparx5_mactable.c */
324void sparx5_mact_pull_work(struct work_struct *work);
325int sparx5_mact_learn(struct sparx5 *sparx5, int port,
326 const unsigned char mac[ETH_ALEN], u16 vid);
327bool sparx5_mact_getnext(struct sparx5 *sparx5,
328 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2);
329int sparx5_mact_find(struct sparx5 *sparx5,
330 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2);
331int sparx5_mact_forget(struct sparx5 *sparx5,
332 const unsigned char mac[ETH_ALEN], u16 vid);
333int sparx5_add_mact_entry(struct sparx5 *sparx5,
334 struct net_device *dev,
335 u16 portno,
336 const unsigned char *addr, u16 vid);
337int sparx5_del_mact_entry(struct sparx5 *sparx5,
338 const unsigned char *addr,
339 u16 vid);
340int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr);
341int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr);
342void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
343void sparx5_mact_init(struct sparx5 *sparx5);
344
345/* sparx5_vlan.c */
346void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
347void sparx5_pgid_clear(struct sparx5 *spx5, int pgid);
348void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]);
349void sparx5_update_fwd(struct sparx5 *sparx5);
350void sparx5_vlan_init(struct sparx5 *sparx5);
351void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
352int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
353 bool untagged);
354int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
355void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
356
357/* sparx5_calendar.c */
358int sparx5_config_auto_calendar(struct sparx5 *sparx5);
359int sparx5_config_dsm_calendar(struct sparx5 *sparx5);
360
361/* sparx5_ethtool.c */
362void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
363int sparx_stats_init(struct sparx5 *sparx5);
364
365/* sparx5_dcb.c */
366#ifdef CONFIG_SPARX5_DCB
367int sparx5_dcb_init(struct sparx5 *sparx5);
368#else
369static inline int sparx5_dcb_init(struct sparx5 *sparx5)
370{
371 return 0;
372}
373#endif
374
375/* sparx5_netdev.c */
376void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp);
377void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op);
378void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type);
379void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset);
380void sparx5_set_port_ifh(void *ifh_hdr, u16 portno);
381bool sparx5_netdevice_check(const struct net_device *dev);
382struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
383int sparx5_register_netdevs(struct sparx5 *sparx5);
384void sparx5_destroy_netdevs(struct sparx5 *sparx5);
385void sparx5_unregister_netdevs(struct sparx5 *sparx5);
386
387/* sparx5_ptp.c */
388int sparx5_ptp_init(struct sparx5 *sparx5);
389void sparx5_ptp_deinit(struct sparx5 *sparx5);
390int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr);
391int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr);
392void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb,
393 u64 timestamp);
394int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
395 struct sk_buff *skb);
396void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
397 struct sk_buff *skb);
398irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
399
400/* sparx5_vcap_impl.c */
401int sparx5_vcap_init(struct sparx5 *sparx5);
402void sparx5_vcap_destroy(struct sparx5 *sparx5);
403
404/* sparx5_pgid.c */
405enum sparx5_pgid_type {
406 SPX5_PGID_FREE,
407 SPX5_PGID_RESERVED,
408 SPX5_PGID_MULTICAST,
409};
410
411void sparx5_pgid_init(struct sparx5 *spx5);
412int sparx5_pgid_alloc_glag(struct sparx5 *spx5, u16 *idx);
413int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx);
414int sparx5_pgid_free(struct sparx5 *spx5, u16 idx);
415
416/* Clock period in picoseconds */
417static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
418{
419 switch (cclock) {
420 case SPX5_CORE_CLOCK_250MHZ:
421 return 4000;
422 case SPX5_CORE_CLOCK_500MHZ:
423 return 2000;
424 case SPX5_CORE_CLOCK_625MHZ:
425 default:
426 return 1600;
427 }
428}
429
430static inline bool sparx5_is_baser(phy_interface_t interface)
431{
432 return interface == PHY_INTERFACE_MODE_5GBASER ||
433 interface == PHY_INTERFACE_MODE_10GBASER ||
434 interface == PHY_INTERFACE_MODE_25GBASER;
435}
436
437extern const struct phylink_mac_ops sparx5_phylink_mac_ops;
438extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops;
439extern const struct ethtool_ops sparx5_ethtool_ops;
440extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops;
441
442/* Calculate raw offset */
443static inline __pure int spx5_offset(int id, int tinst, int tcnt,
444 int gbase, int ginst,
445 int gcnt, int gwidth,
446 int raddr, int rinst,
447 int rcnt, int rwidth)
448{
449 WARN_ON((tinst) >= tcnt);
450 WARN_ON((ginst) >= gcnt);
451 WARN_ON((rinst) >= rcnt);
452 return gbase + ((ginst) * gwidth) +
453 raddr + ((rinst) * rwidth);
454}
455
456/* Read, Write and modify registers content.
457 * The register definition macros start at the id
458 */
459static inline void __iomem *spx5_addr(void __iomem *base[],
460 int id, int tinst, int tcnt,
461 int gbase, int ginst,
462 int gcnt, int gwidth,
463 int raddr, int rinst,
464 int rcnt, int rwidth)
465{
466 WARN_ON((tinst) >= tcnt);
467 WARN_ON((ginst) >= gcnt);
468 WARN_ON((rinst) >= rcnt);
469 return base[id + (tinst)] +
470 gbase + ((ginst) * gwidth) +
471 raddr + ((rinst) * rwidth);
472}
473
474static inline void __iomem *spx5_inst_addr(void __iomem *base,
475 int gbase, int ginst,
476 int gcnt, int gwidth,
477 int raddr, int rinst,
478 int rcnt, int rwidth)
479{
480 WARN_ON((ginst) >= gcnt);
481 WARN_ON((rinst) >= rcnt);
482 return base +
483 gbase + ((ginst) * gwidth) +
484 raddr + ((rinst) * rwidth);
485}
486
487static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt,
488 int gbase, int ginst, int gcnt, int gwidth,
489 int raddr, int rinst, int rcnt, int rwidth)
490{
491 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
492 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
493}
494
495static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt,
496 int gbase, int ginst, int gcnt, int gwidth,
497 int raddr, int rinst, int rcnt, int rwidth)
498{
499 return readl(spx5_inst_addr(iomem, gbase, ginst,
500 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
501}
502
503static inline void spx5_wr(u32 val, struct sparx5 *sparx5,
504 int id, int tinst, int tcnt,
505 int gbase, int ginst, int gcnt, int gwidth,
506 int raddr, int rinst, int rcnt, int rwidth)
507{
508 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
509 gbase, ginst, gcnt, gwidth,
510 raddr, rinst, rcnt, rwidth));
511}
512
513static inline void spx5_inst_wr(u32 val, void __iomem *iomem,
514 int id, int tinst, int tcnt,
515 int gbase, int ginst, int gcnt, int gwidth,
516 int raddr, int rinst, int rcnt, int rwidth)
517{
518 writel(val, spx5_inst_addr(iomem,
519 gbase, ginst, gcnt, gwidth,
520 raddr, rinst, rcnt, rwidth));
521}
522
523static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5,
524 int id, int tinst, int tcnt,
525 int gbase, int ginst, int gcnt, int gwidth,
526 int raddr, int rinst, int rcnt, int rwidth)
527{
528 u32 nval;
529
530 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
531 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
532 nval = (nval & ~mask) | (val & mask);
533 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
534 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
535}
536
537static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
538 int id, int tinst, int tcnt,
539 int gbase, int ginst, int gcnt, int gwidth,
540 int raddr, int rinst, int rcnt, int rwidth)
541{
542 u32 nval;
543
544 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
545 rinst, rcnt, rwidth));
546 nval = (nval & ~mask) | (val & mask);
547 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
548 rinst, rcnt, rwidth));
549}
550
551static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst)
552{
553 return sparx5->regs[id + tinst];
554}
555
556static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5,
557 int id, int tinst, int tcnt,
558 int gbase, int ginst, int gcnt, int gwidth,
559 int raddr, int rinst, int rcnt, int rwidth)
560{
561 return spx5_addr(sparx5->regs, id, tinst, tcnt,
562 gbase, ginst, gcnt, gwidth,
563 raddr, rinst, rcnt, rwidth);
564}
565
566#endif /* __SPARX5_MAIN_H__ */
1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 */
6
7#ifndef __SPARX5_MAIN_H__
8#define __SPARX5_MAIN_H__
9
10#include <linux/types.h>
11#include <linux/phy/phy.h>
12#include <linux/netdevice.h>
13#include <linux/phy.h>
14#include <linux/if_vlan.h>
15#include <linux/bitmap.h>
16#include <linux/phylink.h>
17#include <linux/hrtimer.h>
18
19/* Target chip type */
20enum spx5_target_chiptype {
21 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
22 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
23 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
24 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
25 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
26 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
27 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
28 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
29 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
30 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */
31};
32
33enum sparx5_port_max_tags {
34 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */
35 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */
36 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */
37};
38
39enum sparx5_vlan_port_type {
40 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */
41 SPX5_VLAN_PORT_TYPE_C, /* C-port */
42 SPX5_VLAN_PORT_TYPE_S, /* S-port */
43 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */
44};
45
46#define SPX5_PORTS 65
47#define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */
48#define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */
49#define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */
50#define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */
51#define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */
52#define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/
53#define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */
54
55#define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */
56#define PGID_UC_FLOOD (PGID_BASE + 0)
57#define PGID_MC_FLOOD (PGID_BASE + 1)
58#define PGID_IPV4_MC_DATA (PGID_BASE + 2)
59#define PGID_IPV4_MC_CTRL (PGID_BASE + 3)
60#define PGID_IPV6_MC_DATA (PGID_BASE + 4)
61#define PGID_IPV6_MC_CTRL (PGID_BASE + 5)
62#define PGID_BCAST (PGID_BASE + 6)
63#define PGID_CPU (PGID_BASE + 7)
64
65#define IFH_LEN 9 /* 36 bytes */
66#define NULL_VID 0
67#define SPX5_MACT_PULL_DELAY (2 * HZ)
68#define SPX5_STATS_CHECK_DELAY (1 * HZ)
69#define SPX5_PRIOS 8 /* Number of priority queues */
70#define SPX5_BUFFER_CELL_SZ 184 /* Cell size */
71#define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */
72
73#define XTR_QUEUE 0
74#define INJ_QUEUE 0
75
76struct sparx5;
77
78struct sparx5_port_config {
79 phy_interface_t portmode;
80 u32 bandwidth;
81 int speed;
82 int duplex;
83 enum phy_media media;
84 bool inband;
85 bool power_down;
86 bool autoneg;
87 bool serdes_reset;
88 u32 pause;
89 u32 pause_adv;
90 phy_interface_t phy_mode;
91 u32 sd_sgpio;
92};
93
94struct sparx5_port {
95 struct net_device *ndev;
96 struct sparx5 *sparx5;
97 struct device_node *of_node;
98 struct phy *serdes;
99 struct sparx5_port_config conf;
100 struct phylink_config phylink_config;
101 struct phylink *phylink;
102 struct phylink_pcs phylink_pcs;
103 u16 portno;
104 /* Ingress default VLAN (pvid) */
105 u16 pvid;
106 /* Egress default VLAN (vid) */
107 u16 vid;
108 bool signd_internal;
109 bool signd_active_high;
110 bool signd_enable;
111 bool flow_control;
112 enum sparx5_port_max_tags max_vlan_tags;
113 enum sparx5_vlan_port_type vlan_type;
114 u32 custom_etype;
115 u32 ifh[IFH_LEN];
116 bool vlan_aware;
117 struct hrtimer inj_timer;
118};
119
120enum sparx5_core_clockfreq {
121 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */
122 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */
123 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */
124 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */
125};
126
127struct sparx5 {
128 struct platform_device *pdev;
129 struct device *dev;
130 u32 chip_id;
131 enum spx5_target_chiptype target_ct;
132 void __iomem *regs[NUM_TARGETS];
133 int port_count;
134 struct mutex lock; /* MAC reg lock */
135 /* port structures are in net device */
136 struct sparx5_port *ports[SPX5_PORTS];
137 enum sparx5_core_clockfreq coreclock;
138 /* Statistics */
139 u32 num_stats;
140 u32 num_ethtool_stats;
141 const char * const *stats_layout;
142 u64 *stats;
143 /* Workqueue for reading stats */
144 struct mutex queue_stats_lock;
145 struct delayed_work stats_work;
146 struct workqueue_struct *stats_queue;
147 /* Notifiers */
148 struct notifier_block netdevice_nb;
149 struct notifier_block switchdev_nb;
150 struct notifier_block switchdev_blocking_nb;
151 /* Switch state */
152 u8 base_mac[ETH_ALEN];
153 /* Associated bridge device (when bridged) */
154 struct net_device *hw_bridge_dev;
155 /* Bridged interfaces */
156 DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
157 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
158 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
159 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
160 /* SW MAC table */
161 struct list_head mact_entries;
162 /* mac table list (mact_entries) mutex */
163 struct mutex mact_lock;
164 struct delayed_work mact_work;
165 struct workqueue_struct *mact_queue;
166 /* Board specifics */
167 bool sd_sgpio_remapping;
168 /* Register based inj/xtr */
169 int xtr_irq;
170};
171
172/* sparx5_switchdev.c */
173int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
174void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
175
176/* sparx5_packet.c */
177irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
178int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
179int sparx5_manual_injection_mode(struct sparx5 *sparx5);
180void sparx5_port_inj_timer_setup(struct sparx5_port *port);
181
182/* sparx5_mactable.c */
183void sparx5_mact_pull_work(struct work_struct *work);
184int sparx5_mact_learn(struct sparx5 *sparx5, int port,
185 const unsigned char mac[ETH_ALEN], u16 vid);
186bool sparx5_mact_getnext(struct sparx5 *sparx5,
187 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2);
188int sparx5_mact_forget(struct sparx5 *sparx5,
189 const unsigned char mac[ETH_ALEN], u16 vid);
190int sparx5_add_mact_entry(struct sparx5 *sparx5,
191 struct sparx5_port *port,
192 const unsigned char *addr, u16 vid);
193int sparx5_del_mact_entry(struct sparx5 *sparx5,
194 const unsigned char *addr,
195 u16 vid);
196int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr);
197int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr);
198void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
199void sparx5_mact_init(struct sparx5 *sparx5);
200
201/* sparx5_vlan.c */
202void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
203void sparx5_update_fwd(struct sparx5 *sparx5);
204void sparx5_vlan_init(struct sparx5 *sparx5);
205void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
206int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
207 bool untagged);
208int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
209void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
210
211/* sparx5_calendar.c */
212int sparx5_config_auto_calendar(struct sparx5 *sparx5);
213int sparx5_config_dsm_calendar(struct sparx5 *sparx5);
214
215/* sparx5_ethtool.c */
216void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
217int sparx_stats_init(struct sparx5 *sparx5);
218
219/* sparx5_netdev.c */
220bool sparx5_netdevice_check(const struct net_device *dev);
221struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
222int sparx5_register_netdevs(struct sparx5 *sparx5);
223void sparx5_destroy_netdevs(struct sparx5 *sparx5);
224void sparx5_unregister_netdevs(struct sparx5 *sparx5);
225
226/* Clock period in picoseconds */
227static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
228{
229 switch (cclock) {
230 case SPX5_CORE_CLOCK_250MHZ:
231 return 4000;
232 case SPX5_CORE_CLOCK_500MHZ:
233 return 2000;
234 case SPX5_CORE_CLOCK_625MHZ:
235 default:
236 return 1600;
237 }
238}
239
240static inline bool sparx5_is_baser(phy_interface_t interface)
241{
242 return interface == PHY_INTERFACE_MODE_5GBASER ||
243 interface == PHY_INTERFACE_MODE_10GBASER ||
244 interface == PHY_INTERFACE_MODE_25GBASER;
245}
246
247extern const struct phylink_mac_ops sparx5_phylink_mac_ops;
248extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops;
249extern const struct ethtool_ops sparx5_ethtool_ops;
250
251/* Calculate raw offset */
252static inline __pure int spx5_offset(int id, int tinst, int tcnt,
253 int gbase, int ginst,
254 int gcnt, int gwidth,
255 int raddr, int rinst,
256 int rcnt, int rwidth)
257{
258 WARN_ON((tinst) >= tcnt);
259 WARN_ON((ginst) >= gcnt);
260 WARN_ON((rinst) >= rcnt);
261 return gbase + ((ginst) * gwidth) +
262 raddr + ((rinst) * rwidth);
263}
264
265/* Read, Write and modify registers content.
266 * The register definition macros start at the id
267 */
268static inline void __iomem *spx5_addr(void __iomem *base[],
269 int id, int tinst, int tcnt,
270 int gbase, int ginst,
271 int gcnt, int gwidth,
272 int raddr, int rinst,
273 int rcnt, int rwidth)
274{
275 WARN_ON((tinst) >= tcnt);
276 WARN_ON((ginst) >= gcnt);
277 WARN_ON((rinst) >= rcnt);
278 return base[id + (tinst)] +
279 gbase + ((ginst) * gwidth) +
280 raddr + ((rinst) * rwidth);
281}
282
283static inline void __iomem *spx5_inst_addr(void __iomem *base,
284 int gbase, int ginst,
285 int gcnt, int gwidth,
286 int raddr, int rinst,
287 int rcnt, int rwidth)
288{
289 WARN_ON((ginst) >= gcnt);
290 WARN_ON((rinst) >= rcnt);
291 return base +
292 gbase + ((ginst) * gwidth) +
293 raddr + ((rinst) * rwidth);
294}
295
296static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt,
297 int gbase, int ginst, int gcnt, int gwidth,
298 int raddr, int rinst, int rcnt, int rwidth)
299{
300 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
301 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
302}
303
304static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt,
305 int gbase, int ginst, int gcnt, int gwidth,
306 int raddr, int rinst, int rcnt, int rwidth)
307{
308 return readl(spx5_inst_addr(iomem, gbase, ginst,
309 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
310}
311
312static inline void spx5_wr(u32 val, struct sparx5 *sparx5,
313 int id, int tinst, int tcnt,
314 int gbase, int ginst, int gcnt, int gwidth,
315 int raddr, int rinst, int rcnt, int rwidth)
316{
317 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
318 gbase, ginst, gcnt, gwidth,
319 raddr, rinst, rcnt, rwidth));
320}
321
322static inline void spx5_inst_wr(u32 val, void __iomem *iomem,
323 int id, int tinst, int tcnt,
324 int gbase, int ginst, int gcnt, int gwidth,
325 int raddr, int rinst, int rcnt, int rwidth)
326{
327 writel(val, spx5_inst_addr(iomem,
328 gbase, ginst, gcnt, gwidth,
329 raddr, rinst, rcnt, rwidth));
330}
331
332static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5,
333 int id, int tinst, int tcnt,
334 int gbase, int ginst, int gcnt, int gwidth,
335 int raddr, int rinst, int rcnt, int rwidth)
336{
337 u32 nval;
338
339 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
340 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
341 nval = (nval & ~mask) | (val & mask);
342 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
343 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
344}
345
346static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
347 int id, int tinst, int tcnt,
348 int gbase, int ginst, int gcnt, int gwidth,
349 int raddr, int rinst, int rcnt, int rwidth)
350{
351 u32 nval;
352
353 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
354 rinst, rcnt, rwidth));
355 nval = (nval & ~mask) | (val & mask);
356 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
357 rinst, rcnt, rwidth));
358}
359
360static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst)
361{
362 return sparx5->regs[id + tinst];
363}
364
365static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5,
366 int id, int tinst, int tcnt,
367 int gbase, int ginst, int gcnt, int gwidth,
368 int raddr, int rinst, int rcnt, int rwidth)
369{
370 return spx5_addr(sparx5->regs, id, tinst, tcnt,
371 gbase, ginst, gcnt, gwidth,
372 raddr, rinst, rcnt, rwidth);
373}
374
375#endif /* __SPARX5_MAIN_H__ */