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1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/string_helpers.h>
26
27#include <drm/drm_print.h>
28#include <drm/i915_pciids.h>
29
30#include "display/intel_cdclk.h"
31#include "display/intel_de.h"
32#include "gt/intel_gt_regs.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "i915_utils.h"
36#include "intel_device_info.h"
37
38#define PLATFORM_NAME(x) [INTEL_##x] = #x
39static const char * const platform_names[] = {
40 PLATFORM_NAME(I830),
41 PLATFORM_NAME(I845G),
42 PLATFORM_NAME(I85X),
43 PLATFORM_NAME(I865G),
44 PLATFORM_NAME(I915G),
45 PLATFORM_NAME(I915GM),
46 PLATFORM_NAME(I945G),
47 PLATFORM_NAME(I945GM),
48 PLATFORM_NAME(G33),
49 PLATFORM_NAME(PINEVIEW),
50 PLATFORM_NAME(I965G),
51 PLATFORM_NAME(I965GM),
52 PLATFORM_NAME(G45),
53 PLATFORM_NAME(GM45),
54 PLATFORM_NAME(IRONLAKE),
55 PLATFORM_NAME(SANDYBRIDGE),
56 PLATFORM_NAME(IVYBRIDGE),
57 PLATFORM_NAME(VALLEYVIEW),
58 PLATFORM_NAME(HASWELL),
59 PLATFORM_NAME(BROADWELL),
60 PLATFORM_NAME(CHERRYVIEW),
61 PLATFORM_NAME(SKYLAKE),
62 PLATFORM_NAME(BROXTON),
63 PLATFORM_NAME(KABYLAKE),
64 PLATFORM_NAME(GEMINILAKE),
65 PLATFORM_NAME(COFFEELAKE),
66 PLATFORM_NAME(COMETLAKE),
67 PLATFORM_NAME(ICELAKE),
68 PLATFORM_NAME(ELKHARTLAKE),
69 PLATFORM_NAME(JASPERLAKE),
70 PLATFORM_NAME(TIGERLAKE),
71 PLATFORM_NAME(ROCKETLAKE),
72 PLATFORM_NAME(DG1),
73 PLATFORM_NAME(ALDERLAKE_S),
74 PLATFORM_NAME(ALDERLAKE_P),
75 PLATFORM_NAME(XEHPSDV),
76 PLATFORM_NAME(DG2),
77 PLATFORM_NAME(PONTEVECCHIO),
78 PLATFORM_NAME(METEORLAKE),
79};
80#undef PLATFORM_NAME
81
82const char *intel_platform_name(enum intel_platform platform)
83{
84 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
85
86 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
87 platform_names[platform] == NULL))
88 return "<unknown>";
89
90 return platform_names[platform];
91}
92
93void intel_device_info_print(const struct intel_device_info *info,
94 const struct intel_runtime_info *runtime,
95 struct drm_printer *p)
96{
97 if (runtime->graphics.ip.rel)
98 drm_printf(p, "graphics version: %u.%02u\n",
99 runtime->graphics.ip.ver,
100 runtime->graphics.ip.rel);
101 else
102 drm_printf(p, "graphics version: %u\n",
103 runtime->graphics.ip.ver);
104
105 if (runtime->media.ip.rel)
106 drm_printf(p, "media version: %u.%02u\n",
107 runtime->media.ip.ver,
108 runtime->media.ip.rel);
109 else
110 drm_printf(p, "media version: %u\n",
111 runtime->media.ip.ver);
112
113 if (runtime->display.ip.rel)
114 drm_printf(p, "display version: %u.%02u\n",
115 runtime->display.ip.ver,
116 runtime->display.ip.rel);
117 else
118 drm_printf(p, "display version: %u\n",
119 runtime->display.ip.ver);
120
121 drm_printf(p, "gt: %d\n", info->gt);
122 drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
123 drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
124 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
125 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
126 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
127 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
128
129#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
130 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
131#undef PRINT_FLAG
132
133 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
134
135#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
136 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
137#undef PRINT_FLAG
138
139 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
140 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
141 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
142
143 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
144}
145
146#undef INTEL_VGA_DEVICE
147#define INTEL_VGA_DEVICE(id, info) (id)
148
149static const u16 subplatform_ult_ids[] = {
150 INTEL_HSW_ULT_GT1_IDS(0),
151 INTEL_HSW_ULT_GT2_IDS(0),
152 INTEL_HSW_ULT_GT3_IDS(0),
153 INTEL_BDW_ULT_GT1_IDS(0),
154 INTEL_BDW_ULT_GT2_IDS(0),
155 INTEL_BDW_ULT_GT3_IDS(0),
156 INTEL_BDW_ULT_RSVD_IDS(0),
157 INTEL_SKL_ULT_GT1_IDS(0),
158 INTEL_SKL_ULT_GT2_IDS(0),
159 INTEL_SKL_ULT_GT3_IDS(0),
160 INTEL_KBL_ULT_GT1_IDS(0),
161 INTEL_KBL_ULT_GT2_IDS(0),
162 INTEL_KBL_ULT_GT3_IDS(0),
163 INTEL_CFL_U_GT2_IDS(0),
164 INTEL_CFL_U_GT3_IDS(0),
165 INTEL_WHL_U_GT1_IDS(0),
166 INTEL_WHL_U_GT2_IDS(0),
167 INTEL_WHL_U_GT3_IDS(0),
168 INTEL_CML_U_GT1_IDS(0),
169 INTEL_CML_U_GT2_IDS(0),
170};
171
172static const u16 subplatform_ulx_ids[] = {
173 INTEL_HSW_ULX_GT1_IDS(0),
174 INTEL_HSW_ULX_GT2_IDS(0),
175 INTEL_BDW_ULX_GT1_IDS(0),
176 INTEL_BDW_ULX_GT2_IDS(0),
177 INTEL_BDW_ULX_GT3_IDS(0),
178 INTEL_BDW_ULX_RSVD_IDS(0),
179 INTEL_SKL_ULX_GT1_IDS(0),
180 INTEL_SKL_ULX_GT2_IDS(0),
181 INTEL_KBL_ULX_GT1_IDS(0),
182 INTEL_KBL_ULX_GT2_IDS(0),
183 INTEL_AML_KBL_GT2_IDS(0),
184 INTEL_AML_CFL_GT2_IDS(0),
185};
186
187static const u16 subplatform_portf_ids[] = {
188 INTEL_ICL_PORT_F_IDS(0),
189};
190
191static const u16 subplatform_uy_ids[] = {
192 INTEL_TGL_12_GT2_IDS(0),
193};
194
195static const u16 subplatform_n_ids[] = {
196 INTEL_ADLN_IDS(0),
197};
198
199static const u16 subplatform_rpl_ids[] = {
200 INTEL_RPLS_IDS(0),
201 INTEL_RPLP_IDS(0),
202};
203
204static const u16 subplatform_g10_ids[] = {
205 INTEL_DG2_G10_IDS(0),
206 INTEL_ATS_M150_IDS(0),
207};
208
209static const u16 subplatform_g11_ids[] = {
210 INTEL_DG2_G11_IDS(0),
211 INTEL_ATS_M75_IDS(0),
212};
213
214static const u16 subplatform_g12_ids[] = {
215 INTEL_DG2_G12_IDS(0),
216};
217
218static const u16 subplatform_m_ids[] = {
219 INTEL_MTL_M_IDS(0),
220};
221
222static const u16 subplatform_p_ids[] = {
223 INTEL_MTL_P_IDS(0),
224};
225
226static bool find_devid(u16 id, const u16 *p, unsigned int num)
227{
228 for (; num; num--, p++) {
229 if (*p == id)
230 return true;
231 }
232
233 return false;
234}
235
236static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
237{
238 const struct intel_device_info *info = INTEL_INFO(i915);
239 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
240 const unsigned int pi = __platform_mask_index(rinfo, info->platform);
241 const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
242 u16 devid = INTEL_DEVID(i915);
243 u32 mask = 0;
244
245 /* Make sure IS_<platform> checks are working. */
246 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
247
248 /* Find and mark subplatform bits based on the PCI device id. */
249 if (find_devid(devid, subplatform_ult_ids,
250 ARRAY_SIZE(subplatform_ult_ids))) {
251 mask = BIT(INTEL_SUBPLATFORM_ULT);
252 } else if (find_devid(devid, subplatform_ulx_ids,
253 ARRAY_SIZE(subplatform_ulx_ids))) {
254 mask = BIT(INTEL_SUBPLATFORM_ULX);
255 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
256 /* ULX machines are also considered ULT. */
257 mask |= BIT(INTEL_SUBPLATFORM_ULT);
258 }
259 } else if (find_devid(devid, subplatform_portf_ids,
260 ARRAY_SIZE(subplatform_portf_ids))) {
261 mask = BIT(INTEL_SUBPLATFORM_PORTF);
262 } else if (find_devid(devid, subplatform_uy_ids,
263 ARRAY_SIZE(subplatform_uy_ids))) {
264 mask = BIT(INTEL_SUBPLATFORM_UY);
265 } else if (find_devid(devid, subplatform_n_ids,
266 ARRAY_SIZE(subplatform_n_ids))) {
267 mask = BIT(INTEL_SUBPLATFORM_N);
268 } else if (find_devid(devid, subplatform_rpl_ids,
269 ARRAY_SIZE(subplatform_rpl_ids))) {
270 mask = BIT(INTEL_SUBPLATFORM_RPL);
271 } else if (find_devid(devid, subplatform_g10_ids,
272 ARRAY_SIZE(subplatform_g10_ids))) {
273 mask = BIT(INTEL_SUBPLATFORM_G10);
274 } else if (find_devid(devid, subplatform_g11_ids,
275 ARRAY_SIZE(subplatform_g11_ids))) {
276 mask = BIT(INTEL_SUBPLATFORM_G11);
277 } else if (find_devid(devid, subplatform_g12_ids,
278 ARRAY_SIZE(subplatform_g12_ids))) {
279 mask = BIT(INTEL_SUBPLATFORM_G12);
280 } else if (find_devid(devid, subplatform_m_ids,
281 ARRAY_SIZE(subplatform_m_ids))) {
282 mask = BIT(INTEL_SUBPLATFORM_M);
283 } else if (find_devid(devid, subplatform_p_ids,
284 ARRAY_SIZE(subplatform_p_ids))) {
285 mask = BIT(INTEL_SUBPLATFORM_P);
286 }
287
288 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
289
290 RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
291}
292
293static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
294{
295 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
296 void __iomem *addr;
297 u32 val;
298 u8 expected_ver = ip->ver;
299 u8 expected_rel = ip->rel;
300
301 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
302 if (drm_WARN_ON(&i915->drm, !addr))
303 return;
304
305 val = ioread32(addr);
306 pci_iounmap(pdev, addr);
307
308 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
309 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
310 ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
311
312 /* Sanity check against expected versions from device info */
313 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
314 drm_dbg(&i915->drm,
315 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
316 ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
317}
318
319/*
320 * Setup the graphics version for the current device. This must be done before
321 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
322 * function should be called very early in the driver initialization sequence.
323 *
324 * Regular MMIO access is not yet setup at the point this function is called so
325 * we peek at the appropriate MMIO offset directly. The GMD_ID register is
326 * part of an 'always on' power well by design, so we don't need to worry about
327 * forcewake while reading it.
328 */
329static void intel_ipver_early_init(struct drm_i915_private *i915)
330{
331 struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
332
333 if (!HAS_GMD_ID(i915)) {
334 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
335 /*
336 * On older platforms, graphics and media share the same ip
337 * version and release.
338 */
339 RUNTIME_INFO(i915)->media.ip =
340 RUNTIME_INFO(i915)->graphics.ip;
341 return;
342 }
343
344 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
345 &runtime->graphics.ip);
346 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
347 &runtime->display.ip);
348 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
349 &runtime->media.ip);
350}
351
352/**
353 * intel_device_info_runtime_init_early - initialize early runtime info
354 * @i915: the i915 device
355 *
356 * Determine early intel_device_info fields at runtime. This function needs
357 * to be called before the MMIO has been setup.
358 */
359void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
360{
361 intel_ipver_early_init(i915);
362 intel_device_info_subplatform_init(i915);
363}
364
365/**
366 * intel_device_info_runtime_init - initialize runtime info
367 * @dev_priv: the i915 device
368 *
369 * Determine various intel_device_info fields at runtime.
370 *
371 * Use it when either:
372 * - it's judged too laborious to fill n static structures with the limit
373 * when a simple if statement does the job,
374 * - run-time checks (eg read fuse/strap registers) are needed.
375 *
376 * This function needs to be called:
377 * - after the MMIO has been setup as we are reading registers,
378 * - after the PCH has been detected,
379 * - before the first usage of the fields it can tweak.
380 */
381void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
382{
383 struct intel_device_info *info = mkwrite_device_info(dev_priv);
384 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
385 enum pipe pipe;
386
387 /* Wa_14011765242: adl-s A0,A1 */
388 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
389 for_each_pipe(dev_priv, pipe)
390 runtime->num_scalers[pipe] = 0;
391 else if (DISPLAY_VER(dev_priv) >= 11) {
392 for_each_pipe(dev_priv, pipe)
393 runtime->num_scalers[pipe] = 2;
394 } else if (DISPLAY_VER(dev_priv) >= 9) {
395 runtime->num_scalers[PIPE_A] = 2;
396 runtime->num_scalers[PIPE_B] = 2;
397 runtime->num_scalers[PIPE_C] = 1;
398 }
399
400 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
401
402 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
403 for_each_pipe(dev_priv, pipe)
404 runtime->num_sprites[pipe] = 4;
405 else if (DISPLAY_VER(dev_priv) >= 11)
406 for_each_pipe(dev_priv, pipe)
407 runtime->num_sprites[pipe] = 6;
408 else if (DISPLAY_VER(dev_priv) == 10)
409 for_each_pipe(dev_priv, pipe)
410 runtime->num_sprites[pipe] = 3;
411 else if (IS_BROXTON(dev_priv)) {
412 /*
413 * Skylake and Broxton currently don't expose the topmost plane as its
414 * use is exclusive with the legacy cursor and we only want to expose
415 * one of those, not both. Until we can safely expose the topmost plane
416 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
417 * we don't expose the topmost plane at all to prevent ABI breakage
418 * down the line.
419 */
420
421 runtime->num_sprites[PIPE_A] = 2;
422 runtime->num_sprites[PIPE_B] = 2;
423 runtime->num_sprites[PIPE_C] = 1;
424 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
425 for_each_pipe(dev_priv, pipe)
426 runtime->num_sprites[pipe] = 2;
427 } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
428 for_each_pipe(dev_priv, pipe)
429 runtime->num_sprites[pipe] = 1;
430 }
431
432 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
433 HAS_PCH_SPLIT(dev_priv)) {
434 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
435 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
436
437 /*
438 * SFUSE_STRAP is supposed to have a bit signalling the display
439 * is fused off. Unfortunately it seems that, at least in
440 * certain cases, fused off display means that PCH display
441 * reads don't land anywhere. In that case, we read 0s.
442 *
443 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
444 * should be set when taking over after the firmware.
445 */
446 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
447 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
448 (HAS_PCH_CPT(dev_priv) &&
449 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
450 drm_info(&dev_priv->drm,
451 "Display fused off, disabling\n");
452 runtime->pipe_mask = 0;
453 runtime->cpu_transcoder_mask = 0;
454 runtime->fbc_mask = 0;
455 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
456 drm_info(&dev_priv->drm, "PipeC fused off\n");
457 runtime->pipe_mask &= ~BIT(PIPE_C);
458 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
459 }
460 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
461 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
462
463 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
464 runtime->pipe_mask &= ~BIT(PIPE_A);
465 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
466 runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
467 }
468 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
469 runtime->pipe_mask &= ~BIT(PIPE_B);
470 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
471 }
472 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
473 runtime->pipe_mask &= ~BIT(PIPE_C);
474 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
475 }
476
477 if (DISPLAY_VER(dev_priv) >= 12 &&
478 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
479 runtime->pipe_mask &= ~BIT(PIPE_D);
480 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
481 }
482
483 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
484 runtime->has_hdcp = 0;
485
486 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
487 runtime->fbc_mask = 0;
488
489 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
490 runtime->has_dmc = 0;
491
492 if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
493 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
494 runtime->has_dsc = 0;
495 }
496
497 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
498 drm_info(&dev_priv->drm,
499 "Disabling ppGTT for VT-d support\n");
500 runtime->ppgtt_type = INTEL_PPGTT_NONE;
501 }
502
503 runtime->rawclk_freq = intel_read_rawclk(dev_priv);
504 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
505
506 if (!HAS_DISPLAY(dev_priv)) {
507 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
508 DRIVER_ATOMIC);
509 memset(&info->display, 0, sizeof(info->display));
510
511 runtime->cpu_transcoder_mask = 0;
512 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
513 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
514 runtime->fbc_mask = 0;
515 runtime->has_hdcp = false;
516 runtime->has_dmc = false;
517 runtime->has_dsc = false;
518 }
519
520 /* Disable nuclear pageflip by default on pre-g4x */
521 if (!dev_priv->params.nuclear_pageflip &&
522 DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
523 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
524}
525
526void intel_driver_caps_print(const struct intel_driver_caps *caps,
527 struct drm_printer *p)
528{
529 drm_printf(p, "Has logical contexts? %s\n",
530 str_yes_no(caps->has_logical_contexts));
531 drm_printf(p, "scheduler: %x\n", caps->scheduler);
532}
1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <drm/drm_print.h>
26#include <drm/i915_pciids.h>
27
28#include "display/intel_cdclk.h"
29#include "display/intel_de.h"
30#include "intel_device_info.h"
31#include "i915_drv.h"
32
33#define PLATFORM_NAME(x) [INTEL_##x] = #x
34static const char * const platform_names[] = {
35 PLATFORM_NAME(I830),
36 PLATFORM_NAME(I845G),
37 PLATFORM_NAME(I85X),
38 PLATFORM_NAME(I865G),
39 PLATFORM_NAME(I915G),
40 PLATFORM_NAME(I915GM),
41 PLATFORM_NAME(I945G),
42 PLATFORM_NAME(I945GM),
43 PLATFORM_NAME(G33),
44 PLATFORM_NAME(PINEVIEW),
45 PLATFORM_NAME(I965G),
46 PLATFORM_NAME(I965GM),
47 PLATFORM_NAME(G45),
48 PLATFORM_NAME(GM45),
49 PLATFORM_NAME(IRONLAKE),
50 PLATFORM_NAME(SANDYBRIDGE),
51 PLATFORM_NAME(IVYBRIDGE),
52 PLATFORM_NAME(VALLEYVIEW),
53 PLATFORM_NAME(HASWELL),
54 PLATFORM_NAME(BROADWELL),
55 PLATFORM_NAME(CHERRYVIEW),
56 PLATFORM_NAME(SKYLAKE),
57 PLATFORM_NAME(BROXTON),
58 PLATFORM_NAME(KABYLAKE),
59 PLATFORM_NAME(GEMINILAKE),
60 PLATFORM_NAME(COFFEELAKE),
61 PLATFORM_NAME(COMETLAKE),
62 PLATFORM_NAME(CANNONLAKE),
63 PLATFORM_NAME(ICELAKE),
64 PLATFORM_NAME(ELKHARTLAKE),
65 PLATFORM_NAME(JASPERLAKE),
66 PLATFORM_NAME(TIGERLAKE),
67 PLATFORM_NAME(ROCKETLAKE),
68 PLATFORM_NAME(DG1),
69 PLATFORM_NAME(ALDERLAKE_S),
70 PLATFORM_NAME(ALDERLAKE_P),
71};
72#undef PLATFORM_NAME
73
74const char *intel_platform_name(enum intel_platform platform)
75{
76 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
77
78 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
79 platform_names[platform] == NULL))
80 return "<unknown>";
81
82 return platform_names[platform];
83}
84
85static const char *iommu_name(void)
86{
87 const char *msg = "n/a";
88
89#ifdef CONFIG_INTEL_IOMMU
90 msg = enableddisabled(intel_iommu_gfx_mapped);
91#endif
92
93 return msg;
94}
95
96void intel_device_info_print_static(const struct intel_device_info *info,
97 struct drm_printer *p)
98{
99 drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
100 drm_printf(p, "media_ver: %u\n", info->media_ver);
101 drm_printf(p, "display_ver: %u\n", info->display.ver);
102 drm_printf(p, "gt: %d\n", info->gt);
103 drm_printf(p, "iommu: %s\n", iommu_name());
104 drm_printf(p, "memory-regions: %x\n", info->memory_regions);
105 drm_printf(p, "page-sizes: %x\n", info->page_sizes);
106 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
107 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
108 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
109 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
110
111#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
112 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
113#undef PRINT_FLAG
114
115#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
116 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
117#undef PRINT_FLAG
118}
119
120void intel_device_info_print_runtime(const struct intel_runtime_info *info,
121 struct drm_printer *p)
122{
123 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
124}
125
126#undef INTEL_VGA_DEVICE
127#define INTEL_VGA_DEVICE(id, info) (id)
128
129static const u16 subplatform_ult_ids[] = {
130 INTEL_HSW_ULT_GT1_IDS(0),
131 INTEL_HSW_ULT_GT2_IDS(0),
132 INTEL_HSW_ULT_GT3_IDS(0),
133 INTEL_BDW_ULT_GT1_IDS(0),
134 INTEL_BDW_ULT_GT2_IDS(0),
135 INTEL_BDW_ULT_GT3_IDS(0),
136 INTEL_BDW_ULT_RSVD_IDS(0),
137 INTEL_SKL_ULT_GT1_IDS(0),
138 INTEL_SKL_ULT_GT2_IDS(0),
139 INTEL_SKL_ULT_GT3_IDS(0),
140 INTEL_KBL_ULT_GT1_IDS(0),
141 INTEL_KBL_ULT_GT2_IDS(0),
142 INTEL_KBL_ULT_GT3_IDS(0),
143 INTEL_CFL_U_GT2_IDS(0),
144 INTEL_CFL_U_GT3_IDS(0),
145 INTEL_WHL_U_GT1_IDS(0),
146 INTEL_WHL_U_GT2_IDS(0),
147 INTEL_WHL_U_GT3_IDS(0),
148 INTEL_CML_U_GT1_IDS(0),
149 INTEL_CML_U_GT2_IDS(0),
150};
151
152static const u16 subplatform_ulx_ids[] = {
153 INTEL_HSW_ULX_GT1_IDS(0),
154 INTEL_HSW_ULX_GT2_IDS(0),
155 INTEL_BDW_ULX_GT1_IDS(0),
156 INTEL_BDW_ULX_GT2_IDS(0),
157 INTEL_BDW_ULX_GT3_IDS(0),
158 INTEL_BDW_ULX_RSVD_IDS(0),
159 INTEL_SKL_ULX_GT1_IDS(0),
160 INTEL_SKL_ULX_GT2_IDS(0),
161 INTEL_KBL_ULX_GT1_IDS(0),
162 INTEL_KBL_ULX_GT2_IDS(0),
163 INTEL_AML_KBL_GT2_IDS(0),
164 INTEL_AML_CFL_GT2_IDS(0),
165};
166
167static const u16 subplatform_portf_ids[] = {
168 INTEL_CNL_PORT_F_IDS(0),
169 INTEL_ICL_PORT_F_IDS(0),
170};
171
172static bool find_devid(u16 id, const u16 *p, unsigned int num)
173{
174 for (; num; num--, p++) {
175 if (*p == id)
176 return true;
177 }
178
179 return false;
180}
181
182void intel_device_info_subplatform_init(struct drm_i915_private *i915)
183{
184 const struct intel_device_info *info = INTEL_INFO(i915);
185 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
186 const unsigned int pi = __platform_mask_index(rinfo, info->platform);
187 const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
188 u16 devid = INTEL_DEVID(i915);
189 u32 mask = 0;
190
191 /* Make sure IS_<platform> checks are working. */
192 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
193
194 /* Find and mark subplatform bits based on the PCI device id. */
195 if (find_devid(devid, subplatform_ult_ids,
196 ARRAY_SIZE(subplatform_ult_ids))) {
197 mask = BIT(INTEL_SUBPLATFORM_ULT);
198 } else if (find_devid(devid, subplatform_ulx_ids,
199 ARRAY_SIZE(subplatform_ulx_ids))) {
200 mask = BIT(INTEL_SUBPLATFORM_ULX);
201 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
202 /* ULX machines are also considered ULT. */
203 mask |= BIT(INTEL_SUBPLATFORM_ULT);
204 }
205 } else if (find_devid(devid, subplatform_portf_ids,
206 ARRAY_SIZE(subplatform_portf_ids))) {
207 mask = BIT(INTEL_SUBPLATFORM_PORTF);
208 }
209
210 if (IS_TIGERLAKE(i915)) {
211 struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev);
212
213 root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
214
215 drm_WARN_ON(&i915->drm, mask);
216 drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
217 TGL_ROOT_DEVICE_ID);
218
219 switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
220 case TGL_ROOT_DEVICE_SKU_ULX:
221 mask = BIT(INTEL_SUBPLATFORM_ULX);
222 break;
223 case TGL_ROOT_DEVICE_SKU_ULT:
224 mask = BIT(INTEL_SUBPLATFORM_ULT);
225 break;
226 }
227 }
228
229 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
230
231 RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
232}
233
234/**
235 * intel_device_info_runtime_init - initialize runtime info
236 * @dev_priv: the i915 device
237 *
238 * Determine various intel_device_info fields at runtime.
239 *
240 * Use it when either:
241 * - it's judged too laborious to fill n static structures with the limit
242 * when a simple if statement does the job,
243 * - run-time checks (eg read fuse/strap registers) are needed.
244 *
245 * This function needs to be called:
246 * - after the MMIO has been setup as we are reading registers,
247 * - after the PCH has been detected,
248 * - before the first usage of the fields it can tweak.
249 */
250void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
251{
252 struct intel_device_info *info = mkwrite_device_info(dev_priv);
253 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
254 enum pipe pipe;
255
256 /* Wa_14011765242: adl-s A0 */
257 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
258 for_each_pipe(dev_priv, pipe)
259 runtime->num_scalers[pipe] = 0;
260 else if (GRAPHICS_VER(dev_priv) >= 10) {
261 for_each_pipe(dev_priv, pipe)
262 runtime->num_scalers[pipe] = 2;
263 } else if (GRAPHICS_VER(dev_priv) == 9) {
264 runtime->num_scalers[PIPE_A] = 2;
265 runtime->num_scalers[PIPE_B] = 2;
266 runtime->num_scalers[PIPE_C] = 1;
267 }
268
269 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
270
271 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
272 for_each_pipe(dev_priv, pipe)
273 runtime->num_sprites[pipe] = 4;
274 else if (GRAPHICS_VER(dev_priv) >= 11)
275 for_each_pipe(dev_priv, pipe)
276 runtime->num_sprites[pipe] = 6;
277 else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
278 for_each_pipe(dev_priv, pipe)
279 runtime->num_sprites[pipe] = 3;
280 else if (IS_BROXTON(dev_priv)) {
281 /*
282 * Skylake and Broxton currently don't expose the topmost plane as its
283 * use is exclusive with the legacy cursor and we only want to expose
284 * one of those, not both. Until we can safely expose the topmost plane
285 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
286 * we don't expose the topmost plane at all to prevent ABI breakage
287 * down the line.
288 */
289
290 runtime->num_sprites[PIPE_A] = 2;
291 runtime->num_sprites[PIPE_B] = 2;
292 runtime->num_sprites[PIPE_C] = 1;
293 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
294 for_each_pipe(dev_priv, pipe)
295 runtime->num_sprites[pipe] = 2;
296 } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
297 for_each_pipe(dev_priv, pipe)
298 runtime->num_sprites[pipe] = 1;
299 }
300
301 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
302 HAS_PCH_SPLIT(dev_priv)) {
303 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
304 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
305
306 /*
307 * SFUSE_STRAP is supposed to have a bit signalling the display
308 * is fused off. Unfortunately it seems that, at least in
309 * certain cases, fused off display means that PCH display
310 * reads don't land anywhere. In that case, we read 0s.
311 *
312 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
313 * should be set when taking over after the firmware.
314 */
315 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
316 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
317 (HAS_PCH_CPT(dev_priv) &&
318 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
319 drm_info(&dev_priv->drm,
320 "Display fused off, disabling\n");
321 info->pipe_mask = 0;
322 info->cpu_transcoder_mask = 0;
323 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
324 drm_info(&dev_priv->drm, "PipeC fused off\n");
325 info->pipe_mask &= ~BIT(PIPE_C);
326 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
327 }
328 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
329 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
330
331 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
332 info->pipe_mask &= ~BIT(PIPE_A);
333 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
334 }
335 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
336 info->pipe_mask &= ~BIT(PIPE_B);
337 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
338 }
339 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
340 info->pipe_mask &= ~BIT(PIPE_C);
341 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
342 }
343
344 if (DISPLAY_VER(dev_priv) >= 12 &&
345 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
346 info->pipe_mask &= ~BIT(PIPE_D);
347 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
348 }
349
350 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
351 info->display.has_hdcp = 0;
352
353 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
354 info->display.has_fbc = 0;
355
356 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
357 info->display.has_dmc = 0;
358
359 if (DISPLAY_VER(dev_priv) >= 10 &&
360 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
361 info->display.has_dsc = 0;
362 }
363
364 if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
365 drm_info(&dev_priv->drm,
366 "Disabling ppGTT for VT-d support\n");
367 info->ppgtt_type = INTEL_PPGTT_NONE;
368 }
369
370 runtime->rawclk_freq = intel_read_rawclk(dev_priv);
371 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
372
373 if (!HAS_DISPLAY(dev_priv)) {
374 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
375 DRIVER_ATOMIC);
376 memset(&info->display, 0, sizeof(info->display));
377 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
378 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
379 }
380}
381
382void intel_driver_caps_print(const struct intel_driver_caps *caps,
383 struct drm_printer *p)
384{
385 drm_printf(p, "Has logical contexts? %s\n",
386 yesno(caps->has_logical_contexts));
387 drm_printf(p, "scheduler: %x\n", caps->scheduler);
388}