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1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/syscore_ops.h>
23#include <linux/gpio/driver.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/bug.h>
27
28#define IMX_SCU_WAKEUP_OFF 0
29#define IMX_SCU_WAKEUP_LOW_LVL 4
30#define IMX_SCU_WAKEUP_FALL_EDGE 5
31#define IMX_SCU_WAKEUP_RISE_EDGE 6
32#define IMX_SCU_WAKEUP_HIGH_LVL 7
33
34/* device type dependent stuff */
35struct mxc_gpio_hwdata {
36 unsigned dr_reg;
37 unsigned gdir_reg;
38 unsigned psr_reg;
39 unsigned icr1_reg;
40 unsigned icr2_reg;
41 unsigned imr_reg;
42 unsigned isr_reg;
43 int edge_sel_reg;
44 unsigned low_level;
45 unsigned high_level;
46 unsigned rise_edge;
47 unsigned fall_edge;
48};
49
50struct mxc_gpio_reg_saved {
51 u32 icr1;
52 u32 icr2;
53 u32 imr;
54 u32 gdir;
55 u32 edge_sel;
56 u32 dr;
57};
58
59struct mxc_gpio_port {
60 struct list_head node;
61 void __iomem *base;
62 struct clk *clk;
63 int irq;
64 int irq_high;
65 struct irq_domain *domain;
66 struct gpio_chip gc;
67 struct device *dev;
68 u32 both_edges;
69 struct mxc_gpio_reg_saved gpio_saved_reg;
70 bool power_off;
71 u32 wakeup_pads;
72 bool is_pad_wakeup;
73 u32 pad_type[32];
74 const struct mxc_gpio_hwdata *hwdata;
75};
76
77static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
78 .dr_reg = 0x1c,
79 .gdir_reg = 0x00,
80 .psr_reg = 0x24,
81 .icr1_reg = 0x28,
82 .icr2_reg = 0x2c,
83 .imr_reg = 0x30,
84 .isr_reg = 0x34,
85 .edge_sel_reg = -EINVAL,
86 .low_level = 0x03,
87 .high_level = 0x02,
88 .rise_edge = 0x00,
89 .fall_edge = 0x01,
90};
91
92static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
93 .dr_reg = 0x00,
94 .gdir_reg = 0x04,
95 .psr_reg = 0x08,
96 .icr1_reg = 0x0c,
97 .icr2_reg = 0x10,
98 .imr_reg = 0x14,
99 .isr_reg = 0x18,
100 .edge_sel_reg = -EINVAL,
101 .low_level = 0x00,
102 .high_level = 0x01,
103 .rise_edge = 0x02,
104 .fall_edge = 0x03,
105};
106
107static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
108 .dr_reg = 0x00,
109 .gdir_reg = 0x04,
110 .psr_reg = 0x08,
111 .icr1_reg = 0x0c,
112 .icr2_reg = 0x10,
113 .imr_reg = 0x14,
114 .isr_reg = 0x18,
115 .edge_sel_reg = 0x1c,
116 .low_level = 0x00,
117 .high_level = 0x01,
118 .rise_edge = 0x02,
119 .fall_edge = 0x03,
120};
121
122#define GPIO_DR (port->hwdata->dr_reg)
123#define GPIO_GDIR (port->hwdata->gdir_reg)
124#define GPIO_PSR (port->hwdata->psr_reg)
125#define GPIO_ICR1 (port->hwdata->icr1_reg)
126#define GPIO_ICR2 (port->hwdata->icr2_reg)
127#define GPIO_IMR (port->hwdata->imr_reg)
128#define GPIO_ISR (port->hwdata->isr_reg)
129#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
130
131#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
132#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
133#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
134#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
135#define GPIO_INT_BOTH_EDGES 0x4
136
137static const struct of_device_id mxc_gpio_dt_ids[] = {
138 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
139 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
140 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
141 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
142 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
143 { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata },
144 { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata },
145 { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata },
146 { /* sentinel */ }
147};
148MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
149
150/*
151 * MX2 has one interrupt *for all* gpio ports. The list is used
152 * to save the references to all ports, so that mx2_gpio_irq_handler
153 * can walk through all interrupt status registers.
154 */
155static LIST_HEAD(mxc_gpio_ports);
156
157/* Note: This driver assumes 32 GPIOs are handled in one register */
158
159static int gpio_set_irq_type(struct irq_data *d, u32 type)
160{
161 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
162 struct mxc_gpio_port *port = gc->private;
163 unsigned long flags;
164 u32 bit, val;
165 u32 gpio_idx = d->hwirq;
166 int edge;
167 void __iomem *reg = port->base;
168
169 port->both_edges &= ~(1 << gpio_idx);
170 switch (type) {
171 case IRQ_TYPE_EDGE_RISING:
172 edge = GPIO_INT_RISE_EDGE;
173 break;
174 case IRQ_TYPE_EDGE_FALLING:
175 edge = GPIO_INT_FALL_EDGE;
176 break;
177 case IRQ_TYPE_EDGE_BOTH:
178 if (GPIO_EDGE_SEL >= 0) {
179 edge = GPIO_INT_BOTH_EDGES;
180 } else {
181 val = port->gc.get(&port->gc, gpio_idx);
182 if (val) {
183 edge = GPIO_INT_LOW_LEV;
184 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
185 } else {
186 edge = GPIO_INT_HIGH_LEV;
187 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
188 }
189 port->both_edges |= 1 << gpio_idx;
190 }
191 break;
192 case IRQ_TYPE_LEVEL_LOW:
193 edge = GPIO_INT_LOW_LEV;
194 break;
195 case IRQ_TYPE_LEVEL_HIGH:
196 edge = GPIO_INT_HIGH_LEV;
197 break;
198 default:
199 return -EINVAL;
200 }
201
202 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
203
204 if (GPIO_EDGE_SEL >= 0) {
205 val = readl(port->base + GPIO_EDGE_SEL);
206 if (edge == GPIO_INT_BOTH_EDGES)
207 writel(val | (1 << gpio_idx),
208 port->base + GPIO_EDGE_SEL);
209 else
210 writel(val & ~(1 << gpio_idx),
211 port->base + GPIO_EDGE_SEL);
212 }
213
214 if (edge != GPIO_INT_BOTH_EDGES) {
215 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
216 bit = gpio_idx & 0xf;
217 val = readl(reg) & ~(0x3 << (bit << 1));
218 writel(val | (edge << (bit << 1)), reg);
219 }
220
221 writel(1 << gpio_idx, port->base + GPIO_ISR);
222 port->pad_type[gpio_idx] = type;
223
224 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
225
226 return port->gc.direction_input(&port->gc, gpio_idx);
227}
228
229static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
230{
231 void __iomem *reg = port->base;
232 unsigned long flags;
233 u32 bit, val;
234 int edge;
235
236 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
237
238 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
239 bit = gpio & 0xf;
240 val = readl(reg);
241 edge = (val >> (bit << 1)) & 3;
242 val &= ~(0x3 << (bit << 1));
243 if (edge == GPIO_INT_HIGH_LEV) {
244 edge = GPIO_INT_LOW_LEV;
245 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
246 } else if (edge == GPIO_INT_LOW_LEV) {
247 edge = GPIO_INT_HIGH_LEV;
248 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
249 } else {
250 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
251 gpio, edge);
252 goto unlock;
253 }
254 writel(val | (edge << (bit << 1)), reg);
255
256unlock:
257 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
258}
259
260/* handle 32 interrupts in one status register */
261static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
262{
263 while (irq_stat != 0) {
264 int irqoffset = fls(irq_stat) - 1;
265
266 if (port->both_edges & (1 << irqoffset))
267 mxc_flip_edge(port, irqoffset);
268
269 generic_handle_domain_irq(port->domain, irqoffset);
270
271 irq_stat &= ~(1 << irqoffset);
272 }
273}
274
275/* MX1 and MX3 has one interrupt *per* gpio port */
276static void mx3_gpio_irq_handler(struct irq_desc *desc)
277{
278 u32 irq_stat;
279 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
280 struct irq_chip *chip = irq_desc_get_chip(desc);
281
282 if (port->is_pad_wakeup)
283 return;
284
285 chained_irq_enter(chip, desc);
286
287 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
288
289 mxc_gpio_irq_handler(port, irq_stat);
290
291 chained_irq_exit(chip, desc);
292}
293
294/* MX2 has one interrupt *for all* gpio ports */
295static void mx2_gpio_irq_handler(struct irq_desc *desc)
296{
297 u32 irq_msk, irq_stat;
298 struct mxc_gpio_port *port;
299 struct irq_chip *chip = irq_desc_get_chip(desc);
300
301 chained_irq_enter(chip, desc);
302
303 /* walk through all interrupt status registers */
304 list_for_each_entry(port, &mxc_gpio_ports, node) {
305 irq_msk = readl(port->base + GPIO_IMR);
306 if (!irq_msk)
307 continue;
308
309 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
310 if (irq_stat)
311 mxc_gpio_irq_handler(port, irq_stat);
312 }
313 chained_irq_exit(chip, desc);
314}
315
316/*
317 * Set interrupt number "irq" in the GPIO as a wake-up source.
318 * While system is running, all registered GPIO interrupts need to have
319 * wake-up enabled. When system is suspended, only selected GPIO interrupts
320 * need to have wake-up enabled.
321 * @param irq interrupt source number
322 * @param enable enable as wake-up if equal to non-zero
323 * @return This function returns 0 on success.
324 */
325static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
326{
327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct mxc_gpio_port *port = gc->private;
329 u32 gpio_idx = d->hwirq;
330 int ret;
331
332 if (enable) {
333 if (port->irq_high && (gpio_idx >= 16))
334 ret = enable_irq_wake(port->irq_high);
335 else
336 ret = enable_irq_wake(port->irq);
337 port->wakeup_pads |= (1 << gpio_idx);
338 } else {
339 if (port->irq_high && (gpio_idx >= 16))
340 ret = disable_irq_wake(port->irq_high);
341 else
342 ret = disable_irq_wake(port->irq);
343 port->wakeup_pads &= ~(1 << gpio_idx);
344 }
345
346 return ret;
347}
348
349static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
350{
351 struct irq_chip_generic *gc;
352 struct irq_chip_type *ct;
353 int rv;
354
355 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
356 port->base, handle_level_irq);
357 if (!gc)
358 return -ENOMEM;
359 gc->private = port;
360
361 ct = gc->chip_types;
362 ct->chip.irq_ack = irq_gc_ack_set_bit;
363 ct->chip.irq_mask = irq_gc_mask_clr_bit;
364 ct->chip.irq_unmask = irq_gc_mask_set_bit;
365 ct->chip.irq_set_type = gpio_set_irq_type;
366 ct->chip.irq_set_wake = gpio_set_wake_irq;
367 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
368 ct->regs.ack = GPIO_ISR;
369 ct->regs.mask = GPIO_IMR;
370
371 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
372 IRQ_GC_INIT_NESTED_LOCK,
373 IRQ_NOREQUEST, 0);
374
375 return rv;
376}
377
378static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
379{
380 struct mxc_gpio_port *port = gpiochip_get_data(gc);
381
382 return irq_find_mapping(port->domain, offset);
383}
384
385static int mxc_gpio_probe(struct platform_device *pdev)
386{
387 struct device_node *np = pdev->dev.of_node;
388 struct mxc_gpio_port *port;
389 int irq_count;
390 int irq_base;
391 int err;
392
393 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
394 if (!port)
395 return -ENOMEM;
396
397 port->dev = &pdev->dev;
398 port->hwdata = device_get_match_data(&pdev->dev);
399
400 port->base = devm_platform_ioremap_resource(pdev, 0);
401 if (IS_ERR(port->base))
402 return PTR_ERR(port->base);
403
404 irq_count = platform_irq_count(pdev);
405 if (irq_count < 0)
406 return irq_count;
407
408 if (irq_count > 1) {
409 port->irq_high = platform_get_irq(pdev, 1);
410 if (port->irq_high < 0)
411 port->irq_high = 0;
412 }
413
414 port->irq = platform_get_irq(pdev, 0);
415 if (port->irq < 0)
416 return port->irq;
417
418 /* the controller clock is optional */
419 port->clk = devm_clk_get_optional(&pdev->dev, NULL);
420 if (IS_ERR(port->clk))
421 return PTR_ERR(port->clk);
422
423 err = clk_prepare_enable(port->clk);
424 if (err) {
425 dev_err(&pdev->dev, "Unable to enable clock.\n");
426 return err;
427 }
428
429 if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
430 port->power_off = true;
431
432 /* disable the interrupt and clear the status */
433 writel(0, port->base + GPIO_IMR);
434 writel(~0, port->base + GPIO_ISR);
435
436 if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
437 /*
438 * Setup one handler for all GPIO interrupts. Actually setting
439 * the handler is needed only once, but doing it for every port
440 * is more robust and easier.
441 */
442 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
443 } else {
444 /* setup one handler for each entry */
445 irq_set_chained_handler_and_data(port->irq,
446 mx3_gpio_irq_handler, port);
447 if (port->irq_high > 0)
448 /* setup handler for GPIO 16 to 31 */
449 irq_set_chained_handler_and_data(port->irq_high,
450 mx3_gpio_irq_handler,
451 port);
452 }
453
454 err = bgpio_init(&port->gc, &pdev->dev, 4,
455 port->base + GPIO_PSR,
456 port->base + GPIO_DR, NULL,
457 port->base + GPIO_GDIR, NULL,
458 BGPIOF_READ_OUTPUT_REG_SET);
459 if (err)
460 goto out_bgio;
461
462 port->gc.request = gpiochip_generic_request;
463 port->gc.free = gpiochip_generic_free;
464 port->gc.to_irq = mxc_gpio_to_irq;
465 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
466 pdev->id * 32;
467
468 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
469 if (err)
470 goto out_bgio;
471
472 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
473 if (irq_base < 0) {
474 err = irq_base;
475 goto out_bgio;
476 }
477
478 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
479 &irq_domain_simple_ops, NULL);
480 if (!port->domain) {
481 err = -ENODEV;
482 goto out_bgio;
483 }
484
485 /* gpio-mxc can be a generic irq chip */
486 err = mxc_gpio_init_gc(port, irq_base);
487 if (err < 0)
488 goto out_irqdomain_remove;
489
490 list_add_tail(&port->node, &mxc_gpio_ports);
491
492 platform_set_drvdata(pdev, port);
493
494 return 0;
495
496out_irqdomain_remove:
497 irq_domain_remove(port->domain);
498out_bgio:
499 clk_disable_unprepare(port->clk);
500 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
501 return err;
502}
503
504static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
505{
506 if (!port->power_off)
507 return;
508
509 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
510 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
511 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
512 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
513 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
514 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
515}
516
517static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
518{
519 if (!port->power_off)
520 return;
521
522 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
523 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
524 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
525 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
526 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
527 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
528}
529
530static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
531 unsigned int offset, unsigned long conf)
532{
533 struct device_node *np = port->dev->of_node;
534
535 if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
536 of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
537 of_device_is_compatible(np, "fsl,imx8qm-gpio"))
538 return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
539
540 return false;
541}
542
543static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
544{
545 unsigned long config;
546 bool ret = false;
547 int i, type;
548
549 static const u32 pad_type_map[] = {
550 IMX_SCU_WAKEUP_OFF, /* 0 */
551 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */
552 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */
553 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */
554 IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */
555 IMX_SCU_WAKEUP_OFF, /* 5 */
556 IMX_SCU_WAKEUP_OFF, /* 6 */
557 IMX_SCU_WAKEUP_OFF, /* 7 */
558 IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */
559 };
560
561 for (i = 0; i < 32; i++) {
562 if ((port->wakeup_pads & (1 << i))) {
563 type = port->pad_type[i];
564 if (enable)
565 config = pad_type_map[type];
566 else
567 config = IMX_SCU_WAKEUP_OFF;
568 ret |= mxc_gpio_generic_config(port, i, config);
569 }
570 }
571
572 return ret;
573}
574
575static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev)
576{
577 struct platform_device *pdev = to_platform_device(dev);
578 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
579
580 if (port->wakeup_pads > 0)
581 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
582
583 return 0;
584}
585
586static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev)
587{
588 struct platform_device *pdev = to_platform_device(dev);
589 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
590
591 if (port->wakeup_pads > 0)
592 mxc_gpio_set_pad_wakeup(port, false);
593 port->is_pad_wakeup = false;
594
595 return 0;
596}
597
598static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
599 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
600};
601
602static int mxc_gpio_syscore_suspend(void)
603{
604 struct mxc_gpio_port *port;
605
606 /* walk through all ports */
607 list_for_each_entry(port, &mxc_gpio_ports, node) {
608 mxc_gpio_save_regs(port);
609 clk_disable_unprepare(port->clk);
610 }
611
612 return 0;
613}
614
615static void mxc_gpio_syscore_resume(void)
616{
617 struct mxc_gpio_port *port;
618 int ret;
619
620 /* walk through all ports */
621 list_for_each_entry(port, &mxc_gpio_ports, node) {
622 ret = clk_prepare_enable(port->clk);
623 if (ret) {
624 pr_err("mxc: failed to enable gpio clock %d\n", ret);
625 return;
626 }
627 mxc_gpio_restore_regs(port);
628 }
629}
630
631static struct syscore_ops mxc_gpio_syscore_ops = {
632 .suspend = mxc_gpio_syscore_suspend,
633 .resume = mxc_gpio_syscore_resume,
634};
635
636static struct platform_driver mxc_gpio_driver = {
637 .driver = {
638 .name = "gpio-mxc",
639 .of_match_table = mxc_gpio_dt_ids,
640 .suppress_bind_attrs = true,
641 .pm = &mxc_gpio_dev_pm_ops,
642 },
643 .probe = mxc_gpio_probe,
644};
645
646static int __init gpio_mxc_init(void)
647{
648 register_syscore_ops(&mxc_gpio_syscore_ops);
649
650 return platform_driver_register(&mxc_gpio_driver);
651}
652subsys_initcall(gpio_mxc_init);
653
654MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
655MODULE_DESCRIPTION("i.MX GPIO Driver");
656MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/syscore_ops.h>
22#include <linux/gpio/driver.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/bug.h>
26
27/* device type dependent stuff */
28struct mxc_gpio_hwdata {
29 unsigned dr_reg;
30 unsigned gdir_reg;
31 unsigned psr_reg;
32 unsigned icr1_reg;
33 unsigned icr2_reg;
34 unsigned imr_reg;
35 unsigned isr_reg;
36 int edge_sel_reg;
37 unsigned low_level;
38 unsigned high_level;
39 unsigned rise_edge;
40 unsigned fall_edge;
41};
42
43struct mxc_gpio_reg_saved {
44 u32 icr1;
45 u32 icr2;
46 u32 imr;
47 u32 gdir;
48 u32 edge_sel;
49 u32 dr;
50};
51
52struct mxc_gpio_port {
53 struct list_head node;
54 void __iomem *base;
55 struct clk *clk;
56 int irq;
57 int irq_high;
58 struct irq_domain *domain;
59 struct gpio_chip gc;
60 struct device *dev;
61 u32 both_edges;
62 struct mxc_gpio_reg_saved gpio_saved_reg;
63 bool power_off;
64 const struct mxc_gpio_hwdata *hwdata;
65};
66
67static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
68 .dr_reg = 0x1c,
69 .gdir_reg = 0x00,
70 .psr_reg = 0x24,
71 .icr1_reg = 0x28,
72 .icr2_reg = 0x2c,
73 .imr_reg = 0x30,
74 .isr_reg = 0x34,
75 .edge_sel_reg = -EINVAL,
76 .low_level = 0x03,
77 .high_level = 0x02,
78 .rise_edge = 0x00,
79 .fall_edge = 0x01,
80};
81
82static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
83 .dr_reg = 0x00,
84 .gdir_reg = 0x04,
85 .psr_reg = 0x08,
86 .icr1_reg = 0x0c,
87 .icr2_reg = 0x10,
88 .imr_reg = 0x14,
89 .isr_reg = 0x18,
90 .edge_sel_reg = -EINVAL,
91 .low_level = 0x00,
92 .high_level = 0x01,
93 .rise_edge = 0x02,
94 .fall_edge = 0x03,
95};
96
97static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
98 .dr_reg = 0x00,
99 .gdir_reg = 0x04,
100 .psr_reg = 0x08,
101 .icr1_reg = 0x0c,
102 .icr2_reg = 0x10,
103 .imr_reg = 0x14,
104 .isr_reg = 0x18,
105 .edge_sel_reg = 0x1c,
106 .low_level = 0x00,
107 .high_level = 0x01,
108 .rise_edge = 0x02,
109 .fall_edge = 0x03,
110};
111
112#define GPIO_DR (port->hwdata->dr_reg)
113#define GPIO_GDIR (port->hwdata->gdir_reg)
114#define GPIO_PSR (port->hwdata->psr_reg)
115#define GPIO_ICR1 (port->hwdata->icr1_reg)
116#define GPIO_ICR2 (port->hwdata->icr2_reg)
117#define GPIO_IMR (port->hwdata->imr_reg)
118#define GPIO_ISR (port->hwdata->isr_reg)
119#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
120
121#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
122#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
123#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
124#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
125#define GPIO_INT_BOTH_EDGES 0x4
126
127static const struct of_device_id mxc_gpio_dt_ids[] = {
128 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
129 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
130 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
131 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
132 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
133 { /* sentinel */ }
134};
135MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
136
137/*
138 * MX2 has one interrupt *for all* gpio ports. The list is used
139 * to save the references to all ports, so that mx2_gpio_irq_handler
140 * can walk through all interrupt status registers.
141 */
142static LIST_HEAD(mxc_gpio_ports);
143
144/* Note: This driver assumes 32 GPIOs are handled in one register */
145
146static int gpio_set_irq_type(struct irq_data *d, u32 type)
147{
148 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
149 struct mxc_gpio_port *port = gc->private;
150 u32 bit, val;
151 u32 gpio_idx = d->hwirq;
152 int edge;
153 void __iomem *reg = port->base;
154
155 port->both_edges &= ~(1 << gpio_idx);
156 switch (type) {
157 case IRQ_TYPE_EDGE_RISING:
158 edge = GPIO_INT_RISE_EDGE;
159 break;
160 case IRQ_TYPE_EDGE_FALLING:
161 edge = GPIO_INT_FALL_EDGE;
162 break;
163 case IRQ_TYPE_EDGE_BOTH:
164 if (GPIO_EDGE_SEL >= 0) {
165 edge = GPIO_INT_BOTH_EDGES;
166 } else {
167 val = port->gc.get(&port->gc, gpio_idx);
168 if (val) {
169 edge = GPIO_INT_LOW_LEV;
170 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
171 } else {
172 edge = GPIO_INT_HIGH_LEV;
173 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
174 }
175 port->both_edges |= 1 << gpio_idx;
176 }
177 break;
178 case IRQ_TYPE_LEVEL_LOW:
179 edge = GPIO_INT_LOW_LEV;
180 break;
181 case IRQ_TYPE_LEVEL_HIGH:
182 edge = GPIO_INT_HIGH_LEV;
183 break;
184 default:
185 return -EINVAL;
186 }
187
188 if (GPIO_EDGE_SEL >= 0) {
189 val = readl(port->base + GPIO_EDGE_SEL);
190 if (edge == GPIO_INT_BOTH_EDGES)
191 writel(val | (1 << gpio_idx),
192 port->base + GPIO_EDGE_SEL);
193 else
194 writel(val & ~(1 << gpio_idx),
195 port->base + GPIO_EDGE_SEL);
196 }
197
198 if (edge != GPIO_INT_BOTH_EDGES) {
199 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
200 bit = gpio_idx & 0xf;
201 val = readl(reg) & ~(0x3 << (bit << 1));
202 writel(val | (edge << (bit << 1)), reg);
203 }
204
205 writel(1 << gpio_idx, port->base + GPIO_ISR);
206
207 return 0;
208}
209
210static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
211{
212 void __iomem *reg = port->base;
213 u32 bit, val;
214 int edge;
215
216 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
217 bit = gpio & 0xf;
218 val = readl(reg);
219 edge = (val >> (bit << 1)) & 3;
220 val &= ~(0x3 << (bit << 1));
221 if (edge == GPIO_INT_HIGH_LEV) {
222 edge = GPIO_INT_LOW_LEV;
223 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
224 } else if (edge == GPIO_INT_LOW_LEV) {
225 edge = GPIO_INT_HIGH_LEV;
226 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
227 } else {
228 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
229 gpio, edge);
230 return;
231 }
232 writel(val | (edge << (bit << 1)), reg);
233}
234
235/* handle 32 interrupts in one status register */
236static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
237{
238 while (irq_stat != 0) {
239 int irqoffset = fls(irq_stat) - 1;
240
241 if (port->both_edges & (1 << irqoffset))
242 mxc_flip_edge(port, irqoffset);
243
244 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
245
246 irq_stat &= ~(1 << irqoffset);
247 }
248}
249
250/* MX1 and MX3 has one interrupt *per* gpio port */
251static void mx3_gpio_irq_handler(struct irq_desc *desc)
252{
253 u32 irq_stat;
254 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
255 struct irq_chip *chip = irq_desc_get_chip(desc);
256
257 chained_irq_enter(chip, desc);
258
259 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
260
261 mxc_gpio_irq_handler(port, irq_stat);
262
263 chained_irq_exit(chip, desc);
264}
265
266/* MX2 has one interrupt *for all* gpio ports */
267static void mx2_gpio_irq_handler(struct irq_desc *desc)
268{
269 u32 irq_msk, irq_stat;
270 struct mxc_gpio_port *port;
271 struct irq_chip *chip = irq_desc_get_chip(desc);
272
273 chained_irq_enter(chip, desc);
274
275 /* walk through all interrupt status registers */
276 list_for_each_entry(port, &mxc_gpio_ports, node) {
277 irq_msk = readl(port->base + GPIO_IMR);
278 if (!irq_msk)
279 continue;
280
281 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
282 if (irq_stat)
283 mxc_gpio_irq_handler(port, irq_stat);
284 }
285 chained_irq_exit(chip, desc);
286}
287
288/*
289 * Set interrupt number "irq" in the GPIO as a wake-up source.
290 * While system is running, all registered GPIO interrupts need to have
291 * wake-up enabled. When system is suspended, only selected GPIO interrupts
292 * need to have wake-up enabled.
293 * @param irq interrupt source number
294 * @param enable enable as wake-up if equal to non-zero
295 * @return This function returns 0 on success.
296 */
297static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
298{
299 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
300 struct mxc_gpio_port *port = gc->private;
301 u32 gpio_idx = d->hwirq;
302 int ret;
303
304 if (enable) {
305 if (port->irq_high && (gpio_idx >= 16))
306 ret = enable_irq_wake(port->irq_high);
307 else
308 ret = enable_irq_wake(port->irq);
309 } else {
310 if (port->irq_high && (gpio_idx >= 16))
311 ret = disable_irq_wake(port->irq_high);
312 else
313 ret = disable_irq_wake(port->irq);
314 }
315
316 return ret;
317}
318
319static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
320{
321 struct irq_chip_generic *gc;
322 struct irq_chip_type *ct;
323 int rv;
324
325 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
326 port->base, handle_level_irq);
327 if (!gc)
328 return -ENOMEM;
329 gc->private = port;
330
331 ct = gc->chip_types;
332 ct->chip.irq_ack = irq_gc_ack_set_bit;
333 ct->chip.irq_mask = irq_gc_mask_clr_bit;
334 ct->chip.irq_unmask = irq_gc_mask_set_bit;
335 ct->chip.irq_set_type = gpio_set_irq_type;
336 ct->chip.irq_set_wake = gpio_set_wake_irq;
337 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
338 ct->regs.ack = GPIO_ISR;
339 ct->regs.mask = GPIO_IMR;
340
341 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
342 IRQ_GC_INIT_NESTED_LOCK,
343 IRQ_NOREQUEST, 0);
344
345 return rv;
346}
347
348static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
349{
350 struct mxc_gpio_port *port = gpiochip_get_data(gc);
351
352 return irq_find_mapping(port->domain, offset);
353}
354
355static int mxc_gpio_probe(struct platform_device *pdev)
356{
357 struct device_node *np = pdev->dev.of_node;
358 struct mxc_gpio_port *port;
359 int irq_count;
360 int irq_base;
361 int err;
362
363 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
364 if (!port)
365 return -ENOMEM;
366
367 port->dev = &pdev->dev;
368
369 port->hwdata = device_get_match_data(&pdev->dev);
370
371 port->base = devm_platform_ioremap_resource(pdev, 0);
372 if (IS_ERR(port->base))
373 return PTR_ERR(port->base);
374
375 irq_count = platform_irq_count(pdev);
376 if (irq_count < 0)
377 return irq_count;
378
379 if (irq_count > 1) {
380 port->irq_high = platform_get_irq(pdev, 1);
381 if (port->irq_high < 0)
382 port->irq_high = 0;
383 }
384
385 port->irq = platform_get_irq(pdev, 0);
386 if (port->irq < 0)
387 return port->irq;
388
389 /* the controller clock is optional */
390 port->clk = devm_clk_get_optional(&pdev->dev, NULL);
391 if (IS_ERR(port->clk))
392 return PTR_ERR(port->clk);
393
394 err = clk_prepare_enable(port->clk);
395 if (err) {
396 dev_err(&pdev->dev, "Unable to enable clock.\n");
397 return err;
398 }
399
400 if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
401 port->power_off = true;
402
403 /* disable the interrupt and clear the status */
404 writel(0, port->base + GPIO_IMR);
405 writel(~0, port->base + GPIO_ISR);
406
407 if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
408 /*
409 * Setup one handler for all GPIO interrupts. Actually setting
410 * the handler is needed only once, but doing it for every port
411 * is more robust and easier.
412 */
413 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
414 } else {
415 /* setup one handler for each entry */
416 irq_set_chained_handler_and_data(port->irq,
417 mx3_gpio_irq_handler, port);
418 if (port->irq_high > 0)
419 /* setup handler for GPIO 16 to 31 */
420 irq_set_chained_handler_and_data(port->irq_high,
421 mx3_gpio_irq_handler,
422 port);
423 }
424
425 err = bgpio_init(&port->gc, &pdev->dev, 4,
426 port->base + GPIO_PSR,
427 port->base + GPIO_DR, NULL,
428 port->base + GPIO_GDIR, NULL,
429 BGPIOF_READ_OUTPUT_REG_SET);
430 if (err)
431 goto out_bgio;
432
433 port->gc.request = gpiochip_generic_request;
434 port->gc.free = gpiochip_generic_free;
435 port->gc.to_irq = mxc_gpio_to_irq;
436 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
437 pdev->id * 32;
438
439 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
440 if (err)
441 goto out_bgio;
442
443 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
444 if (irq_base < 0) {
445 err = irq_base;
446 goto out_bgio;
447 }
448
449 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
450 &irq_domain_simple_ops, NULL);
451 if (!port->domain) {
452 err = -ENODEV;
453 goto out_bgio;
454 }
455
456 /* gpio-mxc can be a generic irq chip */
457 err = mxc_gpio_init_gc(port, irq_base);
458 if (err < 0)
459 goto out_irqdomain_remove;
460
461 list_add_tail(&port->node, &mxc_gpio_ports);
462
463 platform_set_drvdata(pdev, port);
464
465 return 0;
466
467out_irqdomain_remove:
468 irq_domain_remove(port->domain);
469out_bgio:
470 clk_disable_unprepare(port->clk);
471 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
472 return err;
473}
474
475static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
476{
477 if (!port->power_off)
478 return;
479
480 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
481 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
482 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
483 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
484 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
485 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
486}
487
488static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
489{
490 if (!port->power_off)
491 return;
492
493 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
494 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
495 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
496 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
497 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
498 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
499}
500
501static int mxc_gpio_syscore_suspend(void)
502{
503 struct mxc_gpio_port *port;
504
505 /* walk through all ports */
506 list_for_each_entry(port, &mxc_gpio_ports, node) {
507 mxc_gpio_save_regs(port);
508 clk_disable_unprepare(port->clk);
509 }
510
511 return 0;
512}
513
514static void mxc_gpio_syscore_resume(void)
515{
516 struct mxc_gpio_port *port;
517 int ret;
518
519 /* walk through all ports */
520 list_for_each_entry(port, &mxc_gpio_ports, node) {
521 ret = clk_prepare_enable(port->clk);
522 if (ret) {
523 pr_err("mxc: failed to enable gpio clock %d\n", ret);
524 return;
525 }
526 mxc_gpio_restore_regs(port);
527 }
528}
529
530static struct syscore_ops mxc_gpio_syscore_ops = {
531 .suspend = mxc_gpio_syscore_suspend,
532 .resume = mxc_gpio_syscore_resume,
533};
534
535static struct platform_driver mxc_gpio_driver = {
536 .driver = {
537 .name = "gpio-mxc",
538 .of_match_table = mxc_gpio_dt_ids,
539 .suppress_bind_attrs = true,
540 },
541 .probe = mxc_gpio_probe,
542};
543
544static int __init gpio_mxc_init(void)
545{
546 register_syscore_ops(&mxc_gpio_syscore_ops);
547
548 return platform_driver_register(&mxc_gpio_driver);
549}
550subsys_initcall(gpio_mxc_init);
551
552MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
553MODULE_DESCRIPTION("i.MX GPIO Driver");
554MODULE_LICENSE("GPL");