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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7#include <linux/acpi.h>
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/property.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23
24#include "gpiolib.h"
25#include "gpiolib-acpi.h"
26
27#define GPIO_SWPORTA_DR 0x00
28#define GPIO_SWPORTA_DDR 0x04
29#define GPIO_SWPORTB_DR 0x0c
30#define GPIO_SWPORTB_DDR 0x10
31#define GPIO_SWPORTC_DR 0x18
32#define GPIO_SWPORTC_DDR 0x1c
33#define GPIO_SWPORTD_DR 0x24
34#define GPIO_SWPORTD_DDR 0x28
35#define GPIO_INTEN 0x30
36#define GPIO_INTMASK 0x34
37#define GPIO_INTTYPE_LEVEL 0x38
38#define GPIO_INT_POLARITY 0x3c
39#define GPIO_INTSTATUS 0x40
40#define GPIO_PORTA_DEBOUNCE 0x48
41#define GPIO_PORTA_EOI 0x4c
42#define GPIO_EXT_PORTA 0x50
43#define GPIO_EXT_PORTB 0x54
44#define GPIO_EXT_PORTC 0x58
45#define GPIO_EXT_PORTD 0x5c
46
47#define DWAPB_DRIVER_NAME "gpio-dwapb"
48#define DWAPB_MAX_PORTS 4
49#define DWAPB_MAX_GPIOS 32
50
51#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
52#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
53#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
54
55#define GPIO_REG_OFFSET_V1 0
56#define GPIO_REG_OFFSET_V2 1
57#define GPIO_REG_OFFSET_MASK BIT(0)
58
59#define GPIO_INTMASK_V2 0x44
60#define GPIO_INTTYPE_LEVEL_V2 0x34
61#define GPIO_INT_POLARITY_V2 0x38
62#define GPIO_INTSTATUS_V2 0x3c
63#define GPIO_PORTA_EOI_V2 0x40
64
65#define DWAPB_NR_CLOCKS 2
66
67struct dwapb_gpio;
68
69struct dwapb_port_property {
70 struct fwnode_handle *fwnode;
71 unsigned int idx;
72 unsigned int ngpio;
73 unsigned int gpio_base;
74 int irq[DWAPB_MAX_GPIOS];
75};
76
77struct dwapb_platform_data {
78 struct dwapb_port_property *properties;
79 unsigned int nports;
80};
81
82#ifdef CONFIG_PM_SLEEP
83/* Store GPIO context across system-wide suspend/resume transitions */
84struct dwapb_context {
85 u32 data;
86 u32 dir;
87 u32 ext;
88 u32 int_en;
89 u32 int_mask;
90 u32 int_type;
91 u32 int_pol;
92 u32 int_deb;
93 u32 wake_en;
94};
95#endif
96
97struct dwapb_gpio_port_irqchip {
98 unsigned int nr_irqs;
99 unsigned int irq[DWAPB_MAX_GPIOS];
100};
101
102struct dwapb_gpio_port {
103 struct gpio_chip gc;
104 struct dwapb_gpio_port_irqchip *pirq;
105 struct dwapb_gpio *gpio;
106#ifdef CONFIG_PM_SLEEP
107 struct dwapb_context *ctx;
108#endif
109 unsigned int idx;
110};
111#define to_dwapb_gpio(_gc) \
112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
113
114struct dwapb_gpio {
115 struct device *dev;
116 void __iomem *regs;
117 struct dwapb_gpio_port *ports;
118 unsigned int nr_ports;
119 unsigned int flags;
120 struct reset_control *rst;
121 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
122};
123
124static inline u32 gpio_reg_v2_convert(unsigned int offset)
125{
126 switch (offset) {
127 case GPIO_INTMASK:
128 return GPIO_INTMASK_V2;
129 case GPIO_INTTYPE_LEVEL:
130 return GPIO_INTTYPE_LEVEL_V2;
131 case GPIO_INT_POLARITY:
132 return GPIO_INT_POLARITY_V2;
133 case GPIO_INTSTATUS:
134 return GPIO_INTSTATUS_V2;
135 case GPIO_PORTA_EOI:
136 return GPIO_PORTA_EOI_V2;
137 }
138
139 return offset;
140}
141
142static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143{
144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
145 return gpio_reg_v2_convert(offset);
146
147 return offset;
148}
149
150static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
151{
152 struct gpio_chip *gc = &gpio->ports[0].gc;
153 void __iomem *reg_base = gpio->regs;
154
155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
156}
157
158static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
159 u32 val)
160{
161 struct gpio_chip *gc = &gpio->ports[0].gc;
162 void __iomem *reg_base = gpio->regs;
163
164 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
165}
166
167static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
168{
169 struct dwapb_gpio_port *port;
170 int i;
171
172 for (i = 0; i < gpio->nr_ports; i++) {
173 port = &gpio->ports[i];
174 if (port->idx == offs / DWAPB_MAX_GPIOS)
175 return port;
176 }
177
178 return NULL;
179}
180
181static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
182{
183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
184 struct gpio_chip *gc;
185 u32 pol;
186 int val;
187
188 if (!port)
189 return;
190 gc = &port->gc;
191
192 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
193 /* Just read the current value right out of the data register */
194 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
195 if (val)
196 pol &= ~BIT(offs);
197 else
198 pol |= BIT(offs);
199
200 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
201}
202
203static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
204{
205 struct gpio_chip *gc = &gpio->ports[0].gc;
206 unsigned long irq_status;
207 irq_hw_number_t hwirq;
208
209 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
210 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
211 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
212 u32 irq_type = irq_get_trigger_type(gpio_irq);
213
214 generic_handle_irq(gpio_irq);
215
216 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
217 dwapb_toggle_trigger(gpio, hwirq);
218 }
219
220 return irq_status;
221}
222
223static void dwapb_irq_handler(struct irq_desc *desc)
224{
225 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
226 struct irq_chip *chip = irq_desc_get_chip(desc);
227
228 chained_irq_enter(chip, desc);
229 dwapb_do_irq(gpio);
230 chained_irq_exit(chip, desc);
231}
232
233static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
234{
235 return IRQ_RETVAL(dwapb_do_irq(dev_id));
236}
237
238static void dwapb_irq_ack(struct irq_data *d)
239{
240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
242 u32 val = BIT(irqd_to_hwirq(d));
243 unsigned long flags;
244
245 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
246 dwapb_write(gpio, GPIO_PORTA_EOI, val);
247 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
248}
249
250static void dwapb_irq_mask(struct irq_data *d)
251{
252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
254 irq_hw_number_t hwirq = irqd_to_hwirq(d);
255 unsigned long flags;
256 u32 val;
257
258 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
260 dwapb_write(gpio, GPIO_INTMASK, val);
261 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
262
263 gpiochip_disable_irq(gc, hwirq);
264}
265
266static void dwapb_irq_unmask(struct irq_data *d)
267{
268 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
269 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
270 irq_hw_number_t hwirq = irqd_to_hwirq(d);
271 unsigned long flags;
272 u32 val;
273
274 gpiochip_enable_irq(gc, hwirq);
275
276 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
277 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
278 dwapb_write(gpio, GPIO_INTMASK, val);
279 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
280}
281
282static void dwapb_irq_enable(struct irq_data *d)
283{
284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
285 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
286 unsigned long flags;
287 u32 val;
288
289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
290 val = dwapb_read(gpio, GPIO_INTEN);
291 val |= BIT(irqd_to_hwirq(d));
292 dwapb_write(gpio, GPIO_INTEN, val);
293 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
294}
295
296static void dwapb_irq_disable(struct irq_data *d)
297{
298 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
299 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
300 unsigned long flags;
301 u32 val;
302
303 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
304 val = dwapb_read(gpio, GPIO_INTEN);
305 val &= ~BIT(irqd_to_hwirq(d));
306 dwapb_write(gpio, GPIO_INTEN, val);
307 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
308}
309
310static int dwapb_irq_set_type(struct irq_data *d, u32 type)
311{
312 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
313 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
314 irq_hw_number_t bit = irqd_to_hwirq(d);
315 unsigned long level, polarity, flags;
316
317 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
318 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
319 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
320
321 switch (type) {
322 case IRQ_TYPE_EDGE_BOTH:
323 level |= BIT(bit);
324 dwapb_toggle_trigger(gpio, bit);
325 break;
326 case IRQ_TYPE_EDGE_RISING:
327 level |= BIT(bit);
328 polarity |= BIT(bit);
329 break;
330 case IRQ_TYPE_EDGE_FALLING:
331 level |= BIT(bit);
332 polarity &= ~BIT(bit);
333 break;
334 case IRQ_TYPE_LEVEL_HIGH:
335 level &= ~BIT(bit);
336 polarity |= BIT(bit);
337 break;
338 case IRQ_TYPE_LEVEL_LOW:
339 level &= ~BIT(bit);
340 polarity &= ~BIT(bit);
341 break;
342 }
343
344 if (type & IRQ_TYPE_LEVEL_MASK)
345 irq_set_handler_locked(d, handle_level_irq);
346 else if (type & IRQ_TYPE_EDGE_BOTH)
347 irq_set_handler_locked(d, handle_edge_irq);
348
349 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
350 if (type != IRQ_TYPE_EDGE_BOTH)
351 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
352 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
353
354 return 0;
355}
356
357#ifdef CONFIG_PM_SLEEP
358static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
359{
360 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
361 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
362 struct dwapb_context *ctx = gpio->ports[0].ctx;
363 irq_hw_number_t bit = irqd_to_hwirq(d);
364
365 if (enable)
366 ctx->wake_en |= BIT(bit);
367 else
368 ctx->wake_en &= ~BIT(bit);
369
370 return 0;
371}
372#else
373#define dwapb_irq_set_wake NULL
374#endif
375
376static const struct irq_chip dwapb_irq_chip = {
377 .name = DWAPB_DRIVER_NAME,
378 .irq_ack = dwapb_irq_ack,
379 .irq_mask = dwapb_irq_mask,
380 .irq_unmask = dwapb_irq_unmask,
381 .irq_set_type = dwapb_irq_set_type,
382 .irq_enable = dwapb_irq_enable,
383 .irq_disable = dwapb_irq_disable,
384 .irq_set_wake = dwapb_irq_set_wake,
385 .flags = IRQCHIP_IMMUTABLE,
386 GPIOCHIP_IRQ_RESOURCE_HELPERS,
387};
388
389static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
390 unsigned offset, unsigned debounce)
391{
392 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
393 struct dwapb_gpio *gpio = port->gpio;
394 unsigned long flags, val_deb;
395 unsigned long mask = BIT(offset);
396
397 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
398
399 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
400 if (debounce)
401 val_deb |= mask;
402 else
403 val_deb &= ~mask;
404 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
405
406 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
407
408 return 0;
409}
410
411static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
412 unsigned long config)
413{
414 u32 debounce;
415
416 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
417 return -ENOTSUPP;
418
419 debounce = pinconf_to_config_argument(config);
420 return dwapb_gpio_set_debounce(gc, offset, debounce);
421}
422
423static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
424 struct dwapb_port_property *pp)
425{
426 int i;
427
428 /* Group all available IRQs into an array of parental IRQs. */
429 for (i = 0; i < pp->ngpio; ++i) {
430 if (!pp->irq[i])
431 continue;
432
433 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
434 }
435
436 return pirq->nr_irqs ? 0 : -ENOENT;
437}
438
439static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
440 struct dwapb_gpio_port *port,
441 struct dwapb_port_property *pp)
442{
443 struct dwapb_gpio_port_irqchip *pirq;
444 struct gpio_chip *gc = &port->gc;
445 struct gpio_irq_chip *girq;
446 int err;
447
448 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
449 if (!pirq)
450 return;
451
452 if (dwapb_convert_irqs(pirq, pp)) {
453 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
454 goto err_kfree_pirq;
455 }
456
457 girq = &gc->irq;
458 girq->handler = handle_bad_irq;
459 girq->default_type = IRQ_TYPE_NONE;
460
461 port->pirq = pirq;
462
463 /*
464 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
465 * IRQ lane shared between several devices. In that case the parental
466 * IRQ has to be handled in the shared way so to be properly delivered
467 * to all the connected devices.
468 */
469 if (has_acpi_companion(gpio->dev)) {
470 girq->num_parents = 0;
471 girq->parents = NULL;
472 girq->parent_handler = NULL;
473
474 err = devm_request_irq(gpio->dev, pp->irq[0],
475 dwapb_irq_handler_mfd,
476 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
477 if (err) {
478 dev_err(gpio->dev, "error requesting IRQ\n");
479 goto err_kfree_pirq;
480 }
481 } else {
482 girq->num_parents = pirq->nr_irqs;
483 girq->parents = pirq->irq;
484 girq->parent_handler_data = gpio;
485 girq->parent_handler = dwapb_irq_handler;
486 }
487
488 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
489
490 return;
491
492err_kfree_pirq:
493 devm_kfree(gpio->dev, pirq);
494}
495
496static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
497 struct dwapb_port_property *pp,
498 unsigned int offs)
499{
500 struct dwapb_gpio_port *port;
501 void __iomem *dat, *set, *dirout;
502 int err;
503
504 port = &gpio->ports[offs];
505 port->gpio = gpio;
506 port->idx = pp->idx;
507
508#ifdef CONFIG_PM_SLEEP
509 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
510 if (!port->ctx)
511 return -ENOMEM;
512#endif
513
514 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
515 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
516 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
517
518 /* This registers 32 GPIO lines per port */
519 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
520 NULL, 0);
521 if (err) {
522 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
523 port->idx);
524 return err;
525 }
526
527 port->gc.fwnode = pp->fwnode;
528 port->gc.ngpio = pp->ngpio;
529 port->gc.base = pp->gpio_base;
530
531 /* Only port A support debounce */
532 if (pp->idx == 0)
533 port->gc.set_config = dwapb_gpio_set_config;
534
535 /* Only port A can provide interrupts in all configurations of the IP */
536 if (pp->idx == 0)
537 dwapb_configure_irqs(gpio, port, pp);
538
539 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
540 if (err) {
541 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
542 port->idx);
543 return err;
544 }
545
546 return 0;
547}
548
549static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
550 struct dwapb_port_property *pp)
551{
552 int irq, j;
553
554 for (j = 0; j < pp->ngpio; j++) {
555 if (has_acpi_companion(dev))
556 irq = platform_get_irq_optional(to_platform_device(dev), j);
557 else
558 irq = fwnode_irq_get(fwnode, j);
559 if (irq > 0)
560 pp->irq[j] = irq;
561 }
562}
563
564static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
565{
566 struct fwnode_handle *fwnode;
567 struct dwapb_platform_data *pdata;
568 struct dwapb_port_property *pp;
569 int nports;
570 int i;
571
572 nports = device_get_child_node_count(dev);
573 if (nports == 0)
574 return ERR_PTR(-ENODEV);
575
576 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
577 if (!pdata)
578 return ERR_PTR(-ENOMEM);
579
580 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
581 if (!pdata->properties)
582 return ERR_PTR(-ENOMEM);
583
584 pdata->nports = nports;
585
586 i = 0;
587 device_for_each_child_node(dev, fwnode) {
588 pp = &pdata->properties[i++];
589 pp->fwnode = fwnode;
590
591 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
592 pp->idx >= DWAPB_MAX_PORTS) {
593 dev_err(dev,
594 "missing/invalid port index for port%d\n", i);
595 fwnode_handle_put(fwnode);
596 return ERR_PTR(-EINVAL);
597 }
598
599 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
600 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
601 dev_info(dev,
602 "failed to get number of gpios for port%d\n",
603 i);
604 pp->ngpio = DWAPB_MAX_GPIOS;
605 }
606
607 pp->gpio_base = -1;
608
609 /* For internal use only, new platforms mustn't exercise this */
610 if (is_software_node(fwnode))
611 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
612
613 /*
614 * Only port A can provide interrupts in all configurations of
615 * the IP.
616 */
617 if (pp->idx == 0)
618 dwapb_get_irq(dev, fwnode, pp);
619 }
620
621 return pdata;
622}
623
624static void dwapb_assert_reset(void *data)
625{
626 struct dwapb_gpio *gpio = data;
627
628 reset_control_assert(gpio->rst);
629}
630
631static int dwapb_get_reset(struct dwapb_gpio *gpio)
632{
633 int err;
634
635 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
636 if (IS_ERR(gpio->rst))
637 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
638 "Cannot get reset descriptor\n");
639
640 err = reset_control_deassert(gpio->rst);
641 if (err) {
642 dev_err(gpio->dev, "Cannot deassert reset lane\n");
643 return err;
644 }
645
646 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
647}
648
649static void dwapb_disable_clks(void *data)
650{
651 struct dwapb_gpio *gpio = data;
652
653 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
654}
655
656static int dwapb_get_clks(struct dwapb_gpio *gpio)
657{
658 int err;
659
660 /* Optional bus and debounce clocks */
661 gpio->clks[0].id = "bus";
662 gpio->clks[1].id = "db";
663 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
664 gpio->clks);
665 if (err)
666 return dev_err_probe(gpio->dev, err,
667 "Cannot get APB/Debounce clocks\n");
668
669 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
670 if (err) {
671 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
672 return err;
673 }
674
675 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
676}
677
678static const struct of_device_id dwapb_of_match[] = {
679 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
680 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
681 { /* Sentinel */ }
682};
683MODULE_DEVICE_TABLE(of, dwapb_of_match);
684
685static const struct acpi_device_id dwapb_acpi_match[] = {
686 {"HISI0181", GPIO_REG_OFFSET_V1},
687 {"APMC0D07", GPIO_REG_OFFSET_V1},
688 {"APMC0D81", GPIO_REG_OFFSET_V2},
689 { }
690};
691MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
692
693static int dwapb_gpio_probe(struct platform_device *pdev)
694{
695 unsigned int i;
696 struct dwapb_gpio *gpio;
697 int err;
698 struct dwapb_platform_data *pdata;
699 struct device *dev = &pdev->dev;
700
701 pdata = dwapb_gpio_get_pdata(dev);
702 if (IS_ERR(pdata))
703 return PTR_ERR(pdata);
704
705 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
706 if (!gpio)
707 return -ENOMEM;
708
709 gpio->dev = &pdev->dev;
710 gpio->nr_ports = pdata->nports;
711
712 err = dwapb_get_reset(gpio);
713 if (err)
714 return err;
715
716 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
717 sizeof(*gpio->ports), GFP_KERNEL);
718 if (!gpio->ports)
719 return -ENOMEM;
720
721 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
722 if (IS_ERR(gpio->regs))
723 return PTR_ERR(gpio->regs);
724
725 err = dwapb_get_clks(gpio);
726 if (err)
727 return err;
728
729 gpio->flags = (uintptr_t)device_get_match_data(dev);
730
731 for (i = 0; i < gpio->nr_ports; i++) {
732 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
733 if (err)
734 return err;
735 }
736
737 platform_set_drvdata(pdev, gpio);
738
739 return 0;
740}
741
742#ifdef CONFIG_PM_SLEEP
743static int dwapb_gpio_suspend(struct device *dev)
744{
745 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
746 struct gpio_chip *gc = &gpio->ports[0].gc;
747 unsigned long flags;
748 int i;
749
750 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
751 for (i = 0; i < gpio->nr_ports; i++) {
752 unsigned int offset;
753 unsigned int idx = gpio->ports[i].idx;
754 struct dwapb_context *ctx = gpio->ports[i].ctx;
755
756 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
757 ctx->dir = dwapb_read(gpio, offset);
758
759 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
760 ctx->data = dwapb_read(gpio, offset);
761
762 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
763 ctx->ext = dwapb_read(gpio, offset);
764
765 /* Only port A can provide interrupts */
766 if (idx == 0) {
767 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
768 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
769 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
770 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
771 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
772
773 /* Mask out interrupts */
774 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
775 }
776 }
777 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
778
779 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
780
781 return 0;
782}
783
784static int dwapb_gpio_resume(struct device *dev)
785{
786 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
787 struct gpio_chip *gc = &gpio->ports[0].gc;
788 unsigned long flags;
789 int i, err;
790
791 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
792 if (err) {
793 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
794 return err;
795 }
796
797 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
798 for (i = 0; i < gpio->nr_ports; i++) {
799 unsigned int offset;
800 unsigned int idx = gpio->ports[i].idx;
801 struct dwapb_context *ctx = gpio->ports[i].ctx;
802
803 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
804 dwapb_write(gpio, offset, ctx->data);
805
806 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
807 dwapb_write(gpio, offset, ctx->dir);
808
809 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
810 dwapb_write(gpio, offset, ctx->ext);
811
812 /* Only port A can provide interrupts */
813 if (idx == 0) {
814 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
815 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
816 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
817 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
818 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
819
820 /* Clear out spurious interrupts */
821 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
822 }
823 }
824 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
825
826 return 0;
827}
828#endif
829
830static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
831 dwapb_gpio_resume);
832
833static struct platform_driver dwapb_gpio_driver = {
834 .driver = {
835 .name = DWAPB_DRIVER_NAME,
836 .pm = &dwapb_gpio_pm_ops,
837 .of_match_table = dwapb_of_match,
838 .acpi_match_table = dwapb_acpi_match,
839 },
840 .probe = dwapb_gpio_probe,
841};
842
843module_platform_driver(dwapb_gpio_driver);
844
845MODULE_LICENSE("GPL");
846MODULE_AUTHOR("Jamie Iles");
847MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
848MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7#include <linux/acpi.h>
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_data/gpio-dwapb.h>
20#include <linux/platform_device.h>
21#include <linux/property.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25
26#include "gpiolib.h"
27#include "gpiolib-acpi.h"
28
29#define GPIO_SWPORTA_DR 0x00
30#define GPIO_SWPORTA_DDR 0x04
31#define GPIO_SWPORTB_DR 0x0c
32#define GPIO_SWPORTB_DDR 0x10
33#define GPIO_SWPORTC_DR 0x18
34#define GPIO_SWPORTC_DDR 0x1c
35#define GPIO_SWPORTD_DR 0x24
36#define GPIO_SWPORTD_DDR 0x28
37#define GPIO_INTEN 0x30
38#define GPIO_INTMASK 0x34
39#define GPIO_INTTYPE_LEVEL 0x38
40#define GPIO_INT_POLARITY 0x3c
41#define GPIO_INTSTATUS 0x40
42#define GPIO_PORTA_DEBOUNCE 0x48
43#define GPIO_PORTA_EOI 0x4c
44#define GPIO_EXT_PORTA 0x50
45#define GPIO_EXT_PORTB 0x54
46#define GPIO_EXT_PORTC 0x58
47#define GPIO_EXT_PORTD 0x5c
48
49#define DWAPB_DRIVER_NAME "gpio-dwapb"
50#define DWAPB_MAX_PORTS 4
51
52#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
53#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
54#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
55
56#define GPIO_REG_OFFSET_V2 1
57
58#define GPIO_INTMASK_V2 0x44
59#define GPIO_INTTYPE_LEVEL_V2 0x34
60#define GPIO_INT_POLARITY_V2 0x38
61#define GPIO_INTSTATUS_V2 0x3c
62#define GPIO_PORTA_EOI_V2 0x40
63
64#define DWAPB_NR_CLOCKS 2
65
66struct dwapb_gpio;
67
68#ifdef CONFIG_PM_SLEEP
69/* Store GPIO context across system-wide suspend/resume transitions */
70struct dwapb_context {
71 u32 data;
72 u32 dir;
73 u32 ext;
74 u32 int_en;
75 u32 int_mask;
76 u32 int_type;
77 u32 int_pol;
78 u32 int_deb;
79 u32 wake_en;
80};
81#endif
82
83struct dwapb_gpio_port_irqchip {
84 struct irq_chip irqchip;
85 unsigned int nr_irqs;
86 unsigned int irq[DWAPB_MAX_GPIOS];
87};
88
89struct dwapb_gpio_port {
90 struct gpio_chip gc;
91 struct dwapb_gpio_port_irqchip *pirq;
92 struct dwapb_gpio *gpio;
93#ifdef CONFIG_PM_SLEEP
94 struct dwapb_context *ctx;
95#endif
96 unsigned int idx;
97};
98#define to_dwapb_gpio(_gc) \
99 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
100
101struct dwapb_gpio {
102 struct device *dev;
103 void __iomem *regs;
104 struct dwapb_gpio_port *ports;
105 unsigned int nr_ports;
106 unsigned int flags;
107 struct reset_control *rst;
108 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
109};
110
111static inline u32 gpio_reg_v2_convert(unsigned int offset)
112{
113 switch (offset) {
114 case GPIO_INTMASK:
115 return GPIO_INTMASK_V2;
116 case GPIO_INTTYPE_LEVEL:
117 return GPIO_INTTYPE_LEVEL_V2;
118 case GPIO_INT_POLARITY:
119 return GPIO_INT_POLARITY_V2;
120 case GPIO_INTSTATUS:
121 return GPIO_INTSTATUS_V2;
122 case GPIO_PORTA_EOI:
123 return GPIO_PORTA_EOI_V2;
124 }
125
126 return offset;
127}
128
129static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
130{
131 if (gpio->flags & GPIO_REG_OFFSET_V2)
132 return gpio_reg_v2_convert(offset);
133
134 return offset;
135}
136
137static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
138{
139 struct gpio_chip *gc = &gpio->ports[0].gc;
140 void __iomem *reg_base = gpio->regs;
141
142 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
143}
144
145static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
146 u32 val)
147{
148 struct gpio_chip *gc = &gpio->ports[0].gc;
149 void __iomem *reg_base = gpio->regs;
150
151 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
152}
153
154static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
155{
156 struct dwapb_gpio_port *port;
157 int i;
158
159 for (i = 0; i < gpio->nr_ports; i++) {
160 port = &gpio->ports[i];
161 if (port->idx == offs / DWAPB_MAX_GPIOS)
162 return port;
163 }
164
165 return NULL;
166}
167
168static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
169{
170 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
171 struct gpio_chip *gc;
172 u32 pol;
173 int val;
174
175 if (!port)
176 return;
177 gc = &port->gc;
178
179 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
180 /* Just read the current value right out of the data register */
181 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
182 if (val)
183 pol &= ~BIT(offs);
184 else
185 pol |= BIT(offs);
186
187 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
188}
189
190static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
191{
192 struct gpio_chip *gc = &gpio->ports[0].gc;
193 unsigned long irq_status;
194 irq_hw_number_t hwirq;
195
196 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
197 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
198 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
199 u32 irq_type = irq_get_trigger_type(gpio_irq);
200
201 generic_handle_irq(gpio_irq);
202
203 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
204 dwapb_toggle_trigger(gpio, hwirq);
205 }
206
207 return irq_status;
208}
209
210static void dwapb_irq_handler(struct irq_desc *desc)
211{
212 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
213 struct irq_chip *chip = irq_desc_get_chip(desc);
214
215 chained_irq_enter(chip, desc);
216 dwapb_do_irq(gpio);
217 chained_irq_exit(chip, desc);
218}
219
220static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
221{
222 return IRQ_RETVAL(dwapb_do_irq(dev_id));
223}
224
225static void dwapb_irq_ack(struct irq_data *d)
226{
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
229 u32 val = BIT(irqd_to_hwirq(d));
230 unsigned long flags;
231
232 spin_lock_irqsave(&gc->bgpio_lock, flags);
233 dwapb_write(gpio, GPIO_PORTA_EOI, val);
234 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235}
236
237static void dwapb_irq_mask(struct irq_data *d)
238{
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
241 unsigned long flags;
242 u32 val;
243
244 spin_lock_irqsave(&gc->bgpio_lock, flags);
245 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
246 dwapb_write(gpio, GPIO_INTMASK, val);
247 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
248}
249
250static void dwapb_irq_unmask(struct irq_data *d)
251{
252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
254 unsigned long flags;
255 u32 val;
256
257 spin_lock_irqsave(&gc->bgpio_lock, flags);
258 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
259 dwapb_write(gpio, GPIO_INTMASK, val);
260 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
261}
262
263static void dwapb_irq_enable(struct irq_data *d)
264{
265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
266 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
267 unsigned long flags;
268 u32 val;
269
270 spin_lock_irqsave(&gc->bgpio_lock, flags);
271 val = dwapb_read(gpio, GPIO_INTEN);
272 val |= BIT(irqd_to_hwirq(d));
273 dwapb_write(gpio, GPIO_INTEN, val);
274 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
275}
276
277static void dwapb_irq_disable(struct irq_data *d)
278{
279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
280 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
281 unsigned long flags;
282 u32 val;
283
284 spin_lock_irqsave(&gc->bgpio_lock, flags);
285 val = dwapb_read(gpio, GPIO_INTEN);
286 val &= ~BIT(irqd_to_hwirq(d));
287 dwapb_write(gpio, GPIO_INTEN, val);
288 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
289}
290
291static int dwapb_irq_set_type(struct irq_data *d, u32 type)
292{
293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
294 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
295 irq_hw_number_t bit = irqd_to_hwirq(d);
296 unsigned long level, polarity, flags;
297
298 spin_lock_irqsave(&gc->bgpio_lock, flags);
299 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
300 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
301
302 switch (type) {
303 case IRQ_TYPE_EDGE_BOTH:
304 level |= BIT(bit);
305 dwapb_toggle_trigger(gpio, bit);
306 break;
307 case IRQ_TYPE_EDGE_RISING:
308 level |= BIT(bit);
309 polarity |= BIT(bit);
310 break;
311 case IRQ_TYPE_EDGE_FALLING:
312 level |= BIT(bit);
313 polarity &= ~BIT(bit);
314 break;
315 case IRQ_TYPE_LEVEL_HIGH:
316 level &= ~BIT(bit);
317 polarity |= BIT(bit);
318 break;
319 case IRQ_TYPE_LEVEL_LOW:
320 level &= ~BIT(bit);
321 polarity &= ~BIT(bit);
322 break;
323 }
324
325 if (type & IRQ_TYPE_LEVEL_MASK)
326 irq_set_handler_locked(d, handle_level_irq);
327 else if (type & IRQ_TYPE_EDGE_BOTH)
328 irq_set_handler_locked(d, handle_edge_irq);
329
330 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
331 if (type != IRQ_TYPE_EDGE_BOTH)
332 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
333 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
334
335 return 0;
336}
337
338#ifdef CONFIG_PM_SLEEP
339static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
340{
341 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
342 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
343 struct dwapb_context *ctx = gpio->ports[0].ctx;
344 irq_hw_number_t bit = irqd_to_hwirq(d);
345
346 if (enable)
347 ctx->wake_en |= BIT(bit);
348 else
349 ctx->wake_en &= ~BIT(bit);
350
351 return 0;
352}
353#endif
354
355static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
356 unsigned offset, unsigned debounce)
357{
358 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
359 struct dwapb_gpio *gpio = port->gpio;
360 unsigned long flags, val_deb;
361 unsigned long mask = BIT(offset);
362
363 spin_lock_irqsave(&gc->bgpio_lock, flags);
364
365 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
366 if (debounce)
367 val_deb |= mask;
368 else
369 val_deb &= ~mask;
370 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
371
372 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
373
374 return 0;
375}
376
377static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
378 unsigned long config)
379{
380 u32 debounce;
381
382 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
383 return -ENOTSUPP;
384
385 debounce = pinconf_to_config_argument(config);
386 return dwapb_gpio_set_debounce(gc, offset, debounce);
387}
388
389static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
390 struct dwapb_port_property *pp)
391{
392 int i;
393
394 /* Group all available IRQs into an array of parental IRQs. */
395 for (i = 0; i < pp->ngpio; ++i) {
396 if (!pp->irq[i])
397 continue;
398
399 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
400 }
401
402 return pirq->nr_irqs ? 0 : -ENOENT;
403}
404
405static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
406 struct dwapb_gpio_port *port,
407 struct dwapb_port_property *pp)
408{
409 struct dwapb_gpio_port_irqchip *pirq;
410 struct gpio_chip *gc = &port->gc;
411 struct gpio_irq_chip *girq;
412 int err;
413
414 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
415 if (!pirq)
416 return;
417
418 if (dwapb_convert_irqs(pirq, pp)) {
419 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
420 goto err_kfree_pirq;
421 }
422
423 girq = &gc->irq;
424 girq->handler = handle_bad_irq;
425 girq->default_type = IRQ_TYPE_NONE;
426
427 port->pirq = pirq;
428 pirq->irqchip.name = DWAPB_DRIVER_NAME;
429 pirq->irqchip.irq_ack = dwapb_irq_ack;
430 pirq->irqchip.irq_mask = dwapb_irq_mask;
431 pirq->irqchip.irq_unmask = dwapb_irq_unmask;
432 pirq->irqchip.irq_set_type = dwapb_irq_set_type;
433 pirq->irqchip.irq_enable = dwapb_irq_enable;
434 pirq->irqchip.irq_disable = dwapb_irq_disable;
435#ifdef CONFIG_PM_SLEEP
436 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
437#endif
438
439 if (!pp->irq_shared) {
440 girq->num_parents = pirq->nr_irqs;
441 girq->parents = pirq->irq;
442 girq->parent_handler_data = gpio;
443 girq->parent_handler = dwapb_irq_handler;
444 } else {
445 /* This will let us handle the parent IRQ in the driver */
446 girq->num_parents = 0;
447 girq->parents = NULL;
448 girq->parent_handler = NULL;
449
450 /*
451 * Request a shared IRQ since where MFD would have devices
452 * using the same irq pin
453 */
454 err = devm_request_irq(gpio->dev, pp->irq[0],
455 dwapb_irq_handler_mfd,
456 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
457 if (err) {
458 dev_err(gpio->dev, "error requesting IRQ\n");
459 goto err_kfree_pirq;
460 }
461 }
462
463 girq->chip = &pirq->irqchip;
464
465 return;
466
467err_kfree_pirq:
468 devm_kfree(gpio->dev, pirq);
469}
470
471static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
472 struct dwapb_port_property *pp,
473 unsigned int offs)
474{
475 struct dwapb_gpio_port *port;
476 void __iomem *dat, *set, *dirout;
477 int err;
478
479 port = &gpio->ports[offs];
480 port->gpio = gpio;
481 port->idx = pp->idx;
482
483#ifdef CONFIG_PM_SLEEP
484 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
485 if (!port->ctx)
486 return -ENOMEM;
487#endif
488
489 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
490 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
491 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
492
493 /* This registers 32 GPIO lines per port */
494 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
495 NULL, 0);
496 if (err) {
497 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
498 port->idx);
499 return err;
500 }
501
502#ifdef CONFIG_OF_GPIO
503 port->gc.of_node = to_of_node(pp->fwnode);
504#endif
505 port->gc.ngpio = pp->ngpio;
506 port->gc.base = pp->gpio_base;
507
508 /* Only port A support debounce */
509 if (pp->idx == 0)
510 port->gc.set_config = dwapb_gpio_set_config;
511
512 /* Only port A can provide interrupts in all configurations of the IP */
513 if (pp->idx == 0)
514 dwapb_configure_irqs(gpio, port, pp);
515
516 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
517 if (err) {
518 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
519 port->idx);
520 return err;
521 }
522
523 return 0;
524}
525
526static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
527 struct dwapb_port_property *pp)
528{
529 int irq, j;
530
531 for (j = 0; j < pp->ngpio; j++) {
532 if (has_acpi_companion(dev))
533 irq = platform_get_irq_optional(to_platform_device(dev), j);
534 else
535 irq = fwnode_irq_get(fwnode, j);
536 if (irq > 0)
537 pp->irq[j] = irq;
538 }
539}
540
541static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
542{
543 struct fwnode_handle *fwnode;
544 struct dwapb_platform_data *pdata;
545 struct dwapb_port_property *pp;
546 int nports;
547 int i;
548
549 nports = device_get_child_node_count(dev);
550 if (nports == 0)
551 return ERR_PTR(-ENODEV);
552
553 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
554 if (!pdata)
555 return ERR_PTR(-ENOMEM);
556
557 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
558 if (!pdata->properties)
559 return ERR_PTR(-ENOMEM);
560
561 pdata->nports = nports;
562
563 i = 0;
564 device_for_each_child_node(dev, fwnode) {
565 pp = &pdata->properties[i++];
566 pp->fwnode = fwnode;
567
568 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
569 pp->idx >= DWAPB_MAX_PORTS) {
570 dev_err(dev,
571 "missing/invalid port index for port%d\n", i);
572 fwnode_handle_put(fwnode);
573 return ERR_PTR(-EINVAL);
574 }
575
576 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
577 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
578 dev_info(dev,
579 "failed to get number of gpios for port%d\n",
580 i);
581 pp->ngpio = DWAPB_MAX_GPIOS;
582 }
583
584 pp->irq_shared = false;
585 pp->gpio_base = -1;
586
587 /*
588 * Only port A can provide interrupts in all configurations of
589 * the IP.
590 */
591 if (pp->idx == 0)
592 dwapb_get_irq(dev, fwnode, pp);
593 }
594
595 return pdata;
596}
597
598static void dwapb_assert_reset(void *data)
599{
600 struct dwapb_gpio *gpio = data;
601
602 reset_control_assert(gpio->rst);
603}
604
605static int dwapb_get_reset(struct dwapb_gpio *gpio)
606{
607 int err;
608
609 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
610 if (IS_ERR(gpio->rst))
611 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
612 "Cannot get reset descriptor\n");
613
614 err = reset_control_deassert(gpio->rst);
615 if (err) {
616 dev_err(gpio->dev, "Cannot deassert reset lane\n");
617 return err;
618 }
619
620 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
621}
622
623static void dwapb_disable_clks(void *data)
624{
625 struct dwapb_gpio *gpio = data;
626
627 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
628}
629
630static int dwapb_get_clks(struct dwapb_gpio *gpio)
631{
632 int err;
633
634 /* Optional bus and debounce clocks */
635 gpio->clks[0].id = "bus";
636 gpio->clks[1].id = "db";
637 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
638 gpio->clks);
639 if (err) {
640 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
641 return err;
642 }
643
644 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
645 if (err) {
646 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
647 return err;
648 }
649
650 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
651}
652
653static const struct of_device_id dwapb_of_match[] = {
654 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
655 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
656 { /* Sentinel */ }
657};
658MODULE_DEVICE_TABLE(of, dwapb_of_match);
659
660static const struct acpi_device_id dwapb_acpi_match[] = {
661 {"HISI0181", 0},
662 {"APMC0D07", 0},
663 {"APMC0D81", GPIO_REG_OFFSET_V2},
664 { }
665};
666MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
667
668static int dwapb_gpio_probe(struct platform_device *pdev)
669{
670 unsigned int i;
671 struct dwapb_gpio *gpio;
672 int err;
673 struct device *dev = &pdev->dev;
674 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
675
676 if (!pdata) {
677 pdata = dwapb_gpio_get_pdata(dev);
678 if (IS_ERR(pdata))
679 return PTR_ERR(pdata);
680 }
681
682 if (!pdata->nports)
683 return -ENODEV;
684
685 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
686 if (!gpio)
687 return -ENOMEM;
688
689 gpio->dev = &pdev->dev;
690 gpio->nr_ports = pdata->nports;
691
692 err = dwapb_get_reset(gpio);
693 if (err)
694 return err;
695
696 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
697 sizeof(*gpio->ports), GFP_KERNEL);
698 if (!gpio->ports)
699 return -ENOMEM;
700
701 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
702 if (IS_ERR(gpio->regs))
703 return PTR_ERR(gpio->regs);
704
705 err = dwapb_get_clks(gpio);
706 if (err)
707 return err;
708
709 gpio->flags = (uintptr_t)device_get_match_data(dev);
710
711 for (i = 0; i < gpio->nr_ports; i++) {
712 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
713 if (err)
714 return err;
715 }
716
717 platform_set_drvdata(pdev, gpio);
718
719 return 0;
720}
721
722#ifdef CONFIG_PM_SLEEP
723static int dwapb_gpio_suspend(struct device *dev)
724{
725 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
726 struct gpio_chip *gc = &gpio->ports[0].gc;
727 unsigned long flags;
728 int i;
729
730 spin_lock_irqsave(&gc->bgpio_lock, flags);
731 for (i = 0; i < gpio->nr_ports; i++) {
732 unsigned int offset;
733 unsigned int idx = gpio->ports[i].idx;
734 struct dwapb_context *ctx = gpio->ports[i].ctx;
735
736 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
737 ctx->dir = dwapb_read(gpio, offset);
738
739 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
740 ctx->data = dwapb_read(gpio, offset);
741
742 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
743 ctx->ext = dwapb_read(gpio, offset);
744
745 /* Only port A can provide interrupts */
746 if (idx == 0) {
747 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
748 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
749 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
750 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
751 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
752
753 /* Mask out interrupts */
754 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
755 }
756 }
757 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
758
759 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
760
761 return 0;
762}
763
764static int dwapb_gpio_resume(struct device *dev)
765{
766 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
767 struct gpio_chip *gc = &gpio->ports[0].gc;
768 unsigned long flags;
769 int i, err;
770
771 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
772 if (err) {
773 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
774 return err;
775 }
776
777 spin_lock_irqsave(&gc->bgpio_lock, flags);
778 for (i = 0; i < gpio->nr_ports; i++) {
779 unsigned int offset;
780 unsigned int idx = gpio->ports[i].idx;
781 struct dwapb_context *ctx = gpio->ports[i].ctx;
782
783 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
784 dwapb_write(gpio, offset, ctx->data);
785
786 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
787 dwapb_write(gpio, offset, ctx->dir);
788
789 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
790 dwapb_write(gpio, offset, ctx->ext);
791
792 /* Only port A can provide interrupts */
793 if (idx == 0) {
794 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
795 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
796 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
797 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
798 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
799
800 /* Clear out spurious interrupts */
801 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
802 }
803 }
804 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
805
806 return 0;
807}
808#endif
809
810static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
811 dwapb_gpio_resume);
812
813static struct platform_driver dwapb_gpio_driver = {
814 .driver = {
815 .name = DWAPB_DRIVER_NAME,
816 .pm = &dwapb_gpio_pm_ops,
817 .of_match_table = dwapb_of_match,
818 .acpi_match_table = dwapb_acpi_match,
819 },
820 .probe = dwapb_gpio_probe,
821};
822
823module_platform_driver(dwapb_gpio_driver);
824
825MODULE_LICENSE("GPL");
826MODULE_AUTHOR("Jamie Iles");
827MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
828MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);