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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TQM 8560 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
7 */
8
9/dts-v1/;
10
11/include/ "fsl/e500v1_power_isa.dtsi"
12
13/ {
14 model = "tqc,tqm8560";
15 compatible = "tqc,tqm8560";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8560@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
50
51 soc@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8560-immr", "simple-bus";
58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
72 memory-controller@2000 {
73 compatible = "fsl,mpc8540-memory-controller";
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>;
76 interrupts = <18 2>;
77 };
78
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
85 interrupts = <16 2>;
86 };
87
88 i2c@3000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c";
93 reg = <0x3000 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>;
96 dfsrr;
97
98 dtt@48 {
99 compatible = "national,lm75";
100 reg = <0x48>;
101 };
102
103 rtc@68 {
104 compatible = "dallas,ds1337";
105 reg = <0x68>;
106 };
107 };
108
109 dma@21300 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
113 reg = <0x21300 0x4>;
114 ranges = <0x0 0x21100 0x200>;
115 cell-index = <0>;
116 dma-channel@0 {
117 compatible = "fsl,mpc8560-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x0 0x80>;
120 cell-index = <0>;
121 interrupt-parent = <&mpic>;
122 interrupts = <20 2>;
123 };
124 dma-channel@80 {
125 compatible = "fsl,mpc8560-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x80 0x80>;
128 cell-index = <1>;
129 interrupt-parent = <&mpic>;
130 interrupts = <21 2>;
131 };
132 dma-channel@100 {
133 compatible = "fsl,mpc8560-dma-channel",
134 "fsl,eloplus-dma-channel";
135 reg = <0x100 0x80>;
136 cell-index = <2>;
137 interrupt-parent = <&mpic>;
138 interrupts = <22 2>;
139 };
140 dma-channel@180 {
141 compatible = "fsl,mpc8560-dma-channel",
142 "fsl,eloplus-dma-channel";
143 reg = <0x180 0x80>;
144 cell-index = <3>;
145 interrupt-parent = <&mpic>;
146 interrupts = <23 2>;
147 };
148 };
149
150 enet0: ethernet@24000 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 cell-index = <0>;
154 device_type = "network";
155 model = "TSEC";
156 compatible = "gianfar";
157 reg = <0x24000 0x1000>;
158 ranges = <0x0 0x24000 0x1000>;
159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <29 2 30 2 34 2>;
161 interrupt-parent = <&mpic>;
162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>;
164
165 mdio@520 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,gianfar-mdio";
169 reg = <0x520 0x20>;
170
171 phy1: ethernet-phy@1 {
172 interrupt-parent = <&mpic>;
173 interrupts = <8 1>;
174 reg = <1>;
175 };
176 phy2: ethernet-phy@2 {
177 interrupt-parent = <&mpic>;
178 interrupts = <8 1>;
179 reg = <2>;
180 };
181 phy3: ethernet-phy@3 {
182 interrupt-parent = <&mpic>;
183 interrupts = <8 1>;
184 reg = <3>;
185 };
186 tbi0: tbi-phy@11 {
187 reg = <0x11>;
188 device_type = "tbi-phy";
189 };
190 };
191 };
192
193 enet1: ethernet@25000 {
194 #address-cells = <1>;
195 #size-cells = <1>;
196 cell-index = <1>;
197 device_type = "network";
198 model = "TSEC";
199 compatible = "gianfar";
200 reg = <0x25000 0x1000>;
201 ranges = <0x0 0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&mpic>;
205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>;
207
208 mdio@520 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,gianfar-tbi";
212 reg = <0x520 0x20>;
213
214 tbi1: tbi-phy@11 {
215 reg = <0x11>;
216 device_type = "tbi-phy";
217 };
218 };
219 };
220
221 mpic: pic@40000 {
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>;
225 reg = <0x40000 0x40000>;
226 device_type = "open-pic";
227 compatible = "chrp,open-pic";
228 };
229
230 cpm@919c0 {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
234 reg = <0x919c0 0x30>;
235 ranges;
236
237 muram@80000 {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0 0x80000 0x10000>;
241
242 data@0 {
243 compatible = "fsl,cpm-muram-data";
244 reg = <0 0x4000 0x9000 0x2000>;
245 };
246 };
247
248 brg@919f0 {
249 compatible = "fsl,mpc8560-brg",
250 "fsl,cpm2-brg",
251 "fsl,cpm-brg";
252 reg = <0x919f0 0x10 0x915f0 0x10>;
253 clock-frequency = <0>;
254 };
255
256 cpmpic: pic@90c00 {
257 interrupt-controller;
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
260 interrupts = <46 2>;
261 interrupt-parent = <&mpic>;
262 reg = <0x90c00 0x80>;
263 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
264 };
265
266 serial0: serial@91a00 {
267 device_type = "serial";
268 compatible = "fsl,mpc8560-scc-uart",
269 "fsl,cpm2-scc-uart";
270 reg = <0x91a00 0x20 0x88000 0x100>;
271 fsl,cpm-brg = <1>;
272 fsl,cpm-command = <0x800000>;
273 current-speed = <115200>;
274 interrupts = <40 8>;
275 interrupt-parent = <&cpmpic>;
276 };
277
278 serial1: serial@91a20 {
279 device_type = "serial";
280 compatible = "fsl,mpc8560-scc-uart",
281 "fsl,cpm2-scc-uart";
282 reg = <0x91a20 0x20 0x88100 0x100>;
283 fsl,cpm-brg = <2>;
284 fsl,cpm-command = <0x4a00000>;
285 current-speed = <115200>;
286 interrupts = <41 8>;
287 interrupt-parent = <&cpmpic>;
288 };
289
290 enet2: ethernet@91340 {
291 device_type = "network";
292 compatible = "fsl,mpc8560-fcc-enet",
293 "fsl,cpm2-fcc-enet";
294 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 fsl,cpm-command = <0x1a400300>;
297 interrupts = <34 8>;
298 interrupt-parent = <&cpmpic>;
299 phy-handle = <&phy3>;
300 };
301 };
302 };
303
304 localbus@e0005000 {
305 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
306 "simple-bus";
307 #address-cells = <2>;
308 #size-cells = <1>;
309 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
310 interrupt-parent = <&mpic>;
311 interrupts = <19 2>;
312
313 ranges = <
314 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
315 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
316 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
317 >;
318
319 flash@1,0 {
320 #address-cells = <1>;
321 #size-cells = <1>;
322 compatible = "cfi-flash";
323 reg = <1 0x0 0x8000000>;
324 bank-width = <4>;
325 device-width = <1>;
326
327 partition@0 {
328 label = "kernel";
329 reg = <0x00000000 0x00200000>;
330 };
331 partition@200000 {
332 label = "root";
333 reg = <0x00200000 0x00300000>;
334 };
335 partition@500000 {
336 label = "user";
337 reg = <0x00500000 0x07a00000>;
338 };
339 partition@7f00000 {
340 label = "env1";
341 reg = <0x07f00000 0x00040000>;
342 };
343 partition@7f40000 {
344 label = "env2";
345 reg = <0x07f40000 0x00040000>;
346 };
347 partition@7f80000 {
348 label = "u-boot";
349 reg = <0x07f80000 0x00080000>;
350 read-only;
351 };
352 };
353
354 /* Note: CAN support needs be enabled in U-Boot */
355 can0@2,0 {
356 compatible = "intel,82527"; // Bosch CC770
357 reg = <2 0x0 0x100>;
358 interrupts = <4 1>;
359 interrupt-parent = <&mpic>;
360 };
361
362 can1@2,100 {
363 compatible = "intel,82527"; // Bosch CC770
364 reg = <2 0x100 0x100>;
365 interrupts = <4 1>;
366 interrupt-parent = <&mpic>;
367 };
368 };
369
370 pci0: pci@e0008000 {
371 #interrupt-cells = <1>;
372 #size-cells = <2>;
373 #address-cells = <3>;
374 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
375 device_type = "pci";
376 reg = <0xe0008000 0x1000>;
377 clock-frequency = <66666666>;
378 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
379 interrupt-map = <
380 /* IDSEL 28 */
381 0xe000 0 0 1 &mpic 2 1
382 0xe000 0 0 2 &mpic 3 1
383 0xe000 0 0 3 &mpic 6 1
384 0xe000 0 0 4 &mpic 5 1
385
386 /* IDSEL 11 */
387 0x5800 0 0 1 &mpic 6 1
388 0x5800 0 0 2 &mpic 5 1
389 >;
390
391 interrupt-parent = <&mpic>;
392 interrupts = <24 2>;
393 bus-range = <0 0>;
394 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
395 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
396 };
397};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TQM 8560 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
7 */
8
9/dts-v1/;
10
11/ {
12 model = "tqc,tqm8560";
13 compatible = "tqc,tqm8560";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 ethernet0 = &enet0;
19 ethernet1 = &enet1;
20 ethernet2 = &enet2;
21 serial0 = &serial0;
22 serial1 = &serial1;
23 pci0 = &pci0;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,8560@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 next-level-cache = <&L2>;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x10000000>;
47 };
48
49 soc@e0000000 {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 device_type = "soc";
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
55 compatible = "fsl,mpc8560-immr", "simple-bus";
56
57 ecm-law@0 {
58 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>;
60 fsl,num-laws = <8>;
61 };
62
63 ecm@1000 {
64 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>;
66 interrupts = <17 2>;
67 interrupt-parent = <&mpic>;
68 };
69
70 memory-controller@2000 {
71 compatible = "fsl,mpc8540-memory-controller";
72 reg = <0x2000 0x1000>;
73 interrupt-parent = <&mpic>;
74 interrupts = <18 2>;
75 };
76
77 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8540-l2-cache-controller";
79 reg = <0x20000 0x1000>;
80 cache-line-size = <32>;
81 cache-size = <0x40000>; // L2, 256K
82 interrupt-parent = <&mpic>;
83 interrupts = <16 2>;
84 };
85
86 i2c@3000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>;
92 interrupts = <43 2>;
93 interrupt-parent = <&mpic>;
94 dfsrr;
95
96 dtt@48 {
97 compatible = "national,lm75";
98 reg = <0x48>;
99 };
100
101 rtc@68 {
102 compatible = "dallas,ds1337";
103 reg = <0x68>;
104 };
105 };
106
107 dma@21300 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
111 reg = <0x21300 0x4>;
112 ranges = <0x0 0x21100 0x200>;
113 cell-index = <0>;
114 dma-channel@0 {
115 compatible = "fsl,mpc8560-dma-channel",
116 "fsl,eloplus-dma-channel";
117 reg = <0x0 0x80>;
118 cell-index = <0>;
119 interrupt-parent = <&mpic>;
120 interrupts = <20 2>;
121 };
122 dma-channel@80 {
123 compatible = "fsl,mpc8560-dma-channel",
124 "fsl,eloplus-dma-channel";
125 reg = <0x80 0x80>;
126 cell-index = <1>;
127 interrupt-parent = <&mpic>;
128 interrupts = <21 2>;
129 };
130 dma-channel@100 {
131 compatible = "fsl,mpc8560-dma-channel",
132 "fsl,eloplus-dma-channel";
133 reg = <0x100 0x80>;
134 cell-index = <2>;
135 interrupt-parent = <&mpic>;
136 interrupts = <22 2>;
137 };
138 dma-channel@180 {
139 compatible = "fsl,mpc8560-dma-channel",
140 "fsl,eloplus-dma-channel";
141 reg = <0x180 0x80>;
142 cell-index = <3>;
143 interrupt-parent = <&mpic>;
144 interrupts = <23 2>;
145 };
146 };
147
148 enet0: ethernet@24000 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 cell-index = <0>;
152 device_type = "network";
153 model = "TSEC";
154 compatible = "gianfar";
155 reg = <0x24000 0x1000>;
156 ranges = <0x0 0x24000 0x1000>;
157 local-mac-address = [ 00 00 00 00 00 00 ];
158 interrupts = <29 2 30 2 34 2>;
159 interrupt-parent = <&mpic>;
160 tbi-handle = <&tbi0>;
161 phy-handle = <&phy2>;
162
163 mdio@520 {
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,gianfar-mdio";
167 reg = <0x520 0x20>;
168
169 phy1: ethernet-phy@1 {
170 interrupt-parent = <&mpic>;
171 interrupts = <8 1>;
172 reg = <1>;
173 };
174 phy2: ethernet-phy@2 {
175 interrupt-parent = <&mpic>;
176 interrupts = <8 1>;
177 reg = <2>;
178 };
179 phy3: ethernet-phy@3 {
180 interrupt-parent = <&mpic>;
181 interrupts = <8 1>;
182 reg = <3>;
183 };
184 tbi0: tbi-phy@11 {
185 reg = <0x11>;
186 device_type = "tbi-phy";
187 };
188 };
189 };
190
191 enet1: ethernet@25000 {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 cell-index = <1>;
195 device_type = "network";
196 model = "TSEC";
197 compatible = "gianfar";
198 reg = <0x25000 0x1000>;
199 ranges = <0x0 0x25000 0x1000>;
200 local-mac-address = [ 00 00 00 00 00 00 ];
201 interrupts = <35 2 36 2 40 2>;
202 interrupt-parent = <&mpic>;
203 tbi-handle = <&tbi1>;
204 phy-handle = <&phy1>;
205
206 mdio@520 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,gianfar-tbi";
210 reg = <0x520 0x20>;
211
212 tbi1: tbi-phy@11 {
213 reg = <0x11>;
214 device_type = "tbi-phy";
215 };
216 };
217 };
218
219 mpic: pic@40000 {
220 interrupt-controller;
221 #address-cells = <0>;
222 #interrupt-cells = <2>;
223 reg = <0x40000 0x40000>;
224 device_type = "open-pic";
225 compatible = "chrp,open-pic";
226 };
227
228 cpm@919c0 {
229 #address-cells = <1>;
230 #size-cells = <1>;
231 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
232 reg = <0x919c0 0x30>;
233 ranges;
234
235 muram@80000 {
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0 0x80000 0x10000>;
239
240 data@0 {
241 compatible = "fsl,cpm-muram-data";
242 reg = <0 0x4000 0x9000 0x2000>;
243 };
244 };
245
246 brg@919f0 {
247 compatible = "fsl,mpc8560-brg",
248 "fsl,cpm2-brg",
249 "fsl,cpm-brg";
250 reg = <0x919f0 0x10 0x915f0 0x10>;
251 clock-frequency = <0>;
252 };
253
254 cpmpic: pic@90c00 {
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <2>;
258 interrupts = <46 2>;
259 interrupt-parent = <&mpic>;
260 reg = <0x90c00 0x80>;
261 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
262 };
263
264 serial0: serial@91a00 {
265 device_type = "serial";
266 compatible = "fsl,mpc8560-scc-uart",
267 "fsl,cpm2-scc-uart";
268 reg = <0x91a00 0x20 0x88000 0x100>;
269 fsl,cpm-brg = <1>;
270 fsl,cpm-command = <0x800000>;
271 current-speed = <115200>;
272 interrupts = <40 8>;
273 interrupt-parent = <&cpmpic>;
274 };
275
276 serial1: serial@91a20 {
277 device_type = "serial";
278 compatible = "fsl,mpc8560-scc-uart",
279 "fsl,cpm2-scc-uart";
280 reg = <0x91a20 0x20 0x88100 0x100>;
281 fsl,cpm-brg = <2>;
282 fsl,cpm-command = <0x4a00000>;
283 current-speed = <115200>;
284 interrupts = <41 8>;
285 interrupt-parent = <&cpmpic>;
286 };
287
288 enet2: ethernet@91340 {
289 device_type = "network";
290 compatible = "fsl,mpc8560-fcc-enet",
291 "fsl,cpm2-fcc-enet";
292 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
293 local-mac-address = [ 00 00 00 00 00 00 ];
294 fsl,cpm-command = <0x1a400300>;
295 interrupts = <34 8>;
296 interrupt-parent = <&cpmpic>;
297 phy-handle = <&phy3>;
298 };
299 };
300 };
301
302 localbus@e0005000 {
303 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
304 "simple-bus";
305 #address-cells = <2>;
306 #size-cells = <1>;
307 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
308 interrupt-parent = <&mpic>;
309 interrupts = <19 2>;
310
311 ranges = <
312 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
313 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
314 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
315 >;
316
317 flash@1,0 {
318 #address-cells = <1>;
319 #size-cells = <1>;
320 compatible = "cfi-flash";
321 reg = <1 0x0 0x8000000>;
322 bank-width = <4>;
323 device-width = <1>;
324
325 partition@0 {
326 label = "kernel";
327 reg = <0x00000000 0x00200000>;
328 };
329 partition@200000 {
330 label = "root";
331 reg = <0x00200000 0x00300000>;
332 };
333 partition@500000 {
334 label = "user";
335 reg = <0x00500000 0x07a00000>;
336 };
337 partition@7f00000 {
338 label = "env1";
339 reg = <0x07f00000 0x00040000>;
340 };
341 partition@7f40000 {
342 label = "env2";
343 reg = <0x07f40000 0x00040000>;
344 };
345 partition@7f80000 {
346 label = "u-boot";
347 reg = <0x07f80000 0x00080000>;
348 read-only;
349 };
350 };
351
352 /* Note: CAN support needs be enabled in U-Boot */
353 can0@2,0 {
354 compatible = "intel,82527"; // Bosch CC770
355 reg = <2 0x0 0x100>;
356 interrupts = <4 1>;
357 interrupt-parent = <&mpic>;
358 };
359
360 can1@2,100 {
361 compatible = "intel,82527"; // Bosch CC770
362 reg = <2 0x100 0x100>;
363 interrupts = <4 1>;
364 interrupt-parent = <&mpic>;
365 };
366 };
367
368 pci0: pci@e0008000 {
369 #interrupt-cells = <1>;
370 #size-cells = <2>;
371 #address-cells = <3>;
372 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
373 device_type = "pci";
374 reg = <0xe0008000 0x1000>;
375 clock-frequency = <66666666>;
376 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
377 interrupt-map = <
378 /* IDSEL 28 */
379 0xe000 0 0 1 &mpic 2 1
380 0xe000 0 0 2 &mpic 3 1
381 0xe000 0 0 3 &mpic 6 1
382 0xe000 0 0 4 &mpic 5 1
383
384 /* IDSEL 11 */
385 0x5800 0 0 1 &mpic 6 1
386 0x5800 0 0 2 &mpic 5 1
387 >;
388
389 interrupt-parent = <&mpic>;
390 interrupts = <24 2>;
391 bus-range = <0 0>;
392 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
393 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
394 };
395};