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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2020 thingy.jp.
4 * Author: Daniel Palmer <daniel@thingy.jp>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mstar-msc313-mpll.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15
16 cpus: cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0x0>;
24 clocks = <&cpupll>;
25 clock-names = "cpuclk";
26 };
27 };
28
29 arch_timer {
30 compatible = "arm,armv7-timer";
31 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
32 | IRQ_TYPE_LEVEL_LOW)>,
33 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
34 | IRQ_TYPE_LEVEL_LOW)>,
35 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
36 | IRQ_TYPE_LEVEL_LOW)>,
37 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
38 | IRQ_TYPE_LEVEL_LOW)>;
39 /*
40 * we shouldn't need this but the vendor
41 * u-boot is broken
42 */
43 clock-frequency = <6000000>;
44 arm,cpu-registers-not-fw-configured;
45 };
46
47 pmu: pmu {
48 compatible = "arm,cortex-a7-pmu";
49 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-affinity = <&cpu0>;
51 };
52
53 clocks: clocks {
54 xtal: xtal {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59
60 rtc_xtal: rtc_xtal {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <32768>;
64 status = "disabled";
65 };
66
67 xtal_div2: xtal_div2 {
68 #clock-cells = <0>;
69 compatible = "fixed-factor-clock";
70 clocks = <&xtal>;
71 clock-div = <2>;
72 clock-mult = <1>;
73 };
74 };
75
76 soc: soc {
77 compatible = "simple-bus";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
83
84 gic: interrupt-controller@16001000 {
85 compatible = "arm,cortex-a7-gic";
86 reg = <0x16001000 0x1000>,
87 <0x16002000 0x2000>,
88 <0x16004000 0x2000>,
89 <0x16006000 0x2000>;
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
93 | IRQ_TYPE_LEVEL_LOW)>;
94 };
95
96 riu: bus@1f000000 {
97 compatible = "simple-bus";
98 reg = <0x1f000000 0x00400000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0x0 0x1f000000 0x00400000>;
102
103 pmsleep: syscon@1c00 {
104 compatible = "mstar,msc313-pmsleep", "syscon";
105 reg = <0x1c00 0x100>;
106 };
107
108 reboot {
109 compatible = "syscon-reboot";
110 regmap = <&pmsleep>;
111 offset = <0xb8>;
112 mask = <0x79>;
113 };
114
115 rtc@2400 {
116 compatible = "mstar,msc313-rtc";
117 reg = <0x2400 0x40>;
118 clocks = <&xtal_div2>;
119 interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
120 };
121
122 watchdog@6000 {
123 compatible = "mstar,msc313e-wdt";
124 reg = <0x6000 0x1f>;
125 clocks = <&xtal_div2>;
126 };
127
128
129 intc_fiq: interrupt-controller@201310 {
130 compatible = "mstar,mst-intc";
131 reg = <0x201310 0x40>;
132 #interrupt-cells = <3>;
133 interrupt-controller;
134 interrupt-parent = <&gic>;
135 mstar,irqs-map-range = <96 127>;
136 };
137
138 intc_irq: interrupt-controller@201350 {
139 compatible = "mstar,mst-intc";
140 reg = <0x201350 0x40>;
141 #interrupt-cells = <3>;
142 interrupt-controller;
143 interrupt-parent = <&gic>;
144 mstar,irqs-map-range = <32 95>;
145 mstar,intc-no-eoi;
146 };
147
148 l3bridge: l3bridge@204400 {
149 compatible = "mstar,l3bridge";
150 reg = <0x204400 0x200>;
151 };
152
153 mpll: mpll@206000 {
154 compatible = "mstar,msc313-mpll";
155 #clock-cells = <1>;
156 reg = <0x206000 0x200>;
157 clocks = <&xtal>;
158 };
159
160 cpupll: cpupll@206400 {
161 compatible = "mstar,msc313-cpupll";
162 reg = <0x206400 0x200>;
163 #clock-cells = <0>;
164 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
165 };
166
167 gpio: gpio@207800 {
168 #gpio-cells = <2>;
169 reg = <0x207800 0x200>;
170 gpio-controller;
171 #interrupt-cells = <2>;
172 interrupt-controller;
173 interrupt-parent = <&intc_fiq>;
174 status = "disabled";
175 };
176
177 pm_uart: uart@221000 {
178 compatible = "ns16550a";
179 reg = <0x221000 0x100>;
180 reg-shift = <3>;
181 interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
182 clock-frequency = <172000000>;
183 status = "disabled";
184 };
185 };
186
187 imi: sram@a0000000 {
188 compatible = "mmio-sram";
189 reg = <0xa0000000 0x10000>;
190 };
191 };
192};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2020 thingy.jp.
4 * Author: Daniel Palmer <daniel@thingy.jp>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mstar-msc313-mpll.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15
16 cpus: cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0x0>;
24 };
25 };
26
27 arch_timer {
28 compatible = "arm,armv7-timer";
29 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
30 | IRQ_TYPE_LEVEL_LOW)>,
31 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
32 | IRQ_TYPE_LEVEL_LOW)>,
33 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
34 | IRQ_TYPE_LEVEL_LOW)>,
35 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
36 | IRQ_TYPE_LEVEL_LOW)>;
37 /*
38 * we shouldn't need this but the vendor
39 * u-boot is broken
40 */
41 clock-frequency = <6000000>;
42 };
43
44 pmu: pmu {
45 compatible = "arm,cortex-a7-pmu";
46 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
47 interrupt-affinity = <&cpu0>;
48 };
49
50 clocks: clocks {
51 xtal: xtal {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <24000000>;
55 };
56
57 rtc_xtal: rtc_xtal {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
61 status = "disabled";
62 };
63
64 xtal_div2: xtal_div2 {
65 #clock-cells = <0>;
66 compatible = "fixed-factor-clock";
67 clocks = <&xtal>;
68 clock-div = <2>;
69 clock-mult = <1>;
70 };
71 };
72
73 soc: soc {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges = <0x16001000 0x16001000 0x00007000>,
78 <0x1f000000 0x1f000000 0x00400000>,
79 <0xa0000000 0xa0000000 0x20000>;
80
81 gic: interrupt-controller@16001000 {
82 compatible = "arm,cortex-a7-gic";
83 reg = <0x16001000 0x1000>,
84 <0x16002000 0x2000>,
85 <0x16004000 0x2000>,
86 <0x16006000 0x2000>;
87 #interrupt-cells = <3>;
88 interrupt-controller;
89 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
90 | IRQ_TYPE_LEVEL_LOW)>;
91 };
92
93 riu: bus@1f000000 {
94 compatible = "simple-bus";
95 reg = <0x1f000000 0x00400000>;
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges = <0x0 0x1f000000 0x00400000>;
99
100 pmsleep: syscon@1c00 {
101 compatible = "mstar,msc313-pmsleep", "syscon";
102 reg = <0x1c00 0x100>;
103 };
104
105 reboot {
106 compatible = "syscon-reboot";
107 regmap = <&pmsleep>;
108 offset = <0xb8>;
109 mask = <0x79>;
110 };
111
112 watchdog@6000 {
113 compatible = "mstar,msc313e-wdt";
114 reg = <0x6000 0x1f>;
115 clocks = <&xtal_div2>;
116 };
117
118 intc_fiq: interrupt-controller@201310 {
119 compatible = "mstar,mst-intc";
120 reg = <0x201310 0x40>;
121 #interrupt-cells = <3>;
122 interrupt-controller;
123 interrupt-parent = <&gic>;
124 mstar,irqs-map-range = <96 127>;
125 };
126
127 intc_irq: interrupt-controller@201350 {
128 compatible = "mstar,mst-intc";
129 reg = <0x201350 0x40>;
130 #interrupt-cells = <3>;
131 interrupt-controller;
132 interrupt-parent = <&gic>;
133 mstar,irqs-map-range = <32 95>;
134 mstar,intc-no-eoi;
135 };
136
137 l3bridge: l3bridge@204400 {
138 compatible = "mstar,l3bridge";
139 reg = <0x204400 0x200>;
140 };
141
142 mpll: mpll@206000 {
143 compatible = "mstar,msc313-mpll";
144 #clock-cells = <1>;
145 reg = <0x206000 0x200>;
146 clocks = <&xtal>;
147 };
148
149 gpio: gpio@207800 {
150 #gpio-cells = <2>;
151 reg = <0x207800 0x200>;
152 gpio-controller;
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 interrupt-parent = <&intc_fiq>;
156 status = "disabled";
157 };
158
159 pm_uart: uart@221000 {
160 compatible = "ns16550a";
161 reg = <0x221000 0x100>;
162 reg-shift = <3>;
163 interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
164 clock-frequency = <172000000>;
165 status = "disabled";
166 };
167 };
168
169 imi: sram@a0000000 {
170 compatible = "mmio-sram";
171 reg = <0xa0000000 0x10000>;
172 };
173 };
174};