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1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2014 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7#include <dt-bindings/display/sdtv-standards.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/media/tvp5150.h>
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
14/ {
15 chosen {
16 stdout-path = &uart4;
17 };
18
19 backlight_lcd: backlight {
20 compatible = "pwm-backlight";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_backlight>;
23 pwms = <&pwm1 0 5000000 0>;
24 brightness-levels = <0 16 64 255>;
25 num-interpolated-steps = <16>;
26 default-brightness-level = <48>;
27 power-supply = <®_3v3>;
28 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
29 };
30
31 backlight_led: backlight-led {
32 compatible = "pwm-backlight";
33 pwms = <&pwm3 0 5000000 0>;
34 brightness-levels = <0 16 64 255>;
35 num-interpolated-steps = <16>;
36 default-brightness-level = <48>;
37 power-supply = <®_3v3>;
38 };
39
40 /* only for backwards compatibility with old HW */
41 backlight_isb: backlight-isb {
42 compatible = "pwm-backlight";
43 pwms = <&pwm2 0 5000000 0>;
44 brightness-levels = <0 8 48 255>;
45 num-interpolated-steps = <5>;
46 default-brightness-level = <0>;
47 power-supply = <®_3v3>;
48 };
49
50 connector {
51 compatible = "composite-video-connector";
52 label = "Composite0";
53 sdtv-standards = <SDTV_STD_PAL_B>;
54
55 port {
56 comp0_out: endpoint {
57 remote-endpoint = <&tvp5150_comp0_in>;
58 };
59 };
60 };
61
62 counter-0 {
63 compatible = "interrupt-counter";
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_counter0>;
66 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
67 };
68
69 counter-1 {
70 compatible = "interrupt-counter";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_counter1>;
73 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
74 };
75
76 counter-2 {
77 compatible = "interrupt-counter";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_counter2>;
80 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
81 };
82
83 leds {
84 compatible = "gpio-leds";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_leds>;
87
88 led-0 {
89 label = "debug0";
90 function = LED_FUNCTION_HEARTBEAT;
91 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
92 linux,default-trigger = "heartbeat";
93 };
94
95 led-1 {
96 label = "debug1";
97 function = LED_FUNCTION_DISK;
98 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
99 linux,default-trigger = "disk-activity";
100 };
101
102 led-2 {
103 label = "power_led";
104 function = LED_FUNCTION_POWER;
105 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
106 default-state = "on";
107 };
108
109 led-3 {
110 label = "isb_led";
111 function = LED_FUNCTION_POWER;
112 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
113 default-state = "on";
114 };
115 };
116
117 reg_1v8: regulator-1v8 {
118 compatible = "regulator-fixed";
119 regulator-name = "1v8";
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 };
123
124 reg_3v3: regulator-3v3 {
125 compatible = "regulator-fixed";
126 regulator-name = "3v3";
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
129 };
130
131 reg_otg_vbus: regulator-otg-vbus {
132 compatible = "regulator-fixed";
133 regulator-name = "otg-vbus";
134 regulator-min-microvolt = <5000000>;
135 regulator-max-microvolt = <5000000>;
136 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
137 enable-active-high;
138 };
139
140 sound {
141 compatible = "simple-audio-card";
142 simple-audio-card,name = "prti6q-sgtl5000";
143 simple-audio-card,format = "i2s";
144 simple-audio-card,widgets =
145 "Microphone", "Microphone Jack",
146 "Line", "Line In Jack",
147 "Headphone", "Headphone Jack",
148 "Speaker", "External Speaker";
149 simple-audio-card,routing =
150 "MIC_IN", "Microphone Jack",
151 "LINE_IN", "Line In Jack",
152 "Headphone Jack", "HP_OUT",
153 "External Speaker", "LINE_OUT";
154
155 simple-audio-card,cpu {
156 sound-dai = <&ssi1>;
157 system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */
158 };
159
160 simple-audio-card,codec {
161 sound-dai = <&codec>;
162 bitclock-master;
163 frame-master;
164 };
165 };
166
167 thermal-zones {
168 chassis-thermal {
169 polling-delay = <20000>;
170 polling-delay-passive = <0>;
171 thermal-sensors = <&tsens0>;
172 };
173 };
174};
175
176&audmux {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_audmux>;
179 status = "okay";
180
181 mux-ssi1 {
182 fsl,audmux-port = <0>;
183 fsl,port-config = <
184 IMX_AUDMUX_V2_PTCR_SYN 0
185 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
186 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
187 IMX_AUDMUX_V2_PTCR_TFSDIR 0
188 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
189 >;
190 };
191
192 mux-pins3 {
193 fsl,audmux-port = <2>;
194 fsl,port-config = <
195 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
196 0 IMX_AUDMUX_V2_PDCR_TXRXEN
197 >;
198 };
199};
200
201&can1 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_can1>;
204 termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
205 termination-ohms = <150>;
206 status = "okay";
207};
208
209&can2 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_can2>;
212 status = "okay";
213};
214
215&clks {
216 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
217 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
218};
219
220&ecspi1 {
221 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_ecspi1>;
224 status = "okay";
225
226 flash@0 {
227 compatible = "jedec,spi-nor";
228 reg = <0>;
229 spi-max-frequency = <20000000>;
230 };
231};
232
233&gpio2 {
234 gpio-line-names =
235 "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "",
236 "", "LED_PWM", "", "", "",
237 "", "", "",
238 "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH",
239 "POWER_LED", "", "", "", "", "", "", "";
240};
241
242&gpio3 {
243 gpio-line-names =
244 "", "", "", "", "", "", "", "",
245 "", "", "", "", "", "", "", "",
246 "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
247 "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ",
248 "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
249 "YACO_RESET";
250};
251
252&gpio7 {
253 gpio-line-names =
254 "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0",
255 "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3",
256 "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "",
257 "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "",
258 "", "", "", "", "", "", "", "";
259};
260
261&i2c1 {
262 clock-frequency = <100000>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_i2c1>;
265 status = "okay";
266
267 codec: audio-codec@a {
268 compatible = "fsl,sgtl5000";
269 reg = <0xa>;
270 #sound-dai-cells = <0>;
271 clocks = <&clks 201>;
272 VDDA-supply = <®_3v3>;
273 VDDIO-supply = <®_3v3>;
274 VDDD-supply = <®_1v8>;
275 };
276
277 video-decoder@5c {
278 compatible = "ti,tvp5150";
279 reg = <0x5c>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282
283 port@0 {
284 reg = <0>;
285
286 tvp5150_comp0_in: endpoint {
287 remote-endpoint = <&comp0_out>;
288 };
289 };
290
291 /* Output port 2 is video output pad */
292 port@2 {
293 reg = <2>;
294
295 tvp5151_to_ipu1_csi0_mux: endpoint {
296 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
297 };
298 };
299 };
300};
301
302&i2c3 {
303 clock-frequency = <100000>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_i2c3>;
306 status = "okay";
307
308 adc@49 {
309 compatible = "ti,ads1015";
310 reg = <0x49>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313
314 channel@4 {
315 reg = <4>;
316 ti,gain = <3>;
317 ti,datarate = <3>;
318 };
319
320 channel@5 {
321 reg = <5>;
322 ti,gain = <3>;
323 ti,datarate = <3>;
324 };
325
326 channel@6 {
327 reg = <6>;
328 ti,gain = <3>;
329 ti,datarate = <3>;
330 };
331
332 channel@7 {
333 reg = <7>;
334 ti,gain = <3>;
335 ti,datarate = <3>;
336 };
337 };
338
339 rtc@51 {
340 compatible = "nxp,pcf8563";
341 reg = <0x51>;
342 };
343
344 tsens0: temperature-sensor@70 {
345 compatible = "ti,tmp103";
346 reg = <0x70>;
347 #thermal-sensor-cells = <0>;
348 };
349};
350
351&ipu1_csi0 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_ipu1_csi0>;
354 status = "okay";
355};
356
357&ipu1_csi0_mux_from_parallel_sensor {
358 remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
359};
360
361&ldb {
362 status = "okay";
363
364 lvds-channel@0 {
365 status = "okay";
366
367 port@4 {
368 reg = <4>;
369
370 lvds0_out: endpoint {
371 remote-endpoint = <&panel_in>;
372 };
373 };
374 };
375};
376
377&pwm1 {
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_pwm1>;
380 status = "okay";
381};
382
383&pwm2 {
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_pwm2>;
386 status = "okay";
387};
388
389&pwm3 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_pwm3>;
392 status = "okay";
393};
394
395&ssi1 {
396 #sound-dai-cells = <0>;
397 fsl,mode = "ac97-slave";
398 status = "okay";
399};
400
401&uart1 {
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_uart1>;
404 status = "okay";
405};
406
407&uart3 {
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_uart3>;
410 status = "okay";
411};
412
413&uart4 {
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_uart4>;
416 status = "okay";
417};
418
419&uart5 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_uart5>;
422 status = "okay";
423};
424
425&usbh1 {
426 pinctrl-names = "default";
427 phy_type = "utmi";
428 dr_mode = "host";
429 status = "okay";
430};
431
432&usbotg {
433 vbus-supply = <®_otg_vbus>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_usbotg>;
436 phy_type = "utmi";
437 dr_mode = "host";
438 disable-over-current;
439 status = "okay";
440};
441
442&usdhc1 {
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_usdhc1>;
445 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
446 no-1-8-v;
447 disable-wp;
448 cap-sd-highspeed;
449 no-mmc;
450 no-sdio;
451 status = "okay";
452};
453
454&usdhc3 {
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_usdhc3>;
457 bus-width = <8>;
458 no-1-8-v;
459 non-removable;
460 no-sd;
461 no-sdio;
462 status = "okay";
463};
464
465&iomuxc {
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_hog>;
468
469 pinctrl_audmux: audmuxgrp {
470 fsl,pins = <
471 /* SGTL5000 sys_mclk */
472 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
473 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
474 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
475 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
476 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
477 >;
478 };
479
480 pinctrl_backlight: backlightgrp {
481 fsl,pins = <
482 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
483 >;
484 };
485
486 pinctrl_can1: can1grp {
487 fsl,pins = <
488 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
489 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
490 /* CAN1_SR */
491 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
492 /* CAN1_TERM */
493 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
494 >;
495 };
496
497 pinctrl_can2: can2grp {
498 fsl,pins = <
499 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
500 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
501 /* CAN2_SR */
502 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
503 >;
504 };
505
506 pinctrl_counter0: counter0grp {
507 fsl,pins = <
508 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000
509 >;
510 };
511
512 pinctrl_counter1: counter1grp {
513 fsl,pins = <
514 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000
515 >;
516 };
517
518 pinctrl_counter2: counter2grp {
519 fsl,pins = <
520 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000
521 >;
522 };
523
524 pinctrl_ecspi1: ecspi1grp {
525 fsl,pins = <
526 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
527 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
528 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
529 /* CS */
530 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
531 >;
532 };
533
534 pinctrl_hog: hoggrp {
535 fsl,pins = <
536 /* ITU656_nRESET */
537 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
538 /* CAM1_MIRROR */
539 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
540 /* CAM2_MIRROR */
541 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
542 /* CAM_nDETECT */
543 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
544 /* ISB_IN1 */
545 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
546 /* ISB_nIN2 */
547 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
548 /* WARN_LIGHT */
549 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
550 /* ON2_FB */
551 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
552 /* YACO_nIRQ */
553 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
554 /* YACO_BOOT0 */
555 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
556 /* YACO_nRESET */
557 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
558 /* FORCE_ON1 */
559 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
560 /* AUDIO_nRESET */
561 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
562 /* ITU656_nPDN */
563 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
564
565 /* New in HW revision 1 */
566 /* ON1_FB */
567 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
568 /* DIP1_FB */
569 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
570 >;
571 };
572
573 pinctrl_i2c1: i2c1grp {
574 fsl,pins = <
575 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
576 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
577 >;
578 };
579
580 pinctrl_i2c3: i2c3grp {
581 fsl,pins = <
582 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
583 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
584 >;
585 };
586
587 pinctrl_ipu1_csi0: ipu1csi0grp {
588 fsl,pins = <
589 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
590 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
591 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
592 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
593 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
594 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
595 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
596 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
597 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
598 >;
599 };
600
601 pinctrl_leds: ledsgrp {
602 fsl,pins = <
603 /* DEBUG0 */
604 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
605 /* DEBUG1 */
606 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
607 /* POWER_LED */
608 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
609 /* ISB_LED */
610 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0
611 >;
612 };
613
614 pinctrl_pwm1: pwm1grp {
615 fsl,pins = <
616 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
617 >;
618 };
619
620 pinctrl_pwm2: pwm2grp {
621 fsl,pins = <
622 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0
623 >;
624 };
625
626 pinctrl_pwm3: pwm3grp {
627 fsl,pins = <
628 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
629 >;
630 };
631
632 /* YaCO AUX Uart */
633 pinctrl_uart1: uart1grp {
634 fsl,pins = <
635 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
636 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
637 >;
638 };
639
640 /* YaCO Touchscreen UART */
641 pinctrl_uart3: uart3grp {
642 fsl,pins = <
643 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
644 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
645 >;
646 };
647
648 pinctrl_uart4: uart4grp {
649 fsl,pins = <
650 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
651 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
652 >;
653 };
654
655 pinctrl_uart5: uart5grp {
656 fsl,pins = <
657 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
658 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
659 >;
660 };
661
662 pinctrl_usbotg: usbotggrp {
663 fsl,pins = <
664 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
665 /* power enable, high active */
666 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
667 >;
668 };
669
670 pinctrl_usdhc1: usdhc1grp {
671 fsl,pins = <
672 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
673 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
674 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
675 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
676 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
677 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
678 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
679 >;
680 };
681
682 pinctrl_usdhc3: usdhc3grp {
683 fsl,pins = <
684 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
685 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
686 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
687 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
688 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
689 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
690 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
691 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
692 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
693 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
694 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
695 >;
696 };
697};
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2014 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7#include <dt-bindings/display/sdtv-standards.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/media/tvp5150.h>
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
14/ {
15 chosen {
16 stdout-path = &uart4;
17 };
18
19 backlight: backlight {
20 compatible = "pwm-backlight";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_backlight>;
23 pwms = <&pwm1 0 5000000 0>;
24 brightness-levels = <0 16 64 255>;
25 num-interpolated-steps = <16>;
26 default-brightness-level = <1>;
27 power-supply = <®_3v3>;
28 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
29 };
30
31 connector {
32 compatible = "composite-video-connector";
33 label = "Composite0";
34 sdtv-standards = <SDTV_STD_PAL_B>;
35
36 port {
37 comp0_out: endpoint {
38 remote-endpoint = <&tvp5150_comp0_in>;
39 };
40 };
41 };
42
43 counter-0 {
44 compatible = "interrupt-counter";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_counter0>;
47 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
48 };
49
50 counter-1 {
51 compatible = "interrupt-counter";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_counter1>;
54 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
55 };
56
57 counter-2 {
58 compatible = "interrupt-counter";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_counter2>;
61 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
62 };
63
64 gpio-keys {
65 compatible = "gpio-keys";
66 autorepeat;
67
68 power {
69 label = "Power Button";
70 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
71 linux,code = <KEY_POWER>;
72 wakeup-source;
73 };
74 };
75
76 leds {
77 compatible = "gpio-leds";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_leds>;
80
81 led-0 {
82 label = "LED_DI0_DEBUG_0";
83 function = LED_FUNCTION_HEARTBEAT;
84 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
85 linux,default-trigger = "heartbeat";
86 };
87
88 led-1 {
89 label = "LED_DI0_DEBUG_1";
90 function = LED_FUNCTION_DISK;
91 gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
92 linux,default-trigger = "disk-activity";
93 };
94
95 led-2 {
96 label = "POWER_LED";
97 function = LED_FUNCTION_POWER;
98 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
99 default-state = "on";
100 };
101 };
102
103 panel {
104 compatible = "kyo,tcg121xglp";
105 backlight = <&backlight>;
106 power-supply = <®_3v3>;
107
108 port {
109 panel_in: endpoint {
110 remote-endpoint = <&lvds0_out>;
111 };
112 };
113 };
114
115 reg_1v8: regulator-1v8 {
116 compatible = "regulator-fixed";
117 regulator-name = "1v8";
118 regulator-min-microvolt = <1800000>;
119 regulator-max-microvolt = <1800000>;
120 };
121
122 reg_3v3: regulator-3v3 {
123 compatible = "regulator-fixed";
124 regulator-name = "3v3";
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
127 };
128
129 reg_h1_vbus: regulator-h1-vbus {
130 compatible = "regulator-fixed";
131 regulator-name = "h1-vbus";
132 regulator-min-microvolt = <5000000>;
133 regulator-max-microvolt = <5000000>;
134 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
135 enable-active-high;
136 };
137
138 reg_otg_vbus: regulator-otg-vbus {
139 compatible = "regulator-fixed";
140 regulator-name = "otg-vbus";
141 regulator-min-microvolt = <5000000>;
142 regulator-max-microvolt = <5000000>;
143 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
144 enable-active-high;
145 };
146
147 reg_wifi: regulator-wifi {
148 compatible = "regulator-fixed";
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_wifi_npd>;
151 regulator-name = "wifi";
152 regulator-min-microvolt = <1800000>;
153 regulator-max-microvolt = <1800000>;
154 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
155 enable-active-high;
156 startup-delay-us = <70000>;
157 };
158
159 sound {
160 compatible = "simple-audio-card";
161 simple-audio-card,name = "prti6q-sgtl5000";
162 simple-audio-card,format = "i2s";
163 simple-audio-card,widgets =
164 "Microphone", "Microphone Jack",
165 "Line", "Line In Jack",
166 "Headphone", "Headphone Jack",
167 "Speaker", "External Speaker";
168 simple-audio-card,routing =
169 "MIC_IN", "Microphone Jack",
170 "LINE_IN", "Line In Jack",
171 "Headphone Jack", "HP_OUT",
172 "External Speaker", "LINE_OUT";
173
174 simple-audio-card,cpu {
175 sound-dai = <&ssi1>;
176 system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */
177 };
178
179 simple-audio-card,codec {
180 sound-dai = <&codec>;
181 bitclock-master;
182 frame-master;
183 };
184 };
185};
186
187&audmux {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_audmux>;
190 status = "okay";
191
192 mux-ssi1 {
193 fsl,audmux-port = <0>;
194 fsl,port-config = <
195 IMX_AUDMUX_V2_PTCR_SYN 0
196 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
197 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
198 IMX_AUDMUX_V2_PTCR_TFSDIR 0
199 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
200 >;
201 };
202
203 mux-pins3 {
204 fsl,audmux-port = <2>;
205 fsl,port-config = <
206 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
207 0 IMX_AUDMUX_V2_PDCR_TXRXEN
208 >;
209 };
210};
211
212&can1 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_can1>;
215 status = "okay";
216};
217
218&can2 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_can2>;
221 status = "okay";
222};
223
224&clks {
225 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
226 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
227};
228
229&ecspi1 {
230 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_ecspi1>;
233 status = "okay";
234
235 flash@0 {
236 compatible = "jedec,spi-nor";
237 reg = <0>;
238 spi-max-frequency = <20000000>;
239 };
240};
241
242&fec {
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_enet>;
245 phy-mode = "rgmii-id";
246 phy-handle = <&rgmii_phy>;
247 status = "okay";
248
249 mdio {
250 #address-cells = <1>;
251 #size-cells = <0>;
252
253 /* Microchip KSZ9031RNX PHY */
254 rgmii_phy: ethernet-phy@0 {
255 reg = <0>;
256 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
257 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
258 reset-assert-us = <10000>;
259 reset-deassert-us = <300>;
260 };
261 };
262};
263
264&gpio1 {
265 gpio-line-names =
266 "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
267 "CAM2_MIRROR", "", "", "SMBALERT",
268 "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3",
269 "SDIO_D2", "SDIO_D1", "SDIO_D0",
270 "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
271 "SD1_DATA3", "", "",
272 "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "",
273 "WL_IRQ", "ETH_MDC";
274};
275
276&gpio2 {
277 gpio-line-names =
278 "count0", "count1", "count2", "", "", "", "", "",
279 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
280 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
281 "", "", "", "", "", "", "", "ON_SWITCH",
282 "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", "";
283};
284
285&gpio3 {
286 gpio-line-names =
287 "", "", "", "", "", "", "", "",
288 "", "", "", "", "", "", "", "",
289 "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
290 "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ",
291 "", "", "", "", "", "", "", "";
292};
293
294&gpio4 {
295 gpio-line-names =
296 "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
297 "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
298 "CAN2_SR", "CAN2_TX", "CAN2_RX",
299 "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "",
300 "", "", "", "", "BL_EN", "BL_PWM", "", "";
301};
302
303&gpio5 {
304 gpio-line-names =
305 "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS",
306 "PCIE_RESET", "", "", "", "", "", "", "",
307 "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
308 "I2S_BITCLK", "I2S_DOUT",
309 "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
310 "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
311};
312
313&gpio6 {
314 gpio-line-names =
315 "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
316 "ITU656_D6", "ITU656_D7", "", "",
317 "", "", "", "", "", "", "", "",
318 "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
319 "RGMII_TD3",
320 "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
321 "RGMII_RD2", "RGMII_RD3", "", "";
322};
323
324&gpio7 {
325 gpio-line-names =
326 "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0",
327 "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3",
328 "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "",
329 "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "",
330 "", "", "", "", "", "", "", "";
331};
332
333&i2c1 {
334 clock-frequency = <100000>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_i2c1>;
337 status = "okay";
338
339 codec: audio-codec@a {
340 compatible = "fsl,sgtl5000";
341 reg = <0xa>;
342 #sound-dai-cells = <0>;
343 clocks = <&clks 201>;
344 VDDA-supply = <®_3v3>;
345 VDDIO-supply = <®_3v3>;
346 VDDD-supply = <®_1v8>;
347 };
348
349 video-decoder@5c {
350 compatible = "ti,tvp5150";
351 reg = <0x5c>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354
355 port@0 {
356 reg = <0>;
357
358 tvp5150_comp0_in: endpoint {
359 remote-endpoint = <&comp0_out>;
360 };
361 };
362
363 /* Output port 2 is video output pad */
364 port@2 {
365 reg = <2>;
366
367 tvp5151_to_ipu1_csi0_mux: endpoint {
368 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
369 };
370 };
371 };
372};
373
374&i2c3 {
375 clock-frequency = <100000>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_i2c3>;
378 status = "okay";
379
380 adc@49 {
381 compatible = "ti,ads1015";
382 reg = <0x49>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385
386 channel@4 {
387 reg = <4>;
388 ti,gain = <3>;
389 ti,datarate = <3>;
390 };
391
392 channel@5 {
393 reg = <5>;
394 ti,gain = <3>;
395 ti,datarate = <3>;
396 };
397
398 channel@6 {
399 reg = <6>;
400 ti,gain = <3>;
401 ti,datarate = <3>;
402 };
403
404 channel@7 {
405 reg = <7>;
406 ti,gain = <3>;
407 ti,datarate = <3>;
408 };
409 };
410
411 rtc@51 {
412 compatible = "nxp,pcf8563";
413 reg = <0x51>;
414 };
415
416 temperature-sensor@70 {
417 compatible = "ti,tmp103";
418 reg = <0x70>;
419 };
420};
421
422&ipu1_csi0 {
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_ipu1_csi0>;
425 status = "okay";
426};
427
428&ipu1_csi0_mux_from_parallel_sensor {
429 remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
430};
431
432&ldb {
433 status = "okay";
434
435 lvds-channel@0 {
436 status = "okay";
437
438 port@4 {
439 reg = <4>;
440
441 lvds0_out: endpoint {
442 remote-endpoint = <&panel_in>;
443 };
444 };
445 };
446};
447
448&pcie {
449 status = "okay";
450};
451
452&pwm1 {
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_pwm1>;
455 status = "okay";
456};
457
458&ssi1 {
459 #sound-dai-cells = <0>;
460 fsl,mode = "ac97-slave";
461 status = "okay";
462};
463
464&uart1 {
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_uart1>;
467 status = "okay";
468};
469
470&uart2 {
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_uart2>;
473 status = "okay";
474};
475
476&uart3 {
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_uart3>;
479 status = "okay";
480};
481
482&uart4 {
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_uart4>;
485 status = "okay";
486};
487
488&uart5 {
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_uart5>;
491 status = "okay";
492};
493
494&usbh1 {
495 vbus-supply = <®_h1_vbus>;
496 pinctrl-names = "default";
497 phy_type = "utmi";
498 dr_mode = "host";
499 status = "okay";
500};
501
502&usbotg {
503 vbus-supply = <®_otg_vbus>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_usbotg>;
506 phy_type = "utmi";
507 dr_mode = "host";
508 disable-over-current;
509 status = "okay";
510};
511
512&usdhc1 {
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_usdhc1>;
515 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
516 no-1-8-v;
517 disable-wp;
518 cap-sd-highspeed;
519 no-mmc;
520 no-sdio;
521 status = "okay";
522};
523
524&usdhc2 {
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_usdhc2>;
527 vmmc-supply = <®_wifi>;
528 non-removable;
529 cap-power-off-card;
530 keep-power-in-suspend;
531 no-1-8-v;
532 no-mmc;
533 no-sd;
534 status = "okay";
535
536 wifi {
537 compatible = "ti,wl1271";
538 interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
539 ref-clock-frequency = "38400000";
540 tcxo-clock-frequency = "19200000";
541 };
542};
543
544&usdhc3 {
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_usdhc3>;
547 bus-width = <8>;
548 no-1-8-v;
549 non-removable;
550 no-sd;
551 no-sdio;
552 status = "okay";
553};
554
555&iomuxc {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_hog>;
558
559 pinctrl_audmux: audmuxgrp {
560 fsl,pins = <
561 /* SGTL5000 sys_mclk */
562 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
563 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
564 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
565 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
566 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
567 >;
568 };
569
570 pinctrl_backlight: backlightgrp {
571 fsl,pins = <
572 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
573 >;
574 };
575
576 pinctrl_can1: can1grp {
577 fsl,pins = <
578 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
579 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
580 /* CAN1_SR */
581 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
582 /* CAN1_TERM */
583 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
584 >;
585 };
586
587 pinctrl_can2: can2grp {
588 fsl,pins = <
589 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
590 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
591 /* CAN2_SR */
592 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
593 >;
594 };
595
596 pinctrl_counter0: counter0grp {
597 fsl,pins = <
598 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000
599 >;
600 };
601
602 pinctrl_counter1: counter1grp {
603 fsl,pins = <
604 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000
605 >;
606 };
607
608 pinctrl_counter2: counter2grp {
609 fsl,pins = <
610 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000
611 >;
612 };
613
614 pinctrl_ecspi1: ecspi1grp {
615 fsl,pins = <
616 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
617 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
618 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
619 /* CS */
620 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
621 >;
622 };
623
624 pinctrl_enet: enetgrp {
625 fsl,pins = <
626 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
627 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
628 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
629 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
630 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
631 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
632 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
633 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
634 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
635 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
636 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
637 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
638 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
639 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
640 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
641 /* Phy reset */
642 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
643 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
644 >;
645 };
646
647 pinctrl_hog: hoggrp {
648 fsl,pins = <
649 /* ITU656_nRESET */
650 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
651 /* CAM1_MIRROR */
652 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
653 /* CAM2_MIRROR */
654 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
655 /* CAM_nDETECT */
656 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
657 /* nON_SWITCH */
658 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
659 /* ISB_IN1 */
660 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
661 /* ISB_nIN2 */
662 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
663 /* WARN_LIGHT */
664 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
665 /* ON2_FB */
666 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
667 /* YACO_nIRQ */
668 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
669 /* YACO_BOOT0 */
670 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
671 /* YACO_nRESET */
672 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
673 /* FORCE_ON1 */
674 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
675 /* AUDIO_nRESET */
676 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
677 /* ITU656_nPDN */
678 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
679
680 /* HW revision detect */
681 /* REV_ID0 */
682 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
683 /* REV_ID1 */
684 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
685 /* REV_ID2 */
686 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
687 /* REV_ID3 */
688 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
689 /* REV_ID4 */
690 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
691
692 /* New in HW revision 1 */
693 /* ON1_FB */
694 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
695 /* DIP1_FB */
696 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
697
698 /* New in UT2: FIXME: ISB PWM should start off, PD */
699 /* ISB_LED_PWM */
700 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0
701 >;
702 };
703
704 pinctrl_i2c1: i2c1grp {
705 fsl,pins = <
706 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
707 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
708 >;
709 };
710
711 pinctrl_i2c3: i2c3grp {
712 fsl,pins = <
713 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
714 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
715 >;
716 };
717
718 pinctrl_ipu1_csi0: ipu1csi0grp {
719 fsl,pins = <
720 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
721 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
722 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
723 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
724 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
725 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
726 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
727 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
728 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
729 >;
730 };
731
732 pinctrl_leds: ledsgrp {
733 fsl,pins = <
734 /* DEBUG0 */
735 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
736 /* DEBUG1 */
737 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
738 /* POWER_LED */
739 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
740 >;
741 };
742
743 pinctrl_pwm1: pwm1grp {
744 fsl,pins = <
745 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
746 >;
747 };
748
749 /* YaCO AUX Uart */
750 pinctrl_uart1: uart1grp {
751 fsl,pins = <
752 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
753 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
754 >;
755 };
756
757 pinctrl_uart2: uart2grp {
758 fsl,pins = <
759 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
760 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
761 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
762 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
763 >;
764 };
765
766 /* YaCO Touchscreen UART */
767 pinctrl_uart3: uart3grp {
768 fsl,pins = <
769 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
770 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
771 >;
772 };
773
774 pinctrl_uart4: uart4grp {
775 fsl,pins = <
776 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
777 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
778 >;
779 };
780
781 pinctrl_uart5: uart5grp {
782 fsl,pins = <
783 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
784 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
785 >;
786 };
787
788 pinctrl_usbotg: usbotggrp {
789 fsl,pins = <
790 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
791 /* power enable, high active */
792 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
793 >;
794 };
795
796 pinctrl_usdhc1: usdhc1grp {
797 fsl,pins = <
798 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
799 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
800 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
801 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
802 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
803 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
804 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
805 >;
806 };
807
808 pinctrl_usdhc2: usdhc2grp {
809 fsl,pins = <
810 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
811 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
812 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
813 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
814 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
815 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
816 /* WL12xx IRQ */
817 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
818 >;
819 };
820
821 pinctrl_usdhc3: usdhc3grp {
822 fsl,pins = <
823 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
824 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
825 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
826 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
827 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
828 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
829 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
830 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
831 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
832 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
833 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
834 >;
835 };
836
837 pinctrl_wifi_npd: wifinpdgrp {
838 fsl,pins = <
839 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
840 >;
841 };
842};