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1// SPDX-License-Identifier: GPL-2.0-only
2//
3// tegra210_amx.c - Tegra210 AMX driver
4//
5// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
6
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/regmap.h>
16#include <sound/core.h>
17#include <sound/pcm.h>
18#include <sound/pcm_params.h>
19#include <sound/soc.h>
20
21#include "tegra210_amx.h"
22#include "tegra_cif.h"
23
24/*
25 * The counter is in terms of AHUB clock cycles. If a frame is not
26 * received within these clock cycles, the AMX input channel gets
27 * automatically disabled. For now the counter is calculated as a
28 * function of sample rate (8 kHz) and AHUB clock (49.152 MHz).
29 * If later an accurate number is needed, the counter needs to be
30 * calculated at runtime.
31 *
32 * count = ahub_clk / sample_rate
33 */
34#define TEGRA194_MAX_FRAME_IDLE_COUNT 0x1800
35
36#define AMX_CH_REG(id, reg) ((reg) + ((id) * TEGRA210_AMX_AUDIOCIF_CH_STRIDE))
37
38static const struct reg_default tegra210_amx_reg_defaults[] = {
39 { TEGRA210_AMX_RX_INT_MASK, 0x0000000f},
40 { TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000},
41 { TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000},
42 { TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000},
43 { TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000},
44 { TEGRA210_AMX_TX_INT_MASK, 0x00000001},
45 { TEGRA210_AMX_TX_CIF_CTRL, 0x00007000},
46 { TEGRA210_AMX_CG, 0x1},
47 { TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000},
48};
49
50static void tegra210_amx_write_map_ram(struct tegra210_amx *amx)
51{
52 int i;
53
54 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL,
55 TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
56 TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN |
57 TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE);
58
59 for (i = 0; i < TEGRA210_AMX_RAM_DEPTH; i++)
60 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA,
61 amx->map[i]);
62
63 regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN0, amx->byte_mask[0]);
64 regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN1, amx->byte_mask[1]);
65}
66
67static int tegra210_amx_startup(struct snd_pcm_substream *substream,
68 struct snd_soc_dai *dai)
69{
70 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
71 unsigned int val;
72 int err;
73
74 /* Ensure if AMX is disabled */
75 err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_STATUS, val,
76 !(val & 0x1), 10, 10000);
77 if (err < 0) {
78 dev_err(dai->dev, "failed to stop AMX, err = %d\n", err);
79 return err;
80 }
81
82 /*
83 * Soft Reset: Below performs module soft reset which clears
84 * all FSM logic, flushes flow control of FIFO and resets the
85 * state register. It also brings module back to disabled
86 * state (without flushing the data in the pipe).
87 */
88 regmap_update_bits(amx->regmap, TEGRA210_AMX_SOFT_RESET,
89 TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK,
90 TEGRA210_AMX_SOFT_RESET_SOFT_EN);
91
92 err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_SOFT_RESET,
93 val, !(val & 0x1), 10, 10000);
94 if (err < 0) {
95 dev_err(dai->dev, "failed to reset AMX, err = %d\n", err);
96 return err;
97 }
98
99 return 0;
100}
101
102static int __maybe_unused tegra210_amx_runtime_suspend(struct device *dev)
103{
104 struct tegra210_amx *amx = dev_get_drvdata(dev);
105
106 regcache_cache_only(amx->regmap, true);
107 regcache_mark_dirty(amx->regmap);
108
109 return 0;
110}
111
112static int __maybe_unused tegra210_amx_runtime_resume(struct device *dev)
113{
114 struct tegra210_amx *amx = dev_get_drvdata(dev);
115
116 regcache_cache_only(amx->regmap, false);
117 regcache_sync(amx->regmap);
118
119 regmap_update_bits(amx->regmap,
120 TEGRA210_AMX_CTRL,
121 TEGRA210_AMX_CTRL_RX_DEP_MASK,
122 TEGRA210_AMX_WAIT_ON_ANY << TEGRA210_AMX_CTRL_RX_DEP_SHIFT);
123
124 tegra210_amx_write_map_ram(amx);
125
126 return 0;
127}
128
129static int tegra210_amx_set_audio_cif(struct snd_soc_dai *dai,
130 struct snd_pcm_hw_params *params,
131 unsigned int reg)
132{
133 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
134 int channels, audio_bits;
135 struct tegra_cif_conf cif_conf;
136
137 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
138
139 channels = params_channels(params);
140
141 switch (params_format(params)) {
142 case SNDRV_PCM_FORMAT_S8:
143 audio_bits = TEGRA_ACIF_BITS_8;
144 break;
145 case SNDRV_PCM_FORMAT_S16_LE:
146 audio_bits = TEGRA_ACIF_BITS_16;
147 break;
148 case SNDRV_PCM_FORMAT_S32_LE:
149 audio_bits = TEGRA_ACIF_BITS_32;
150 break;
151 default:
152 return -EINVAL;
153 }
154
155 cif_conf.audio_ch = channels;
156 cif_conf.client_ch = channels;
157 cif_conf.audio_bits = audio_bits;
158 cif_conf.client_bits = audio_bits;
159
160 tegra_set_cif(amx->regmap, reg, &cif_conf);
161
162 return 0;
163}
164
165static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream,
166 struct snd_pcm_hw_params *params,
167 struct snd_soc_dai *dai)
168{
169 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
170
171 if (amx->soc_data->auto_disable) {
172 regmap_write(amx->regmap,
173 AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD),
174 TEGRA194_MAX_FRAME_IDLE_COUNT);
175 regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1);
176 }
177
178 return tegra210_amx_set_audio_cif(dai, params,
179 AMX_CH_REG(dai->id, TEGRA210_AMX_RX1_CIF_CTRL));
180}
181
182static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream,
183 struct snd_pcm_hw_params *params,
184 struct snd_soc_dai *dai)
185{
186 return tegra210_amx_set_audio_cif(dai, params,
187 TEGRA210_AMX_TX_CIF_CTRL);
188}
189
190static int tegra210_amx_get_byte_map(struct snd_kcontrol *kcontrol,
191 struct snd_ctl_elem_value *ucontrol)
192{
193 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
194 struct soc_mixer_control *mc =
195 (struct soc_mixer_control *)kcontrol->private_value;
196 struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
197 unsigned char *bytes_map = (unsigned char *)&amx->map;
198 int reg = mc->reg;
199 int enabled;
200
201 if (reg > 31)
202 enabled = amx->byte_mask[1] & (1 << (reg - 32));
203 else
204 enabled = amx->byte_mask[0] & (1 << reg);
205
206 if (enabled)
207 ucontrol->value.integer.value[0] = bytes_map[reg];
208 else
209 ucontrol->value.integer.value[0] = 0;
210
211 return 0;
212}
213
214static int tegra210_amx_put_byte_map(struct snd_kcontrol *kcontrol,
215 struct snd_ctl_elem_value *ucontrol)
216{
217 struct soc_mixer_control *mc =
218 (struct soc_mixer_control *)kcontrol->private_value;
219 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
220 struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
221 unsigned char *bytes_map = (unsigned char *)&amx->map;
222 int reg = mc->reg;
223 int value = ucontrol->value.integer.value[0];
224
225 if (value == bytes_map[reg])
226 return 0;
227
228 if (value >= 0 && value <= 255) {
229 /* Update byte map and enable slot */
230 bytes_map[reg] = value;
231 if (reg > 31)
232 amx->byte_mask[1] |= (1 << (reg - 32));
233 else
234 amx->byte_mask[0] |= (1 << reg);
235 } else {
236 /* Reset byte map and disable slot */
237 bytes_map[reg] = 0;
238 if (reg > 31)
239 amx->byte_mask[1] &= ~(1 << (reg - 32));
240 else
241 amx->byte_mask[0] &= ~(1 << reg);
242 }
243
244 return 1;
245}
246
247static const struct snd_soc_dai_ops tegra210_amx_out_dai_ops = {
248 .hw_params = tegra210_amx_out_hw_params,
249 .startup = tegra210_amx_startup,
250};
251
252static const struct snd_soc_dai_ops tegra210_amx_in_dai_ops = {
253 .hw_params = tegra210_amx_in_hw_params,
254};
255
256#define IN_DAI(id) \
257 { \
258 .name = "AMX-RX-CIF" #id, \
259 .playback = { \
260 .stream_name = "RX" #id "-CIF-Playback",\
261 .channels_min = 1, \
262 .channels_max = 16, \
263 .rates = SNDRV_PCM_RATE_8000_192000, \
264 .formats = SNDRV_PCM_FMTBIT_S8 | \
265 SNDRV_PCM_FMTBIT_S16_LE | \
266 SNDRV_PCM_FMTBIT_S32_LE, \
267 }, \
268 .capture = { \
269 .stream_name = "RX" #id "-CIF-Capture", \
270 .channels_min = 1, \
271 .channels_max = 16, \
272 .rates = SNDRV_PCM_RATE_8000_192000, \
273 .formats = SNDRV_PCM_FMTBIT_S8 | \
274 SNDRV_PCM_FMTBIT_S16_LE | \
275 SNDRV_PCM_FMTBIT_S32_LE, \
276 }, \
277 .ops = &tegra210_amx_in_dai_ops, \
278 }
279
280#define OUT_DAI \
281 { \
282 .name = "AMX-TX-CIF", \
283 .playback = { \
284 .stream_name = "TX-CIF-Playback", \
285 .channels_min = 1, \
286 .channels_max = 16, \
287 .rates = SNDRV_PCM_RATE_8000_192000, \
288 .formats = SNDRV_PCM_FMTBIT_S8 | \
289 SNDRV_PCM_FMTBIT_S16_LE | \
290 SNDRV_PCM_FMTBIT_S32_LE, \
291 }, \
292 .capture = { \
293 .stream_name = "TX-CIF-Capture", \
294 .channels_min = 1, \
295 .channels_max = 16, \
296 .rates = SNDRV_PCM_RATE_8000_192000, \
297 .formats = SNDRV_PCM_FMTBIT_S8 | \
298 SNDRV_PCM_FMTBIT_S16_LE | \
299 SNDRV_PCM_FMTBIT_S32_LE, \
300 }, \
301 .ops = &tegra210_amx_out_dai_ops, \
302 }
303
304static struct snd_soc_dai_driver tegra210_amx_dais[] = {
305 IN_DAI(1),
306 IN_DAI(2),
307 IN_DAI(3),
308 IN_DAI(4),
309 OUT_DAI,
310};
311
312static const struct snd_soc_dapm_widget tegra210_amx_widgets[] = {
313 SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, TEGRA210_AMX_CTRL, 0, 0),
314 SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, TEGRA210_AMX_CTRL, 1, 0),
315 SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, TEGRA210_AMX_CTRL, 2, 0),
316 SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, TEGRA210_AMX_CTRL, 3, 0),
317 SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_AMX_ENABLE,
318 TEGRA210_AMX_ENABLE_SHIFT, 0),
319};
320
321#define STREAM_ROUTES(id, sname) \
322 { "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
323 { "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname },\
324 { "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
325 { "TX", NULL, "RX" #id }, \
326 { "TX-CIF-" sname, NULL, "TX" }, \
327 { "XBAR-" sname, NULL, "TX-CIF-" sname }, \
328 { "XBAR-RX", NULL, "XBAR-" sname }
329
330#define AMX_ROUTES(id) \
331 STREAM_ROUTES(id, "Playback"), \
332 STREAM_ROUTES(id, "Capture")
333
334static const struct snd_soc_dapm_route tegra210_amx_routes[] = {
335 AMX_ROUTES(1),
336 AMX_ROUTES(2),
337 AMX_ROUTES(3),
338 AMX_ROUTES(4),
339};
340
341#define TEGRA210_AMX_BYTE_MAP_CTRL(reg) \
342 SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \
343 tegra210_amx_get_byte_map, \
344 tegra210_amx_put_byte_map)
345
346static struct snd_kcontrol_new tegra210_amx_controls[] = {
347 TEGRA210_AMX_BYTE_MAP_CTRL(0),
348 TEGRA210_AMX_BYTE_MAP_CTRL(1),
349 TEGRA210_AMX_BYTE_MAP_CTRL(2),
350 TEGRA210_AMX_BYTE_MAP_CTRL(3),
351 TEGRA210_AMX_BYTE_MAP_CTRL(4),
352 TEGRA210_AMX_BYTE_MAP_CTRL(5),
353 TEGRA210_AMX_BYTE_MAP_CTRL(6),
354 TEGRA210_AMX_BYTE_MAP_CTRL(7),
355 TEGRA210_AMX_BYTE_MAP_CTRL(8),
356 TEGRA210_AMX_BYTE_MAP_CTRL(9),
357 TEGRA210_AMX_BYTE_MAP_CTRL(10),
358 TEGRA210_AMX_BYTE_MAP_CTRL(11),
359 TEGRA210_AMX_BYTE_MAP_CTRL(12),
360 TEGRA210_AMX_BYTE_MAP_CTRL(13),
361 TEGRA210_AMX_BYTE_MAP_CTRL(14),
362 TEGRA210_AMX_BYTE_MAP_CTRL(15),
363 TEGRA210_AMX_BYTE_MAP_CTRL(16),
364 TEGRA210_AMX_BYTE_MAP_CTRL(17),
365 TEGRA210_AMX_BYTE_MAP_CTRL(18),
366 TEGRA210_AMX_BYTE_MAP_CTRL(19),
367 TEGRA210_AMX_BYTE_MAP_CTRL(20),
368 TEGRA210_AMX_BYTE_MAP_CTRL(21),
369 TEGRA210_AMX_BYTE_MAP_CTRL(22),
370 TEGRA210_AMX_BYTE_MAP_CTRL(23),
371 TEGRA210_AMX_BYTE_MAP_CTRL(24),
372 TEGRA210_AMX_BYTE_MAP_CTRL(25),
373 TEGRA210_AMX_BYTE_MAP_CTRL(26),
374 TEGRA210_AMX_BYTE_MAP_CTRL(27),
375 TEGRA210_AMX_BYTE_MAP_CTRL(28),
376 TEGRA210_AMX_BYTE_MAP_CTRL(29),
377 TEGRA210_AMX_BYTE_MAP_CTRL(30),
378 TEGRA210_AMX_BYTE_MAP_CTRL(31),
379 TEGRA210_AMX_BYTE_MAP_CTRL(32),
380 TEGRA210_AMX_BYTE_MAP_CTRL(33),
381 TEGRA210_AMX_BYTE_MAP_CTRL(34),
382 TEGRA210_AMX_BYTE_MAP_CTRL(35),
383 TEGRA210_AMX_BYTE_MAP_CTRL(36),
384 TEGRA210_AMX_BYTE_MAP_CTRL(37),
385 TEGRA210_AMX_BYTE_MAP_CTRL(38),
386 TEGRA210_AMX_BYTE_MAP_CTRL(39),
387 TEGRA210_AMX_BYTE_MAP_CTRL(40),
388 TEGRA210_AMX_BYTE_MAP_CTRL(41),
389 TEGRA210_AMX_BYTE_MAP_CTRL(42),
390 TEGRA210_AMX_BYTE_MAP_CTRL(43),
391 TEGRA210_AMX_BYTE_MAP_CTRL(44),
392 TEGRA210_AMX_BYTE_MAP_CTRL(45),
393 TEGRA210_AMX_BYTE_MAP_CTRL(46),
394 TEGRA210_AMX_BYTE_MAP_CTRL(47),
395 TEGRA210_AMX_BYTE_MAP_CTRL(48),
396 TEGRA210_AMX_BYTE_MAP_CTRL(49),
397 TEGRA210_AMX_BYTE_MAP_CTRL(50),
398 TEGRA210_AMX_BYTE_MAP_CTRL(51),
399 TEGRA210_AMX_BYTE_MAP_CTRL(52),
400 TEGRA210_AMX_BYTE_MAP_CTRL(53),
401 TEGRA210_AMX_BYTE_MAP_CTRL(54),
402 TEGRA210_AMX_BYTE_MAP_CTRL(55),
403 TEGRA210_AMX_BYTE_MAP_CTRL(56),
404 TEGRA210_AMX_BYTE_MAP_CTRL(57),
405 TEGRA210_AMX_BYTE_MAP_CTRL(58),
406 TEGRA210_AMX_BYTE_MAP_CTRL(59),
407 TEGRA210_AMX_BYTE_MAP_CTRL(60),
408 TEGRA210_AMX_BYTE_MAP_CTRL(61),
409 TEGRA210_AMX_BYTE_MAP_CTRL(62),
410 TEGRA210_AMX_BYTE_MAP_CTRL(63),
411};
412
413static const struct snd_soc_component_driver tegra210_amx_cmpnt = {
414 .dapm_widgets = tegra210_amx_widgets,
415 .num_dapm_widgets = ARRAY_SIZE(tegra210_amx_widgets),
416 .dapm_routes = tegra210_amx_routes,
417 .num_dapm_routes = ARRAY_SIZE(tegra210_amx_routes),
418 .controls = tegra210_amx_controls,
419 .num_controls = ARRAY_SIZE(tegra210_amx_controls),
420};
421
422static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg)
423{
424 switch (reg) {
425 case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL:
426 case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG:
427 case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA:
428 case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA:
429 return true;
430 default:
431 return false;
432 }
433}
434
435static bool tegra194_amx_wr_reg(struct device *dev, unsigned int reg)
436{
437 switch (reg) {
438 case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
439 return true;
440 default:
441 return tegra210_amx_wr_reg(dev, reg);
442 }
443}
444
445static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg)
446{
447 switch (reg) {
448 case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA:
449 return true;
450 default:
451 return false;
452 }
453}
454
455static bool tegra194_amx_rd_reg(struct device *dev, unsigned int reg)
456{
457 switch (reg) {
458 case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
459 return true;
460 default:
461 return tegra210_amx_rd_reg(dev, reg);
462 }
463}
464
465static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg)
466{
467 switch (reg) {
468 case TEGRA210_AMX_RX_STATUS:
469 case TEGRA210_AMX_RX_INT_STATUS:
470 case TEGRA210_AMX_RX_INT_SET:
471 case TEGRA210_AMX_TX_STATUS:
472 case TEGRA210_AMX_TX_INT_STATUS:
473 case TEGRA210_AMX_TX_INT_SET:
474 case TEGRA210_AMX_SOFT_RESET:
475 case TEGRA210_AMX_STATUS:
476 case TEGRA210_AMX_INT_STATUS:
477 case TEGRA210_AMX_CFG_RAM_CTRL:
478 case TEGRA210_AMX_CFG_RAM_DATA:
479 return true;
480 default:
481 break;
482 }
483
484 return false;
485}
486
487static const struct regmap_config tegra210_amx_regmap_config = {
488 .reg_bits = 32,
489 .reg_stride = 4,
490 .val_bits = 32,
491 .max_register = TEGRA210_AMX_CFG_RAM_DATA,
492 .writeable_reg = tegra210_amx_wr_reg,
493 .readable_reg = tegra210_amx_rd_reg,
494 .volatile_reg = tegra210_amx_volatile_reg,
495 .reg_defaults = tegra210_amx_reg_defaults,
496 .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
497 .cache_type = REGCACHE_FLAT,
498};
499
500static const struct regmap_config tegra194_amx_regmap_config = {
501 .reg_bits = 32,
502 .reg_stride = 4,
503 .val_bits = 32,
504 .max_register = TEGRA194_AMX_RX4_LAST_FRAME_PERIOD,
505 .writeable_reg = tegra194_amx_wr_reg,
506 .readable_reg = tegra194_amx_rd_reg,
507 .volatile_reg = tegra210_amx_volatile_reg,
508 .reg_defaults = tegra210_amx_reg_defaults,
509 .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
510 .cache_type = REGCACHE_FLAT,
511};
512
513static const struct tegra210_amx_soc_data soc_data_tegra210 = {
514 .regmap_conf = &tegra210_amx_regmap_config,
515};
516
517static const struct tegra210_amx_soc_data soc_data_tegra194 = {
518 .regmap_conf = &tegra194_amx_regmap_config,
519 .auto_disable = true,
520};
521
522static const struct of_device_id tegra210_amx_of_match[] = {
523 { .compatible = "nvidia,tegra210-amx", .data = &soc_data_tegra210 },
524 { .compatible = "nvidia,tegra194-amx", .data = &soc_data_tegra194 },
525 {},
526};
527MODULE_DEVICE_TABLE(of, tegra210_amx_of_match);
528
529static int tegra210_amx_platform_probe(struct platform_device *pdev)
530{
531 struct device *dev = &pdev->dev;
532 struct tegra210_amx *amx;
533 void __iomem *regs;
534 int err;
535 const struct of_device_id *match;
536 struct tegra210_amx_soc_data *soc_data;
537
538 match = of_match_device(tegra210_amx_of_match, dev);
539
540 soc_data = (struct tegra210_amx_soc_data *)match->data;
541
542 amx = devm_kzalloc(dev, sizeof(*amx), GFP_KERNEL);
543 if (!amx)
544 return -ENOMEM;
545
546 amx->soc_data = soc_data;
547
548 dev_set_drvdata(dev, amx);
549
550 regs = devm_platform_ioremap_resource(pdev, 0);
551 if (IS_ERR(regs))
552 return PTR_ERR(regs);
553
554 amx->regmap = devm_regmap_init_mmio(dev, regs,
555 soc_data->regmap_conf);
556 if (IS_ERR(amx->regmap)) {
557 dev_err(dev, "regmap init failed\n");
558 return PTR_ERR(amx->regmap);
559 }
560
561 regcache_cache_only(amx->regmap, true);
562
563 err = devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt,
564 tegra210_amx_dais,
565 ARRAY_SIZE(tegra210_amx_dais));
566 if (err) {
567 dev_err(dev, "can't register AMX component, err: %d\n", err);
568 return err;
569 }
570
571 pm_runtime_enable(dev);
572
573 return 0;
574}
575
576static int tegra210_amx_platform_remove(struct platform_device *pdev)
577{
578 pm_runtime_disable(&pdev->dev);
579
580 return 0;
581}
582
583static const struct dev_pm_ops tegra210_amx_pm_ops = {
584 SET_RUNTIME_PM_OPS(tegra210_amx_runtime_suspend,
585 tegra210_amx_runtime_resume, NULL)
586 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
587 pm_runtime_force_resume)
588};
589
590static struct platform_driver tegra210_amx_driver = {
591 .driver = {
592 .name = "tegra210-amx",
593 .of_match_table = tegra210_amx_of_match,
594 .pm = &tegra210_amx_pm_ops,
595 },
596 .probe = tegra210_amx_platform_probe,
597 .remove = tegra210_amx_platform_remove,
598};
599module_platform_driver(tegra210_amx_driver);
600
601MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
602MODULE_DESCRIPTION("Tegra210 AMX ASoC driver");
603MODULE_LICENSE("GPL v2");