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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * IMG I2S input controller driver
4 *
5 * Copyright (C) 2015 Imagination Technologies Ltd.
6 *
7 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include <sound/core.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/initval.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25
26#define IMG_I2S_IN_RX_FIFO 0x0
27
28#define IMG_I2S_IN_CTL 0x4
29#define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK 0xfffffffc
30#define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT 2
31#define IMG_I2S_IN_CTL_16PACK_MASK BIT(1)
32#define IMG_I2S_IN_CTL_ME_MASK BIT(0)
33
34#define IMG_I2S_IN_CH_CTL 0x4
35#define IMG_I2S_IN_CH_CTL_CCDEL_MASK 0x38000
36#define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT 15
37#define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14)
38#define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13)
39#define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12)
40#define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10)
41#define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9)
42#define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8)
43#define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7)
44#define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6)
45#define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3)
46#define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2)
47#define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1)
48#define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0)
49
50#define IMG_I2S_IN_CH_STRIDE 0x20
51
52struct img_i2s_in {
53 void __iomem *base;
54 struct clk *clk_sys;
55 struct snd_dmaengine_dai_dma_data dma_data;
56 struct device *dev;
57 unsigned int max_i2s_chan;
58 void __iomem *channel_base;
59 unsigned int active_channels;
60 struct snd_soc_dai_driver dai_driver;
61 u32 suspend_ctl;
62 u32 *suspend_ch_ctl;
63};
64
65static int img_i2s_in_runtime_suspend(struct device *dev)
66{
67 struct img_i2s_in *i2s = dev_get_drvdata(dev);
68
69 clk_disable_unprepare(i2s->clk_sys);
70
71 return 0;
72}
73
74static int img_i2s_in_runtime_resume(struct device *dev)
75{
76 struct img_i2s_in *i2s = dev_get_drvdata(dev);
77 int ret;
78
79 ret = clk_prepare_enable(i2s->clk_sys);
80 if (ret) {
81 dev_err(dev, "Unable to enable sys clock\n");
82 return ret;
83 }
84
85 return 0;
86}
87
88static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
89{
90 writel(val, i2s->base + reg);
91}
92
93static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
94{
95 return readl(i2s->base + reg);
96}
97
98static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
99 u32 val, u32 reg)
100{
101 writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
102}
103
104static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
105 u32 reg)
106{
107 return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
108}
109
110static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
111{
112 u32 reg;
113
114 reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
115 reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
116 img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
117}
118
119static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
120{
121 u32 reg;
122
123 reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
124 reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
125 img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
126}
127
128static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
129{
130 u32 reg;
131
132 reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
133 reg &= ~IMG_I2S_IN_CTL_ME_MASK;
134 img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
135}
136
137static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
138{
139 u32 reg;
140
141 reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
142 reg |= IMG_I2S_IN_CTL_ME_MASK;
143 img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
144}
145
146static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
147{
148 int i;
149 u32 reg;
150
151 for (i = 0; i < i2s->active_channels; i++) {
152 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
153 reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
154 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
155 reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
156 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
157 }
158}
159
160static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
161 struct snd_soc_dai *dai)
162{
163 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
164
165 switch (cmd) {
166 case SNDRV_PCM_TRIGGER_START:
167 case SNDRV_PCM_TRIGGER_RESUME:
168 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
169 img_i2s_in_enable(i2s);
170 break;
171
172 case SNDRV_PCM_TRIGGER_STOP:
173 case SNDRV_PCM_TRIGGER_SUSPEND:
174 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
175 img_i2s_in_disable(i2s);
176 break;
177 default:
178 return -EINVAL;
179 }
180
181 return 0;
182}
183
184static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
185 unsigned int sample_rate, unsigned int frame_size,
186 unsigned int *bclk_filter_enable,
187 unsigned int *bclk_filter_value)
188{
189 unsigned int bclk_freq, cur_freq;
190
191 bclk_freq = sample_rate * frame_size;
192
193 cur_freq = clk_get_rate(i2s->clk_sys);
194
195 if (cur_freq >= bclk_freq * 8) {
196 *bclk_filter_enable = 1;
197 *bclk_filter_value = 0;
198 } else if (cur_freq >= bclk_freq * 7) {
199 *bclk_filter_enable = 1;
200 *bclk_filter_value = 1;
201 } else if (cur_freq >= bclk_freq * 6) {
202 *bclk_filter_enable = 0;
203 *bclk_filter_value = 0;
204 } else {
205 dev_err(i2s->dev,
206 "Sys clock rate %u insufficient for sample rate %u\n",
207 cur_freq, sample_rate);
208 return -EINVAL;
209 }
210
211 return 0;
212}
213
214static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
215 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
216{
217 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
218 unsigned int rate, channels, i2s_channels, frame_size;
219 unsigned int bclk_filter_enable, bclk_filter_value;
220 int i, ret = 0;
221 u32 reg, control_mask, chan_control_mask;
222 u32 control_set = 0, chan_control_set = 0;
223 snd_pcm_format_t format;
224
225 rate = params_rate(params);
226 format = params_format(params);
227 channels = params_channels(params);
228 i2s_channels = channels / 2;
229
230 switch (format) {
231 case SNDRV_PCM_FORMAT_S32_LE:
232 frame_size = 64;
233 chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
234 chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
235 chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
236 break;
237 case SNDRV_PCM_FORMAT_S24_LE:
238 frame_size = 64;
239 chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
240 chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
241 break;
242 case SNDRV_PCM_FORMAT_S16_LE:
243 frame_size = 32;
244 control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
245 chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
246 break;
247 default:
248 return -EINVAL;
249 }
250
251 if ((channels < 2) ||
252 (channels > (i2s->max_i2s_chan * 2)) ||
253 (channels % 2))
254 return -EINVAL;
255
256 control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
257
258 ret = img_i2s_in_check_rate(i2s, rate, frame_size,
259 &bclk_filter_enable, &bclk_filter_value);
260 if (ret < 0)
261 return ret;
262
263 if (bclk_filter_enable)
264 chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
265
266 if (bclk_filter_value)
267 chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
268
269 control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
270 IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
271
272 chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
273 IMG_I2S_IN_CH_CTL_FEN_MASK |
274 IMG_I2S_IN_CH_CTL_FMODE_MASK |
275 IMG_I2S_IN_CH_CTL_SW_MASK |
276 IMG_I2S_IN_CH_CTL_FW_MASK |
277 IMG_I2S_IN_CH_CTL_PACKH_MASK;
278
279 reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
280 reg = (reg & ~control_mask) | control_set;
281 img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
282
283 for (i = 0; i < i2s->active_channels; i++)
284 img_i2s_in_ch_disable(i2s, i);
285
286 for (i = 0; i < i2s->max_i2s_chan; i++) {
287 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
288 reg = (reg & ~chan_control_mask) | chan_control_set;
289 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
290 }
291
292 i2s->active_channels = i2s_channels;
293
294 img_i2s_in_flush(i2s);
295
296 for (i = 0; i < i2s->active_channels; i++)
297 img_i2s_in_ch_enable(i2s, i);
298
299 return 0;
300}
301
302static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
303{
304 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
305 int i, ret;
306 u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
307 u32 reg;
308
309 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
310 case SND_SOC_DAIFMT_NB_NF:
311 lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
312 break;
313 case SND_SOC_DAIFMT_NB_IF:
314 break;
315 case SND_SOC_DAIFMT_IB_NF:
316 lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
317 blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
318 break;
319 case SND_SOC_DAIFMT_IB_IF:
320 blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
321 break;
322 default:
323 return -EINVAL;
324 }
325
326 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
327 case SND_SOC_DAIFMT_I2S:
328 chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
329 break;
330 case SND_SOC_DAIFMT_LEFT_J:
331 break;
332 default:
333 return -EINVAL;
334 }
335
336 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
337 case SND_SOC_DAIFMT_BC_FC:
338 break;
339 default:
340 return -EINVAL;
341 }
342
343 chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
344
345 ret = pm_runtime_resume_and_get(i2s->dev);
346 if (ret < 0)
347 return ret;
348
349 for (i = 0; i < i2s->active_channels; i++)
350 img_i2s_in_ch_disable(i2s, i);
351
352 /*
353 * BLKP and LRD must be set during separate register writes
354 */
355 for (i = 0; i < i2s->max_i2s_chan; i++) {
356 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
357 reg = (reg & ~chan_control_mask) | chan_control_set;
358 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
359 reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
360 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
361 reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
362 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
363 }
364
365 for (i = 0; i < i2s->active_channels; i++)
366 img_i2s_in_ch_enable(i2s, i);
367
368 pm_runtime_put(i2s->dev);
369
370 return 0;
371}
372
373static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
374 .trigger = img_i2s_in_trigger,
375 .hw_params = img_i2s_in_hw_params,
376 .set_fmt = img_i2s_in_set_fmt
377};
378
379static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
380{
381 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
382
383 snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
384
385 return 0;
386}
387
388static const struct snd_soc_component_driver img_i2s_in_component = {
389 .name = "img-i2s-in",
390 .legacy_dai_naming = 1,
391};
392
393static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
394 struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
395{
396 unsigned int i2s_channels = params_channels(params) / 2;
397 struct snd_soc_pcm_runtime *rtd = st->private_data;
398 struct snd_dmaengine_dai_dma_data *dma_data;
399 int ret;
400
401 dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
402
403 ret = snd_hwparams_to_dma_slave_config(st, params, sc);
404 if (ret)
405 return ret;
406
407 sc->src_addr = dma_data->addr;
408 sc->src_addr_width = dma_data->addr_width;
409 sc->src_maxburst = 4 * i2s_channels;
410
411 return 0;
412}
413
414static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
415 .prepare_slave_config = img_i2s_in_dma_prepare_slave_config
416};
417
418static int img_i2s_in_probe(struct platform_device *pdev)
419{
420 struct img_i2s_in *i2s;
421 struct resource *res;
422 void __iomem *base;
423 int ret, i;
424 struct reset_control *rst;
425 unsigned int max_i2s_chan_pow_2;
426 struct device *dev = &pdev->dev;
427
428 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
429 if (!i2s)
430 return -ENOMEM;
431
432 platform_set_drvdata(pdev, i2s);
433
434 i2s->dev = dev;
435
436 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
437 if (IS_ERR(base))
438 return PTR_ERR(base);
439
440 i2s->base = base;
441
442 if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
443 &i2s->max_i2s_chan)) {
444 dev_err(dev, "No img,i2s-channels property\n");
445 return -EINVAL;
446 }
447
448 max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
449
450 i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
451
452 i2s->clk_sys = devm_clk_get(dev, "sys");
453 if (IS_ERR(i2s->clk_sys))
454 return dev_err_probe(dev, PTR_ERR(i2s->clk_sys),
455 "Failed to acquire clock 'sys'\n");
456
457 pm_runtime_enable(&pdev->dev);
458 if (!pm_runtime_enabled(&pdev->dev)) {
459 ret = img_i2s_in_runtime_resume(&pdev->dev);
460 if (ret)
461 goto err_pm_disable;
462 }
463 ret = pm_runtime_resume_and_get(&pdev->dev);
464 if (ret < 0)
465 goto err_suspend;
466
467 i2s->active_channels = 1;
468 i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
469 i2s->dma_data.addr_width = 4;
470
471 i2s->dai_driver.probe = img_i2s_in_dai_probe;
472 i2s->dai_driver.capture.channels_min = 2;
473 i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
474 i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
475 i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
476 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
477 i2s->dai_driver.ops = &img_i2s_in_dai_ops;
478
479 rst = devm_reset_control_get_exclusive(dev, "rst");
480 if (IS_ERR(rst)) {
481 if (PTR_ERR(rst) == -EPROBE_DEFER) {
482 ret = -EPROBE_DEFER;
483 pm_runtime_put(&pdev->dev);
484 goto err_suspend;
485 }
486
487 dev_dbg(dev, "No top level reset found\n");
488
489 img_i2s_in_disable(i2s);
490
491 for (i = 0; i < i2s->max_i2s_chan; i++)
492 img_i2s_in_ch_disable(i2s, i);
493 } else {
494 reset_control_assert(rst);
495 reset_control_deassert(rst);
496 }
497
498 img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
499
500 for (i = 0; i < i2s->max_i2s_chan; i++)
501 img_i2s_in_ch_writel(i2s, i,
502 (4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
503 IMG_I2S_IN_CH_CTL_JUST_MASK |
504 IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
505
506 pm_runtime_put(&pdev->dev);
507
508 i2s->suspend_ch_ctl = devm_kcalloc(dev,
509 i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
510 if (!i2s->suspend_ch_ctl) {
511 ret = -ENOMEM;
512 goto err_suspend;
513 }
514
515 ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
516 &i2s->dai_driver, 1);
517 if (ret)
518 goto err_suspend;
519
520 ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
521 if (ret)
522 goto err_suspend;
523
524 return 0;
525
526err_suspend:
527 if (!pm_runtime_enabled(&pdev->dev))
528 img_i2s_in_runtime_suspend(&pdev->dev);
529err_pm_disable:
530 pm_runtime_disable(&pdev->dev);
531
532 return ret;
533}
534
535static int img_i2s_in_dev_remove(struct platform_device *pdev)
536{
537 pm_runtime_disable(&pdev->dev);
538 if (!pm_runtime_status_suspended(&pdev->dev))
539 img_i2s_in_runtime_suspend(&pdev->dev);
540
541 return 0;
542}
543
544#ifdef CONFIG_PM_SLEEP
545static int img_i2s_in_suspend(struct device *dev)
546{
547 struct img_i2s_in *i2s = dev_get_drvdata(dev);
548 int i, ret;
549 u32 reg;
550
551 if (pm_runtime_status_suspended(dev)) {
552 ret = img_i2s_in_runtime_resume(dev);
553 if (ret)
554 return ret;
555 }
556
557 for (i = 0; i < i2s->max_i2s_chan; i++) {
558 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
559 i2s->suspend_ch_ctl[i] = reg;
560 }
561
562 i2s->suspend_ctl = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
563
564 img_i2s_in_runtime_suspend(dev);
565
566 return 0;
567}
568
569static int img_i2s_in_resume(struct device *dev)
570{
571 struct img_i2s_in *i2s = dev_get_drvdata(dev);
572 int i, ret;
573 u32 reg;
574
575 ret = img_i2s_in_runtime_resume(dev);
576 if (ret)
577 return ret;
578
579 for (i = 0; i < i2s->max_i2s_chan; i++) {
580 reg = i2s->suspend_ch_ctl[i];
581 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
582 }
583
584 img_i2s_in_writel(i2s, i2s->suspend_ctl, IMG_I2S_IN_CTL);
585
586 if (pm_runtime_status_suspended(dev))
587 img_i2s_in_runtime_suspend(dev);
588
589 return 0;
590}
591#endif
592
593static const struct of_device_id img_i2s_in_of_match[] = {
594 { .compatible = "img,i2s-in" },
595 {}
596};
597MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
598
599static const struct dev_pm_ops img_i2s_in_pm_ops = {
600 SET_RUNTIME_PM_OPS(img_i2s_in_runtime_suspend,
601 img_i2s_in_runtime_resume, NULL)
602 SET_SYSTEM_SLEEP_PM_OPS(img_i2s_in_suspend, img_i2s_in_resume)
603};
604
605static struct platform_driver img_i2s_in_driver = {
606 .driver = {
607 .name = "img-i2s-in",
608 .of_match_table = img_i2s_in_of_match,
609 .pm = &img_i2s_in_pm_ops
610 },
611 .probe = img_i2s_in_probe,
612 .remove = img_i2s_in_dev_remove
613};
614module_platform_driver(img_i2s_in_driver);
615
616MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
617MODULE_DESCRIPTION("IMG I2S Input Driver");
618MODULE_LICENSE("GPL v2");
1/*
2 * IMG I2S input controller driver
3 *
4 * Copyright (C) 2015 Imagination Technologies Ltd.
5 *
6 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/reset.h>
20
21#include <sound/core.h>
22#include <sound/dmaengine_pcm.h>
23#include <sound/initval.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27
28#define IMG_I2S_IN_RX_FIFO 0x0
29
30#define IMG_I2S_IN_CTL 0x4
31#define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK 0xfffffffc
32#define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT 2
33#define IMG_I2S_IN_CTL_16PACK_MASK BIT(1)
34#define IMG_I2S_IN_CTL_ME_MASK BIT(0)
35
36#define IMG_I2S_IN_CH_CTL 0x4
37#define IMG_I2S_IN_CH_CTL_CCDEL_MASK 0x38000
38#define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT 15
39#define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14)
40#define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13)
41#define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12)
42#define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10)
43#define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9)
44#define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8)
45#define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7)
46#define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6)
47#define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3)
48#define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2)
49#define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1)
50#define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0)
51
52#define IMG_I2S_IN_CH_STRIDE 0x20
53
54struct img_i2s_in {
55 void __iomem *base;
56 struct clk *clk_sys;
57 struct snd_dmaengine_dai_dma_data dma_data;
58 struct device *dev;
59 unsigned int max_i2s_chan;
60 void __iomem *channel_base;
61 unsigned int active_channels;
62 struct snd_soc_dai_driver dai_driver;
63};
64
65static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
66{
67 writel(val, i2s->base + reg);
68}
69
70static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
71{
72 return readl(i2s->base + reg);
73}
74
75static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
76 u32 val, u32 reg)
77{
78 writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
79}
80
81static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
82 u32 reg)
83{
84 return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
85}
86
87static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
88{
89 u32 reg;
90
91 reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
92 reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
93 img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
94}
95
96static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
97{
98 u32 reg;
99
100 reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
101 reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
102 img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
103}
104
105static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
106{
107 u32 reg;
108
109 reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
110 reg &= ~IMG_I2S_IN_CTL_ME_MASK;
111 img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
112}
113
114static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
115{
116 u32 reg;
117
118 reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
119 reg |= IMG_I2S_IN_CTL_ME_MASK;
120 img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
121}
122
123static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
124{
125 int i;
126 u32 reg;
127
128 for (i = 0; i < i2s->active_channels; i++) {
129 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
130 reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
131 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
132 reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
133 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
134 }
135}
136
137static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
138 struct snd_soc_dai *dai)
139{
140 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
141
142 switch (cmd) {
143 case SNDRV_PCM_TRIGGER_START:
144 case SNDRV_PCM_TRIGGER_RESUME:
145 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
146 img_i2s_in_enable(i2s);
147 break;
148
149 case SNDRV_PCM_TRIGGER_STOP:
150 case SNDRV_PCM_TRIGGER_SUSPEND:
151 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
152 img_i2s_in_disable(i2s);
153 break;
154 default:
155 return -EINVAL;
156 }
157
158 return 0;
159}
160
161static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
162 unsigned int sample_rate, unsigned int frame_size,
163 unsigned int *bclk_filter_enable,
164 unsigned int *bclk_filter_value)
165{
166 unsigned int bclk_freq, cur_freq;
167
168 bclk_freq = sample_rate * frame_size;
169
170 cur_freq = clk_get_rate(i2s->clk_sys);
171
172 if (cur_freq >= bclk_freq * 8) {
173 *bclk_filter_enable = 1;
174 *bclk_filter_value = 0;
175 } else if (cur_freq >= bclk_freq * 7) {
176 *bclk_filter_enable = 1;
177 *bclk_filter_value = 1;
178 } else if (cur_freq >= bclk_freq * 6) {
179 *bclk_filter_enable = 0;
180 *bclk_filter_value = 0;
181 } else {
182 dev_err(i2s->dev,
183 "Sys clock rate %u insufficient for sample rate %u\n",
184 cur_freq, sample_rate);
185 return -EINVAL;
186 }
187
188 return 0;
189}
190
191static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
192 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
193{
194 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
195 unsigned int rate, channels, i2s_channels, frame_size;
196 unsigned int bclk_filter_enable, bclk_filter_value;
197 int i, ret = 0;
198 u32 reg, control_mask, chan_control_mask;
199 u32 control_set = 0, chan_control_set = 0;
200 snd_pcm_format_t format;
201
202 rate = params_rate(params);
203 format = params_format(params);
204 channels = params_channels(params);
205 i2s_channels = channels / 2;
206
207 switch (format) {
208 case SNDRV_PCM_FORMAT_S32_LE:
209 frame_size = 64;
210 chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
211 chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
212 chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
213 break;
214 case SNDRV_PCM_FORMAT_S24_LE:
215 frame_size = 64;
216 chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
217 chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
218 break;
219 case SNDRV_PCM_FORMAT_S16_LE:
220 frame_size = 32;
221 control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
222 chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
223 break;
224 default:
225 return -EINVAL;
226 }
227
228 if ((channels < 2) ||
229 (channels > (i2s->max_i2s_chan * 2)) ||
230 (channels % 2))
231 return -EINVAL;
232
233 control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
234
235 ret = img_i2s_in_check_rate(i2s, rate, frame_size,
236 &bclk_filter_enable, &bclk_filter_value);
237 if (ret < 0)
238 return ret;
239
240 if (bclk_filter_enable)
241 chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
242
243 if (bclk_filter_value)
244 chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
245
246 control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
247 IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
248
249 chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
250 IMG_I2S_IN_CH_CTL_FEN_MASK |
251 IMG_I2S_IN_CH_CTL_FMODE_MASK |
252 IMG_I2S_IN_CH_CTL_SW_MASK |
253 IMG_I2S_IN_CH_CTL_FW_MASK |
254 IMG_I2S_IN_CH_CTL_PACKH_MASK;
255
256 reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
257 reg = (reg & ~control_mask) | control_set;
258 img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
259
260 for (i = 0; i < i2s->active_channels; i++)
261 img_i2s_in_ch_disable(i2s, i);
262
263 for (i = 0; i < i2s->max_i2s_chan; i++) {
264 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
265 reg = (reg & ~chan_control_mask) | chan_control_set;
266 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
267 }
268
269 i2s->active_channels = i2s_channels;
270
271 img_i2s_in_flush(i2s);
272
273 for (i = 0; i < i2s->active_channels; i++)
274 img_i2s_in_ch_enable(i2s, i);
275
276 return 0;
277}
278
279static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
280{
281 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
282 int i;
283 u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
284 u32 reg;
285
286 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
287 case SND_SOC_DAIFMT_NB_NF:
288 lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
289 break;
290 case SND_SOC_DAIFMT_NB_IF:
291 break;
292 case SND_SOC_DAIFMT_IB_NF:
293 lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
294 blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
295 break;
296 case SND_SOC_DAIFMT_IB_IF:
297 blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
298 break;
299 default:
300 return -EINVAL;
301 }
302
303 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
304 case SND_SOC_DAIFMT_I2S:
305 chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
306 break;
307 case SND_SOC_DAIFMT_LEFT_J:
308 break;
309 default:
310 return -EINVAL;
311 }
312
313 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
314 case SND_SOC_DAIFMT_CBM_CFM:
315 break;
316 default:
317 return -EINVAL;
318 }
319
320 chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
321
322 for (i = 0; i < i2s->active_channels; i++)
323 img_i2s_in_ch_disable(i2s, i);
324
325 /*
326 * BLKP and LRD must be set during separate register writes
327 */
328 for (i = 0; i < i2s->max_i2s_chan; i++) {
329 reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
330 reg = (reg & ~chan_control_mask) | chan_control_set;
331 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
332 reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
333 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
334 reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
335 img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
336 }
337
338 for (i = 0; i < i2s->active_channels; i++)
339 img_i2s_in_ch_enable(i2s, i);
340
341 return 0;
342}
343
344static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
345 .trigger = img_i2s_in_trigger,
346 .hw_params = img_i2s_in_hw_params,
347 .set_fmt = img_i2s_in_set_fmt
348};
349
350static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
351{
352 struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
353
354 snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
355
356 return 0;
357}
358
359static const struct snd_soc_component_driver img_i2s_in_component = {
360 .name = "img-i2s-in"
361};
362
363static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
364 struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
365{
366 unsigned int i2s_channels = params_channels(params) / 2;
367 struct snd_soc_pcm_runtime *rtd = st->private_data;
368 struct snd_dmaengine_dai_dma_data *dma_data;
369 int ret;
370
371 dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, st);
372
373 ret = snd_hwparams_to_dma_slave_config(st, params, sc);
374 if (ret)
375 return ret;
376
377 sc->src_addr = dma_data->addr;
378 sc->src_addr_width = dma_data->addr_width;
379 sc->src_maxburst = 4 * i2s_channels;
380
381 return 0;
382}
383
384static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
385 .prepare_slave_config = img_i2s_in_dma_prepare_slave_config
386};
387
388static int img_i2s_in_probe(struct platform_device *pdev)
389{
390 struct img_i2s_in *i2s;
391 struct resource *res;
392 void __iomem *base;
393 int ret, i;
394 struct reset_control *rst;
395 unsigned int max_i2s_chan_pow_2;
396 struct device *dev = &pdev->dev;
397
398 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
399 if (!i2s)
400 return -ENOMEM;
401
402 platform_set_drvdata(pdev, i2s);
403
404 i2s->dev = dev;
405
406 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407 base = devm_ioremap_resource(dev, res);
408 if (IS_ERR(base))
409 return PTR_ERR(base);
410
411 i2s->base = base;
412
413 if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
414 &i2s->max_i2s_chan)) {
415 dev_err(dev, "No img,i2s-channels property\n");
416 return -EINVAL;
417 }
418
419 max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
420
421 i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
422
423 i2s->clk_sys = devm_clk_get(dev, "sys");
424 if (IS_ERR(i2s->clk_sys)) {
425 if (PTR_ERR(i2s->clk_sys) != -EPROBE_DEFER)
426 dev_err(dev, "Failed to acquire clock 'sys'\n");
427 return PTR_ERR(i2s->clk_sys);
428 }
429
430 ret = clk_prepare_enable(i2s->clk_sys);
431 if (ret)
432 return ret;
433
434 i2s->active_channels = 1;
435 i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
436 i2s->dma_data.addr_width = 4;
437
438 i2s->dai_driver.probe = img_i2s_in_dai_probe;
439 i2s->dai_driver.capture.channels_min = 2;
440 i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
441 i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
442 i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
443 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
444 i2s->dai_driver.ops = &img_i2s_in_dai_ops;
445
446 rst = devm_reset_control_get(dev, "rst");
447 if (IS_ERR(rst)) {
448 if (PTR_ERR(rst) == -EPROBE_DEFER) {
449 ret = -EPROBE_DEFER;
450 goto err_clk_disable;
451 }
452
453 dev_dbg(dev, "No top level reset found\n");
454
455 img_i2s_in_disable(i2s);
456
457 for (i = 0; i < i2s->max_i2s_chan; i++)
458 img_i2s_in_ch_disable(i2s, i);
459 } else {
460 reset_control_assert(rst);
461 reset_control_deassert(rst);
462 }
463
464 img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
465
466 for (i = 0; i < i2s->max_i2s_chan; i++)
467 img_i2s_in_ch_writel(i2s, i,
468 (4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
469 IMG_I2S_IN_CH_CTL_JUST_MASK |
470 IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
471
472 ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
473 &i2s->dai_driver, 1);
474 if (ret)
475 goto err_clk_disable;
476
477 ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
478 if (ret)
479 goto err_clk_disable;
480
481 return 0;
482
483err_clk_disable:
484 clk_disable_unprepare(i2s->clk_sys);
485
486 return ret;
487}
488
489static int img_i2s_in_dev_remove(struct platform_device *pdev)
490{
491 struct img_i2s_in *i2s = platform_get_drvdata(pdev);
492
493 clk_disable_unprepare(i2s->clk_sys);
494
495 return 0;
496}
497
498static const struct of_device_id img_i2s_in_of_match[] = {
499 { .compatible = "img,i2s-in" },
500 {}
501};
502MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
503
504static struct platform_driver img_i2s_in_driver = {
505 .driver = {
506 .name = "img-i2s-in",
507 .of_match_table = img_i2s_in_of_match
508 },
509 .probe = img_i2s_in_probe,
510 .remove = img_i2s_in_dev_remove
511};
512module_platform_driver(img_i2s_in_driver);
513
514MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
515MODULE_DESCRIPTION("IMG I2S Input Driver");
516MODULE_LICENSE("GPL v2");