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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/nvmem-consumer.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/io.h>
22#include <linux/thermal.h>
23#include <linux/reset.h>
24#include <linux/types.h>
25
26#include "thermal_hwmon.h"
27
28/* AUXADC Registers */
29#define AUXADC_CON1_SET_V 0x008
30#define AUXADC_CON1_CLR_V 0x00c
31#define AUXADC_CON2_V 0x010
32#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
33
34#define APMIXED_SYS_TS_CON1 0x604
35
36/* Thermal Controller Registers */
37#define TEMP_MONCTL0 0x000
38#define TEMP_MONCTL1 0x004
39#define TEMP_MONCTL2 0x008
40#define TEMP_MONIDET0 0x014
41#define TEMP_MONIDET1 0x018
42#define TEMP_MSRCTL0 0x038
43#define TEMP_MSRCTL1 0x03c
44#define TEMP_AHBPOLL 0x040
45#define TEMP_AHBTO 0x044
46#define TEMP_ADCPNP0 0x048
47#define TEMP_ADCPNP1 0x04c
48#define TEMP_ADCPNP2 0x050
49#define TEMP_ADCPNP3 0x0b4
50
51#define TEMP_ADCMUX 0x054
52#define TEMP_ADCEN 0x060
53#define TEMP_PNPMUXADDR 0x064
54#define TEMP_ADCMUXADDR 0x068
55#define TEMP_ADCENADDR 0x074
56#define TEMP_ADCVALIDADDR 0x078
57#define TEMP_ADCVOLTADDR 0x07c
58#define TEMP_RDCTRL 0x080
59#define TEMP_ADCVALIDMASK 0x084
60#define TEMP_ADCVOLTAGESHIFT 0x088
61#define TEMP_ADCWRITECTRL 0x08c
62#define TEMP_MSR0 0x090
63#define TEMP_MSR1 0x094
64#define TEMP_MSR2 0x098
65#define TEMP_MSR3 0x0B8
66
67#define TEMP_SPARE0 0x0f0
68
69#define TEMP_ADCPNP0_1 0x148
70#define TEMP_ADCPNP1_1 0x14c
71#define TEMP_ADCPNP2_1 0x150
72#define TEMP_MSR0_1 0x190
73#define TEMP_MSR1_1 0x194
74#define TEMP_MSR2_1 0x198
75#define TEMP_ADCPNP3_1 0x1b4
76#define TEMP_MSR3_1 0x1B8
77
78#define PTPCORESEL 0x400
79
80#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
81
82#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
83#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
84
85#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
86
87#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
88#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
89
90#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
91#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
92
93/* MT8173 thermal sensors */
94#define MT8173_TS1 0
95#define MT8173_TS2 1
96#define MT8173_TS3 2
97#define MT8173_TS4 3
98#define MT8173_TSABB 4
99
100/* AUXADC channel 11 is used for the temperature sensors */
101#define MT8173_TEMP_AUXADC_CHANNEL 11
102
103/* The total number of temperature sensors in the MT8173 */
104#define MT8173_NUM_SENSORS 5
105
106/* The number of banks in the MT8173 */
107#define MT8173_NUM_ZONES 4
108
109/* The number of sensing points per bank */
110#define MT8173_NUM_SENSORS_PER_ZONE 4
111
112/* The number of controller in the MT8173 */
113#define MT8173_NUM_CONTROLLER 1
114
115/* The calibration coefficient of sensor */
116#define MT8173_CALIBRATION 165
117
118/*
119 * Layout of the fuses providing the calibration data
120 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
121 * MT8183 has 6 sensors and needs 6 VTS calibration data.
122 * MT8173 has 5 sensors and needs 5 VTS calibration data.
123 * MT2701 has 3 sensors and needs 3 VTS calibration data.
124 * MT2712 has 4 sensors and needs 4 VTS calibration data.
125 */
126#define CALIB_BUF0_VALID_V1 BIT(0)
127#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
128#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
129#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
130#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
131#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
132#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
133#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
134#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
135#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
136#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
137#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
138
139/*
140 * Layout of the fuses providing the calibration data
141 * These macros could be used for MT7622.
142 */
143#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
144#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
145#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
146#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
147#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
148#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
149#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
150#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
151#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
152
153enum {
154 VTS1,
155 VTS2,
156 VTS3,
157 VTS4,
158 VTS5,
159 VTSABB,
160 MAX_NUM_VTS,
161};
162
163enum mtk_thermal_version {
164 MTK_THERMAL_V1 = 1,
165 MTK_THERMAL_V2,
166};
167
168/* MT2701 thermal sensors */
169#define MT2701_TS1 0
170#define MT2701_TS2 1
171#define MT2701_TSABB 2
172
173/* AUXADC channel 11 is used for the temperature sensors */
174#define MT2701_TEMP_AUXADC_CHANNEL 11
175
176/* The total number of temperature sensors in the MT2701 */
177#define MT2701_NUM_SENSORS 3
178
179/* The number of sensing points per bank */
180#define MT2701_NUM_SENSORS_PER_ZONE 3
181
182/* The number of controller in the MT2701 */
183#define MT2701_NUM_CONTROLLER 1
184
185/* The calibration coefficient of sensor */
186#define MT2701_CALIBRATION 165
187
188/* MT2712 thermal sensors */
189#define MT2712_TS1 0
190#define MT2712_TS2 1
191#define MT2712_TS3 2
192#define MT2712_TS4 3
193
194/* AUXADC channel 11 is used for the temperature sensors */
195#define MT2712_TEMP_AUXADC_CHANNEL 11
196
197/* The total number of temperature sensors in the MT2712 */
198#define MT2712_NUM_SENSORS 4
199
200/* The number of sensing points per bank */
201#define MT2712_NUM_SENSORS_PER_ZONE 4
202
203/* The number of controller in the MT2712 */
204#define MT2712_NUM_CONTROLLER 1
205
206/* The calibration coefficient of sensor */
207#define MT2712_CALIBRATION 165
208
209#define MT7622_TEMP_AUXADC_CHANNEL 11
210#define MT7622_NUM_SENSORS 1
211#define MT7622_NUM_ZONES 1
212#define MT7622_NUM_SENSORS_PER_ZONE 1
213#define MT7622_TS1 0
214#define MT7622_NUM_CONTROLLER 1
215
216/* The maximum number of banks */
217#define MAX_NUM_ZONES 8
218
219/* The calibration coefficient of sensor */
220#define MT7622_CALIBRATION 165
221
222/* MT8183 thermal sensors */
223#define MT8183_TS1 0
224#define MT8183_TS2 1
225#define MT8183_TS3 2
226#define MT8183_TS4 3
227#define MT8183_TS5 4
228#define MT8183_TSABB 5
229
230/* AUXADC channel is used for the temperature sensors */
231#define MT8183_TEMP_AUXADC_CHANNEL 11
232
233/* The total number of temperature sensors in the MT8183 */
234#define MT8183_NUM_SENSORS 6
235
236/* The number of banks in the MT8183 */
237#define MT8183_NUM_ZONES 1
238
239/* The number of sensing points per bank */
240#define MT8183_NUM_SENSORS_PER_ZONE 6
241
242/* The number of controller in the MT8183 */
243#define MT8183_NUM_CONTROLLER 2
244
245/* The calibration coefficient of sensor */
246#define MT8183_CALIBRATION 153
247
248struct mtk_thermal;
249
250struct thermal_bank_cfg {
251 unsigned int num_sensors;
252 const int *sensors;
253};
254
255struct mtk_thermal_bank {
256 struct mtk_thermal *mt;
257 int id;
258};
259
260struct mtk_thermal_data {
261 s32 num_banks;
262 s32 num_sensors;
263 s32 auxadc_channel;
264 const int *vts_index;
265 const int *sensor_mux_values;
266 const int *msr;
267 const int *adcpnp;
268 const int cali_val;
269 const int num_controller;
270 const int *controller_offset;
271 bool need_switch_bank;
272 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
273 enum mtk_thermal_version version;
274};
275
276struct mtk_thermal {
277 struct device *dev;
278 void __iomem *thermal_base;
279
280 struct clk *clk_peri_therm;
281 struct clk *clk_auxadc;
282 /* lock: for getting and putting banks */
283 struct mutex lock;
284
285 /* Calibration values */
286 s32 adc_ge;
287 s32 adc_oe;
288 s32 degc_cali;
289 s32 o_slope;
290 s32 o_slope_sign;
291 s32 vts[MAX_NUM_VTS];
292
293 const struct mtk_thermal_data *conf;
294 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
295};
296
297/* MT8183 thermal sensor data */
298static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
299 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
300};
301
302static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
303 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
304};
305
306static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
307 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
308 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
309};
310
311static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
312static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
313
314static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
315 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
316};
317
318/* MT8173 thermal sensor data */
319static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
320 { MT8173_TS2, MT8173_TS3 },
321 { MT8173_TS2, MT8173_TS4 },
322 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
323 { MT8173_TS2 },
324};
325
326static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
327 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
328};
329
330static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
331 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
332};
333
334static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
335static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
336
337static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
338 VTS1, VTS2, VTS3, VTS4, VTSABB
339};
340
341/* MT2701 thermal sensor data */
342static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
343 MT2701_TS1, MT2701_TS2, MT2701_TSABB
344};
345
346static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
347 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
348};
349
350static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
351 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
352};
353
354static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
355static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
356
357static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
358 VTS1, VTS2, VTS3
359};
360
361/* MT2712 thermal sensor data */
362static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
363 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
364};
365
366static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
367 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
368};
369
370static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
371 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
372};
373
374static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
375static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
376
377static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
378 VTS1, VTS2, VTS3, VTS4
379};
380
381/* MT7622 thermal sensor data */
382static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
383static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
384static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
385static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
386static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
387static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
388
389/*
390 * The MT8173 thermal controller has four banks. Each bank can read up to
391 * four temperature sensors simultaneously. The MT8173 has a total of 5
392 * temperature sensors. We use each bank to measure a certain area of the
393 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
394 * areas, hence is used in different banks.
395 *
396 * The thermal core only gets the maximum temperature of all banks, so
397 * the bank concept wouldn't be necessary here. However, the SVS (Smart
398 * Voltage Scaling) unit makes its decisions based on the same bank
399 * data, and this indeed needs the temperatures of the individual banks
400 * for making better decisions.
401 */
402static const struct mtk_thermal_data mt8173_thermal_data = {
403 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
404 .num_banks = MT8173_NUM_ZONES,
405 .num_sensors = MT8173_NUM_SENSORS,
406 .vts_index = mt8173_vts_index,
407 .cali_val = MT8173_CALIBRATION,
408 .num_controller = MT8173_NUM_CONTROLLER,
409 .controller_offset = mt8173_tc_offset,
410 .need_switch_bank = true,
411 .bank_data = {
412 {
413 .num_sensors = 2,
414 .sensors = mt8173_bank_data[0],
415 }, {
416 .num_sensors = 2,
417 .sensors = mt8173_bank_data[1],
418 }, {
419 .num_sensors = 3,
420 .sensors = mt8173_bank_data[2],
421 }, {
422 .num_sensors = 1,
423 .sensors = mt8173_bank_data[3],
424 },
425 },
426 .msr = mt8173_msr,
427 .adcpnp = mt8173_adcpnp,
428 .sensor_mux_values = mt8173_mux_values,
429 .version = MTK_THERMAL_V1,
430};
431
432/*
433 * The MT2701 thermal controller has one bank, which can read up to
434 * three temperature sensors simultaneously. The MT2701 has a total of 3
435 * temperature sensors.
436 *
437 * The thermal core only gets the maximum temperature of this one bank,
438 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
439 * Voltage Scaling) unit makes its decisions based on the same bank
440 * data.
441 */
442static const struct mtk_thermal_data mt2701_thermal_data = {
443 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
444 .num_banks = 1,
445 .num_sensors = MT2701_NUM_SENSORS,
446 .vts_index = mt2701_vts_index,
447 .cali_val = MT2701_CALIBRATION,
448 .num_controller = MT2701_NUM_CONTROLLER,
449 .controller_offset = mt2701_tc_offset,
450 .need_switch_bank = true,
451 .bank_data = {
452 {
453 .num_sensors = 3,
454 .sensors = mt2701_bank_data,
455 },
456 },
457 .msr = mt2701_msr,
458 .adcpnp = mt2701_adcpnp,
459 .sensor_mux_values = mt2701_mux_values,
460 .version = MTK_THERMAL_V1,
461};
462
463/*
464 * The MT2712 thermal controller has one bank, which can read up to
465 * four temperature sensors simultaneously. The MT2712 has a total of 4
466 * temperature sensors.
467 *
468 * The thermal core only gets the maximum temperature of this one bank,
469 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
470 * Voltage Scaling) unit makes its decisions based on the same bank
471 * data.
472 */
473static const struct mtk_thermal_data mt2712_thermal_data = {
474 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
475 .num_banks = 1,
476 .num_sensors = MT2712_NUM_SENSORS,
477 .vts_index = mt2712_vts_index,
478 .cali_val = MT2712_CALIBRATION,
479 .num_controller = MT2712_NUM_CONTROLLER,
480 .controller_offset = mt2712_tc_offset,
481 .need_switch_bank = true,
482 .bank_data = {
483 {
484 .num_sensors = 4,
485 .sensors = mt2712_bank_data,
486 },
487 },
488 .msr = mt2712_msr,
489 .adcpnp = mt2712_adcpnp,
490 .sensor_mux_values = mt2712_mux_values,
491 .version = MTK_THERMAL_V1,
492};
493
494/*
495 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
496 * access.
497 */
498static const struct mtk_thermal_data mt7622_thermal_data = {
499 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
500 .num_banks = MT7622_NUM_ZONES,
501 .num_sensors = MT7622_NUM_SENSORS,
502 .vts_index = mt7622_vts_index,
503 .cali_val = MT7622_CALIBRATION,
504 .num_controller = MT7622_NUM_CONTROLLER,
505 .controller_offset = mt7622_tc_offset,
506 .need_switch_bank = true,
507 .bank_data = {
508 {
509 .num_sensors = 1,
510 .sensors = mt7622_bank_data,
511 },
512 },
513 .msr = mt7622_msr,
514 .adcpnp = mt7622_adcpnp,
515 .sensor_mux_values = mt7622_mux_values,
516 .version = MTK_THERMAL_V2,
517};
518
519/*
520 * The MT8183 thermal controller has one bank for the current SW framework.
521 * The MT8183 has a total of 6 temperature sensors.
522 * There are two thermal controller to control the six sensor.
523 * The first one bind 2 sensor, and the other bind 4 sensors.
524 * The thermal core only gets the maximum temperature of all sensor, so
525 * the bank concept wouldn't be necessary here. However, the SVS (Smart
526 * Voltage Scaling) unit makes its decisions based on the same bank
527 * data, and this indeed needs the temperatures of the individual banks
528 * for making better decisions.
529 */
530static const struct mtk_thermal_data mt8183_thermal_data = {
531 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
532 .num_banks = MT8183_NUM_ZONES,
533 .num_sensors = MT8183_NUM_SENSORS,
534 .vts_index = mt8183_vts_index,
535 .cali_val = MT8183_CALIBRATION,
536 .num_controller = MT8183_NUM_CONTROLLER,
537 .controller_offset = mt8183_tc_offset,
538 .need_switch_bank = false,
539 .bank_data = {
540 {
541 .num_sensors = 6,
542 .sensors = mt8183_bank_data,
543 },
544 },
545
546 .msr = mt8183_msr,
547 .adcpnp = mt8183_adcpnp,
548 .sensor_mux_values = mt8183_mux_values,
549 .version = MTK_THERMAL_V1,
550};
551
552/**
553 * raw_to_mcelsius - convert a raw ADC value to mcelsius
554 * @mt: The thermal controller
555 * @sensno: sensor number
556 * @raw: raw ADC value
557 *
558 * This converts the raw ADC value to mcelsius using the SoC specific
559 * calibration constants
560 */
561static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
562{
563 s32 tmp;
564
565 raw &= 0xfff;
566
567 tmp = 203450520 << 3;
568 tmp /= mt->conf->cali_val + mt->o_slope;
569 tmp /= 10000 + mt->adc_ge;
570 tmp *= raw - mt->vts[sensno] - 3350;
571 tmp >>= 3;
572
573 return mt->degc_cali * 500 - tmp;
574}
575
576static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
577{
578 s32 format_1;
579 s32 format_2;
580 s32 g_oe;
581 s32 g_gain;
582 s32 g_x_roomt;
583 s32 tmp;
584
585 if (raw == 0)
586 return 0;
587
588 raw &= 0xfff;
589 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
590 g_oe = mt->adc_oe - 512;
591 format_1 = mt->vts[VTS2] + 3105 - g_oe;
592 format_2 = (mt->degc_cali * 10) >> 1;
593 g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
594
595 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
596 tmp = tmp * 10 * 100 / 11;
597
598 if (mt->o_slope_sign == 0)
599 tmp = tmp / (165 - mt->o_slope);
600 else
601 tmp = tmp / (165 + mt->o_slope);
602
603 return (format_2 - tmp) * 100;
604}
605
606/**
607 * mtk_thermal_get_bank - get bank
608 * @bank: The bank
609 *
610 * The bank registers are banked, we have to select a bank in the
611 * PTPCORESEL register to access it.
612 */
613static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
614{
615 struct mtk_thermal *mt = bank->mt;
616 u32 val;
617
618 if (mt->conf->need_switch_bank) {
619 mutex_lock(&mt->lock);
620
621 val = readl(mt->thermal_base + PTPCORESEL);
622 val &= ~0xf;
623 val |= bank->id;
624 writel(val, mt->thermal_base + PTPCORESEL);
625 }
626}
627
628/**
629 * mtk_thermal_put_bank - release bank
630 * @bank: The bank
631 *
632 * release a bank previously taken with mtk_thermal_get_bank,
633 */
634static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
635{
636 struct mtk_thermal *mt = bank->mt;
637
638 if (mt->conf->need_switch_bank)
639 mutex_unlock(&mt->lock);
640}
641
642/**
643 * mtk_thermal_bank_temperature - get the temperature of a bank
644 * @bank: The bank
645 *
646 * The temperature of a bank is considered the maximum temperature of
647 * the sensors associated to the bank.
648 */
649static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
650{
651 struct mtk_thermal *mt = bank->mt;
652 const struct mtk_thermal_data *conf = mt->conf;
653 int i, temp = INT_MIN, max = INT_MIN;
654 u32 raw;
655
656 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
657 raw = readl(mt->thermal_base + conf->msr[i]);
658
659 if (mt->conf->version == MTK_THERMAL_V1) {
660 temp = raw_to_mcelsius_v1(
661 mt, conf->bank_data[bank->id].sensors[i], raw);
662 } else {
663 temp = raw_to_mcelsius_v2(
664 mt, conf->bank_data[bank->id].sensors[i], raw);
665 }
666
667 /*
668 * The first read of a sensor often contains very high bogus
669 * temperature value. Filter these out so that the system does
670 * not immediately shut down.
671 */
672 if (temp > 200000)
673 temp = 0;
674
675 if (temp > max)
676 max = temp;
677 }
678
679 return max;
680}
681
682static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
683{
684 struct mtk_thermal *mt = tz->devdata;
685 int i;
686 int tempmax = INT_MIN;
687
688 for (i = 0; i < mt->conf->num_banks; i++) {
689 struct mtk_thermal_bank *bank = &mt->banks[i];
690
691 mtk_thermal_get_bank(bank);
692
693 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
694
695 mtk_thermal_put_bank(bank);
696 }
697
698 *temperature = tempmax;
699
700 return 0;
701}
702
703static const struct thermal_zone_device_ops mtk_thermal_ops = {
704 .get_temp = mtk_read_temp,
705};
706
707static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
708 u32 apmixed_phys_base, u32 auxadc_phys_base,
709 int ctrl_id)
710{
711 struct mtk_thermal_bank *bank = &mt->banks[num];
712 const struct mtk_thermal_data *conf = mt->conf;
713 int i;
714
715 int offset = mt->conf->controller_offset[ctrl_id];
716 void __iomem *controller_base = mt->thermal_base + offset;
717
718 bank->id = num;
719 bank->mt = mt;
720
721 mtk_thermal_get_bank(bank);
722
723 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
724 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
725
726 /*
727 * filt interval is 1 * 46.540us = 46.54us,
728 * sen interval is 429 * 46.540us = 19.96ms
729 */
730 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
731 TEMP_MONCTL2_SENSOR_INTERVAL(429),
732 controller_base + TEMP_MONCTL2);
733
734 /* poll is set to 10u */
735 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
736 controller_base + TEMP_AHBPOLL);
737
738 /* temperature sampling control, 1 sample */
739 writel(0x0, controller_base + TEMP_MSRCTL0);
740
741 /* exceed this polling time, IRQ would be inserted */
742 writel(0xffffffff, controller_base + TEMP_AHBTO);
743
744 /* number of interrupts per event, 1 is enough */
745 writel(0x0, controller_base + TEMP_MONIDET0);
746 writel(0x0, controller_base + TEMP_MONIDET1);
747
748 /*
749 * The MT8173 thermal controller does not have its own ADC. Instead it
750 * uses AHB bus accesses to control the AUXADC. To do this the thermal
751 * controller has to be programmed with the physical addresses of the
752 * AUXADC registers and with the various bit positions in the AUXADC.
753 * Also the thermal controller controls a mux in the APMIXEDSYS register
754 * space.
755 */
756
757 /*
758 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
759 * automatically by hw
760 */
761 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
762
763 /* AHB address for auxadc mux selection */
764 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
765 controller_base + TEMP_ADCMUXADDR);
766
767 if (mt->conf->version == MTK_THERMAL_V1) {
768 /* AHB address for pnp sensor mux selection */
769 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
770 controller_base + TEMP_PNPMUXADDR);
771 }
772
773 /* AHB value for auxadc enable */
774 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
775
776 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
777 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
778 controller_base + TEMP_ADCENADDR);
779
780 /* AHB address for auxadc valid bit */
781 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
782 controller_base + TEMP_ADCVALIDADDR);
783
784 /* AHB address for auxadc voltage output */
785 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
786 controller_base + TEMP_ADCVOLTADDR);
787
788 /* read valid & voltage are at the same register */
789 writel(0x0, controller_base + TEMP_RDCTRL);
790
791 /* indicate where the valid bit is */
792 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
793 controller_base + TEMP_ADCVALIDMASK);
794
795 /* no shift */
796 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
797
798 /* enable auxadc mux write transaction */
799 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
800 controller_base + TEMP_ADCWRITECTRL);
801
802 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
803 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
804 mt->thermal_base + conf->adcpnp[i]);
805
806 writel((1 << conf->bank_data[num].num_sensors) - 1,
807 controller_base + TEMP_MONCTL0);
808
809 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
810 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
811 controller_base + TEMP_ADCWRITECTRL);
812
813 mtk_thermal_put_bank(bank);
814}
815
816static u64 of_get_phys_base(struct device_node *np)
817{
818 u64 size64;
819 const __be32 *regaddr_p;
820
821 regaddr_p = of_get_address(np, 0, &size64, NULL);
822 if (!regaddr_p)
823 return OF_BAD_ADDR;
824
825 return of_translate_address(np, regaddr_p);
826}
827
828static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
829{
830 int i;
831
832 if (!(buf[0] & CALIB_BUF0_VALID_V1))
833 return -EINVAL;
834
835 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
836
837 for (i = 0; i < mt->conf->num_sensors; i++) {
838 switch (mt->conf->vts_index[i]) {
839 case VTS1:
840 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
841 break;
842 case VTS2:
843 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
844 break;
845 case VTS3:
846 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
847 break;
848 case VTS4:
849 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
850 break;
851 case VTS5:
852 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
853 break;
854 case VTSABB:
855 mt->vts[VTSABB] =
856 CALIB_BUF2_VTS_TSABB_V1(buf[2]);
857 break;
858 default:
859 break;
860 }
861 }
862
863 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
864 if (CALIB_BUF1_ID_V1(buf[1]) &
865 CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
866 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
867 else
868 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
869
870 return 0;
871}
872
873static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
874{
875 if (!CALIB_BUF1_VALID_V2(buf[1]))
876 return -EINVAL;
877
878 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
879 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
880 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
881 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
882 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
883 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
884 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
885 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
886
887 return 0;
888}
889
890static int mtk_thermal_get_calibration_data(struct device *dev,
891 struct mtk_thermal *mt)
892{
893 struct nvmem_cell *cell;
894 u32 *buf;
895 size_t len;
896 int i, ret = 0;
897
898 /* Start with default values */
899 mt->adc_ge = 512;
900 for (i = 0; i < mt->conf->num_sensors; i++)
901 mt->vts[i] = 260;
902 mt->degc_cali = 40;
903 mt->o_slope = 0;
904
905 cell = nvmem_cell_get(dev, "calibration-data");
906 if (IS_ERR(cell)) {
907 if (PTR_ERR(cell) == -EPROBE_DEFER)
908 return PTR_ERR(cell);
909 return 0;
910 }
911
912 buf = (u32 *)nvmem_cell_read(cell, &len);
913
914 nvmem_cell_put(cell);
915
916 if (IS_ERR(buf))
917 return PTR_ERR(buf);
918
919 if (len < 3 * sizeof(u32)) {
920 dev_warn(dev, "invalid calibration data\n");
921 ret = -EINVAL;
922 goto out;
923 }
924
925 if (mt->conf->version == MTK_THERMAL_V1)
926 ret = mtk_thermal_extract_efuse_v1(mt, buf);
927 else
928 ret = mtk_thermal_extract_efuse_v2(mt, buf);
929
930 if (ret) {
931 dev_info(dev, "Device not calibrated, using default calibration values\n");
932 ret = 0;
933 }
934
935out:
936 kfree(buf);
937
938 return ret;
939}
940
941static const struct of_device_id mtk_thermal_of_match[] = {
942 {
943 .compatible = "mediatek,mt8173-thermal",
944 .data = (void *)&mt8173_thermal_data,
945 },
946 {
947 .compatible = "mediatek,mt2701-thermal",
948 .data = (void *)&mt2701_thermal_data,
949 },
950 {
951 .compatible = "mediatek,mt2712-thermal",
952 .data = (void *)&mt2712_thermal_data,
953 },
954 {
955 .compatible = "mediatek,mt7622-thermal",
956 .data = (void *)&mt7622_thermal_data,
957 },
958 {
959 .compatible = "mediatek,mt8183-thermal",
960 .data = (void *)&mt8183_thermal_data,
961 }, {
962 },
963};
964MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
965
966static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
967{
968 int tmp;
969
970 tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
971 tmp &= ~(0x37);
972 tmp |= 0x1;
973 writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
974 udelay(200);
975}
976
977static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
978 void __iomem *auxadc_base)
979{
980 int tmp;
981
982 writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
983 writel(0x1, mt->thermal_base + TEMP_MONCTL0);
984 tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
985 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
986}
987
988static int mtk_thermal_probe(struct platform_device *pdev)
989{
990 int ret, i, ctrl_id;
991 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
992 struct mtk_thermal *mt;
993 struct resource *res;
994 u64 auxadc_phys_base, apmixed_phys_base;
995 struct thermal_zone_device *tzdev;
996 void __iomem *apmixed_base, *auxadc_base;
997
998 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
999 if (!mt)
1000 return -ENOMEM;
1001
1002 mt->conf = of_device_get_match_data(&pdev->dev);
1003
1004 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
1005 if (IS_ERR(mt->clk_peri_therm))
1006 return PTR_ERR(mt->clk_peri_therm);
1007
1008 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
1009 if (IS_ERR(mt->clk_auxadc))
1010 return PTR_ERR(mt->clk_auxadc);
1011
1012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1013 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
1014 if (IS_ERR(mt->thermal_base))
1015 return PTR_ERR(mt->thermal_base);
1016
1017 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1018 if (ret)
1019 return ret;
1020
1021 mutex_init(&mt->lock);
1022
1023 mt->dev = &pdev->dev;
1024
1025 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1026 if (!auxadc) {
1027 dev_err(&pdev->dev, "missing auxadc node\n");
1028 return -ENODEV;
1029 }
1030
1031 auxadc_base = of_iomap(auxadc, 0);
1032 auxadc_phys_base = of_get_phys_base(auxadc);
1033
1034 of_node_put(auxadc);
1035
1036 if (auxadc_phys_base == OF_BAD_ADDR) {
1037 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1038 return -EINVAL;
1039 }
1040
1041 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1042 if (!apmixedsys) {
1043 dev_err(&pdev->dev, "missing apmixedsys node\n");
1044 return -ENODEV;
1045 }
1046
1047 apmixed_base = of_iomap(apmixedsys, 0);
1048 apmixed_phys_base = of_get_phys_base(apmixedsys);
1049
1050 of_node_put(apmixedsys);
1051
1052 if (apmixed_phys_base == OF_BAD_ADDR) {
1053 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1054 return -EINVAL;
1055 }
1056
1057 ret = device_reset_optional(&pdev->dev);
1058 if (ret)
1059 return ret;
1060
1061 ret = clk_prepare_enable(mt->clk_auxadc);
1062 if (ret) {
1063 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1064 return ret;
1065 }
1066
1067 ret = clk_prepare_enable(mt->clk_peri_therm);
1068 if (ret) {
1069 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1070 goto err_disable_clk_auxadc;
1071 }
1072
1073 if (mt->conf->version == MTK_THERMAL_V2) {
1074 mtk_thermal_turn_on_buffer(apmixed_base);
1075 mtk_thermal_release_periodic_ts(mt, auxadc_base);
1076 }
1077
1078 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1079 for (i = 0; i < mt->conf->num_banks; i++)
1080 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1081 auxadc_phys_base, ctrl_id);
1082
1083 platform_set_drvdata(pdev, mt);
1084
1085 tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
1086 &mtk_thermal_ops);
1087 if (IS_ERR(tzdev)) {
1088 ret = PTR_ERR(tzdev);
1089 goto err_disable_clk_peri_therm;
1090 }
1091
1092 ret = devm_thermal_add_hwmon_sysfs(tzdev);
1093 if (ret)
1094 dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
1095
1096 return 0;
1097
1098err_disable_clk_peri_therm:
1099 clk_disable_unprepare(mt->clk_peri_therm);
1100err_disable_clk_auxadc:
1101 clk_disable_unprepare(mt->clk_auxadc);
1102
1103 return ret;
1104}
1105
1106static int mtk_thermal_remove(struct platform_device *pdev)
1107{
1108 struct mtk_thermal *mt = platform_get_drvdata(pdev);
1109
1110 clk_disable_unprepare(mt->clk_peri_therm);
1111 clk_disable_unprepare(mt->clk_auxadc);
1112
1113 return 0;
1114}
1115
1116static struct platform_driver mtk_thermal_driver = {
1117 .probe = mtk_thermal_probe,
1118 .remove = mtk_thermal_remove,
1119 .driver = {
1120 .name = "mtk-thermal",
1121 .of_match_table = mtk_thermal_of_match,
1122 },
1123};
1124
1125module_platform_driver(mtk_thermal_driver);
1126
1127MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1128MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1129MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1130MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1131MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1132MODULE_DESCRIPTION("Mediatek thermal driver");
1133MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
4 * Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/nvmem-consumer.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/io.h>
27#include <linux/thermal.h>
28#include <linux/reset.h>
29#include <linux/types.h>
30
31/* AUXADC Registers */
32#define AUXADC_CON0_V 0x000
33#define AUXADC_CON1_V 0x004
34#define AUXADC_CON1_SET_V 0x008
35#define AUXADC_CON1_CLR_V 0x00c
36#define AUXADC_CON2_V 0x010
37#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
38#define AUXADC_MISC_V 0x094
39
40#define AUXADC_CON1_CHANNEL(x) BIT(x)
41
42#define APMIXED_SYS_TS_CON1 0x604
43
44/* Thermal Controller Registers */
45#define TEMP_MONCTL0 0x000
46#define TEMP_MONCTL1 0x004
47#define TEMP_MONCTL2 0x008
48#define TEMP_MONIDET0 0x014
49#define TEMP_MONIDET1 0x018
50#define TEMP_MSRCTL0 0x038
51#define TEMP_AHBPOLL 0x040
52#define TEMP_AHBTO 0x044
53#define TEMP_ADCPNP0 0x048
54#define TEMP_ADCPNP1 0x04c
55#define TEMP_ADCPNP2 0x050
56#define TEMP_ADCPNP3 0x0b4
57
58#define TEMP_ADCMUX 0x054
59#define TEMP_ADCEN 0x060
60#define TEMP_PNPMUXADDR 0x064
61#define TEMP_ADCMUXADDR 0x068
62#define TEMP_ADCENADDR 0x074
63#define TEMP_ADCVALIDADDR 0x078
64#define TEMP_ADCVOLTADDR 0x07c
65#define TEMP_RDCTRL 0x080
66#define TEMP_ADCVALIDMASK 0x084
67#define TEMP_ADCVOLTAGESHIFT 0x088
68#define TEMP_ADCWRITECTRL 0x08c
69#define TEMP_MSR0 0x090
70#define TEMP_MSR1 0x094
71#define TEMP_MSR2 0x098
72#define TEMP_MSR3 0x0B8
73
74#define TEMP_SPARE0 0x0f0
75
76#define PTPCORESEL 0x400
77
78#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
79
80#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
81#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
82
83#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
84
85#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
86#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
87
88#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
89#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
90
91#define MT8173_TS1 0
92#define MT8173_TS2 1
93#define MT8173_TS3 2
94#define MT8173_TS4 3
95#define MT8173_TSABB 4
96
97/* AUXADC channel 11 is used for the temperature sensors */
98#define MT8173_TEMP_AUXADC_CHANNEL 11
99
100/* The total number of temperature sensors in the MT8173 */
101#define MT8173_NUM_SENSORS 5
102
103/* The number of banks in the MT8173 */
104#define MT8173_NUM_ZONES 4
105
106/* The number of sensing points per bank */
107#define MT8173_NUM_SENSORS_PER_ZONE 4
108
109/* Layout of the fuses providing the calibration data */
110#define MT8173_CALIB_BUF0_VALID BIT(0)
111#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
112#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
113#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
114#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
115#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
116#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
117#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
118#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
119
120#define THERMAL_NAME "mtk-thermal"
121
122struct mtk_thermal;
123
124struct mtk_thermal_bank {
125 struct mtk_thermal *mt;
126 int id;
127};
128
129struct mtk_thermal {
130 struct device *dev;
131 void __iomem *thermal_base;
132
133 struct clk *clk_peri_therm;
134 struct clk *clk_auxadc;
135
136 struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
137
138 /* lock: for getting and putting banks */
139 struct mutex lock;
140
141 /* Calibration values */
142 s32 adc_ge;
143 s32 degc_cali;
144 s32 o_slope;
145 s32 vts[MT8173_NUM_SENSORS];
146
147 struct thermal_zone_device *tzd;
148};
149
150struct mtk_thermal_bank_cfg {
151 unsigned int num_sensors;
152 unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
153};
154
155static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
156
157/*
158 * The MT8173 thermal controller has four banks. Each bank can read up to
159 * four temperature sensors simultaneously. The MT8173 has a total of 5
160 * temperature sensors. We use each bank to measure a certain area of the
161 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
162 * areas, hence is used in different banks.
163 *
164 * The thermal core only gets the maximum temperature of all banks, so
165 * the bank concept wouldn't be necessary here. However, the SVS (Smart
166 * Voltage Scaling) unit makes its decisions based on the same bank
167 * data, and this indeed needs the temperatures of the individual banks
168 * for making better decisions.
169 */
170static const struct mtk_thermal_bank_cfg bank_data[] = {
171 {
172 .num_sensors = 2,
173 .sensors = { MT8173_TS2, MT8173_TS3 },
174 }, {
175 .num_sensors = 2,
176 .sensors = { MT8173_TS2, MT8173_TS4 },
177 }, {
178 .num_sensors = 3,
179 .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
180 }, {
181 .num_sensors = 1,
182 .sensors = { MT8173_TS2 },
183 },
184};
185
186struct mtk_thermal_sense_point {
187 int msr;
188 int adcpnp;
189};
190
191static const struct mtk_thermal_sense_point
192 sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
193 {
194 .msr = TEMP_MSR0,
195 .adcpnp = TEMP_ADCPNP0,
196 }, {
197 .msr = TEMP_MSR1,
198 .adcpnp = TEMP_ADCPNP1,
199 }, {
200 .msr = TEMP_MSR2,
201 .adcpnp = TEMP_ADCPNP2,
202 }, {
203 .msr = TEMP_MSR3,
204 .adcpnp = TEMP_ADCPNP3,
205 },
206};
207
208/**
209 * raw_to_mcelsius - convert a raw ADC value to mcelsius
210 * @mt: The thermal controller
211 * @raw: raw ADC value
212 *
213 * This converts the raw ADC value to mcelsius using the SoC specific
214 * calibration constants
215 */
216static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
217{
218 s32 tmp;
219
220 raw &= 0xfff;
221
222 tmp = 203450520 << 3;
223 tmp /= 165 + mt->o_slope;
224 tmp /= 10000 + mt->adc_ge;
225 tmp *= raw - mt->vts[sensno] - 3350;
226 tmp >>= 3;
227
228 return mt->degc_cali * 500 - tmp;
229}
230
231/**
232 * mtk_thermal_get_bank - get bank
233 * @bank: The bank
234 *
235 * The bank registers are banked, we have to select a bank in the
236 * PTPCORESEL register to access it.
237 */
238static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
239{
240 struct mtk_thermal *mt = bank->mt;
241 u32 val;
242
243 mutex_lock(&mt->lock);
244
245 val = readl(mt->thermal_base + PTPCORESEL);
246 val &= ~0xf;
247 val |= bank->id;
248 writel(val, mt->thermal_base + PTPCORESEL);
249}
250
251/**
252 * mtk_thermal_put_bank - release bank
253 * @bank: The bank
254 *
255 * release a bank previously taken with mtk_thermal_get_bank,
256 */
257static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
258{
259 struct mtk_thermal *mt = bank->mt;
260
261 mutex_unlock(&mt->lock);
262}
263
264/**
265 * mtk_thermal_bank_temperature - get the temperature of a bank
266 * @bank: The bank
267 *
268 * The temperature of a bank is considered the maximum temperature of
269 * the sensors associated to the bank.
270 */
271static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
272{
273 struct mtk_thermal *mt = bank->mt;
274 int i, temp = INT_MIN, max = INT_MIN;
275 u32 raw;
276
277 for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
278 raw = readl(mt->thermal_base + sensing_points[i].msr);
279
280 temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);
281
282 /*
283 * The first read of a sensor often contains very high bogus
284 * temperature value. Filter these out so that the system does
285 * not immediately shut down.
286 */
287 if (temp > 200000)
288 temp = 0;
289
290 if (temp > max)
291 max = temp;
292 }
293
294 return max;
295}
296
297static int mtk_read_temp(void *data, int *temperature)
298{
299 struct mtk_thermal *mt = data;
300 int i;
301 int tempmax = INT_MIN;
302
303 for (i = 0; i < MT8173_NUM_ZONES; i++) {
304 struct mtk_thermal_bank *bank = &mt->banks[i];
305
306 mtk_thermal_get_bank(bank);
307
308 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
309
310 mtk_thermal_put_bank(bank);
311 }
312
313 *temperature = tempmax;
314
315 return 0;
316}
317
318static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
319 .get_temp = mtk_read_temp,
320};
321
322static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
323 u32 apmixed_phys_base, u32 auxadc_phys_base)
324{
325 struct mtk_thermal_bank *bank = &mt->banks[num];
326 const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
327 int i;
328
329 bank->id = num;
330 bank->mt = mt;
331
332 mtk_thermal_get_bank(bank);
333
334 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
335 writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
336
337 /*
338 * filt interval is 1 * 46.540us = 46.54us,
339 * sen interval is 429 * 46.540us = 19.96ms
340 */
341 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
342 TEMP_MONCTL2_SENSOR_INTERVAL(429),
343 mt->thermal_base + TEMP_MONCTL2);
344
345 /* poll is set to 10u */
346 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
347 mt->thermal_base + TEMP_AHBPOLL);
348
349 /* temperature sampling control, 1 sample */
350 writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
351
352 /* exceed this polling time, IRQ would be inserted */
353 writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
354
355 /* number of interrupts per event, 1 is enough */
356 writel(0x0, mt->thermal_base + TEMP_MONIDET0);
357 writel(0x0, mt->thermal_base + TEMP_MONIDET1);
358
359 /*
360 * The MT8173 thermal controller does not have its own ADC. Instead it
361 * uses AHB bus accesses to control the AUXADC. To do this the thermal
362 * controller has to be programmed with the physical addresses of the
363 * AUXADC registers and with the various bit positions in the AUXADC.
364 * Also the thermal controller controls a mux in the APMIXEDSYS register
365 * space.
366 */
367
368 /*
369 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
370 * automatically by hw
371 */
372 writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);
373
374 /* AHB address for auxadc mux selection */
375 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
376 mt->thermal_base + TEMP_ADCMUXADDR);
377
378 /* AHB address for pnp sensor mux selection */
379 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
380 mt->thermal_base + TEMP_PNPMUXADDR);
381
382 /* AHB value for auxadc enable */
383 writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
384
385 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
386 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
387 mt->thermal_base + TEMP_ADCENADDR);
388
389 /* AHB address for auxadc valid bit */
390 writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
391 mt->thermal_base + TEMP_ADCVALIDADDR);
392
393 /* AHB address for auxadc voltage output */
394 writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
395 mt->thermal_base + TEMP_ADCVOLTADDR);
396
397 /* read valid & voltage are at the same register */
398 writel(0x0, mt->thermal_base + TEMP_RDCTRL);
399
400 /* indicate where the valid bit is */
401 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
402 mt->thermal_base + TEMP_ADCVALIDMASK);
403
404 /* no shift */
405 writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
406
407 /* enable auxadc mux write transaction */
408 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
409 mt->thermal_base + TEMP_ADCWRITECTRL);
410
411 for (i = 0; i < cfg->num_sensors; i++)
412 writel(sensor_mux_values[cfg->sensors[i]],
413 mt->thermal_base + sensing_points[i].adcpnp);
414
415 writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
416
417 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
418 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
419 mt->thermal_base + TEMP_ADCWRITECTRL);
420
421 mtk_thermal_put_bank(bank);
422}
423
424static u64 of_get_phys_base(struct device_node *np)
425{
426 u64 size64;
427 const __be32 *regaddr_p;
428
429 regaddr_p = of_get_address(np, 0, &size64, NULL);
430 if (!regaddr_p)
431 return OF_BAD_ADDR;
432
433 return of_translate_address(np, regaddr_p);
434}
435
436static int mtk_thermal_get_calibration_data(struct device *dev,
437 struct mtk_thermal *mt)
438{
439 struct nvmem_cell *cell;
440 u32 *buf;
441 size_t len;
442 int i, ret = 0;
443
444 /* Start with default values */
445 mt->adc_ge = 512;
446 for (i = 0; i < MT8173_NUM_SENSORS; i++)
447 mt->vts[i] = 260;
448 mt->degc_cali = 40;
449 mt->o_slope = 0;
450
451 cell = nvmem_cell_get(dev, "calibration-data");
452 if (IS_ERR(cell)) {
453 if (PTR_ERR(cell) == -EPROBE_DEFER)
454 return PTR_ERR(cell);
455 return 0;
456 }
457
458 buf = (u32 *)nvmem_cell_read(cell, &len);
459
460 nvmem_cell_put(cell);
461
462 if (IS_ERR(buf))
463 return PTR_ERR(buf);
464
465 if (len < 3 * sizeof(u32)) {
466 dev_warn(dev, "invalid calibration data\n");
467 ret = -EINVAL;
468 goto out;
469 }
470
471 if (buf[0] & MT8173_CALIB_BUF0_VALID) {
472 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
473 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
474 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
475 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
476 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
477 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
478 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
479 mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
480 } else {
481 dev_info(dev, "Device not calibrated, using default calibration values\n");
482 }
483
484out:
485 kfree(buf);
486
487 return ret;
488}
489
490static int mtk_thermal_probe(struct platform_device *pdev)
491{
492 int ret, i;
493 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
494 struct mtk_thermal *mt;
495 struct resource *res;
496 u64 auxadc_phys_base, apmixed_phys_base;
497
498 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
499 if (!mt)
500 return -ENOMEM;
501
502 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
503 if (IS_ERR(mt->clk_peri_therm))
504 return PTR_ERR(mt->clk_peri_therm);
505
506 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
507 if (IS_ERR(mt->clk_auxadc))
508 return PTR_ERR(mt->clk_auxadc);
509
510 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
511 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
512 if (IS_ERR(mt->thermal_base))
513 return PTR_ERR(mt->thermal_base);
514
515 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
516 if (ret)
517 return ret;
518
519 mutex_init(&mt->lock);
520
521 mt->dev = &pdev->dev;
522
523 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
524 if (!auxadc) {
525 dev_err(&pdev->dev, "missing auxadc node\n");
526 return -ENODEV;
527 }
528
529 auxadc_phys_base = of_get_phys_base(auxadc);
530
531 of_node_put(auxadc);
532
533 if (auxadc_phys_base == OF_BAD_ADDR) {
534 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
535 return -EINVAL;
536 }
537
538 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
539 if (!apmixedsys) {
540 dev_err(&pdev->dev, "missing apmixedsys node\n");
541 return -ENODEV;
542 }
543
544 apmixed_phys_base = of_get_phys_base(apmixedsys);
545
546 of_node_put(apmixedsys);
547
548 if (apmixed_phys_base == OF_BAD_ADDR) {
549 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
550 return -EINVAL;
551 }
552
553 ret = clk_prepare_enable(mt->clk_auxadc);
554 if (ret) {
555 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
556 return ret;
557 }
558
559 ret = device_reset(&pdev->dev);
560 if (ret)
561 goto err_disable_clk_auxadc;
562
563 ret = clk_prepare_enable(mt->clk_peri_therm);
564 if (ret) {
565 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
566 goto err_disable_clk_auxadc;
567 }
568
569 for (i = 0; i < MT8173_NUM_ZONES; i++)
570 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
571 auxadc_phys_base);
572
573 platform_set_drvdata(pdev, mt);
574
575 mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
576 &mtk_thermal_ops);
577 if (IS_ERR(mt->tzd))
578 goto err_register;
579
580 return 0;
581
582err_register:
583 clk_disable_unprepare(mt->clk_peri_therm);
584
585err_disable_clk_auxadc:
586 clk_disable_unprepare(mt->clk_auxadc);
587
588 return ret;
589}
590
591static int mtk_thermal_remove(struct platform_device *pdev)
592{
593 struct mtk_thermal *mt = platform_get_drvdata(pdev);
594
595 thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd);
596
597 clk_disable_unprepare(mt->clk_peri_therm);
598 clk_disable_unprepare(mt->clk_auxadc);
599
600 return 0;
601}
602
603static const struct of_device_id mtk_thermal_of_match[] = {
604 {
605 .compatible = "mediatek,mt8173-thermal",
606 }, {
607 },
608};
609
610static struct platform_driver mtk_thermal_driver = {
611 .probe = mtk_thermal_probe,
612 .remove = mtk_thermal_remove,
613 .driver = {
614 .name = THERMAL_NAME,
615 .of_match_table = mtk_thermal_of_match,
616 },
617};
618
619module_platform_driver(mtk_thermal_driver);
620
621MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
622MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
623MODULE_DESCRIPTION("Mediatek thermal driver");
624MODULE_LICENSE("GPL v2");