1/*
  2 * Copyright (C) 2014 Marvell Technology Group Ltd.
  3 *
  4 * Antoine Tenart <antoine.tenart@free-electrons.com>
  5 * Jisheng Zhang <jszhang@marvell.com>
  6 *
  7 * This file is licensed under the terms of the GNU General Public
  8 * License version 2. This program is licensed "as is" without any
  9 * warranty of any kind, whether express or implied.
 10 */
 11
 12#include <linux/io.h>
 13#include <linux/module.h>
 14#include <linux/of_device.h>
 15#include <linux/phy/phy.h>
 16#include <linux/platform_device.h>
 17#include <linux/reset.h>
 18
 19#define USB_PHY_PLL		0x04
 20#define USB_PHY_PLL_CONTROL	0x08
 21#define USB_PHY_TX_CTRL0	0x10
 22#define USB_PHY_TX_CTRL1	0x14
 23#define USB_PHY_TX_CTRL2	0x18
 24#define USB_PHY_RX_CTRL		0x20
 25#define USB_PHY_ANALOG		0x34
 26
 27/* USB_PHY_PLL */
 28#define CLK_REF_DIV(x)		((x) << 4)
 29#define FEEDBACK_CLK_DIV(x)	((x) << 8)
 30
 31/* USB_PHY_PLL_CONTROL */
 32#define CLK_STABLE		BIT(0)
 33#define PLL_CTRL_PIN		BIT(1)
 34#define PLL_CTRL_REG		BIT(2)
 35#define PLL_ON			BIT(3)
 36#define PHASE_OFF_TOL_125	(0x0 << 5)
 37#define PHASE_OFF_TOL_250	BIT(5)
 38#define KVC0_CALIB		(0x0 << 9)
 39#define KVC0_REG_CTRL		BIT(9)
 40#define KVC0_HIGH		(0x0 << 10)
 41#define KVC0_LOW		(0x3 << 10)
 42#define CLK_BLK_EN		BIT(13)
 43
 44/* USB_PHY_TX_CTRL0 */
 45#define EXT_HS_RCAL_EN		BIT(3)
 46#define EXT_FS_RCAL_EN		BIT(4)
 47#define IMPCAL_VTH_DIV(x)	((x) << 5)
 48#define EXT_RS_RCAL_DIV(x)	((x) << 8)
 49#define EXT_FS_RCAL_DIV(x)	((x) << 12)
 50
 51/* USB_PHY_TX_CTRL1 */
 52#define TX_VDD15_14		(0x0 << 4)
 53#define TX_VDD15_15		BIT(4)
 54#define TX_VDD15_16		(0x2 << 4)
 55#define TX_VDD15_17		(0x3 << 4)
 56#define TX_VDD12_VDD		(0x0 << 6)
 57#define TX_VDD12_11		BIT(6)
 58#define TX_VDD12_12		(0x2 << 6)
 59#define TX_VDD12_13		(0x3 << 6)
 60#define LOW_VDD_EN		BIT(8)
 61#define TX_OUT_AMP(x)		((x) << 9)
 62
 63/* USB_PHY_TX_CTRL2 */
 64#define TX_CHAN_CTRL_REG(x)	((x) << 0)
 65#define DRV_SLEWRATE(x)		((x) << 4)
 66#define IMP_CAL_FS_HS_DLY_0	(0x0 << 6)
 67#define IMP_CAL_FS_HS_DLY_1	BIT(6)
 68#define IMP_CAL_FS_HS_DLY_2	(0x2 << 6)
 69#define IMP_CAL_FS_HS_DLY_3	(0x3 << 6)
 70#define FS_DRV_EN_MASK(x)	((x) << 8)
 71#define HS_DRV_EN_MASK(x)	((x) << 12)
 72
 73/* USB_PHY_RX_CTRL */
 74#define PHASE_FREEZE_DLY_2_CL	(0x0 << 0)
 75#define PHASE_FREEZE_DLY_4_CL	BIT(0)
 76#define ACK_LENGTH_8_CL		(0x0 << 2)
 77#define ACK_LENGTH_12_CL	BIT(2)
 78#define ACK_LENGTH_16_CL	(0x2 << 2)
 79#define ACK_LENGTH_20_CL	(0x3 << 2)
 80#define SQ_LENGTH_3		(0x0 << 4)
 81#define SQ_LENGTH_6		BIT(4)
 82#define SQ_LENGTH_9		(0x2 << 4)
 83#define SQ_LENGTH_12		(0x3 << 4)
 84#define DISCON_THRESHOLD_260	(0x0 << 6)
 85#define DISCON_THRESHOLD_270	BIT(6)
 86#define DISCON_THRESHOLD_280	(0x2 << 6)
 87#define DISCON_THRESHOLD_290	(0x3 << 6)
 88#define SQ_THRESHOLD(x)		((x) << 8)
 89#define LPF_COEF(x)		((x) << 12)
 90#define INTPL_CUR_10		(0x0 << 14)
 91#define INTPL_CUR_20		BIT(14)
 92#define INTPL_CUR_30		(0x2 << 14)
 93#define INTPL_CUR_40		(0x3 << 14)
 94
 95/* USB_PHY_ANALOG */
 96#define ANA_PWR_UP		BIT(1)
 97#define ANA_PWR_DOWN		BIT(2)
 98#define V2I_VCO_RATIO(x)	((x) << 7)
 99#define R_ROTATE_90		(0x0 << 10)
100#define R_ROTATE_0		BIT(10)
101#define MODE_TEST_EN		BIT(11)
102#define ANA_TEST_DC_CTRL(x)	((x) << 12)
103
104static const u32 phy_berlin_pll_dividers[] = {
105	/* Berlin 2 */
106	CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
107	/* Berlin 2CD/Q */
108	CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
109};
110
111struct phy_berlin_usb_priv {
112	void __iomem		*base;
113	struct reset_control	*rst_ctrl;
114	u32			pll_divider;
115};
116
117static int phy_berlin_usb_power_on(struct phy *phy)
118{
119	struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
120
121	reset_control_reset(priv->rst_ctrl);
122
123	writel(priv->pll_divider,
124	       priv->base + USB_PHY_PLL);
125	writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
126	       CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
127	writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
128	       priv->base + USB_PHY_ANALOG);
129	writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
130	       DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
131	       INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
132
133	writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
134	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
135	       priv->base + USB_PHY_TX_CTRL0);
136
137	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
138	       EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
139
140	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
141	       priv->base + USB_PHY_TX_CTRL0);
142	writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
143	       FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
144
145	return 0;
146}
147
148static const struct phy_ops phy_berlin_usb_ops = {
149	.power_on	= phy_berlin_usb_power_on,
150	.owner		= THIS_MODULE,
151};
152
153static const struct of_device_id phy_berlin_usb_of_match[] = {
154	{
155		.compatible = "marvell,berlin2-usb-phy",
156		.data = &phy_berlin_pll_dividers[0],
157	},
158	{
159		.compatible = "marvell,berlin2cd-usb-phy",
160		.data = &phy_berlin_pll_dividers[1],
161	},
162	{ },
163};
164MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match);
165
166static int phy_berlin_usb_probe(struct platform_device *pdev)
167{
168	const struct of_device_id *match =
169		of_match_device(phy_berlin_usb_of_match, &pdev->dev);
170	struct phy_berlin_usb_priv *priv;
171	struct resource *res;
172	struct phy *phy;
173	struct phy_provider *phy_provider;
174
175	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
176	if (!priv)
177		return -ENOMEM;
178
179	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
180	priv->base = devm_ioremap_resource(&pdev->dev, res);
181	if (IS_ERR(priv->base))
182		return PTR_ERR(priv->base);
183
184	priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
185	if (IS_ERR(priv->rst_ctrl))
186		return PTR_ERR(priv->rst_ctrl);
187
188	priv->pll_divider = *((u32 *)match->data);
189
190	phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
191	if (IS_ERR(phy)) {
192		dev_err(&pdev->dev, "failed to create PHY\n");
193		return PTR_ERR(phy);
194	}
195
196	phy_set_drvdata(phy, priv);
197
198	phy_provider =
199		devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
200	return PTR_ERR_OR_ZERO(phy_provider);
201}
202
203static struct platform_driver phy_berlin_usb_driver = {
204	.probe	= phy_berlin_usb_probe,
205	.driver	= {
206		.name		= "phy-berlin-usb",
207		.of_match_table	= phy_berlin_usb_of_match,
208	},
209};
210module_platform_driver(phy_berlin_usb_driver);
211
212MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
213MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
214MODULE_LICENSE("GPL");