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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence Torrent SD0801 PHY driver.
4 *
5 * Copyright 2018 Cadence Design Systems, Inc.
6 *
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/phy/phy-cadence.h>
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/phy/phy.h>
23#include <linux/platform_device.h>
24#include <linux/reset.h>
25#include <linux/regmap.h>
26
27#define REF_CLK_19_2MHZ 19200000
28#define REF_CLK_25MHZ 25000000
29#define REF_CLK_100MHZ 100000000
30
31#define MAX_NUM_LANES 4
32#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
33
34#define NUM_SSC_MODE 3
35#define NUM_REF_CLK 3
36#define NUM_PHY_TYPE 6
37
38#define POLL_TIMEOUT_US 5000
39#define PLL_LOCK_TIMEOUT 100000
40
41#define TORRENT_COMMON_CDB_OFFSET 0x0
42
43#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
44 ((0x4000 << (block_offset)) + \
45 (((ln) << 9) << (reg_offset)))
46
47#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
48 ((0x8000 << (block_offset)) + \
49 (((ln) << 9) << (reg_offset)))
50
51#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
52 (0xC000 << (block_offset))
53
54#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
55 ((0xD000 << (block_offset)) + \
56 (((ln) << 8) << (reg_offset)))
57
58#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
59 (0xE000 << (block_offset))
60
61#define TORRENT_DPTX_PHY_OFFSET 0x0
62
63/*
64 * register offsets from DPTX PHY register block base (i.e MHDP
65 * register base + 0x30a00)
66 */
67#define PHY_AUX_CTRL 0x04
68#define PHY_RESET 0x20
69#define PMA_TX_ELEC_IDLE_MASK 0xF0U
70#define PMA_TX_ELEC_IDLE_SHIFT 4
71#define PHY_L00_RESET_N_MASK 0x01U
72#define PHY_PMA_XCVR_PLLCLK_EN 0x24
73#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
74#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
75#define PHY_POWER_STATE_LN_0 0x0000
76#define PHY_POWER_STATE_LN_1 0x0008
77#define PHY_POWER_STATE_LN_2 0x0010
78#define PHY_POWER_STATE_LN_3 0x0018
79#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
80#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
81#define PHY_PMA_CMN_READY 0x34
82
83/*
84 * register offsets from SD0801 PHY register block base (i.e MHDP
85 * register base + 0x500000)
86 */
87#define CMN_SSM_BANDGAP_TMR 0x0021U
88#define CMN_SSM_BIAS_TMR 0x0022U
89#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
90#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
91#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
92#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
93#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
94#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
95#define CMN_CDIAG_REFCLK_OVRD 0x004CU
96#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
97#define CMN_BGCAL_INIT_TMR 0x0064U
98#define CMN_BGCAL_ITER_TMR 0x0065U
99#define CMN_IBCAL_INIT_TMR 0x0074U
100#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
101#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
102#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
103#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
104#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
105#define CMN_PLL0_INTDIV_M0 0x0090U
106#define CMN_PLL0_FRACDIVL_M0 0x0091U
107#define CMN_PLL0_FRACDIVH_M0 0x0092U
108#define CMN_PLL0_HIGH_THR_M0 0x0093U
109#define CMN_PLL0_DSM_DIAG_M0 0x0094U
110#define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
111#define CMN_PLL0_SS_CTRL1_M0 0x0098U
112#define CMN_PLL0_SS_CTRL2_M0 0x0099U
113#define CMN_PLL0_SS_CTRL3_M0 0x009AU
114#define CMN_PLL0_SS_CTRL4_M0 0x009BU
115#define CMN_PLL0_LOCK_REFCNT_START 0x009CU
116#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
117#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
118#define CMN_PLL0_INTDIV_M1 0x00A0U
119#define CMN_PLL0_FRACDIVH_M1 0x00A2U
120#define CMN_PLL0_HIGH_THR_M1 0x00A3U
121#define CMN_PLL0_DSM_DIAG_M1 0x00A4U
122#define CMN_PLL0_SS_CTRL1_M1 0x00A8U
123#define CMN_PLL0_SS_CTRL2_M1 0x00A9U
124#define CMN_PLL0_SS_CTRL3_M1 0x00AAU
125#define CMN_PLL0_SS_CTRL4_M1 0x00ABU
126#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
127#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
128#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
129#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
130#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
131#define CMN_PLL1_INTDIV_M0 0x00D0U
132#define CMN_PLL1_FRACDIVL_M0 0x00D1U
133#define CMN_PLL1_FRACDIVH_M0 0x00D2U
134#define CMN_PLL1_HIGH_THR_M0 0x00D3U
135#define CMN_PLL1_DSM_DIAG_M0 0x00D4U
136#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
137#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
138#define CMN_PLL1_SS_CTRL1_M0 0x00D8U
139#define CMN_PLL1_SS_CTRL2_M0 0x00D9U
140#define CMN_PLL1_SS_CTRL3_M0 0x00DAU
141#define CMN_PLL1_SS_CTRL4_M0 0x00DBU
142#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
143#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
144#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
145#define CMN_TXPUCAL_TUNE 0x0103U
146#define CMN_TXPUCAL_INIT_TMR 0x0104U
147#define CMN_TXPUCAL_ITER_TMR 0x0105U
148#define CMN_TXPDCAL_TUNE 0x010BU
149#define CMN_TXPDCAL_INIT_TMR 0x010CU
150#define CMN_TXPDCAL_ITER_TMR 0x010DU
151#define CMN_RXCAL_INIT_TMR 0x0114U
152#define CMN_RXCAL_ITER_TMR 0x0115U
153#define CMN_SD_CAL_INIT_TMR 0x0124U
154#define CMN_SD_CAL_ITER_TMR 0x0125U
155#define CMN_SD_CAL_REFTIM_START 0x0126U
156#define CMN_SD_CAL_PLLCNT_START 0x0128U
157#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
158#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
159#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
160#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
161#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
162#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
163#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
164#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
165#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
166#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
167#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
168#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
169#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
170#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
171#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
172#define CMN_DIAG_BIAS_OVRD1 0x01E1U
173
174/* PMA TX Lane registers */
175#define TX_TXCC_CTRL 0x0040U
176#define TX_TXCC_CPOST_MULT_00 0x004CU
177#define TX_TXCC_CPOST_MULT_01 0x004DU
178#define TX_TXCC_MGNFS_MULT_000 0x0050U
179#define TX_TXCC_MGNFS_MULT_100 0x0054U
180#define DRV_DIAG_TX_DRV 0x00C6U
181#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
182#define XCVR_DIAG_HSCLK_SEL 0x00E6U
183#define XCVR_DIAG_HSCLK_DIV 0x00E7U
184#define XCVR_DIAG_RXCLK_CTRL 0x00E9U
185#define XCVR_DIAG_BIDI_CTRL 0x00EAU
186#define XCVR_DIAG_PSC_OVRD 0x00EBU
187#define TX_PSC_A0 0x0100U
188#define TX_PSC_A1 0x0101U
189#define TX_PSC_A2 0x0102U
190#define TX_PSC_A3 0x0103U
191#define TX_RCVDET_ST_TMR 0x0123U
192#define TX_DIAG_ACYA 0x01E7U
193#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
194
195/* PMA RX Lane registers */
196#define RX_PSC_A0 0x0000U
197#define RX_PSC_A1 0x0001U
198#define RX_PSC_A2 0x0002U
199#define RX_PSC_A3 0x0003U
200#define RX_PSC_CAL 0x0006U
201#define RX_CDRLF_CNFG 0x0080U
202#define RX_CDRLF_CNFG3 0x0082U
203#define RX_SIGDET_HL_FILT_TMR 0x0090U
204#define RX_REE_GCSM1_CTRL 0x0108U
205#define RX_REE_GCSM1_EQENM_PH1 0x0109U
206#define RX_REE_GCSM1_EQENM_PH2 0x010AU
207#define RX_REE_GCSM2_CTRL 0x0110U
208#define RX_REE_PERGCSM_CTRL 0x0118U
209#define RX_REE_ATTEN_THR 0x0149U
210#define RX_REE_TAP1_CLIP 0x0171U
211#define RX_REE_TAP2TON_CLIP 0x0172U
212#define RX_REE_SMGM_CTRL1 0x0177U
213#define RX_REE_SMGM_CTRL2 0x0178U
214#define RX_DIAG_DFE_CTRL 0x01E0U
215#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
216#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
217#define RX_DIAG_NQST_CTRL 0x01E5U
218#define RX_DIAG_SIGDET_TUNE 0x01E8U
219#define RX_DIAG_PI_RATE 0x01F4U
220#define RX_DIAG_PI_CAP 0x01F5U
221#define RX_DIAG_ACYA 0x01FFU
222
223/* PHY PCS common registers */
224#define PHY_PIPE_CMN_CTRL1 0x0000U
225#define PHY_PLL_CFG 0x000EU
226#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
227#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
228#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
229
230/* PHY PCS lane registers */
231#define PHY_PCS_ISO_LINK_CTRL 0x000BU
232
233/* PHY PMA common registers */
234#define PHY_PMA_CMN_CTRL1 0x0000U
235#define PHY_PMA_CMN_CTRL2 0x0001U
236#define PHY_PMA_PLL_RAW_CTRL 0x0003U
237
238#define CDNS_TORRENT_OUTPUT_CLOCKS 3
239
240static const char * const clk_names[] = {
241 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
242 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
243 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
244};
245
246static const struct reg_field phy_pll_cfg =
247 REG_FIELD(PHY_PLL_CFG, 0, 1);
248
249static const struct reg_field phy_pma_cmn_ctrl_1 =
250 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
251
252static const struct reg_field phy_pma_cmn_ctrl_2 =
253 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
254
255static const struct reg_field phy_pma_pll_raw_ctrl =
256 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
257
258static const struct reg_field phy_reset_ctrl =
259 REG_FIELD(PHY_RESET, 8, 8);
260
261static const struct reg_field phy_pcs_iso_link_ctrl_1 =
262 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
263
264static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
265
266static const struct reg_field cmn_cdiag_refclk_ovrd_4 =
267 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);
268
269#define REFCLK_OUT_NUM_CMN_CONFIG 4
270
271enum cdns_torrent_refclk_out_cmn {
272 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
273 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
274 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
275 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
276};
277
278static const struct reg_field refclk_out_cmn_cfg[] = {
279 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
280 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
281 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
282 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
283};
284
285static const int refclk_driver_parent_index[] = {
286 CDNS_TORRENT_DERIVED_REFCLK,
287 CDNS_TORRENT_RECEIVED_REFCLK
288};
289
290static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };
291
292enum cdns_torrent_phy_type {
293 TYPE_NONE,
294 TYPE_DP,
295 TYPE_PCIE,
296 TYPE_SGMII,
297 TYPE_QSGMII,
298 TYPE_USB,
299};
300
301enum cdns_torrent_ref_clk {
302 CLK_19_2_MHZ,
303 CLK_25_MHZ,
304 CLK_100_MHZ
305};
306
307enum cdns_torrent_ssc_mode {
308 NO_SSC,
309 EXTERNAL_SSC,
310 INTERNAL_SSC
311};
312
313struct cdns_torrent_inst {
314 struct phy *phy;
315 u32 mlane;
316 enum cdns_torrent_phy_type phy_type;
317 u32 num_lanes;
318 struct reset_control *lnk_rst;
319 enum cdns_torrent_ssc_mode ssc_mode;
320};
321
322struct cdns_torrent_phy {
323 void __iomem *base; /* DPTX registers base */
324 void __iomem *sd_base; /* SD0801 registers base */
325 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
326 struct reset_control *phy_rst;
327 struct reset_control *apb_rst;
328 struct device *dev;
329 struct clk *clk;
330 enum cdns_torrent_ref_clk ref_clk_rate;
331 struct cdns_torrent_inst phys[MAX_NUM_LANES];
332 int nsubnodes;
333 const struct cdns_torrent_data *init_data;
334 struct regmap *regmap_common_cdb;
335 struct regmap *regmap_phy_pcs_common_cdb;
336 struct regmap *regmap_phy_pma_common_cdb;
337 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
338 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
339 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
340 struct regmap *regmap_dptx_phy_reg;
341 struct regmap_field *phy_pll_cfg;
342 struct regmap_field *phy_pipe_cmn_ctrl1_0;
343 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
344 struct regmap_field *phy_pma_cmn_ctrl_1;
345 struct regmap_field *phy_pma_cmn_ctrl_2;
346 struct regmap_field *phy_pma_pll_raw_ctrl;
347 struct regmap_field *phy_reset_ctrl;
348 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
349 struct clk_hw_onecell_data *clk_hw_data;
350};
351
352enum phy_powerstate {
353 POWERSTATE_A0 = 0,
354 /* Powerstate A1 is unused */
355 POWERSTATE_A2 = 2,
356 POWERSTATE_A3 = 3,
357};
358
359struct cdns_torrent_refclk_driver {
360 struct clk_hw hw;
361 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
362 struct clk_init_data clk_data;
363};
364
365#define to_cdns_torrent_refclk_driver(_hw) \
366 container_of(_hw, struct cdns_torrent_refclk_driver, hw)
367
368struct cdns_torrent_derived_refclk {
369 struct clk_hw hw;
370 struct regmap_field *phy_pipe_cmn_ctrl1_0;
371 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
372 struct clk_init_data clk_data;
373};
374
375#define to_cdns_torrent_derived_refclk(_hw) \
376 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
377
378struct cdns_torrent_received_refclk {
379 struct clk_hw hw;
380 struct regmap_field *phy_pipe_cmn_ctrl1_0;
381 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
382 struct clk_init_data clk_data;
383};
384
385#define to_cdns_torrent_received_refclk(_hw) \
386 container_of(_hw, struct cdns_torrent_received_refclk, hw)
387
388struct cdns_reg_pairs {
389 u32 val;
390 u32 off;
391};
392
393struct cdns_torrent_vals {
394 struct cdns_reg_pairs *reg_pairs;
395 u32 num_regs;
396};
397
398struct cdns_torrent_data {
399 u8 block_offset_shift;
400 u8 reg_offset_shift;
401 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
402 [NUM_SSC_MODE];
403 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
404 [NUM_SSC_MODE];
405 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
406 [NUM_SSC_MODE];
407 struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE]
408 [NUM_PHY_TYPE][NUM_SSC_MODE];
409 struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
410 [NUM_PHY_TYPE][NUM_SSC_MODE];
411 struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
412 [NUM_PHY_TYPE][NUM_SSC_MODE];
413};
414
415struct cdns_regmap_cdb_context {
416 struct device *dev;
417 void __iomem *base;
418 u8 reg_offset_shift;
419};
420
421static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
422{
423 struct cdns_regmap_cdb_context *ctx = context;
424 u32 offset = reg << ctx->reg_offset_shift;
425
426 writew(val, ctx->base + offset);
427
428 return 0;
429}
430
431static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
432{
433 struct cdns_regmap_cdb_context *ctx = context;
434 u32 offset = reg << ctx->reg_offset_shift;
435
436 *val = readw(ctx->base + offset);
437 return 0;
438}
439
440static int cdns_regmap_dptx_write(void *context, unsigned int reg,
441 unsigned int val)
442{
443 struct cdns_regmap_cdb_context *ctx = context;
444 u32 offset = reg;
445
446 writel(val, ctx->base + offset);
447
448 return 0;
449}
450
451static int cdns_regmap_dptx_read(void *context, unsigned int reg,
452 unsigned int *val)
453{
454 struct cdns_regmap_cdb_context *ctx = context;
455 u32 offset = reg;
456
457 *val = readl(ctx->base + offset);
458 return 0;
459}
460
461#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
462{ \
463 .name = "torrent_tx_lane" n "_cdb", \
464 .reg_stride = 1, \
465 .fast_io = true, \
466 .reg_write = cdns_regmap_write, \
467 .reg_read = cdns_regmap_read, \
468}
469
470#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
471{ \
472 .name = "torrent_rx_lane" n "_cdb", \
473 .reg_stride = 1, \
474 .fast_io = true, \
475 .reg_write = cdns_regmap_write, \
476 .reg_read = cdns_regmap_read, \
477}
478
479static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
480 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
481 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
482 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
483 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
484};
485
486static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
487 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
488 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
489 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
490 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
491};
492
493static const struct regmap_config cdns_torrent_common_cdb_config = {
494 .name = "torrent_common_cdb",
495 .reg_stride = 1,
496 .fast_io = true,
497 .reg_write = cdns_regmap_write,
498 .reg_read = cdns_regmap_read,
499};
500
501#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
502{ \
503 .name = "torrent_phy_pcs_lane" n "_cdb", \
504 .reg_stride = 1, \
505 .fast_io = true, \
506 .reg_write = cdns_regmap_write, \
507 .reg_read = cdns_regmap_read, \
508}
509
510static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
511 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
512 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
513 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
514 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
515};
516
517static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
518 .name = "torrent_phy_pcs_cmn_cdb",
519 .reg_stride = 1,
520 .fast_io = true,
521 .reg_write = cdns_regmap_write,
522 .reg_read = cdns_regmap_read,
523};
524
525static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
526 .name = "torrent_phy_pma_cmn_cdb",
527 .reg_stride = 1,
528 .fast_io = true,
529 .reg_write = cdns_regmap_write,
530 .reg_read = cdns_regmap_read,
531};
532
533static const struct regmap_config cdns_torrent_dptx_phy_config = {
534 .name = "torrent_dptx_phy",
535 .reg_stride = 1,
536 .fast_io = true,
537 .reg_write = cdns_regmap_dptx_write,
538 .reg_read = cdns_regmap_dptx_read,
539};
540
541/* PHY mmr access functions */
542
543static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
544{
545 regmap_write(regmap, offset, val);
546}
547
548static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
549{
550 unsigned int val;
551
552 regmap_read(regmap, offset, &val);
553 return val;
554}
555
556/* DPTX mmr access functions */
557
558static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
559{
560 regmap_write(regmap, offset, val);
561}
562
563static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
564{
565 u32 val;
566
567 regmap_read(regmap, offset, &val);
568 return val;
569}
570
571/*
572 * Structure used to store values of PHY registers for voltage-related
573 * coefficients, for particular voltage swing and pre-emphasis level. Values
574 * are shared across all physical lanes.
575 */
576struct coefficients {
577 /* Value of DRV_DIAG_TX_DRV register to use */
578 u16 diag_tx_drv;
579 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
580 u16 mgnfs_mult;
581 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
582 u16 cpost_mult;
583};
584
585/*
586 * Array consists of values of voltage-related registers for sd0801 PHY. A value
587 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
588 */
589static const struct coefficients vltg_coeff[4][4] = {
590 /* voltage swing 0, pre-emphasis 0->3 */
591 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
592 .cpost_mult = 0x0000},
593 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
594 .cpost_mult = 0x0014},
595 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
596 .cpost_mult = 0x0020},
597 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
598 .cpost_mult = 0x002A}
599 },
600
601 /* voltage swing 1, pre-emphasis 0->3 */
602 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
603 .cpost_mult = 0x0000},
604 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
605 .cpost_mult = 0x0012},
606 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
607 .cpost_mult = 0x001F},
608 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
609 .cpost_mult = 0xFFFF}
610 },
611
612 /* voltage swing 2, pre-emphasis 0->3 */
613 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
614 .cpost_mult = 0x0000},
615 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
616 .cpost_mult = 0x0013},
617 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
618 .cpost_mult = 0xFFFF},
619 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
620 .cpost_mult = 0xFFFF}
621 },
622
623 /* voltage swing 3, pre-emphasis 0->3 */
624 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
625 .cpost_mult = 0x0000},
626 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
627 .cpost_mult = 0xFFFF},
628 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
629 .cpost_mult = 0xFFFF},
630 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
631 .cpost_mult = 0xFFFF}
632 }
633};
634
635static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
636{
637 switch (phy_type) {
638 case TYPE_DP:
639 return "DisplayPort";
640 case TYPE_PCIE:
641 return "PCIe";
642 case TYPE_SGMII:
643 return "SGMII";
644 case TYPE_QSGMII:
645 return "QSGMII";
646 case TYPE_USB:
647 return "USB";
648 default:
649 return "None";
650 }
651}
652
653/*
654 * Set registers responsible for enabling and configuring SSC, with second and
655 * third register values provided by parameters.
656 */
657static
658void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
659 u32 ctrl2_val, u32 ctrl3_val)
660{
661 struct regmap *regmap = cdns_phy->regmap_common_cdb;
662
663 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
664 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
665 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
666 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
667 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
668 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
669 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
670 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
671}
672
673static
674void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
675 u32 rate, bool ssc)
676{
677 struct regmap *regmap = cdns_phy->regmap_common_cdb;
678
679 /* Assumes 19.2 MHz refclock */
680 switch (rate) {
681 /* Setting VCO for 10.8GHz */
682 case 2700:
683 case 5400:
684 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
685 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
686 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
687 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
688 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
689 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
690 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
691 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
692 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
693 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
694 if (ssc)
695 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
696 break;
697 /* Setting VCO for 9.72GHz */
698 case 1620:
699 case 2430:
700 case 3240:
701 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
702 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
703 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
704 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
705 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
706 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
707 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
708 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
709 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
710 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
711 if (ssc)
712 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
713 break;
714 /* Setting VCO for 8.64GHz */
715 case 2160:
716 case 4320:
717 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
718 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
719 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
720 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
721 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
722 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
723 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
724 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
725 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
726 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
727 if (ssc)
728 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
729 break;
730 /* Setting VCO for 8.1GHz */
731 case 8100:
732 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
733 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
734 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
735 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
736 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
737 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
738 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
739 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
740 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
741 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
742 if (ssc)
743 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
744 break;
745 }
746
747 if (ssc) {
748 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
749 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
750 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
751 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
752 } else {
753 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
754 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
755 /* Set reset register values to disable SSC */
756 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
757 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
758 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
759 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
760 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
761 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
762 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
763 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
764 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
765 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
766 }
767
768 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
769 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
770 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
771 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
772}
773
774/*
775 * Set registers responsible for enabling and configuring SSC, with second
776 * register value provided by a parameter.
777 */
778static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
779 u32 ctrl2_val)
780{
781 struct regmap *regmap = cdns_phy->regmap_common_cdb;
782
783 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
784 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
785 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
786 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
787 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
788 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
789 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
790 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
791}
792
793static
794void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
795 u32 rate, bool ssc)
796{
797 struct regmap *regmap = cdns_phy->regmap_common_cdb;
798
799 /* Assumes 25 MHz refclock */
800 switch (rate) {
801 /* Setting VCO for 10.8GHz */
802 case 2700:
803 case 5400:
804 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
805 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
806 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
807 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
808 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
809 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
810 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
811 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
812 if (ssc)
813 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
814 break;
815 /* Setting VCO for 9.72GHz */
816 case 1620:
817 case 2430:
818 case 3240:
819 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
820 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
821 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
822 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
823 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
824 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
825 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
826 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
827 if (ssc)
828 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
829 break;
830 /* Setting VCO for 8.64GHz */
831 case 2160:
832 case 4320:
833 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
834 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
835 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
836 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
837 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
838 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
839 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
840 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
841 if (ssc)
842 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
843 break;
844 /* Setting VCO for 8.1GHz */
845 case 8100:
846 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
847 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
848 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
849 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
850 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
851 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
852 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
853 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
854 if (ssc)
855 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
856 break;
857 }
858
859 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
860 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
861
862 if (ssc) {
863 cdns_torrent_phy_write(regmap,
864 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
865 cdns_torrent_phy_write(regmap,
866 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
867 cdns_torrent_phy_write(regmap,
868 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
869 cdns_torrent_phy_write(regmap,
870 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
871 } else {
872 cdns_torrent_phy_write(regmap,
873 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
874 cdns_torrent_phy_write(regmap,
875 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
876 /* Set reset register values to disable SSC */
877 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
878 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
879 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
880 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
881 cdns_torrent_phy_write(regmap,
882 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
883 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
884 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
885 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
886 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
887 cdns_torrent_phy_write(regmap,
888 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
889 }
890
891 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
892 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
893 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
894 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
895}
896
897static
898void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
899 u32 rate, bool ssc)
900{
901 struct regmap *regmap = cdns_phy->regmap_common_cdb;
902
903 /* Assumes 100 MHz refclock */
904 switch (rate) {
905 /* Setting VCO for 10.8GHz */
906 case 2700:
907 case 5400:
908 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
909 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
910 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
911 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
912 break;
913 /* Setting VCO for 9.72GHz */
914 case 1620:
915 case 2430:
916 case 3240:
917 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
918 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
919 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
920 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
921 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
922 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
923 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
925 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
926 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
927 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
928 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
929 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
930 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
931 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
932 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
933 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
934 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
935 break;
936 /* Setting VCO for 8.64GHz */
937 case 2160:
938 case 4320:
939 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
940 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
941 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
942 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
943 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
944 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
945 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
946 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
947 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
948 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
949 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
950 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
951 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
952 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
953 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
954 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
955 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
956 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
957 break;
958 /* Setting VCO for 8.1GHz */
959 case 8100:
960 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
961 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
962 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
963 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
964 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
965 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
966 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
967 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
968 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
969 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
970 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
971 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
972 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
973 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
974 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
975 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
976 break;
977 }
978}
979
980/*
981 * Enable or disable PLL for selected lanes.
982 */
983static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
984 struct phy_configure_opts_dp *dp,
985 bool enable)
986{
987 u32 rd_val;
988 u32 ret;
989 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
990
991 /*
992 * Used to determine, which bits to check for or enable in
993 * PHY_PMA_XCVR_PLLCLK_EN register.
994 */
995 u32 pll_bits;
996 /* Used to enable or disable lanes. */
997 u32 pll_val;
998
999 /* Select values of registers and mask, depending on enabled lane
1000 * count.
1001 */
1002 switch (dp->lanes) {
1003 /* lane 0 */
1004 case (1):
1005 pll_bits = 0x00000001;
1006 break;
1007 /* lanes 0-1 */
1008 case (2):
1009 pll_bits = 0x00000003;
1010 break;
1011 /* lanes 0-3, all */
1012 default:
1013 pll_bits = 0x0000000F;
1014 break;
1015 }
1016
1017 if (enable)
1018 pll_val = pll_bits;
1019 else
1020 pll_val = 0x00000000;
1021
1022 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
1023
1024 /* Wait for acknowledgment from PHY. */
1025 ret = regmap_read_poll_timeout(regmap,
1026 PHY_PMA_XCVR_PLLCLK_EN_ACK,
1027 rd_val,
1028 (rd_val & pll_bits) == pll_val,
1029 0, POLL_TIMEOUT_US);
1030 ndelay(100);
1031 return ret;
1032}
1033
1034static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1035 u32 num_lanes,
1036 enum phy_powerstate powerstate)
1037{
1038 /* Register value for power state for a single byte. */
1039 u32 value_part;
1040 u32 value;
1041 u32 mask;
1042 u32 read_val;
1043 u32 ret;
1044 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1045
1046 switch (powerstate) {
1047 case (POWERSTATE_A0):
1048 value_part = 0x01U;
1049 break;
1050 case (POWERSTATE_A2):
1051 value_part = 0x04U;
1052 break;
1053 default:
1054 /* Powerstate A3 */
1055 value_part = 0x08U;
1056 break;
1057 }
1058
1059 /* Select values of registers and mask, depending on enabled
1060 * lane count.
1061 */
1062 switch (num_lanes) {
1063 /* lane 0 */
1064 case (1):
1065 value = value_part;
1066 mask = 0x0000003FU;
1067 break;
1068 /* lanes 0-1 */
1069 case (2):
1070 value = (value_part
1071 | (value_part << 8));
1072 mask = 0x00003F3FU;
1073 break;
1074 /* lanes 0-3, all */
1075 default:
1076 value = (value_part
1077 | (value_part << 8)
1078 | (value_part << 16)
1079 | (value_part << 24));
1080 mask = 0x3F3F3F3FU;
1081 break;
1082 }
1083
1084 /* Set power state A<n>. */
1085 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1086 /* Wait, until PHY acknowledges power state completion. */
1087 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1088 read_val, (read_val & mask) == value, 0,
1089 POLL_TIMEOUT_US);
1090 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1091 ndelay(100);
1092
1093 return ret;
1094}
1095
1096static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1097{
1098 unsigned int read_val;
1099 int ret;
1100 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1101
1102 /*
1103 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1104 * master lane
1105 */
1106 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1107 read_val, read_val & 1,
1108 0, POLL_TIMEOUT_US);
1109 if (ret == -ETIMEDOUT) {
1110 dev_err(cdns_phy->dev,
1111 "timeout waiting for link PLL clock enable ack\n");
1112 return ret;
1113 }
1114
1115 ndelay(100);
1116
1117 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1118 POWERSTATE_A2);
1119 if (ret)
1120 return ret;
1121
1122 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1123 POWERSTATE_A0);
1124
1125 return ret;
1126}
1127
1128static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1129{
1130 unsigned int reg;
1131 int ret;
1132 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1133
1134 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1135 reg & 1, 0, POLL_TIMEOUT_US);
1136 if (ret == -ETIMEDOUT) {
1137 dev_err(cdns_phy->dev,
1138 "timeout waiting for PMA common ready\n");
1139 return -ETIMEDOUT;
1140 }
1141
1142 return 0;
1143}
1144
1145static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1146 u32 rate, u32 num_lanes)
1147{
1148 unsigned int clk_sel_val = 0;
1149 unsigned int hsclk_div_val = 0;
1150 unsigned int i;
1151
1152 switch (rate) {
1153 case 1620:
1154 clk_sel_val = 0x0f01;
1155 hsclk_div_val = 2;
1156 break;
1157 case 2160:
1158 case 2430:
1159 case 2700:
1160 clk_sel_val = 0x0701;
1161 hsclk_div_val = 1;
1162 break;
1163 case 3240:
1164 clk_sel_val = 0x0b00;
1165 hsclk_div_val = 2;
1166 break;
1167 case 4320:
1168 case 5400:
1169 clk_sel_val = 0x0301;
1170 hsclk_div_val = 0;
1171 break;
1172 case 8100:
1173 clk_sel_val = 0x0200;
1174 hsclk_div_val = 0;
1175 break;
1176 }
1177
1178 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1179 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1180 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1181 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1182
1183 /* PMA lane configuration to deal with multi-link operation */
1184 for (i = 0; i < num_lanes; i++)
1185 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1186 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1187}
1188
1189/*
1190 * Perform register operations related to setting link rate, once powerstate is
1191 * set and PLL disable request was processed.
1192 */
1193static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
1194 struct phy_configure_opts_dp *dp)
1195{
1196 u32 read_val, ret;
1197
1198 /* Disable the cmn_pll0_en before re-programming the new data rate. */
1199 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
1200
1201 /*
1202 * Wait for PLL ready de-assertion.
1203 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
1204 */
1205 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1206 read_val,
1207 ((read_val >> 2) & 0x01) != 0,
1208 0, POLL_TIMEOUT_US);
1209 if (ret)
1210 return ret;
1211 ndelay(200);
1212
1213 /* DP Rate Change - VCO Output settings. */
1214 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1215 /* PMA common configuration 19.2MHz */
1216 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
1217 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1218 /* PMA common configuration 25MHz */
1219 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
1220 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1221 /* PMA common configuration 100MHz */
1222 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
1223
1224 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
1225
1226 /* Enable the cmn_pll0_en. */
1227 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
1228
1229 /*
1230 * Wait for PLL ready assertion.
1231 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
1232 */
1233 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1234 read_val,
1235 (read_val & 0x01) != 0,
1236 0, POLL_TIMEOUT_US);
1237 return ret;
1238}
1239
1240/*
1241 * Verify, that parameters to configure PHY with are correct.
1242 */
1243static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
1244 struct phy_configure_opts_dp *dp)
1245{
1246 u8 i;
1247
1248 /* If changing link rate was required, verify it's supported. */
1249 if (dp->set_rate) {
1250 switch (dp->link_rate) {
1251 case 1620:
1252 case 2160:
1253 case 2430:
1254 case 2700:
1255 case 3240:
1256 case 4320:
1257 case 5400:
1258 case 8100:
1259 /* valid bit rate */
1260 break;
1261 default:
1262 return -EINVAL;
1263 }
1264 }
1265
1266 /* Verify lane count. */
1267 switch (dp->lanes) {
1268 case 1:
1269 case 2:
1270 case 4:
1271 /* valid lane count. */
1272 break;
1273 default:
1274 return -EINVAL;
1275 }
1276
1277 /* Check against actual number of PHY's lanes. */
1278 if (dp->lanes > inst->num_lanes)
1279 return -EINVAL;
1280
1281 /*
1282 * If changing voltages is required, check swing and pre-emphasis
1283 * levels, per-lane.
1284 */
1285 if (dp->set_voltages) {
1286 /* Lane count verified previously. */
1287 for (i = 0; i < dp->lanes; i++) {
1288 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1289 return -EINVAL;
1290
1291 /* Sum of voltage swing and pre-emphasis levels cannot
1292 * exceed 3.
1293 */
1294 if (dp->voltage[i] + dp->pre[i] > 3)
1295 return -EINVAL;
1296 }
1297 }
1298
1299 return 0;
1300}
1301
1302/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
1303static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
1304 u32 num_lanes)
1305{
1306 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1307 u32 pwr_state = cdns_torrent_dp_read(regmap,
1308 PHY_PMA_XCVR_POWER_STATE_REQ);
1309 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
1310 PHY_PMA_XCVR_PLLCLK_EN);
1311
1312 /* Lane 0 is always enabled. */
1313 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1314 PHY_POWER_STATE_LN_0);
1315 pll_clk_en &= ~0x01U;
1316
1317 if (num_lanes > 1) {
1318 /* lane 1 */
1319 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1320 PHY_POWER_STATE_LN_1);
1321 pll_clk_en &= ~(0x01U << 1);
1322 }
1323
1324 if (num_lanes > 2) {
1325 /* lanes 2 and 3 */
1326 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1327 PHY_POWER_STATE_LN_2);
1328 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1329 PHY_POWER_STATE_LN_3);
1330 pll_clk_en &= ~(0x01U << 2);
1331 pll_clk_en &= ~(0x01U << 3);
1332 }
1333
1334 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
1335 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
1336}
1337
1338/* Configure lane count as required. */
1339static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
1340 struct phy_configure_opts_dp *dp)
1341{
1342 u32 value;
1343 u32 ret;
1344 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1345 u8 lane_mask = (1 << dp->lanes) - 1;
1346
1347 value = cdns_torrent_dp_read(regmap, PHY_RESET);
1348 /* clear pma_tx_elec_idle_ln_* bits. */
1349 value &= ~PMA_TX_ELEC_IDLE_MASK;
1350 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
1351 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
1352 PMA_TX_ELEC_IDLE_MASK;
1353 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1354
1355 /* reset the link by asserting phy_l00_reset_n low */
1356 cdns_torrent_dp_write(regmap, PHY_RESET,
1357 value & (~PHY_L00_RESET_N_MASK));
1358
1359 /*
1360 * Assert lane reset on unused lanes and lane 0 so they remain in reset
1361 * and powered down when re-enabling the link
1362 */
1363 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
1364 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1365
1366 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
1367
1368 /* release phy_l0*_reset_n based on used laneCount */
1369 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
1370 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1371
1372 /* Wait, until PHY gets ready after releasing PHY reset signal. */
1373 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1374 if (ret)
1375 return ret;
1376
1377 ndelay(100);
1378
1379 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1380 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1381
1382 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
1383
1384 return ret;
1385}
1386
1387/* Configure link rate as required. */
1388static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
1389 struct phy_configure_opts_dp *dp)
1390{
1391 u32 ret;
1392
1393 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1394 POWERSTATE_A3);
1395 if (ret)
1396 return ret;
1397 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
1398 if (ret)
1399 return ret;
1400 ndelay(200);
1401
1402 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
1403 if (ret)
1404 return ret;
1405 ndelay(200);
1406
1407 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
1408 if (ret)
1409 return ret;
1410 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1411 POWERSTATE_A2);
1412 if (ret)
1413 return ret;
1414 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1415 POWERSTATE_A0);
1416 if (ret)
1417 return ret;
1418 ndelay(900);
1419
1420 return ret;
1421}
1422
1423/* Configure voltage swing and pre-emphasis for all enabled lanes. */
1424static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
1425 struct phy_configure_opts_dp *dp)
1426{
1427 u8 lane;
1428 u16 val;
1429
1430 for (lane = 0; lane < dp->lanes; lane++) {
1431 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
1432 TX_DIAG_ACYA);
1433 /*
1434 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
1435 * current state of the analog TX driver.
1436 */
1437 val |= TX_DIAG_ACYA_HBDC_MASK;
1438 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1439 TX_DIAG_ACYA, val);
1440
1441 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1442 TX_TXCC_CTRL, 0x08A4);
1443 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
1444 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1445 DRV_DIAG_TX_DRV, val);
1446 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
1447 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1448 TX_TXCC_MGNFS_MULT_000,
1449 val);
1450 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
1451 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1452 TX_TXCC_CPOST_MULT_00,
1453 val);
1454
1455 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
1456 TX_DIAG_ACYA);
1457 /*
1458 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
1459 * analog TX driver to reflect the new programmed one.
1460 */
1461 val &= ~TX_DIAG_ACYA_HBDC_MASK;
1462 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1463 TX_DIAG_ACYA, val);
1464 }
1465};
1466
1467static int cdns_torrent_dp_configure(struct phy *phy,
1468 union phy_configure_opts *opts)
1469{
1470 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1471 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1472 int ret;
1473
1474 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
1475 if (ret) {
1476 dev_err(&phy->dev, "invalid params for phy configure\n");
1477 return ret;
1478 }
1479
1480 if (opts->dp.set_lanes) {
1481 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
1482 if (ret) {
1483 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
1484 return ret;
1485 }
1486 }
1487
1488 if (opts->dp.set_rate) {
1489 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
1490 if (ret) {
1491 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
1492 return ret;
1493 }
1494 }
1495
1496 if (opts->dp.set_voltages)
1497 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
1498
1499 return ret;
1500}
1501
1502static int cdns_torrent_phy_on(struct phy *phy)
1503{
1504 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1505 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1506 u32 read_val;
1507 int ret;
1508
1509 if (cdns_phy->nsubnodes == 1) {
1510 /* Take the PHY lane group out of reset */
1511 reset_control_deassert(inst->lnk_rst);
1512
1513 /* Take the PHY out of reset */
1514 ret = reset_control_deassert(cdns_phy->phy_rst);
1515 if (ret)
1516 return ret;
1517 }
1518
1519 /*
1520 * Wait for cmn_ready assertion
1521 * PHY_PMA_CMN_CTRL1[0] == 1
1522 */
1523 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1524 read_val, read_val, 1000,
1525 PLL_LOCK_TIMEOUT);
1526 if (ret) {
1527 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1528 return ret;
1529 }
1530
1531 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
1532 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
1533 read_val, !read_val, 1000,
1534 PLL_LOCK_TIMEOUT);
1535 if (ret == -ETIMEDOUT) {
1536 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
1537 return ret;
1538 }
1539 }
1540
1541 return 0;
1542}
1543
1544static int cdns_torrent_phy_off(struct phy *phy)
1545{
1546 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1547 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1548 int ret;
1549
1550 if (cdns_phy->nsubnodes != 1)
1551 return 0;
1552
1553 ret = reset_control_assert(cdns_phy->phy_rst);
1554 if (ret)
1555 return ret;
1556
1557 return reset_control_assert(inst->lnk_rst);
1558}
1559
1560static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
1561 struct cdns_torrent_inst *inst)
1562{
1563 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1564 unsigned char lane_bits;
1565
1566 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1567
1568 /*
1569 * Set lines power state to A0
1570 * Set lines pll clk enable to 0
1571 */
1572 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
1573
1574 /*
1575 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1576 * used lanes
1577 */
1578 lane_bits = (1 << inst->num_lanes) - 1;
1579 cdns_torrent_dp_write(regmap, PHY_RESET,
1580 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
1581
1582 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1583 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1584
1585 /*
1586 * PHY PMA registers configuration functions
1587 * Initialize PHY with max supported link rate, without SSC.
1588 */
1589 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1590 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1591 cdns_phy->max_bit_rate,
1592 false);
1593 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1594 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1595 cdns_phy->max_bit_rate,
1596 false);
1597 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1598 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
1599 cdns_phy->max_bit_rate,
1600 false);
1601
1602 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
1603 inst->num_lanes);
1604
1605 /* take out of reset */
1606 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1607}
1608
1609static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
1610 struct cdns_torrent_inst *inst,
1611 struct phy *phy)
1612{
1613 int ret;
1614
1615 cdns_torrent_phy_on(phy);
1616
1617 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1618 if (ret)
1619 return ret;
1620
1621 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
1622
1623 return ret;
1624}
1625
1626static int cdns_torrent_dp_init(struct phy *phy)
1627{
1628 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1629 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1630
1631 switch (cdns_phy->ref_clk_rate) {
1632 case CLK_19_2_MHZ:
1633 case CLK_25_MHZ:
1634 case CLK_100_MHZ:
1635 /* Valid Ref Clock Rate */
1636 break;
1637 default:
1638 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1639 return -EINVAL;
1640 }
1641
1642 cdns_torrent_dp_common_init(cdns_phy, inst);
1643
1644 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1645}
1646
1647static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1648{
1649 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1650
1651 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);
1652 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1653
1654 return 0;
1655}
1656
1657static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1658{
1659 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1660
1661 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1662 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);
1663}
1664
1665static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1666{
1667 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1668 int val;
1669
1670 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);
1671
1672 return !!val;
1673}
1674
1675static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1676 .enable = cdns_torrent_derived_refclk_enable,
1677 .disable = cdns_torrent_derived_refclk_disable,
1678 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1679};
1680
1681static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1682{
1683 struct cdns_torrent_derived_refclk *derived_refclk;
1684 struct device *dev = cdns_phy->dev;
1685 struct clk_init_data *init;
1686 const char *parent_name;
1687 char clk_name[100];
1688 struct clk_hw *hw;
1689 struct clk *clk;
1690 int ret;
1691
1692 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1693 if (!derived_refclk)
1694 return -ENOMEM;
1695
1696 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1697 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);
1698
1699 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1700 if (IS_ERR(clk)) {
1701 dev_err(dev, "No parent clock for derived_refclk\n");
1702 return PTR_ERR(clk);
1703 }
1704
1705 init = &derived_refclk->clk_data;
1706
1707 if (clk) {
1708 parent_name = __clk_get_name(clk);
1709 init->parent_names = &parent_name;
1710 init->num_parents = 1;
1711 }
1712 init->ops = &cdns_torrent_derived_refclk_ops;
1713 init->flags = 0;
1714 init->name = clk_name;
1715
1716 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1717 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1718
1719 derived_refclk->hw.init = init;
1720
1721 hw = &derived_refclk->hw;
1722 ret = devm_clk_hw_register(dev, hw);
1723 if (ret)
1724 return ret;
1725
1726 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;
1727
1728 return 0;
1729}
1730
1731static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)
1732{
1733 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1734
1735 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);
1736
1737 return 0;
1738}
1739
1740static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)
1741{
1742 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1743
1744 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);
1745}
1746
1747static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)
1748{
1749 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1750 int val, cmn_val;
1751
1752 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);
1753 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);
1754
1755 return val && !cmn_val;
1756}
1757
1758static const struct clk_ops cdns_torrent_received_refclk_ops = {
1759 .enable = cdns_torrent_received_refclk_enable,
1760 .disable = cdns_torrent_received_refclk_disable,
1761 .is_enabled = cdns_torrent_received_refclk_is_enabled,
1762};
1763
1764static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)
1765{
1766 struct cdns_torrent_received_refclk *received_refclk;
1767 struct device *dev = cdns_phy->dev;
1768 struct clk_init_data *init;
1769 const char *parent_name;
1770 char clk_name[100];
1771 struct clk_hw *hw;
1772 struct clk *clk;
1773 int ret;
1774
1775 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);
1776 if (!received_refclk)
1777 return -ENOMEM;
1778
1779 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1780 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);
1781
1782 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1783 if (IS_ERR(clk)) {
1784 dev_err(dev, "No parent clock for received_refclk\n");
1785 return PTR_ERR(clk);
1786 }
1787
1788 init = &received_refclk->clk_data;
1789
1790 if (clk) {
1791 parent_name = __clk_get_name(clk);
1792 init->parent_names = &parent_name;
1793 init->num_parents = 1;
1794 }
1795 init->ops = &cdns_torrent_received_refclk_ops;
1796 init->flags = 0;
1797 init->name = clk_name;
1798
1799 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1800 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1801
1802 received_refclk->hw.init = init;
1803
1804 hw = &received_refclk->hw;
1805 ret = devm_clk_hw_register(dev, hw);
1806 if (ret)
1807 return ret;
1808
1809 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;
1810
1811 return 0;
1812}
1813
1814static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)
1815{
1816 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1817
1818 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1819 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1820 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1821
1822 return 0;
1823}
1824
1825static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)
1826{
1827 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1828
1829 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);
1830}
1831
1832static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)
1833{
1834 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1835 int val;
1836
1837 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);
1838
1839 return !val;
1840}
1841
1842static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)
1843{
1844 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1845 unsigned int val;
1846
1847 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);
1848 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);
1849}
1850
1851static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)
1852{
1853 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1854 unsigned int val;
1855
1856 val = cdns_torrent_refclk_driver_mux_table[index];
1857 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);
1858}
1859
1860static const struct clk_ops cdns_torrent_refclk_driver_ops = {
1861 .enable = cdns_torrent_refclk_driver_enable,
1862 .disable = cdns_torrent_refclk_driver_disable,
1863 .is_enabled = cdns_torrent_refclk_driver_is_enabled,
1864 .set_parent = cdns_torrent_refclk_driver_set_parent,
1865 .get_parent = cdns_torrent_refclk_driver_get_parent,
1866};
1867
1868static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)
1869{
1870 struct cdns_torrent_refclk_driver *refclk_driver;
1871 struct device *dev = cdns_phy->dev;
1872 struct regmap_field *field;
1873 struct clk_init_data *init;
1874 const char **parent_names;
1875 unsigned int num_parents;
1876 struct regmap *regmap;
1877 char clk_name[100];
1878 struct clk_hw *hw;
1879 int i, ret;
1880
1881 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);
1882 if (!refclk_driver)
1883 return -ENOMEM;
1884
1885 num_parents = ARRAY_SIZE(refclk_driver_parent_index);
1886 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
1887 if (!parent_names)
1888 return -ENOMEM;
1889
1890 for (i = 0; i < num_parents; i++) {
1891 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];
1892 if (IS_ERR_OR_NULL(hw)) {
1893 dev_err(dev, "No parent clock for refclk driver clock\n");
1894 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;
1895 }
1896 parent_names[i] = clk_hw_get_name(hw);
1897 }
1898
1899 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1900 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
1901
1902 init = &refclk_driver->clk_data;
1903
1904 init->ops = &cdns_torrent_refclk_driver_ops;
1905 init->flags = CLK_SET_RATE_NO_REPARENT;
1906 init->parent_names = parent_names;
1907 init->num_parents = num_parents;
1908 init->name = clk_name;
1909
1910 regmap = cdns_phy->regmap_common_cdb;
1911
1912 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
1913 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
1914 if (IS_ERR(field)) {
1915 dev_err(dev, "Refclk driver CMN reg field init failed\n");
1916 return PTR_ERR(field);
1917 }
1918 refclk_driver->cmn_fields[i] = field;
1919 }
1920
1921 /* Enable Derived reference clock as default */
1922 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
1923
1924 refclk_driver->hw.init = init;
1925
1926 hw = &refclk_driver->hw;
1927 ret = devm_clk_hw_register(dev, hw);
1928 if (ret)
1929 return ret;
1930
1931 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;
1932
1933 return 0;
1934}
1935
1936static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1937 u32 block_offset,
1938 u8 reg_offset_shift,
1939 const struct regmap_config *config)
1940{
1941 struct cdns_regmap_cdb_context *ctx;
1942
1943 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1944 if (!ctx)
1945 return ERR_PTR(-ENOMEM);
1946
1947 ctx->dev = dev;
1948 ctx->base = base + block_offset;
1949 ctx->reg_offset_shift = reg_offset_shift;
1950
1951 return devm_regmap_init(dev, NULL, ctx, config);
1952}
1953
1954static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
1955{
1956 struct device *dev = cdns_phy->dev;
1957 struct regmap_field *field;
1958 struct regmap *regmap;
1959
1960 regmap = cdns_phy->regmap_dptx_phy_reg;
1961 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1962 if (IS_ERR(field)) {
1963 dev_err(dev, "PHY_RESET reg field init failed\n");
1964 return PTR_ERR(field);
1965 }
1966 cdns_phy->phy_reset_ctrl = field;
1967
1968 return 0;
1969}
1970
1971static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
1972{
1973 struct device *dev = cdns_phy->dev;
1974 struct regmap_field *field;
1975 struct regmap *regmap;
1976 int i;
1977
1978 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1979 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1980 if (IS_ERR(field)) {
1981 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1982 return PTR_ERR(field);
1983 }
1984 cdns_phy->phy_pll_cfg = field;
1985
1986 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1987 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
1988 if (IS_ERR(field)) {
1989 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
1990 return PTR_ERR(field);
1991 }
1992 cdns_phy->phy_pipe_cmn_ctrl1_0 = field;
1993
1994 regmap = cdns_phy->regmap_common_cdb;
1995 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);
1996 if (IS_ERR(field)) {
1997 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");
1998 return PTR_ERR(field);
1999 }
2000 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;
2001
2002 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2003 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
2004 if (IS_ERR(field)) {
2005 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
2006 return PTR_ERR(field);
2007 }
2008 cdns_phy->phy_pma_cmn_ctrl_1 = field;
2009
2010 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2011 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
2012 if (IS_ERR(field)) {
2013 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
2014 return PTR_ERR(field);
2015 }
2016 cdns_phy->phy_pma_cmn_ctrl_2 = field;
2017
2018 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2019 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
2020 if (IS_ERR(field)) {
2021 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
2022 return PTR_ERR(field);
2023 }
2024 cdns_phy->phy_pma_pll_raw_ctrl = field;
2025
2026 for (i = 0; i < MAX_NUM_LANES; i++) {
2027 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
2028 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
2029 if (IS_ERR(field)) {
2030 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
2031 return PTR_ERR(field);
2032 }
2033 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
2034 }
2035
2036 return 0;
2037}
2038
2039static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
2040{
2041 void __iomem *base = cdns_phy->base;
2042 struct device *dev = cdns_phy->dev;
2043 struct regmap *regmap;
2044 u8 reg_offset_shift;
2045 u32 block_offset;
2046
2047 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2048
2049 block_offset = TORRENT_DPTX_PHY_OFFSET;
2050 regmap = cdns_regmap_init(dev, base, block_offset,
2051 reg_offset_shift,
2052 &cdns_torrent_dptx_phy_config);
2053 if (IS_ERR(regmap)) {
2054 dev_err(dev, "Failed to init DPTX PHY regmap\n");
2055 return PTR_ERR(regmap);
2056 }
2057 cdns_phy->regmap_dptx_phy_reg = regmap;
2058
2059 return 0;
2060}
2061
2062static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
2063{
2064 void __iomem *sd_base = cdns_phy->sd_base;
2065 u8 block_offset_shift, reg_offset_shift;
2066 struct device *dev = cdns_phy->dev;
2067 struct regmap *regmap;
2068 u32 block_offset;
2069 int i;
2070
2071 block_offset_shift = cdns_phy->init_data->block_offset_shift;
2072 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2073
2074 for (i = 0; i < MAX_NUM_LANES; i++) {
2075 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
2076 reg_offset_shift);
2077 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2078 reg_offset_shift,
2079 &cdns_torrent_tx_lane_cdb_config[i]);
2080 if (IS_ERR(regmap)) {
2081 dev_err(dev, "Failed to init tx lane CDB regmap\n");
2082 return PTR_ERR(regmap);
2083 }
2084 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
2085
2086 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
2087 reg_offset_shift);
2088 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2089 reg_offset_shift,
2090 &cdns_torrent_rx_lane_cdb_config[i]);
2091 if (IS_ERR(regmap)) {
2092 dev_err(dev, "Failed to init rx lane CDB regmap\n");
2093 return PTR_ERR(regmap);
2094 }
2095 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
2096
2097 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
2098 reg_offset_shift);
2099 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2100 reg_offset_shift,
2101 &cdns_torrent_phy_pcs_lane_cdb_config[i]);
2102 if (IS_ERR(regmap)) {
2103 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
2104 return PTR_ERR(regmap);
2105 }
2106 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
2107 }
2108
2109 block_offset = TORRENT_COMMON_CDB_OFFSET;
2110 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2111 reg_offset_shift,
2112 &cdns_torrent_common_cdb_config);
2113 if (IS_ERR(regmap)) {
2114 dev_err(dev, "Failed to init common CDB regmap\n");
2115 return PTR_ERR(regmap);
2116 }
2117 cdns_phy->regmap_common_cdb = regmap;
2118
2119 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
2120 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2121 reg_offset_shift,
2122 &cdns_torrent_phy_pcs_cmn_cdb_config);
2123 if (IS_ERR(regmap)) {
2124 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
2125 return PTR_ERR(regmap);
2126 }
2127 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
2128
2129 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
2130 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2131 reg_offset_shift,
2132 &cdns_torrent_phy_pma_cmn_cdb_config);
2133 if (IS_ERR(regmap)) {
2134 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
2135 return PTR_ERR(regmap);
2136 }
2137 cdns_phy->regmap_phy_pma_common_cdb = regmap;
2138
2139 return 0;
2140}
2141
2142static int cdns_torrent_phy_init(struct phy *phy)
2143{
2144 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
2145 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2146 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2147 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2148 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2149 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
2150 enum cdns_torrent_phy_type phy_type = inst->phy_type;
2151 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
2152 struct cdns_torrent_vals *pcs_cmn_vals;
2153 struct cdns_reg_pairs *reg_pairs;
2154 struct regmap *regmap;
2155 u32 num_regs;
2156 int i, j;
2157
2158 if (cdns_phy->nsubnodes > 1)
2159 return 0;
2160
2161 /**
2162 * Spread spectrum generation is not required or supported
2163 * for SGMII/QSGMII
2164 */
2165 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
2166 ssc = NO_SSC;
2167
2168 /* PHY configuration specific registers for single link */
2169 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
2170 if (link_cmn_vals) {
2171 reg_pairs = link_cmn_vals->reg_pairs;
2172 num_regs = link_cmn_vals->num_regs;
2173 regmap = cdns_phy->regmap_common_cdb;
2174
2175 /**
2176 * First array value in link_cmn_vals must be of
2177 * PHY_PLL_CFG register
2178 */
2179 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2180
2181 for (i = 1; i < num_regs; i++)
2182 regmap_write(regmap, reg_pairs[i].off,
2183 reg_pairs[i].val);
2184 }
2185
2186 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
2187 if (xcvr_diag_vals) {
2188 reg_pairs = xcvr_diag_vals->reg_pairs;
2189 num_regs = xcvr_diag_vals->num_regs;
2190 for (i = 0; i < inst->num_lanes; i++) {
2191 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2192 for (j = 0; j < num_regs; j++)
2193 regmap_write(regmap, reg_pairs[j].off,
2194 reg_pairs[j].val);
2195 }
2196 }
2197
2198 /* PHY PCS common registers configurations */
2199 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
2200 if (pcs_cmn_vals) {
2201 reg_pairs = pcs_cmn_vals->reg_pairs;
2202 num_regs = pcs_cmn_vals->num_regs;
2203 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2204 for (i = 0; i < num_regs; i++)
2205 regmap_write(regmap, reg_pairs[i].off,
2206 reg_pairs[i].val);
2207 }
2208
2209 /* PMA common registers configurations */
2210 cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2211 if (cmn_vals) {
2212 reg_pairs = cmn_vals->reg_pairs;
2213 num_regs = cmn_vals->num_regs;
2214 regmap = cdns_phy->regmap_common_cdb;
2215 for (i = 0; i < num_regs; i++)
2216 regmap_write(regmap, reg_pairs[i].off,
2217 reg_pairs[i].val);
2218 }
2219
2220 /* PMA TX lane registers configurations */
2221 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2222 if (tx_ln_vals) {
2223 reg_pairs = tx_ln_vals->reg_pairs;
2224 num_regs = tx_ln_vals->num_regs;
2225 for (i = 0; i < inst->num_lanes; i++) {
2226 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2227 for (j = 0; j < num_regs; j++)
2228 regmap_write(regmap, reg_pairs[j].off,
2229 reg_pairs[j].val);
2230 }
2231 }
2232
2233 /* PMA RX lane registers configurations */
2234 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2235 if (rx_ln_vals) {
2236 reg_pairs = rx_ln_vals->reg_pairs;
2237 num_regs = rx_ln_vals->num_regs;
2238 for (i = 0; i < inst->num_lanes; i++) {
2239 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2240 for (j = 0; j < num_regs; j++)
2241 regmap_write(regmap, reg_pairs[j].off,
2242 reg_pairs[j].val);
2243 }
2244 }
2245
2246 if (phy_type == TYPE_DP)
2247 return cdns_torrent_dp_init(phy);
2248
2249 return 0;
2250}
2251
2252static const struct phy_ops cdns_torrent_phy_ops = {
2253 .init = cdns_torrent_phy_init,
2254 .configure = cdns_torrent_dp_configure,
2255 .power_on = cdns_torrent_phy_on,
2256 .power_off = cdns_torrent_phy_off,
2257 .owner = THIS_MODULE,
2258};
2259
2260static int cdns_torrent_noop_phy_on(struct phy *phy)
2261{
2262 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
2263 usleep_range(5000, 10000);
2264
2265 return 0;
2266}
2267
2268static const struct phy_ops noop_ops = {
2269 .power_on = cdns_torrent_noop_phy_on,
2270 .owner = THIS_MODULE,
2271};
2272
2273static
2274int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2275{
2276 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2277 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2278 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2279 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2280 enum cdns_torrent_phy_type phy_t1, phy_t2;
2281 struct cdns_torrent_vals *pcs_cmn_vals;
2282 int i, j, node, mlane, num_lanes, ret;
2283 struct cdns_reg_pairs *reg_pairs;
2284 enum cdns_torrent_ssc_mode ssc;
2285 struct regmap *regmap;
2286 u32 num_regs;
2287
2288 /* Maximum 2 links (subnodes) are supported */
2289 if (cdns_phy->nsubnodes != 2)
2290 return -EINVAL;
2291
2292 phy_t1 = cdns_phy->phys[0].phy_type;
2293 phy_t2 = cdns_phy->phys[1].phy_type;
2294
2295 /**
2296 * First configure the PHY for first link with phy_t1. Get the array
2297 * values as [phy_t1][phy_t2][ssc].
2298 */
2299 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2300 if (node == 1) {
2301 /**
2302 * If first link with phy_t1 is configured, then
2303 * configure the PHY for second link with phy_t2.
2304 * Get the array values as [phy_t2][phy_t1][ssc].
2305 */
2306 swap(phy_t1, phy_t2);
2307 }
2308
2309 mlane = cdns_phy->phys[node].mlane;
2310 ssc = cdns_phy->phys[node].ssc_mode;
2311 num_lanes = cdns_phy->phys[node].num_lanes;
2312
2313 /**
2314 * PHY configuration specific registers:
2315 * link_cmn_vals depend on combination of PHY types being
2316 * configured and are common for both PHY types, so array
2317 * values should be same for [phy_t1][phy_t2][ssc] and
2318 * [phy_t2][phy_t1][ssc].
2319 * xcvr_diag_vals also depend on combination of PHY types
2320 * being configured, but these can be different for particular
2321 * PHY type and are per lane.
2322 */
2323 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
2324 if (link_cmn_vals) {
2325 reg_pairs = link_cmn_vals->reg_pairs;
2326 num_regs = link_cmn_vals->num_regs;
2327 regmap = cdns_phy->regmap_common_cdb;
2328
2329 /**
2330 * First array value in link_cmn_vals must be of
2331 * PHY_PLL_CFG register
2332 */
2333 regmap_field_write(cdns_phy->phy_pll_cfg,
2334 reg_pairs[0].val);
2335
2336 for (i = 1; i < num_regs; i++)
2337 regmap_write(regmap, reg_pairs[i].off,
2338 reg_pairs[i].val);
2339 }
2340
2341 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
2342 if (xcvr_diag_vals) {
2343 reg_pairs = xcvr_diag_vals->reg_pairs;
2344 num_regs = xcvr_diag_vals->num_regs;
2345 for (i = 0; i < num_lanes; i++) {
2346 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2347 for (j = 0; j < num_regs; j++)
2348 regmap_write(regmap, reg_pairs[j].off,
2349 reg_pairs[j].val);
2350 }
2351 }
2352
2353 /* PHY PCS common registers configurations */
2354 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
2355 if (pcs_cmn_vals) {
2356 reg_pairs = pcs_cmn_vals->reg_pairs;
2357 num_regs = pcs_cmn_vals->num_regs;
2358 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2359 for (i = 0; i < num_regs; i++)
2360 regmap_write(regmap, reg_pairs[i].off,
2361 reg_pairs[i].val);
2362 }
2363
2364 /* PMA common registers configurations */
2365 cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc];
2366 if (cmn_vals) {
2367 reg_pairs = cmn_vals->reg_pairs;
2368 num_regs = cmn_vals->num_regs;
2369 regmap = cdns_phy->regmap_common_cdb;
2370 for (i = 0; i < num_regs; i++)
2371 regmap_write(regmap, reg_pairs[i].off,
2372 reg_pairs[i].val);
2373 }
2374
2375 /* PMA TX lane registers configurations */
2376 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2377 if (tx_ln_vals) {
2378 reg_pairs = tx_ln_vals->reg_pairs;
2379 num_regs = tx_ln_vals->num_regs;
2380 for (i = 0; i < num_lanes; i++) {
2381 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2382 for (j = 0; j < num_regs; j++)
2383 regmap_write(regmap, reg_pairs[j].off,
2384 reg_pairs[j].val);
2385 }
2386 }
2387
2388 /* PMA RX lane registers configurations */
2389 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2390 if (rx_ln_vals) {
2391 reg_pairs = rx_ln_vals->reg_pairs;
2392 num_regs = rx_ln_vals->num_regs;
2393 for (i = 0; i < num_lanes; i++) {
2394 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2395 for (j = 0; j < num_regs; j++)
2396 regmap_write(regmap, reg_pairs[j].off,
2397 reg_pairs[j].val);
2398 }
2399 }
2400
2401 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2402 }
2403
2404 /* Take the PHY out of reset */
2405 ret = reset_control_deassert(cdns_phy->phy_rst);
2406 if (ret)
2407 return ret;
2408
2409 return 0;
2410}
2411
2412static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2413{
2414 struct device *dev = cdns_phy->dev;
2415
2416 of_clk_del_provider(dev->of_node);
2417}
2418
2419static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2420{
2421 struct device *dev = cdns_phy->dev;
2422 struct device_node *node = dev->of_node;
2423 struct clk_hw_onecell_data *data;
2424 int ret;
2425
2426 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);
2427 if (!data)
2428 return -ENOMEM;
2429
2430 data->num = CDNS_TORRENT_OUTPUT_CLOCKS;
2431 cdns_phy->clk_hw_data = data;
2432
2433 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2434 if (ret) {
2435 dev_err(dev, "failed to register derived refclk\n");
2436 return ret;
2437 }
2438
2439 ret = cdns_torrent_received_refclk_register(cdns_phy);
2440 if (ret) {
2441 dev_err(dev, "failed to register received refclk\n");
2442 return ret;
2443 }
2444
2445 ret = cdns_torrent_refclk_driver_register(cdns_phy);
2446 if (ret) {
2447 dev_err(dev, "failed to register refclk driver\n");
2448 return ret;
2449 }
2450
2451 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
2452 if (ret) {
2453 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2454 return ret;
2455 }
2456
2457 return 0;
2458}
2459
2460static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2461{
2462 struct device *dev = cdns_phy->dev;
2463
2464 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2465 if (IS_ERR(cdns_phy->phy_rst)) {
2466 dev_err(dev, "%s: failed to get reset\n",
2467 dev->of_node->full_name);
2468 return PTR_ERR(cdns_phy->phy_rst);
2469 }
2470
2471 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2472 if (IS_ERR(cdns_phy->apb_rst)) {
2473 dev_err(dev, "%s: failed to get apb reset\n",
2474 dev->of_node->full_name);
2475 return PTR_ERR(cdns_phy->apb_rst);
2476 }
2477
2478 return 0;
2479}
2480
2481static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2482{
2483 struct device *dev = cdns_phy->dev;
2484 unsigned long ref_clk_rate;
2485 int ret;
2486
2487 cdns_phy->clk = devm_clk_get(dev, "refclk");
2488 if (IS_ERR(cdns_phy->clk)) {
2489 dev_err(dev, "phy ref clock not found\n");
2490 return PTR_ERR(cdns_phy->clk);
2491 }
2492
2493 ret = clk_prepare_enable(cdns_phy->clk);
2494 if (ret) {
2495 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2496 return ret;
2497 }
2498
2499 ref_clk_rate = clk_get_rate(cdns_phy->clk);
2500 if (!ref_clk_rate) {
2501 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2502 clk_disable_unprepare(cdns_phy->clk);
2503 return -EINVAL;
2504 }
2505
2506 switch (ref_clk_rate) {
2507 case REF_CLK_19_2MHZ:
2508 cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
2509 break;
2510 case REF_CLK_25MHZ:
2511 cdns_phy->ref_clk_rate = CLK_25_MHZ;
2512 break;
2513 case REF_CLK_100MHZ:
2514 cdns_phy->ref_clk_rate = CLK_100_MHZ;
2515 break;
2516 default:
2517 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2518 clk_disable_unprepare(cdns_phy->clk);
2519 return -EINVAL;
2520 }
2521
2522 return 0;
2523}
2524
2525static int cdns_torrent_phy_probe(struct platform_device *pdev)
2526{
2527 struct cdns_torrent_phy *cdns_phy;
2528 struct device *dev = &pdev->dev;
2529 struct phy_provider *phy_provider;
2530 const struct cdns_torrent_data *data;
2531 struct device_node *child;
2532 int ret, subnodes, node = 0, i;
2533 u32 total_num_lanes = 0;
2534 int already_configured;
2535 u8 init_dp_regmap = 0;
2536 u32 phy_type;
2537
2538 /* Get init data for this PHY */
2539 data = of_device_get_match_data(dev);
2540 if (!data)
2541 return -EINVAL;
2542
2543 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2544 if (!cdns_phy)
2545 return -ENOMEM;
2546
2547 dev_set_drvdata(dev, cdns_phy);
2548 cdns_phy->dev = dev;
2549 cdns_phy->init_data = data;
2550
2551 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2552 if (IS_ERR(cdns_phy->sd_base))
2553 return PTR_ERR(cdns_phy->sd_base);
2554
2555 subnodes = of_get_available_child_count(dev->of_node);
2556 if (subnodes == 0) {
2557 dev_err(dev, "No available link subnodes found\n");
2558 return -EINVAL;
2559 }
2560
2561 ret = cdns_torrent_regmap_init(cdns_phy);
2562 if (ret)
2563 return ret;
2564
2565 ret = cdns_torrent_regfield_init(cdns_phy);
2566 if (ret)
2567 return ret;
2568
2569 ret = cdns_torrent_clk_register(cdns_phy);
2570 if (ret)
2571 return ret;
2572
2573 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2574
2575 if (!already_configured) {
2576 ret = cdns_torrent_reset(cdns_phy);
2577 if (ret)
2578 goto clk_cleanup;
2579
2580 ret = cdns_torrent_clk(cdns_phy);
2581 if (ret)
2582 goto clk_cleanup;
2583
2584 /* Enable APB */
2585 reset_control_deassert(cdns_phy->apb_rst);
2586 }
2587
2588 for_each_available_child_of_node(dev->of_node, child) {
2589 struct phy *gphy;
2590
2591 /* PHY subnode name must be 'phy'. */
2592 if (!(of_node_name_eq(child, "phy")))
2593 continue;
2594
2595 cdns_phy->phys[node].lnk_rst =
2596 of_reset_control_array_get_exclusive(child);
2597 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2598 dev_err(dev, "%s: failed to get reset\n",
2599 child->full_name);
2600 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2601 goto put_lnk_rst;
2602 }
2603
2604 if (of_property_read_u32(child, "reg",
2605 &cdns_phy->phys[node].mlane)) {
2606 dev_err(dev, "%s: No \"reg\"-property.\n",
2607 child->full_name);
2608 ret = -EINVAL;
2609 goto put_child;
2610 }
2611
2612 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2613 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2614 child->full_name);
2615 ret = -EINVAL;
2616 goto put_child;
2617 }
2618
2619 switch (phy_type) {
2620 case PHY_TYPE_PCIE:
2621 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2622 break;
2623 case PHY_TYPE_DP:
2624 cdns_phy->phys[node].phy_type = TYPE_DP;
2625 break;
2626 case PHY_TYPE_SGMII:
2627 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2628 break;
2629 case PHY_TYPE_QSGMII:
2630 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2631 break;
2632 case PHY_TYPE_USB3:
2633 cdns_phy->phys[node].phy_type = TYPE_USB;
2634 break;
2635 default:
2636 dev_err(dev, "Unsupported protocol\n");
2637 ret = -EINVAL;
2638 goto put_child;
2639 }
2640
2641 if (of_property_read_u32(child, "cdns,num-lanes",
2642 &cdns_phy->phys[node].num_lanes)) {
2643 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2644 child->full_name);
2645 ret = -EINVAL;
2646 goto put_child;
2647 }
2648
2649 total_num_lanes += cdns_phy->phys[node].num_lanes;
2650
2651 /* Get SSC mode */
2652 cdns_phy->phys[node].ssc_mode = NO_SSC;
2653 of_property_read_u32(child, "cdns,ssc-mode",
2654 &cdns_phy->phys[node].ssc_mode);
2655
2656 if (!already_configured)
2657 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2658 else
2659 gphy = devm_phy_create(dev, child, &noop_ops);
2660 if (IS_ERR(gphy)) {
2661 ret = PTR_ERR(gphy);
2662 goto put_child;
2663 }
2664
2665 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2666 switch (cdns_phy->phys[node].num_lanes) {
2667 case 1:
2668 case 2:
2669 case 4:
2670 /* valid number of lanes */
2671 break;
2672 default:
2673 dev_err(dev, "unsupported number of lanes: %d\n",
2674 cdns_phy->phys[node].num_lanes);
2675 ret = -EINVAL;
2676 goto put_child;
2677 }
2678
2679 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2680 of_property_read_u32(child, "cdns,max-bit-rate",
2681 &cdns_phy->max_bit_rate);
2682
2683 switch (cdns_phy->max_bit_rate) {
2684 case 1620:
2685 case 2160:
2686 case 2430:
2687 case 2700:
2688 case 3240:
2689 case 4320:
2690 case 5400:
2691 case 8100:
2692 /* valid bit rate */
2693 break;
2694 default:
2695 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2696 cdns_phy->max_bit_rate);
2697 ret = -EINVAL;
2698 goto put_child;
2699 }
2700
2701 /* DPTX registers */
2702 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2703 if (IS_ERR(cdns_phy->base)) {
2704 ret = PTR_ERR(cdns_phy->base);
2705 goto put_child;
2706 }
2707
2708 if (!init_dp_regmap) {
2709 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2710 if (ret)
2711 goto put_child;
2712
2713 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2714 if (ret)
2715 goto put_child;
2716
2717 init_dp_regmap++;
2718 }
2719
2720 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
2721 cdns_phy->max_bit_rate / 1000,
2722 cdns_phy->max_bit_rate % 1000);
2723
2724 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2725 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2726 gphy->attrs.mode = PHY_MODE_DP;
2727 }
2728
2729 cdns_phy->phys[node].phy = gphy;
2730 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2731
2732 node++;
2733 }
2734 cdns_phy->nsubnodes = node;
2735
2736 if (total_num_lanes > MAX_NUM_LANES) {
2737 dev_err(dev, "Invalid lane configuration\n");
2738 ret = -EINVAL;
2739 goto put_lnk_rst;
2740 }
2741
2742 if (cdns_phy->nsubnodes > 1 && !already_configured) {
2743 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2744 if (ret)
2745 goto put_lnk_rst;
2746 }
2747
2748 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2749 if (IS_ERR(phy_provider)) {
2750 ret = PTR_ERR(phy_provider);
2751 goto put_lnk_rst;
2752 }
2753
2754 if (cdns_phy->nsubnodes > 1)
2755 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
2756 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2757 cdns_phy->phys[0].num_lanes,
2758 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
2759 cdns_phy->phys[1].num_lanes);
2760 else
2761 dev_dbg(dev, "Single link: %s (%d lanes)",
2762 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2763 cdns_phy->phys[0].num_lanes);
2764
2765 return 0;
2766
2767put_child:
2768 node++;
2769put_lnk_rst:
2770 for (i = 0; i < node; i++)
2771 reset_control_put(cdns_phy->phys[i].lnk_rst);
2772 of_node_put(child);
2773 reset_control_assert(cdns_phy->apb_rst);
2774 clk_disable_unprepare(cdns_phy->clk);
2775clk_cleanup:
2776 cdns_torrent_clk_cleanup(cdns_phy);
2777 return ret;
2778}
2779
2780static int cdns_torrent_phy_remove(struct platform_device *pdev)
2781{
2782 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2783 int i;
2784
2785 reset_control_assert(cdns_phy->phy_rst);
2786 reset_control_assert(cdns_phy->apb_rst);
2787 for (i = 0; i < cdns_phy->nsubnodes; i++) {
2788 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2789 reset_control_put(cdns_phy->phys[i].lnk_rst);
2790 }
2791
2792 clk_disable_unprepare(cdns_phy->clk);
2793 cdns_torrent_clk_cleanup(cdns_phy);
2794
2795 return 0;
2796}
2797
2798/* Single DisplayPort(DP) link configuration */
2799static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
2800 {0x0000, PHY_PLL_CFG},
2801};
2802
2803static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
2804 {0x0000, XCVR_DIAG_HSCLK_SEL},
2805 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
2806};
2807
2808static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
2809 .reg_pairs = sl_dp_link_cmn_regs,
2810 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
2811};
2812
2813static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
2814 .reg_pairs = sl_dp_xcvr_diag_ln_regs,
2815 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
2816};
2817
2818/* Single DP, 19.2 MHz Ref clk, no SSC */
2819static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
2820 {0x0014, CMN_SSM_BIAS_TMR},
2821 {0x0027, CMN_PLLSM0_PLLPRE_TMR},
2822 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
2823 {0x0027, CMN_PLLSM1_PLLPRE_TMR},
2824 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
2825 {0x0060, CMN_BGCAL_INIT_TMR},
2826 {0x0060, CMN_BGCAL_ITER_TMR},
2827 {0x0014, CMN_IBCAL_INIT_TMR},
2828 {0x0018, CMN_TXPUCAL_INIT_TMR},
2829 {0x0005, CMN_TXPUCAL_ITER_TMR},
2830 {0x0018, CMN_TXPDCAL_INIT_TMR},
2831 {0x0005, CMN_TXPDCAL_ITER_TMR},
2832 {0x0240, CMN_RXCAL_INIT_TMR},
2833 {0x0005, CMN_RXCAL_ITER_TMR},
2834 {0x0002, CMN_SD_CAL_INIT_TMR},
2835 {0x0002, CMN_SD_CAL_ITER_TMR},
2836 {0x000B, CMN_SD_CAL_REFTIM_START},
2837 {0x0137, CMN_SD_CAL_PLLCNT_START},
2838 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2839 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2840 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2841 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2842 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2843 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2844 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2845 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2846 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
2847 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
2848 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
2849 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
2850 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
2851 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2852 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
2853 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2854};
2855
2856static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
2857 {0x0780, TX_RCVDET_ST_TMR},
2858 {0x00FB, TX_PSC_A0},
2859 {0x04AA, TX_PSC_A2},
2860 {0x04AA, TX_PSC_A3},
2861 {0x000F, XCVR_DIAG_BIDI_CTRL}
2862};
2863
2864static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
2865 {0x0000, RX_PSC_A0},
2866 {0x0000, RX_PSC_A2},
2867 {0x0000, RX_PSC_A3},
2868 {0x0000, RX_PSC_CAL},
2869 {0x0000, RX_REE_GCSM1_CTRL},
2870 {0x0000, RX_REE_GCSM2_CTRL},
2871 {0x0000, RX_REE_PERGCSM_CTRL}
2872};
2873
2874static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
2875 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
2876 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
2877};
2878
2879static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
2880 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
2881 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
2882};
2883
2884static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
2885 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
2886 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
2887};
2888
2889/* Single DP, 25 MHz Ref clk, no SSC */
2890static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
2891 {0x0019, CMN_SSM_BIAS_TMR},
2892 {0x0032, CMN_PLLSM0_PLLPRE_TMR},
2893 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
2894 {0x0032, CMN_PLLSM1_PLLPRE_TMR},
2895 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
2896 {0x007D, CMN_BGCAL_INIT_TMR},
2897 {0x007D, CMN_BGCAL_ITER_TMR},
2898 {0x0019, CMN_IBCAL_INIT_TMR},
2899 {0x001E, CMN_TXPUCAL_INIT_TMR},
2900 {0x0006, CMN_TXPUCAL_ITER_TMR},
2901 {0x001E, CMN_TXPDCAL_INIT_TMR},
2902 {0x0006, CMN_TXPDCAL_ITER_TMR},
2903 {0x02EE, CMN_RXCAL_INIT_TMR},
2904 {0x0006, CMN_RXCAL_ITER_TMR},
2905 {0x0002, CMN_SD_CAL_INIT_TMR},
2906 {0x0002, CMN_SD_CAL_ITER_TMR},
2907 {0x000E, CMN_SD_CAL_REFTIM_START},
2908 {0x012B, CMN_SD_CAL_PLLCNT_START},
2909 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2910 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2911 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2912 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2913 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2914 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2915 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2916 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2917 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
2918 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
2919 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
2920 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
2921 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
2922 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2923 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
2924 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2925};
2926
2927static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
2928 {0x09C4, TX_RCVDET_ST_TMR},
2929 {0x00FB, TX_PSC_A0},
2930 {0x04AA, TX_PSC_A2},
2931 {0x04AA, TX_PSC_A3},
2932 {0x000F, XCVR_DIAG_BIDI_CTRL}
2933};
2934
2935static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
2936 {0x0000, RX_PSC_A0},
2937 {0x0000, RX_PSC_A2},
2938 {0x0000, RX_PSC_A3},
2939 {0x0000, RX_PSC_CAL},
2940 {0x0000, RX_REE_GCSM1_CTRL},
2941 {0x0000, RX_REE_GCSM2_CTRL},
2942 {0x0000, RX_REE_PERGCSM_CTRL}
2943};
2944
2945static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
2946 .reg_pairs = sl_dp_25_no_ssc_cmn_regs,
2947 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
2948};
2949
2950static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
2951 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
2952 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
2953};
2954
2955static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
2956 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
2957 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
2958};
2959
2960/* Single DP, 100 MHz Ref clk, no SSC */
2961static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
2962 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2963 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2964};
2965
2966static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
2967 {0x00FB, TX_PSC_A0},
2968 {0x04AA, TX_PSC_A2},
2969 {0x04AA, TX_PSC_A3},
2970 {0x000F, XCVR_DIAG_BIDI_CTRL}
2971};
2972
2973static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
2974 {0x0000, RX_PSC_A0},
2975 {0x0000, RX_PSC_A2},
2976 {0x0000, RX_PSC_A3},
2977 {0x0000, RX_PSC_CAL},
2978 {0x0000, RX_REE_GCSM1_CTRL},
2979 {0x0000, RX_REE_GCSM2_CTRL},
2980 {0x0000, RX_REE_PERGCSM_CTRL}
2981};
2982
2983static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
2984 .reg_pairs = sl_dp_100_no_ssc_cmn_regs,
2985 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
2986};
2987
2988static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
2989 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
2990 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
2991};
2992
2993static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
2994 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
2995 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
2996};
2997
2998/* USB and SGMII/QSGMII link configuration */
2999static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
3000 {0x0002, PHY_PLL_CFG},
3001 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
3002 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3003};
3004
3005static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
3006 {0x0000, XCVR_DIAG_HSCLK_SEL},
3007 {0x0001, XCVR_DIAG_HSCLK_DIV},
3008 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3009};
3010
3011static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
3012 {0x0011, XCVR_DIAG_HSCLK_SEL},
3013 {0x0003, XCVR_DIAG_HSCLK_DIV},
3014 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3015};
3016
3017static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
3018 .reg_pairs = usb_sgmii_link_cmn_regs,
3019 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
3020};
3021
3022static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
3023 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
3024 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
3025};
3026
3027static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
3028 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
3029 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
3030};
3031
3032/* PCIe and USB Unique SSC link configuration */
3033static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
3034 {0x0003, PHY_PLL_CFG},
3035 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3036 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3037 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
3038};
3039
3040static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
3041 {0x0000, XCVR_DIAG_HSCLK_SEL},
3042 {0x0001, XCVR_DIAG_HSCLK_DIV},
3043 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3044};
3045
3046static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
3047 {0x0011, XCVR_DIAG_HSCLK_SEL},
3048 {0x0001, XCVR_DIAG_HSCLK_DIV},
3049 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
3050};
3051
3052static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
3053 .reg_pairs = pcie_usb_link_cmn_regs,
3054 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
3055};
3056
3057static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
3058 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
3059 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
3060};
3061
3062static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
3063 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
3064 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
3065};
3066
3067/* USB 100 MHz Ref clk, internal SSC */
3068static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
3069 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3070 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3071 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3072 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3073 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3074 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3075 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3076 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3077 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3078 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3079 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3080 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3081 {0x0064, CMN_PLL0_INTDIV_M0},
3082 {0x0050, CMN_PLL0_INTDIV_M1},
3083 {0x0064, CMN_PLL1_INTDIV_M0},
3084 {0x0002, CMN_PLL0_FRACDIVH_M0},
3085 {0x0002, CMN_PLL0_FRACDIVH_M1},
3086 {0x0002, CMN_PLL1_FRACDIVH_M0},
3087 {0x0044, CMN_PLL0_HIGH_THR_M0},
3088 {0x0036, CMN_PLL0_HIGH_THR_M1},
3089 {0x0044, CMN_PLL1_HIGH_THR_M0},
3090 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3091 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3092 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3093 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3094 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3095 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3096 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3097 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3098 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3099 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3100 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3101 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3102 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3103 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3104 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3105 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3106 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3107 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3108 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3109 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3110 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3111 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3112 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3113 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3114 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3115 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3116 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3117 {0x007F, CMN_TXPUCAL_TUNE},
3118 {0x007F, CMN_TXPDCAL_TUNE}
3119};
3120
3121static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
3122 .reg_pairs = usb_100_int_ssc_cmn_regs,
3123 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
3124};
3125
3126/* Single USB link configuration */
3127static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
3128 {0x0000, PHY_PLL_CFG},
3129 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3130};
3131
3132static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
3133 {0x0000, XCVR_DIAG_HSCLK_SEL},
3134 {0x0001, XCVR_DIAG_HSCLK_DIV},
3135 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3136};
3137
3138static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
3139 .reg_pairs = sl_usb_link_cmn_regs,
3140 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
3141};
3142
3143static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
3144 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
3145 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
3146};
3147
3148/* USB PHY PCS common configuration */
3149static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
3150 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
3151 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
3152 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
3153};
3154
3155static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
3156 .reg_pairs = usb_phy_pcs_cmn_regs,
3157 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
3158};
3159
3160/* USB 100 MHz Ref clk, no SSC */
3161static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
3162 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3163 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3164 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3165 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3166 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3167 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3168 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3169};
3170
3171static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
3172 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
3173 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
3174};
3175
3176static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
3177 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3178 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3179 {0x007F, CMN_TXPUCAL_TUNE},
3180 {0x007F, CMN_TXPDCAL_TUNE}
3181};
3182
3183static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
3184 {0x02FF, TX_PSC_A0},
3185 {0x06AF, TX_PSC_A1},
3186 {0x06AE, TX_PSC_A2},
3187 {0x06AE, TX_PSC_A3},
3188 {0x2A82, TX_TXCC_CTRL},
3189 {0x0014, TX_TXCC_CPOST_MULT_01},
3190 {0x0003, XCVR_DIAG_PSC_OVRD}
3191};
3192
3193static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
3194 {0x0D1D, RX_PSC_A0},
3195 {0x0D1D, RX_PSC_A1},
3196 {0x0D00, RX_PSC_A2},
3197 {0x0500, RX_PSC_A3},
3198 {0x0013, RX_SIGDET_HL_FILT_TMR},
3199 {0x0000, RX_REE_GCSM1_CTRL},
3200 {0x0C02, RX_REE_ATTEN_THR},
3201 {0x0330, RX_REE_SMGM_CTRL1},
3202 {0x0300, RX_REE_SMGM_CTRL2},
3203 {0x0019, RX_REE_TAP1_CLIP},
3204 {0x0019, RX_REE_TAP2TON_CLIP},
3205 {0x1004, RX_DIAG_SIGDET_TUNE},
3206 {0x00F9, RX_DIAG_NQST_CTRL},
3207 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3208 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3209 {0x0000, RX_DIAG_PI_CAP},
3210 {0x0031, RX_DIAG_PI_RATE},
3211 {0x0001, RX_DIAG_ACYA},
3212 {0x018C, RX_CDRLF_CNFG},
3213 {0x0003, RX_CDRLF_CNFG3}
3214};
3215
3216static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
3217 .reg_pairs = usb_100_no_ssc_cmn_regs,
3218 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
3219};
3220
3221static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
3222 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
3223 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
3224};
3225
3226static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
3227 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
3228 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
3229};
3230
3231/* Single link USB, 100 MHz Ref clk, internal SSC */
3232static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
3233 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3234 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3235 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3236 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3237 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3238 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3239 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3240 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3241 {0x0064, CMN_PLL0_INTDIV_M0},
3242 {0x0064, CMN_PLL1_INTDIV_M0},
3243 {0x0002, CMN_PLL0_FRACDIVH_M0},
3244 {0x0002, CMN_PLL1_FRACDIVH_M0},
3245 {0x0044, CMN_PLL0_HIGH_THR_M0},
3246 {0x0044, CMN_PLL1_HIGH_THR_M0},
3247 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3248 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3249 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3250 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3251 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3252 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3253 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3254 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3255 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3256 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3257 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3258 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3259 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3260 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3261 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3262 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3263 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3264 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3265 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3266 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3267 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3268 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3269 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3270 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3271};
3272
3273static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
3274 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
3275 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
3276};
3277
3278/* PCIe and SGMII/QSGMII Unique SSC link configuration */
3279static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
3280 {0x0003, PHY_PLL_CFG},
3281 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3282 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3283 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3284};
3285
3286static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
3287 {0x0000, XCVR_DIAG_HSCLK_SEL},
3288 {0x0001, XCVR_DIAG_HSCLK_DIV},
3289 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3290};
3291
3292static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
3293 {0x0011, XCVR_DIAG_HSCLK_SEL},
3294 {0x0003, XCVR_DIAG_HSCLK_DIV},
3295 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3296};
3297
3298static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
3299 .reg_pairs = pcie_sgmii_link_cmn_regs,
3300 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
3301};
3302
3303static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
3304 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
3305 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
3306};
3307
3308static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
3309 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
3310 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
3311};
3312
3313/* SGMII 100 MHz Ref clk, no SSC */
3314static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
3315 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3316 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3317 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3318 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3319 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3320};
3321
3322static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
3323 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
3324 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
3325};
3326
3327static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
3328 {0x007F, CMN_TXPUCAL_TUNE},
3329 {0x007F, CMN_TXPDCAL_TUNE}
3330};
3331
3332static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
3333 {0x00F3, TX_PSC_A0},
3334 {0x04A2, TX_PSC_A2},
3335 {0x04A2, TX_PSC_A3},
3336 {0x0000, TX_TXCC_CPOST_MULT_00},
3337 {0x00B3, DRV_DIAG_TX_DRV}
3338};
3339
3340static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
3341 {0x00F3, TX_PSC_A0},
3342 {0x04A2, TX_PSC_A2},
3343 {0x04A2, TX_PSC_A3},
3344 {0x0000, TX_TXCC_CPOST_MULT_00},
3345 {0x00B3, DRV_DIAG_TX_DRV},
3346 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3347};
3348
3349static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
3350 {0x091D, RX_PSC_A0},
3351 {0x0900, RX_PSC_A2},
3352 {0x0100, RX_PSC_A3},
3353 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3354 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3355 {0x0000, RX_DIAG_DFE_CTRL},
3356 {0x0019, RX_REE_TAP1_CLIP},
3357 {0x0019, RX_REE_TAP2TON_CLIP},
3358 {0x0098, RX_DIAG_NQST_CTRL},
3359 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3360 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3361 {0x0000, RX_DIAG_PI_CAP},
3362 {0x0010, RX_DIAG_PI_RATE},
3363 {0x0001, RX_DIAG_ACYA},
3364 {0x018C, RX_CDRLF_CNFG},
3365};
3366
3367static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
3368 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
3369 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
3370};
3371
3372static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
3373 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
3374 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
3375};
3376
3377static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
3378 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
3379 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
3380};
3381
3382static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
3383 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
3384 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
3385};
3386
3387/* SGMII 100 MHz Ref clk, internal SSC */
3388static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
3389 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3390 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3391 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3392 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3393 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3394 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3395 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3396 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3397 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3398 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3399 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3400 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3401 {0x0064, CMN_PLL0_INTDIV_M0},
3402 {0x0050, CMN_PLL0_INTDIV_M1},
3403 {0x0064, CMN_PLL1_INTDIV_M0},
3404 {0x0002, CMN_PLL0_FRACDIVH_M0},
3405 {0x0002, CMN_PLL0_FRACDIVH_M1},
3406 {0x0002, CMN_PLL1_FRACDIVH_M0},
3407 {0x0044, CMN_PLL0_HIGH_THR_M0},
3408 {0x0036, CMN_PLL0_HIGH_THR_M1},
3409 {0x0044, CMN_PLL1_HIGH_THR_M0},
3410 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3411 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3412 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3413 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3414 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3415 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3416 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3417 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3418 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3419 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3420 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3421 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3422 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3423 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3424 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3425 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3426 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3427 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3428 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3429 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3430 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3431 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3432 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3433 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3434 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3435 {0x007F, CMN_TXPUCAL_TUNE},
3436 {0x007F, CMN_TXPDCAL_TUNE}
3437};
3438
3439static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
3440 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
3441 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
3442};
3443
3444/* QSGMII 100 MHz Ref clk, no SSC */
3445static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
3446 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3447 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3448 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3449 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3450 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3451};
3452
3453static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
3454 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
3455 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
3456};
3457
3458static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
3459 {0x007F, CMN_TXPUCAL_TUNE},
3460 {0x007F, CMN_TXPDCAL_TUNE}
3461};
3462
3463static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
3464 {0x00F3, TX_PSC_A0},
3465 {0x04A2, TX_PSC_A2},
3466 {0x04A2, TX_PSC_A3},
3467 {0x0000, TX_TXCC_CPOST_MULT_00},
3468 {0x0011, TX_TXCC_MGNFS_MULT_100},
3469 {0x0003, DRV_DIAG_TX_DRV}
3470};
3471
3472static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
3473 {0x00F3, TX_PSC_A0},
3474 {0x04A2, TX_PSC_A2},
3475 {0x04A2, TX_PSC_A3},
3476 {0x0000, TX_TXCC_CPOST_MULT_00},
3477 {0x0011, TX_TXCC_MGNFS_MULT_100},
3478 {0x0003, DRV_DIAG_TX_DRV},
3479 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3480};
3481
3482static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
3483 {0x091D, RX_PSC_A0},
3484 {0x0900, RX_PSC_A2},
3485 {0x0100, RX_PSC_A3},
3486 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3487 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3488 {0x0000, RX_DIAG_DFE_CTRL},
3489 {0x0019, RX_REE_TAP1_CLIP},
3490 {0x0019, RX_REE_TAP2TON_CLIP},
3491 {0x0098, RX_DIAG_NQST_CTRL},
3492 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3493 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3494 {0x0000, RX_DIAG_PI_CAP},
3495 {0x0010, RX_DIAG_PI_RATE},
3496 {0x0001, RX_DIAG_ACYA},
3497 {0x018C, RX_CDRLF_CNFG},
3498};
3499
3500static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
3501 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
3502 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
3503};
3504
3505static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
3506 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
3507 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
3508};
3509
3510static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
3511 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
3512 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
3513};
3514
3515static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
3516 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
3517 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3518};
3519
3520/* QSGMII 100 MHz Ref clk, internal SSC */
3521static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
3522 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3523 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3524 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3525 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3526 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3527 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3528 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3529 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3530 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3531 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3532 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3533 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3534 {0x0064, CMN_PLL0_INTDIV_M0},
3535 {0x0050, CMN_PLL0_INTDIV_M1},
3536 {0x0064, CMN_PLL1_INTDIV_M0},
3537 {0x0002, CMN_PLL0_FRACDIVH_M0},
3538 {0x0002, CMN_PLL0_FRACDIVH_M1},
3539 {0x0002, CMN_PLL1_FRACDIVH_M0},
3540 {0x0044, CMN_PLL0_HIGH_THR_M0},
3541 {0x0036, CMN_PLL0_HIGH_THR_M1},
3542 {0x0044, CMN_PLL1_HIGH_THR_M0},
3543 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3544 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3545 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3546 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3547 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3548 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3549 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3550 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3551 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3552 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3553 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3554 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3555 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3556 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3557 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3558 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3559 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3560 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3561 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3562 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3563 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3564 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3565 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3566 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3567 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3568 {0x007F, CMN_TXPUCAL_TUNE},
3569 {0x007F, CMN_TXPDCAL_TUNE}
3570};
3571
3572static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
3573 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
3574 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
3575};
3576
3577/* Single SGMII/QSGMII link configuration */
3578static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
3579 {0x0000, PHY_PLL_CFG},
3580 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3581};
3582
3583static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
3584 {0x0000, XCVR_DIAG_HSCLK_SEL},
3585 {0x0003, XCVR_DIAG_HSCLK_DIV},
3586 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
3587};
3588
3589static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
3590 .reg_pairs = sl_sgmii_link_cmn_regs,
3591 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
3592};
3593
3594static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
3595 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
3596 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
3597};
3598
3599/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3600static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
3601 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3602 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3603 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3604 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3605 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3606 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3607 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3608 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3609 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3610 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3611 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3612 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3613 {0x0064, CMN_PLL0_INTDIV_M0},
3614 {0x0050, CMN_PLL0_INTDIV_M1},
3615 {0x0064, CMN_PLL1_INTDIV_M0},
3616 {0x0002, CMN_PLL0_FRACDIVH_M0},
3617 {0x0002, CMN_PLL0_FRACDIVH_M1},
3618 {0x0002, CMN_PLL1_FRACDIVH_M0},
3619 {0x0044, CMN_PLL0_HIGH_THR_M0},
3620 {0x0036, CMN_PLL0_HIGH_THR_M1},
3621 {0x0044, CMN_PLL1_HIGH_THR_M0},
3622 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3623 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3624 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3625 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3626 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3627 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3628 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3629 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3630 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3631 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3632 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3633 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3634 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3635 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3636 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3637 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3638 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3639 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3640 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3641 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3642 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3643 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3644 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3645 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3646 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3647};
3648
3649static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
3650 .reg_pairs = pcie_100_int_ssc_cmn_regs,
3651 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
3652};
3653
3654/* Single link PCIe, 100 MHz Ref clk, internal SSC */
3655static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
3656 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3657 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3658 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3659 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3660 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3661 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3662 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3663 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3664 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3665 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3666 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3667 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3668 {0x0064, CMN_PLL0_INTDIV_M0},
3669 {0x0050, CMN_PLL0_INTDIV_M1},
3670 {0x0050, CMN_PLL1_INTDIV_M0},
3671 {0x0002, CMN_PLL0_FRACDIVH_M0},
3672 {0x0002, CMN_PLL0_FRACDIVH_M1},
3673 {0x0002, CMN_PLL1_FRACDIVH_M0},
3674 {0x0044, CMN_PLL0_HIGH_THR_M0},
3675 {0x0036, CMN_PLL0_HIGH_THR_M1},
3676 {0x0036, CMN_PLL1_HIGH_THR_M0},
3677 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3678 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3679 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3680 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3681 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3682 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3683 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3684 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3685 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3686 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3687 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3688 {0x0058, CMN_PLL1_SS_CTRL3_M0},
3689 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3690 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3691 {0x0012, CMN_PLL1_SS_CTRL4_M0},
3692 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3693 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3694 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3695 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3696 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3697 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3698 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3699 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3700 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3701 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3702};
3703
3704static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
3705 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
3706 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
3707};
3708
3709/* PCIe, 100 MHz Ref clk, no SSC & external SSC */
3710static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
3711 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3712 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3713 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
3714};
3715
3716static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
3717 {0x0019, RX_REE_TAP1_CLIP},
3718 {0x0019, RX_REE_TAP2TON_CLIP},
3719 {0x0001, RX_DIAG_ACYA}
3720};
3721
3722static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
3723 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
3724 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
3725};
3726
3727static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
3728 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
3729 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
3730};
3731
3732static const struct cdns_torrent_data cdns_map_torrent = {
3733 .block_offset_shift = 0x2,
3734 .reg_offset_shift = 0x2,
3735 .link_cmn_vals = {
3736 [TYPE_DP] = {
3737 [TYPE_NONE] = {
3738 [NO_SSC] = &sl_dp_link_cmn_vals,
3739 },
3740 },
3741 [TYPE_PCIE] = {
3742 [TYPE_NONE] = {
3743 [NO_SSC] = NULL,
3744 [EXTERNAL_SSC] = NULL,
3745 [INTERNAL_SSC] = NULL,
3746 },
3747 [TYPE_SGMII] = {
3748 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3749 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3750 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3751 },
3752 [TYPE_QSGMII] = {
3753 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3754 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3755 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3756 },
3757 [TYPE_USB] = {
3758 [NO_SSC] = &pcie_usb_link_cmn_vals,
3759 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3760 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3761 },
3762 },
3763 [TYPE_SGMII] = {
3764 [TYPE_NONE] = {
3765 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3766 },
3767 [TYPE_PCIE] = {
3768 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3769 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3770 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3771 },
3772 [TYPE_USB] = {
3773 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3774 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3775 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3776 },
3777 },
3778 [TYPE_QSGMII] = {
3779 [TYPE_NONE] = {
3780 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3781 },
3782 [TYPE_PCIE] = {
3783 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3784 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3785 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3786 },
3787 [TYPE_USB] = {
3788 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3789 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3790 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3791 },
3792 },
3793 [TYPE_USB] = {
3794 [TYPE_NONE] = {
3795 [NO_SSC] = &sl_usb_link_cmn_vals,
3796 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3797 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3798 },
3799 [TYPE_PCIE] = {
3800 [NO_SSC] = &pcie_usb_link_cmn_vals,
3801 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3802 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3803 },
3804 [TYPE_SGMII] = {
3805 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3806 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3807 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3808 },
3809 [TYPE_QSGMII] = {
3810 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3811 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3812 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3813 },
3814 },
3815 },
3816 .xcvr_diag_vals = {
3817 [TYPE_DP] = {
3818 [TYPE_NONE] = {
3819 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
3820 },
3821 },
3822 [TYPE_PCIE] = {
3823 [TYPE_NONE] = {
3824 [NO_SSC] = NULL,
3825 [EXTERNAL_SSC] = NULL,
3826 [INTERNAL_SSC] = NULL,
3827 },
3828 [TYPE_SGMII] = {
3829 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3830 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3831 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3832 },
3833 [TYPE_QSGMII] = {
3834 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3835 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3836 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3837 },
3838 [TYPE_USB] = {
3839 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3840 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3841 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3842 },
3843 },
3844 [TYPE_SGMII] = {
3845 [TYPE_NONE] = {
3846 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3847 },
3848 [TYPE_PCIE] = {
3849 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3850 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3851 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3852 },
3853 [TYPE_USB] = {
3854 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3855 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3856 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3857 },
3858 },
3859 [TYPE_QSGMII] = {
3860 [TYPE_NONE] = {
3861 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3862 },
3863 [TYPE_PCIE] = {
3864 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3865 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3866 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3867 },
3868 [TYPE_USB] = {
3869 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3870 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3871 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3872 },
3873 },
3874 [TYPE_USB] = {
3875 [TYPE_NONE] = {
3876 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3877 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3878 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3879 },
3880 [TYPE_PCIE] = {
3881 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3882 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3883 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3884 },
3885 [TYPE_SGMII] = {
3886 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3887 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3888 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3889 },
3890 [TYPE_QSGMII] = {
3891 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3892 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3893 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3894 },
3895 },
3896 },
3897 .pcs_cmn_vals = {
3898 [TYPE_USB] = {
3899 [TYPE_NONE] = {
3900 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3901 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3902 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3903 },
3904 [TYPE_PCIE] = {
3905 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3906 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3907 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3908 },
3909 [TYPE_SGMII] = {
3910 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3911 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3912 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3913 },
3914 [TYPE_QSGMII] = {
3915 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3916 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3917 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3918 },
3919 },
3920 },
3921 .cmn_vals = {
3922 [CLK_19_2_MHZ] = {
3923 [TYPE_DP] = {
3924 [TYPE_NONE] = {
3925 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
3926 },
3927 },
3928 },
3929 [CLK_25_MHZ] = {
3930 [TYPE_DP] = {
3931 [TYPE_NONE] = {
3932 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
3933 },
3934 },
3935 },
3936 [CLK_100_MHZ] = {
3937 [TYPE_DP] = {
3938 [TYPE_NONE] = {
3939 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
3940 },
3941 },
3942 [TYPE_PCIE] = {
3943 [TYPE_NONE] = {
3944 [NO_SSC] = NULL,
3945 [EXTERNAL_SSC] = NULL,
3946 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3947 },
3948 [TYPE_SGMII] = {
3949 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3950 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3951 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3952 },
3953 [TYPE_QSGMII] = {
3954 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3955 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3956 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3957 },
3958 [TYPE_USB] = {
3959 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3960 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3961 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3962 },
3963 },
3964 [TYPE_SGMII] = {
3965 [TYPE_NONE] = {
3966 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
3967 },
3968 [TYPE_PCIE] = {
3969 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3970 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3971 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3972 },
3973 [TYPE_USB] = {
3974 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3975 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3976 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3977 },
3978 },
3979 [TYPE_QSGMII] = {
3980 [TYPE_NONE] = {
3981 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
3982 },
3983 [TYPE_PCIE] = {
3984 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3985 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3986 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3987 },
3988 [TYPE_USB] = {
3989 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3990 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3991 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3992 },
3993 },
3994 [TYPE_USB] = {
3995 [TYPE_NONE] = {
3996 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3997 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3998 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3999 },
4000 [TYPE_PCIE] = {
4001 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4002 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4003 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4004 },
4005 [TYPE_SGMII] = {
4006 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4007 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4008 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4009 },
4010 [TYPE_QSGMII] = {
4011 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4012 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4013 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4014 },
4015 },
4016 },
4017 },
4018 .tx_ln_vals = {
4019 [CLK_19_2_MHZ] = {
4020 [TYPE_DP] = {
4021 [TYPE_NONE] = {
4022 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4023 },
4024 },
4025 },
4026 [CLK_25_MHZ] = {
4027 [TYPE_DP] = {
4028 [TYPE_NONE] = {
4029 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4030 },
4031 },
4032 },
4033 [CLK_100_MHZ] = {
4034 [TYPE_DP] = {
4035 [TYPE_NONE] = {
4036 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4037 },
4038 },
4039 [TYPE_PCIE] = {
4040 [TYPE_NONE] = {
4041 [NO_SSC] = NULL,
4042 [EXTERNAL_SSC] = NULL,
4043 [INTERNAL_SSC] = NULL,
4044 },
4045 [TYPE_SGMII] = {
4046 [NO_SSC] = NULL,
4047 [EXTERNAL_SSC] = NULL,
4048 [INTERNAL_SSC] = NULL,
4049 },
4050 [TYPE_QSGMII] = {
4051 [NO_SSC] = NULL,
4052 [EXTERNAL_SSC] = NULL,
4053 [INTERNAL_SSC] = NULL,
4054 },
4055 [TYPE_USB] = {
4056 [NO_SSC] = NULL,
4057 [EXTERNAL_SSC] = NULL,
4058 [INTERNAL_SSC] = NULL,
4059 },
4060 },
4061 [TYPE_SGMII] = {
4062 [TYPE_NONE] = {
4063 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4064 },
4065 [TYPE_PCIE] = {
4066 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4067 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4068 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4069 },
4070 [TYPE_USB] = {
4071 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4072 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4073 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4074 },
4075 },
4076 [TYPE_QSGMII] = {
4077 [TYPE_NONE] = {
4078 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4079 },
4080 [TYPE_PCIE] = {
4081 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4082 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4083 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4084 },
4085 [TYPE_USB] = {
4086 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4087 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4088 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4089 },
4090 },
4091 [TYPE_USB] = {
4092 [TYPE_NONE] = {
4093 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4094 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4095 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4096 },
4097 [TYPE_PCIE] = {
4098 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4099 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4100 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4101 },
4102 [TYPE_SGMII] = {
4103 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4104 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4105 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4106 },
4107 [TYPE_QSGMII] = {
4108 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4109 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4110 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4111 },
4112 },
4113 },
4114 },
4115 .rx_ln_vals = {
4116 [CLK_19_2_MHZ] = {
4117 [TYPE_DP] = {
4118 [TYPE_NONE] = {
4119 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4120 },
4121 },
4122 },
4123 [CLK_25_MHZ] = {
4124 [TYPE_DP] = {
4125 [TYPE_NONE] = {
4126 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4127 },
4128 },
4129 },
4130 [CLK_100_MHZ] = {
4131 [TYPE_DP] = {
4132 [TYPE_NONE] = {
4133 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4134 },
4135 },
4136 [TYPE_PCIE] = {
4137 [TYPE_NONE] = {
4138 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4139 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4140 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4141 },
4142 [TYPE_SGMII] = {
4143 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4144 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4145 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4146 },
4147 [TYPE_QSGMII] = {
4148 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4149 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4150 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4151 },
4152 [TYPE_USB] = {
4153 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4154 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4155 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4156 },
4157 },
4158 [TYPE_SGMII] = {
4159 [TYPE_NONE] = {
4160 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4161 },
4162 [TYPE_PCIE] = {
4163 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4164 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4165 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4166 },
4167 [TYPE_USB] = {
4168 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4169 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4170 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4171 },
4172 },
4173 [TYPE_QSGMII] = {
4174 [TYPE_NONE] = {
4175 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4176 },
4177 [TYPE_PCIE] = {
4178 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4179 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4180 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4181 },
4182 [TYPE_USB] = {
4183 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4184 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4185 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4186 },
4187 },
4188 [TYPE_USB] = {
4189 [TYPE_NONE] = {
4190 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4191 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4192 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4193 },
4194 [TYPE_PCIE] = {
4195 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4196 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4197 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4198 },
4199 [TYPE_SGMII] = {
4200 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4201 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4202 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4203 },
4204 [TYPE_QSGMII] = {
4205 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4206 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4207 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4208 },
4209 },
4210 },
4211 },
4212};
4213
4214static const struct cdns_torrent_data ti_j721e_map_torrent = {
4215 .block_offset_shift = 0x0,
4216 .reg_offset_shift = 0x1,
4217 .link_cmn_vals = {
4218 [TYPE_DP] = {
4219 [TYPE_NONE] = {
4220 [NO_SSC] = &sl_dp_link_cmn_vals,
4221 },
4222 },
4223 [TYPE_PCIE] = {
4224 [TYPE_NONE] = {
4225 [NO_SSC] = NULL,
4226 [EXTERNAL_SSC] = NULL,
4227 [INTERNAL_SSC] = NULL,
4228 },
4229 [TYPE_SGMII] = {
4230 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4231 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4232 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4233 },
4234 [TYPE_QSGMII] = {
4235 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4236 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4237 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4238 },
4239 [TYPE_USB] = {
4240 [NO_SSC] = &pcie_usb_link_cmn_vals,
4241 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4242 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4243 },
4244 },
4245 [TYPE_SGMII] = {
4246 [TYPE_NONE] = {
4247 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4248 },
4249 [TYPE_PCIE] = {
4250 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4251 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4252 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4253 },
4254 [TYPE_USB] = {
4255 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4256 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4257 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4258 },
4259 },
4260 [TYPE_QSGMII] = {
4261 [TYPE_NONE] = {
4262 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4263 },
4264 [TYPE_PCIE] = {
4265 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4266 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4267 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4268 },
4269 [TYPE_USB] = {
4270 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4271 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4272 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4273 },
4274 },
4275 [TYPE_USB] = {
4276 [TYPE_NONE] = {
4277 [NO_SSC] = &sl_usb_link_cmn_vals,
4278 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
4279 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
4280 },
4281 [TYPE_PCIE] = {
4282 [NO_SSC] = &pcie_usb_link_cmn_vals,
4283 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4284 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4285 },
4286 [TYPE_SGMII] = {
4287 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4288 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4289 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4290 },
4291 [TYPE_QSGMII] = {
4292 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4293 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4294 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4295 },
4296 },
4297 },
4298 .xcvr_diag_vals = {
4299 [TYPE_DP] = {
4300 [TYPE_NONE] = {
4301 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
4302 },
4303 },
4304 [TYPE_PCIE] = {
4305 [TYPE_NONE] = {
4306 [NO_SSC] = NULL,
4307 [EXTERNAL_SSC] = NULL,
4308 [INTERNAL_SSC] = NULL,
4309 },
4310 [TYPE_SGMII] = {
4311 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4312 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4313 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4314 },
4315 [TYPE_QSGMII] = {
4316 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4317 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4318 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4319 },
4320 [TYPE_USB] = {
4321 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4322 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4323 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4324 },
4325 },
4326 [TYPE_SGMII] = {
4327 [TYPE_NONE] = {
4328 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4329 },
4330 [TYPE_PCIE] = {
4331 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4332 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4333 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4334 },
4335 [TYPE_USB] = {
4336 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4337 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4338 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4339 },
4340 },
4341 [TYPE_QSGMII] = {
4342 [TYPE_NONE] = {
4343 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4344 },
4345 [TYPE_PCIE] = {
4346 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4347 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4348 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4349 },
4350 [TYPE_USB] = {
4351 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4352 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4353 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4354 },
4355 },
4356 [TYPE_USB] = {
4357 [TYPE_NONE] = {
4358 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
4359 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4360 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4361 },
4362 [TYPE_PCIE] = {
4363 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4364 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4365 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4366 },
4367 [TYPE_SGMII] = {
4368 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4369 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4370 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4371 },
4372 [TYPE_QSGMII] = {
4373 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4374 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4375 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4376 },
4377 },
4378 },
4379 .pcs_cmn_vals = {
4380 [TYPE_USB] = {
4381 [TYPE_NONE] = {
4382 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4383 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4384 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4385 },
4386 [TYPE_PCIE] = {
4387 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4388 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4389 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4390 },
4391 [TYPE_SGMII] = {
4392 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4393 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4394 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4395 },
4396 [TYPE_QSGMII] = {
4397 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4398 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4399 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4400 },
4401 },
4402 },
4403 .cmn_vals = {
4404 [CLK_19_2_MHZ] = {
4405 [TYPE_DP] = {
4406 [TYPE_NONE] = {
4407 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
4408 },
4409 },
4410 },
4411 [CLK_25_MHZ] = {
4412 [TYPE_DP] = {
4413 [TYPE_NONE] = {
4414 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
4415 },
4416 },
4417 },
4418 [CLK_100_MHZ] = {
4419 [TYPE_DP] = {
4420 [TYPE_NONE] = {
4421 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4422 },
4423 },
4424 [TYPE_PCIE] = {
4425 [TYPE_NONE] = {
4426 [NO_SSC] = NULL,
4427 [EXTERNAL_SSC] = NULL,
4428 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
4429 },
4430 [TYPE_SGMII] = {
4431 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4432 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4433 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4434 },
4435 [TYPE_QSGMII] = {
4436 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4437 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4438 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4439 },
4440 [TYPE_USB] = {
4441 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4442 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4443 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4444 },
4445 },
4446 [TYPE_SGMII] = {
4447 [TYPE_NONE] = {
4448 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
4449 },
4450 [TYPE_PCIE] = {
4451 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4452 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4453 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
4454 },
4455 [TYPE_USB] = {
4456 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4457 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4458 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4459 },
4460 },
4461 [TYPE_QSGMII] = {
4462 [TYPE_NONE] = {
4463 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
4464 },
4465 [TYPE_PCIE] = {
4466 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4467 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4468 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
4469 },
4470 [TYPE_USB] = {
4471 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4472 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4473 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4474 },
4475 },
4476 [TYPE_USB] = {
4477 [TYPE_NONE] = {
4478 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4479 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4480 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4481 },
4482 [TYPE_PCIE] = {
4483 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4484 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4485 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4486 },
4487 [TYPE_SGMII] = {
4488 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4489 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4490 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4491 },
4492 [TYPE_QSGMII] = {
4493 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4494 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4495 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4496 },
4497 },
4498 },
4499 },
4500 .tx_ln_vals = {
4501 [CLK_19_2_MHZ] = {
4502 [TYPE_DP] = {
4503 [TYPE_NONE] = {
4504 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4505 },
4506 },
4507 },
4508 [CLK_25_MHZ] = {
4509 [TYPE_DP] = {
4510 [TYPE_NONE] = {
4511 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4512 },
4513 },
4514 },
4515 [CLK_100_MHZ] = {
4516 [TYPE_DP] = {
4517 [TYPE_NONE] = {
4518 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4519 },
4520 },
4521 [TYPE_PCIE] = {
4522 [TYPE_NONE] = {
4523 [NO_SSC] = NULL,
4524 [EXTERNAL_SSC] = NULL,
4525 [INTERNAL_SSC] = NULL,
4526 },
4527 [TYPE_SGMII] = {
4528 [NO_SSC] = NULL,
4529 [EXTERNAL_SSC] = NULL,
4530 [INTERNAL_SSC] = NULL,
4531 },
4532 [TYPE_QSGMII] = {
4533 [NO_SSC] = NULL,
4534 [EXTERNAL_SSC] = NULL,
4535 [INTERNAL_SSC] = NULL,
4536 },
4537 [TYPE_USB] = {
4538 [NO_SSC] = NULL,
4539 [EXTERNAL_SSC] = NULL,
4540 [INTERNAL_SSC] = NULL,
4541 },
4542 },
4543 [TYPE_SGMII] = {
4544 [TYPE_NONE] = {
4545 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4546 },
4547 [TYPE_PCIE] = {
4548 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4549 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4550 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4551 },
4552 [TYPE_USB] = {
4553 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4554 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4555 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4556 },
4557 },
4558 [TYPE_QSGMII] = {
4559 [TYPE_NONE] = {
4560 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4561 },
4562 [TYPE_PCIE] = {
4563 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4564 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4565 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4566 },
4567 [TYPE_USB] = {
4568 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4569 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4570 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4571 },
4572 },
4573 [TYPE_USB] = {
4574 [TYPE_NONE] = {
4575 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4576 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4577 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4578 },
4579 [TYPE_PCIE] = {
4580 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4581 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4582 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4583 },
4584 [TYPE_SGMII] = {
4585 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4586 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4587 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4588 },
4589 [TYPE_QSGMII] = {
4590 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4591 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4592 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4593 },
4594 },
4595 },
4596 },
4597 .rx_ln_vals = {
4598 [CLK_19_2_MHZ] = {
4599 [TYPE_DP] = {
4600 [TYPE_NONE] = {
4601 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4602 },
4603 },
4604 },
4605 [CLK_25_MHZ] = {
4606 [TYPE_DP] = {
4607 [TYPE_NONE] = {
4608 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4609 },
4610 },
4611 },
4612 [CLK_100_MHZ] = {
4613 [TYPE_DP] = {
4614 [TYPE_NONE] = {
4615 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4616 },
4617 },
4618 [TYPE_PCIE] = {
4619 [TYPE_NONE] = {
4620 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4621 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4622 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4623 },
4624 [TYPE_SGMII] = {
4625 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4626 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4627 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4628 },
4629 [TYPE_QSGMII] = {
4630 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4631 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4632 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4633 },
4634 [TYPE_USB] = {
4635 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4636 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4637 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4638 },
4639 },
4640 [TYPE_SGMII] = {
4641 [TYPE_NONE] = {
4642 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4643 },
4644 [TYPE_PCIE] = {
4645 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4646 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4647 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4648 },
4649 [TYPE_USB] = {
4650 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4651 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4652 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4653 },
4654 },
4655 [TYPE_QSGMII] = {
4656 [TYPE_NONE] = {
4657 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4658 },
4659 [TYPE_PCIE] = {
4660 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4661 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4662 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4663 },
4664 [TYPE_USB] = {
4665 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4666 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4667 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4668 },
4669 },
4670 [TYPE_USB] = {
4671 [TYPE_NONE] = {
4672 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4673 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4674 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4675 },
4676 [TYPE_PCIE] = {
4677 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4678 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4679 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4680 },
4681 [TYPE_SGMII] = {
4682 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4683 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4684 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4685 },
4686 [TYPE_QSGMII] = {
4687 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4688 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4689 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4690 },
4691 },
4692 },
4693 },
4694};
4695
4696static const struct of_device_id cdns_torrent_phy_of_match[] = {
4697 {
4698 .compatible = "cdns,torrent-phy",
4699 .data = &cdns_map_torrent,
4700 },
4701 {
4702 .compatible = "ti,j721e-serdes-10g",
4703 .data = &ti_j721e_map_torrent,
4704 },
4705 {}
4706};
4707MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
4708
4709static struct platform_driver cdns_torrent_phy_driver = {
4710 .probe = cdns_torrent_phy_probe,
4711 .remove = cdns_torrent_phy_remove,
4712 .driver = {
4713 .name = "cdns-torrent-phy",
4714 .of_match_table = cdns_torrent_phy_of_match,
4715 }
4716};
4717module_platform_driver(cdns_torrent_phy_driver);
4718
4719MODULE_AUTHOR("Cadence Design Systems, Inc.");
4720MODULE_DESCRIPTION("Cadence Torrent PHY driver");
4721MODULE_LICENSE("GPL v2");