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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
11 *
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Resource sorting
14 */
15
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/cache.h>
22#include <linux/slab.h>
23#include "pci.h"
24
25static void pci_std_update_resource(struct pci_dev *dev, int resno)
26{
27 struct pci_bus_region region;
28 bool disable;
29 u16 cmd;
30 u32 new, check, mask;
31 int reg;
32 struct resource *res = dev->resource + resno;
33
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
35 if (dev->is_virtfn)
36 return;
37
38 /*
39 * Ignore resources for unimplemented BARs and unused resource slots
40 * for 64 bit BARs.
41 */
42 if (!res->flags)
43 return;
44
45 if (res->flags & IORESOURCE_UNSET)
46 return;
47
48 /*
49 * Ignore non-moveable resources. This might be legacy resources for
50 * which no functional BAR register exists or another important
51 * system resource we shouldn't move around.
52 */
53 if (res->flags & IORESOURCE_PCI_FIXED)
54 return;
55
56 pcibios_resource_to_bus(dev->bus, ®ion, res);
57 new = region.start;
58
59 if (res->flags & IORESOURCE_IO) {
60 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
61 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
62 } else if (resno == PCI_ROM_RESOURCE) {
63 mask = PCI_ROM_ADDRESS_MASK;
64 } else {
65 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
66 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
67 }
68
69 if (resno < PCI_ROM_RESOURCE) {
70 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
71 } else if (resno == PCI_ROM_RESOURCE) {
72
73 /*
74 * Apparently some Matrox devices have ROM BARs that read
75 * as zero when disabled, so don't update ROM BARs unless
76 * they're enabled. See
77 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
78 * But we must update ROM BAR for buggy devices where even a
79 * disabled ROM can conflict with other BARs.
80 */
81 if (!(res->flags & IORESOURCE_ROM_ENABLE) &&
82 !dev->rom_bar_overlap)
83 return;
84
85 reg = dev->rom_base_reg;
86 if (res->flags & IORESOURCE_ROM_ENABLE)
87 new |= PCI_ROM_ADDRESS_ENABLE;
88 } else
89 return;
90
91 /*
92 * We can't update a 64-bit BAR atomically, so when possible,
93 * disable decoding so that a half-updated BAR won't conflict
94 * with another device.
95 */
96 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
97 if (disable) {
98 pci_read_config_word(dev, PCI_COMMAND, &cmd);
99 pci_write_config_word(dev, PCI_COMMAND,
100 cmd & ~PCI_COMMAND_MEMORY);
101 }
102
103 pci_write_config_dword(dev, reg, new);
104 pci_read_config_dword(dev, reg, &check);
105
106 if ((new ^ check) & mask) {
107 pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
108 resno, new, check);
109 }
110
111 if (res->flags & IORESOURCE_MEM_64) {
112 new = region.start >> 16 >> 16;
113 pci_write_config_dword(dev, reg + 4, new);
114 pci_read_config_dword(dev, reg + 4, &check);
115 if (check != new) {
116 pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
117 resno, new, check);
118 }
119 }
120
121 if (disable)
122 pci_write_config_word(dev, PCI_COMMAND, cmd);
123}
124
125void pci_update_resource(struct pci_dev *dev, int resno)
126{
127 if (resno <= PCI_ROM_RESOURCE)
128 pci_std_update_resource(dev, resno);
129#ifdef CONFIG_PCI_IOV
130 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
131 pci_iov_update_resource(dev, resno);
132#endif
133}
134
135int pci_claim_resource(struct pci_dev *dev, int resource)
136{
137 struct resource *res = &dev->resource[resource];
138 struct resource *root, *conflict;
139
140 if (res->flags & IORESOURCE_UNSET) {
141 pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
142 resource, res);
143 return -EINVAL;
144 }
145
146 /*
147 * If we have a shadow copy in RAM, the PCI device doesn't respond
148 * to the shadow range, so we don't need to claim it, and upstream
149 * bridges don't need to route the range to the device.
150 */
151 if (res->flags & IORESOURCE_ROM_SHADOW)
152 return 0;
153
154 root = pci_find_parent_resource(dev, res);
155 if (!root) {
156 pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
157 resource, res);
158 res->flags |= IORESOURCE_UNSET;
159 return -EINVAL;
160 }
161
162 conflict = request_resource_conflict(root, res);
163 if (conflict) {
164 pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
165 resource, res, conflict->name, conflict);
166 res->flags |= IORESOURCE_UNSET;
167 return -EBUSY;
168 }
169
170 return 0;
171}
172EXPORT_SYMBOL(pci_claim_resource);
173
174void pci_disable_bridge_window(struct pci_dev *dev)
175{
176 /* MMIO Base/Limit */
177 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
178
179 /* Prefetchable MMIO Base/Limit */
180 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
181 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
182 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
183}
184
185/*
186 * Generic function that returns a value indicating that the device's
187 * original BIOS BAR address was not saved and so is not available for
188 * reinstatement.
189 *
190 * Can be over-ridden by architecture specific code that implements
191 * reinstatement functionality rather than leaving it disabled when
192 * normal allocation attempts fail.
193 */
194resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
195{
196 return 0;
197}
198
199static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
200 int resno, resource_size_t size)
201{
202 struct resource *root, *conflict;
203 resource_size_t fw_addr, start, end;
204
205 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
206 if (!fw_addr)
207 return -ENOMEM;
208
209 start = res->start;
210 end = res->end;
211 res->start = fw_addr;
212 res->end = res->start + size - 1;
213 res->flags &= ~IORESOURCE_UNSET;
214
215 root = pci_find_parent_resource(dev, res);
216 if (!root) {
217 /*
218 * If dev is behind a bridge, accesses will only reach it
219 * if res is inside the relevant bridge window.
220 */
221 if (pci_upstream_bridge(dev))
222 return -ENXIO;
223
224 /*
225 * On the root bus, assume the host bridge will forward
226 * everything.
227 */
228 if (res->flags & IORESOURCE_IO)
229 root = &ioport_resource;
230 else
231 root = &iomem_resource;
232 }
233
234 pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
235 resno, res);
236 conflict = request_resource_conflict(root, res);
237 if (conflict) {
238 pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
239 resno, res, conflict->name, conflict);
240 res->start = start;
241 res->end = end;
242 res->flags |= IORESOURCE_UNSET;
243 return -EBUSY;
244 }
245 return 0;
246}
247
248/*
249 * We don't have to worry about legacy ISA devices, so nothing to do here.
250 * This is marked as __weak because multiple architectures define it; it should
251 * eventually go away.
252 */
253resource_size_t __weak pcibios_align_resource(void *data,
254 const struct resource *res,
255 resource_size_t size,
256 resource_size_t align)
257{
258 return res->start;
259}
260
261static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
262 int resno, resource_size_t size, resource_size_t align)
263{
264 struct resource *res = dev->resource + resno;
265 resource_size_t min;
266 int ret;
267
268 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
269
270 /*
271 * First, try exact prefetching match. Even if a 64-bit
272 * prefetchable bridge window is below 4GB, we can't put a 32-bit
273 * prefetchable resource in it because pbus_size_mem() assumes a
274 * 64-bit window will contain no 32-bit resources. If we assign
275 * things differently than they were sized, not everything will fit.
276 */
277 ret = pci_bus_alloc_resource(bus, res, size, align, min,
278 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
279 pcibios_align_resource, dev);
280 if (ret == 0)
281 return 0;
282
283 /*
284 * If the prefetchable window is only 32 bits wide, we can put
285 * 64-bit prefetchable resources in it.
286 */
287 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
288 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
289 ret = pci_bus_alloc_resource(bus, res, size, align, min,
290 IORESOURCE_PREFETCH,
291 pcibios_align_resource, dev);
292 if (ret == 0)
293 return 0;
294 }
295
296 /*
297 * If we didn't find a better match, we can put any memory resource
298 * in a non-prefetchable window. If this resource is 32 bits and
299 * non-prefetchable, the first call already tried the only possibility
300 * so we don't need to try again.
301 */
302 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
303 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
304 pcibios_align_resource, dev);
305
306 return ret;
307}
308
309static int _pci_assign_resource(struct pci_dev *dev, int resno,
310 resource_size_t size, resource_size_t min_align)
311{
312 struct pci_bus *bus;
313 int ret;
314
315 bus = dev->bus;
316 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
317 if (!bus->parent || !bus->self->transparent)
318 break;
319 bus = bus->parent;
320 }
321
322 return ret;
323}
324
325int pci_assign_resource(struct pci_dev *dev, int resno)
326{
327 struct resource *res = dev->resource + resno;
328 resource_size_t align, size;
329 int ret;
330
331 if (res->flags & IORESOURCE_PCI_FIXED)
332 return 0;
333
334 res->flags |= IORESOURCE_UNSET;
335 align = pci_resource_alignment(dev, res);
336 if (!align) {
337 pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
338 resno, res);
339 return -EINVAL;
340 }
341
342 size = resource_size(res);
343 ret = _pci_assign_resource(dev, resno, size, align);
344
345 /*
346 * If we failed to assign anything, let's try the address
347 * where firmware left it. That at least has a chance of
348 * working, which is better than just leaving it disabled.
349 */
350 if (ret < 0) {
351 pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
352 ret = pci_revert_fw_address(res, dev, resno, size);
353 }
354
355 if (ret < 0) {
356 pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
357 return ret;
358 }
359
360 res->flags &= ~IORESOURCE_UNSET;
361 res->flags &= ~IORESOURCE_STARTALIGN;
362 pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
363 if (resno < PCI_BRIDGE_RESOURCES)
364 pci_update_resource(dev, resno);
365
366 return 0;
367}
368EXPORT_SYMBOL(pci_assign_resource);
369
370int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
371 resource_size_t min_align)
372{
373 struct resource *res = dev->resource + resno;
374 unsigned long flags;
375 resource_size_t new_size;
376 int ret;
377
378 if (res->flags & IORESOURCE_PCI_FIXED)
379 return 0;
380
381 flags = res->flags;
382 res->flags |= IORESOURCE_UNSET;
383 if (!res->parent) {
384 pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
385 resno, res);
386 return -EINVAL;
387 }
388
389 /* already aligned with min_align */
390 new_size = resource_size(res) + addsize;
391 ret = _pci_assign_resource(dev, resno, new_size, min_align);
392 if (ret) {
393 res->flags = flags;
394 pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
395 resno, res, (unsigned long long) addsize);
396 return ret;
397 }
398
399 res->flags &= ~IORESOURCE_UNSET;
400 res->flags &= ~IORESOURCE_STARTALIGN;
401 pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
402 resno, res, (unsigned long long) addsize);
403 if (resno < PCI_BRIDGE_RESOURCES)
404 pci_update_resource(dev, resno);
405
406 return 0;
407}
408
409void pci_release_resource(struct pci_dev *dev, int resno)
410{
411 struct resource *res = dev->resource + resno;
412
413 pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
414
415 if (!res->parent)
416 return;
417
418 release_resource(res);
419 res->end = resource_size(res) - 1;
420 res->start = 0;
421 res->flags |= IORESOURCE_UNSET;
422}
423EXPORT_SYMBOL(pci_release_resource);
424
425int pci_resize_resource(struct pci_dev *dev, int resno, int size)
426{
427 struct resource *res = dev->resource + resno;
428 struct pci_host_bridge *host;
429 int old, ret;
430 u32 sizes;
431 u16 cmd;
432
433 /* Check if we must preserve the firmware's resource assignment */
434 host = pci_find_host_bridge(dev->bus);
435 if (host->preserve_config)
436 return -ENOTSUPP;
437
438 /* Make sure the resource isn't assigned before resizing it. */
439 if (!(res->flags & IORESOURCE_UNSET))
440 return -EBUSY;
441
442 pci_read_config_word(dev, PCI_COMMAND, &cmd);
443 if (cmd & PCI_COMMAND_MEMORY)
444 return -EBUSY;
445
446 sizes = pci_rebar_get_possible_sizes(dev, resno);
447 if (!sizes)
448 return -ENOTSUPP;
449
450 if (!(sizes & BIT(size)))
451 return -EINVAL;
452
453 old = pci_rebar_get_current_size(dev, resno);
454 if (old < 0)
455 return old;
456
457 ret = pci_rebar_set_size(dev, resno, size);
458 if (ret)
459 return ret;
460
461 res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
462
463 /* Check if the new config works by trying to assign everything. */
464 if (dev->bus->self) {
465 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
466 if (ret)
467 goto error_resize;
468 }
469 return 0;
470
471error_resize:
472 pci_rebar_set_size(dev, resno, old);
473 res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
474 return ret;
475}
476EXPORT_SYMBOL(pci_resize_resource);
477
478int pci_enable_resources(struct pci_dev *dev, int mask)
479{
480 u16 cmd, old_cmd;
481 int i;
482 struct resource *r;
483
484 pci_read_config_word(dev, PCI_COMMAND, &cmd);
485 old_cmd = cmd;
486
487 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
488 if (!(mask & (1 << i)))
489 continue;
490
491 r = &dev->resource[i];
492
493 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
494 continue;
495 if ((i == PCI_ROM_RESOURCE) &&
496 (!(r->flags & IORESOURCE_ROM_ENABLE)))
497 continue;
498
499 if (r->flags & IORESOURCE_UNSET) {
500 pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
501 i, r);
502 return -EINVAL;
503 }
504
505 if (!r->parent) {
506 pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
507 i, r);
508 return -EINVAL;
509 }
510
511 if (r->flags & IORESOURCE_IO)
512 cmd |= PCI_COMMAND_IO;
513 if (r->flags & IORESOURCE_MEM)
514 cmd |= PCI_COMMAND_MEMORY;
515 }
516
517 if (cmd != old_cmd) {
518 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
519 pci_write_config_word(dev, PCI_COMMAND, cmd);
520 }
521 return 0;
522}
1/*
2 * drivers/pci/setup-res.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13
14/*
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Resource sorting
17 */
18
19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/cache.h>
25#include <linux/slab.h>
26#include "pci.h"
27
28
29void pci_update_resource(struct pci_dev *dev, int resno)
30{
31 struct pci_bus_region region;
32 bool disable;
33 u16 cmd;
34 u32 new, check, mask;
35 int reg;
36 enum pci_bar_type type;
37 struct resource *res = dev->resource + resno;
38
39 if (dev->is_virtfn) {
40 dev_warn(&dev->dev, "can't update VF BAR%d\n", resno);
41 return;
42 }
43
44 /*
45 * Ignore resources for unimplemented BARs and unused resource slots
46 * for 64 bit BARs.
47 */
48 if (!res->flags)
49 return;
50
51 if (res->flags & IORESOURCE_UNSET)
52 return;
53
54 /*
55 * Ignore non-moveable resources. This might be legacy resources for
56 * which no functional BAR register exists or another important
57 * system resource we shouldn't move around.
58 */
59 if (res->flags & IORESOURCE_PCI_FIXED)
60 return;
61
62 pcibios_resource_to_bus(dev->bus, ®ion, res);
63
64 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
65 if (res->flags & IORESOURCE_IO)
66 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
67 else
68 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
69
70 reg = pci_resource_bar(dev, resno, &type);
71 if (!reg)
72 return;
73 if (type != pci_bar_unknown) {
74 if (!(res->flags & IORESOURCE_ROM_ENABLE))
75 return;
76 new |= PCI_ROM_ADDRESS_ENABLE;
77 }
78
79 /*
80 * We can't update a 64-bit BAR atomically, so when possible,
81 * disable decoding so that a half-updated BAR won't conflict
82 * with another device.
83 */
84 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
85 if (disable) {
86 pci_read_config_word(dev, PCI_COMMAND, &cmd);
87 pci_write_config_word(dev, PCI_COMMAND,
88 cmd & ~PCI_COMMAND_MEMORY);
89 }
90
91 pci_write_config_dword(dev, reg, new);
92 pci_read_config_dword(dev, reg, &check);
93
94 if ((new ^ check) & mask) {
95 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
96 resno, new, check);
97 }
98
99 if (res->flags & IORESOURCE_MEM_64) {
100 new = region.start >> 16 >> 16;
101 pci_write_config_dword(dev, reg + 4, new);
102 pci_read_config_dword(dev, reg + 4, &check);
103 if (check != new) {
104 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
105 resno, new, check);
106 }
107 }
108
109 if (disable)
110 pci_write_config_word(dev, PCI_COMMAND, cmd);
111}
112
113int pci_claim_resource(struct pci_dev *dev, int resource)
114{
115 struct resource *res = &dev->resource[resource];
116 struct resource *root, *conflict;
117
118 if (res->flags & IORESOURCE_UNSET) {
119 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
120 resource, res);
121 return -EINVAL;
122 }
123
124 root = pci_find_parent_resource(dev, res);
125 if (!root) {
126 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
127 resource, res);
128 res->flags |= IORESOURCE_UNSET;
129 return -EINVAL;
130 }
131
132 conflict = request_resource_conflict(root, res);
133 if (conflict) {
134 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
135 resource, res, conflict->name, conflict);
136 res->flags |= IORESOURCE_UNSET;
137 return -EBUSY;
138 }
139
140 return 0;
141}
142EXPORT_SYMBOL(pci_claim_resource);
143
144void pci_disable_bridge_window(struct pci_dev *dev)
145{
146 dev_info(&dev->dev, "disabling bridge mem windows\n");
147
148 /* MMIO Base/Limit */
149 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
150
151 /* Prefetchable MMIO Base/Limit */
152 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
153 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
154 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
155}
156
157/*
158 * Generic function that returns a value indicating that the device's
159 * original BIOS BAR address was not saved and so is not available for
160 * reinstatement.
161 *
162 * Can be over-ridden by architecture specific code that implements
163 * reinstatement functionality rather than leaving it disabled when
164 * normal allocation attempts fail.
165 */
166resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
167{
168 return 0;
169}
170
171static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
172 int resno, resource_size_t size)
173{
174 struct resource *root, *conflict;
175 resource_size_t fw_addr, start, end;
176
177 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
178 if (!fw_addr)
179 return -ENOMEM;
180
181 start = res->start;
182 end = res->end;
183 res->start = fw_addr;
184 res->end = res->start + size - 1;
185 res->flags &= ~IORESOURCE_UNSET;
186
187 root = pci_find_parent_resource(dev, res);
188 if (!root) {
189 if (res->flags & IORESOURCE_IO)
190 root = &ioport_resource;
191 else
192 root = &iomem_resource;
193 }
194
195 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
196 resno, res);
197 conflict = request_resource_conflict(root, res);
198 if (conflict) {
199 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
200 resno, res, conflict->name, conflict);
201 res->start = start;
202 res->end = end;
203 res->flags |= IORESOURCE_UNSET;
204 return -EBUSY;
205 }
206 return 0;
207}
208
209static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
210 int resno, resource_size_t size, resource_size_t align)
211{
212 struct resource *res = dev->resource + resno;
213 resource_size_t min;
214 int ret;
215
216 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
217
218 /*
219 * First, try exact prefetching match. Even if a 64-bit
220 * prefetchable bridge window is below 4GB, we can't put a 32-bit
221 * prefetchable resource in it because pbus_size_mem() assumes a
222 * 64-bit window will contain no 32-bit resources. If we assign
223 * things differently than they were sized, not everything will fit.
224 */
225 ret = pci_bus_alloc_resource(bus, res, size, align, min,
226 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
227 pcibios_align_resource, dev);
228 if (ret == 0)
229 return 0;
230
231 /*
232 * If the prefetchable window is only 32 bits wide, we can put
233 * 64-bit prefetchable resources in it.
234 */
235 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
236 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
237 ret = pci_bus_alloc_resource(bus, res, size, align, min,
238 IORESOURCE_PREFETCH,
239 pcibios_align_resource, dev);
240 if (ret == 0)
241 return 0;
242 }
243
244 /*
245 * If we didn't find a better match, we can put any memory resource
246 * in a non-prefetchable window. If this resource is 32 bits and
247 * non-prefetchable, the first call already tried the only possibility
248 * so we don't need to try again.
249 */
250 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
251 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
252 pcibios_align_resource, dev);
253
254 return ret;
255}
256
257static int _pci_assign_resource(struct pci_dev *dev, int resno,
258 resource_size_t size, resource_size_t min_align)
259{
260 struct pci_bus *bus;
261 int ret;
262
263 bus = dev->bus;
264 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
265 if (!bus->parent || !bus->self->transparent)
266 break;
267 bus = bus->parent;
268 }
269
270 return ret;
271}
272
273int pci_assign_resource(struct pci_dev *dev, int resno)
274{
275 struct resource *res = dev->resource + resno;
276 resource_size_t align, size;
277 int ret;
278
279 if (res->flags & IORESOURCE_PCI_FIXED)
280 return 0;
281
282 res->flags |= IORESOURCE_UNSET;
283 align = pci_resource_alignment(dev, res);
284 if (!align) {
285 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
286 resno, res);
287 return -EINVAL;
288 }
289
290 size = resource_size(res);
291 ret = _pci_assign_resource(dev, resno, size, align);
292
293 /*
294 * If we failed to assign anything, let's try the address
295 * where firmware left it. That at least has a chance of
296 * working, which is better than just leaving it disabled.
297 */
298 if (ret < 0) {
299 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
300 ret = pci_revert_fw_address(res, dev, resno, size);
301 }
302
303 if (ret < 0) {
304 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
305 res);
306 return ret;
307 }
308
309 res->flags &= ~IORESOURCE_UNSET;
310 res->flags &= ~IORESOURCE_STARTALIGN;
311 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
312 if (resno < PCI_BRIDGE_RESOURCES)
313 pci_update_resource(dev, resno);
314
315 return 0;
316}
317EXPORT_SYMBOL(pci_assign_resource);
318
319int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
320 resource_size_t min_align)
321{
322 struct resource *res = dev->resource + resno;
323 unsigned long flags;
324 resource_size_t new_size;
325 int ret;
326
327 if (res->flags & IORESOURCE_PCI_FIXED)
328 return 0;
329
330 flags = res->flags;
331 res->flags |= IORESOURCE_UNSET;
332 if (!res->parent) {
333 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
334 resno, res);
335 return -EINVAL;
336 }
337
338 /* already aligned with min_align */
339 new_size = resource_size(res) + addsize;
340 ret = _pci_assign_resource(dev, resno, new_size, min_align);
341 if (ret) {
342 res->flags = flags;
343 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
344 resno, res, (unsigned long long) addsize);
345 return ret;
346 }
347
348 res->flags &= ~IORESOURCE_UNSET;
349 res->flags &= ~IORESOURCE_STARTALIGN;
350 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
351 resno, res, (unsigned long long) addsize);
352 if (resno < PCI_BRIDGE_RESOURCES)
353 pci_update_resource(dev, resno);
354
355 return 0;
356}
357
358int pci_enable_resources(struct pci_dev *dev, int mask)
359{
360 u16 cmd, old_cmd;
361 int i;
362 struct resource *r;
363
364 pci_read_config_word(dev, PCI_COMMAND, &cmd);
365 old_cmd = cmd;
366
367 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
368 if (!(mask & (1 << i)))
369 continue;
370
371 r = &dev->resource[i];
372
373 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
374 continue;
375 if ((i == PCI_ROM_RESOURCE) &&
376 (!(r->flags & IORESOURCE_ROM_ENABLE)))
377 continue;
378
379 if (r->flags & IORESOURCE_UNSET) {
380 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
381 i, r);
382 return -EINVAL;
383 }
384
385 if (!r->parent) {
386 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
387 i, r);
388 return -EINVAL;
389 }
390
391 if (r->flags & IORESOURCE_IO)
392 cmd |= PCI_COMMAND_IO;
393 if (r->flags & IORESOURCE_MEM)
394 cmd |= PCI_COMMAND_MEMORY;
395 }
396
397 if (cmd != old_cmd) {
398 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
399 old_cmd, cmd);
400 pci_write_config_word(dev, PCI_COMMAND, cmd);
401 }
402 return 0;
403}