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1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * BSD LICENSE
15 *
16 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 *
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copy
26 * notice, this list of conditions and the following disclaimer in
27 * the documentation and/or other materials provided with the
28 * distribution.
29 * * Neither the name of Intel Corporation nor the names of its
30 * contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * Intel PCIe NTB Linux driver
46 */
47
48#ifndef NTB_HW_INTEL_H
49#define NTB_HW_INTEL_H
50
51#include <linux/ntb.h>
52#include <linux/pci.h>
53#include <linux/io-64-nonatomic-lo-hi.h>
54
55/* PCI device IDs */
56#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
57#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
58#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
59#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
60#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
61#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
62#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
63#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
64#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
65#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
66#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
67#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
68#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
69#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
70#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
71#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
72#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
73#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
74
75/* Ntb control and link status */
76#define NTB_CTL_CFG_LOCK BIT(0)
77#define NTB_CTL_DISABLE BIT(1)
78#define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
79#define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
80#define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
81#define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
82#define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
83#define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
84
85#define NTB_LNK_STA_ACTIVE_BIT 0x2000
86#define NTB_LNK_STA_SPEED_MASK 0x000f
87#define NTB_LNK_STA_WIDTH_MASK 0x03f0
88#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
89#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
90#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
91
92/* flags to indicate unsafe api */
93#define NTB_UNSAFE_DB BIT_ULL(0)
94#define NTB_UNSAFE_SPAD BIT_ULL(1)
95
96#define NTB_BAR_MASK_64 ~(0xfull)
97#define NTB_BAR_MASK_32 ~(0xfu)
98
99struct intel_ntb_dev;
100
101struct intel_ntb_reg {
102 int (*poll_link)(struct intel_ntb_dev *ndev);
103 int (*link_is_up)(struct intel_ntb_dev *ndev);
104 u64 (*db_ioread)(const void __iomem *mmio);
105 void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
106 unsigned long ntb_ctl;
107 resource_size_t db_size;
108 int mw_bar[];
109};
110
111struct intel_ntb_alt_reg {
112 unsigned long db_bell;
113 unsigned long db_mask;
114 unsigned long db_clear;
115 unsigned long spad;
116};
117
118struct intel_ntb_xlat_reg {
119 unsigned long bar0_base;
120 unsigned long bar2_xlat;
121 unsigned long bar2_limit;
122 unsigned short bar2_idx;
123};
124
125struct intel_b2b_addr {
126 phys_addr_t bar0_addr;
127 phys_addr_t bar2_addr64;
128 phys_addr_t bar4_addr64;
129 phys_addr_t bar4_addr32;
130 phys_addr_t bar5_addr32;
131};
132
133struct intel_ntb_vec {
134 struct intel_ntb_dev *ndev;
135 int num;
136};
137
138struct intel_ntb_dev {
139 struct ntb_dev ntb;
140
141 /* offset of peer bar0 in b2b bar */
142 unsigned long b2b_off;
143 /* mw idx used to access peer bar0 */
144 unsigned int b2b_idx;
145
146 /* BAR45 is split into BAR4 and BAR5 */
147 bool bar4_split;
148
149 u32 ntb_ctl;
150 u32 lnk_sta;
151
152 unsigned char mw_count;
153 unsigned char spad_count;
154 unsigned char db_count;
155 unsigned char db_vec_count;
156 unsigned char db_vec_shift;
157
158 u64 db_valid_mask;
159 u64 db_link_mask;
160 u64 db_mask;
161
162 /* synchronize rmw access of db_mask and hw reg */
163 spinlock_t db_mask_lock;
164
165 struct msix_entry *msix;
166 struct intel_ntb_vec *vec;
167
168 const struct intel_ntb_reg *reg;
169 const struct intel_ntb_alt_reg *self_reg;
170 const struct intel_ntb_alt_reg *peer_reg;
171 const struct intel_ntb_xlat_reg *xlat_reg;
172 void __iomem *self_mmio;
173 void __iomem *peer_mmio;
174 phys_addr_t peer_addr;
175
176 unsigned long last_ts;
177 struct delayed_work hb_timer;
178
179 unsigned long hwerr_flags;
180 unsigned long unsafe_flags;
181 unsigned long unsafe_flags_ignore;
182
183 struct dentry *debugfs_dir;
184 struct dentry *debugfs_info;
185
186 /* gen4 entries */
187 int dev_up;
188};
189
190#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
191#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
192 hb_timer.work)
193
194static inline int pdev_is_gen1(struct pci_dev *pdev)
195{
196 switch (pdev->device) {
197 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
198 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
199 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
200 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
201 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
202 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
203 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
204 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
205 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
206 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
207 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
208 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
209 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
210 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
211 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
212 return 1;
213 }
214 return 0;
215}
216
217static inline int pdev_is_gen3(struct pci_dev *pdev)
218{
219 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
220 return 1;
221
222 return 0;
223}
224
225static inline int pdev_is_gen4(struct pci_dev *pdev)
226{
227 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
228 return 1;
229
230 return 0;
231}
232
233static inline int pdev_is_gen5(struct pci_dev *pdev)
234{
235 return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
236}
237
238#endif
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * BSD LICENSE
15 *
16 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 *
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copy
26 * notice, this list of conditions and the following disclaimer in
27 * the documentation and/or other materials provided with the
28 * distribution.
29 * * Neither the name of Intel Corporation nor the names of its
30 * contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * Intel PCIe NTB Linux driver
46 *
47 * Contact Information:
48 * Jon Mason <jon.mason@intel.com>
49 */
50
51#ifndef NTB_HW_INTEL_H
52#define NTB_HW_INTEL_H
53
54#include <linux/ntb.h>
55#include <linux/pci.h>
56
57#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
58#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
59#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
60#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
61#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
62#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
63#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
64#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
65#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
66#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
67#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
68#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
69#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
70#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
71#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
72#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
73
74/* Intel Xeon hardware */
75
76#define XEON_PBAR23LMT_OFFSET 0x0000
77#define XEON_PBAR45LMT_OFFSET 0x0008
78#define XEON_PBAR4LMT_OFFSET 0x0008
79#define XEON_PBAR5LMT_OFFSET 0x000c
80#define XEON_PBAR23XLAT_OFFSET 0x0010
81#define XEON_PBAR45XLAT_OFFSET 0x0018
82#define XEON_PBAR4XLAT_OFFSET 0x0018
83#define XEON_PBAR5XLAT_OFFSET 0x001c
84#define XEON_SBAR23LMT_OFFSET 0x0020
85#define XEON_SBAR45LMT_OFFSET 0x0028
86#define XEON_SBAR4LMT_OFFSET 0x0028
87#define XEON_SBAR5LMT_OFFSET 0x002c
88#define XEON_SBAR23XLAT_OFFSET 0x0030
89#define XEON_SBAR45XLAT_OFFSET 0x0038
90#define XEON_SBAR4XLAT_OFFSET 0x0038
91#define XEON_SBAR5XLAT_OFFSET 0x003c
92#define XEON_SBAR0BASE_OFFSET 0x0040
93#define XEON_SBAR23BASE_OFFSET 0x0048
94#define XEON_SBAR45BASE_OFFSET 0x0050
95#define XEON_SBAR4BASE_OFFSET 0x0050
96#define XEON_SBAR5BASE_OFFSET 0x0054
97#define XEON_SBDF_OFFSET 0x005c
98#define XEON_NTBCNTL_OFFSET 0x0058
99#define XEON_PDOORBELL_OFFSET 0x0060
100#define XEON_PDBMSK_OFFSET 0x0062
101#define XEON_SDOORBELL_OFFSET 0x0064
102#define XEON_SDBMSK_OFFSET 0x0066
103#define XEON_USMEMMISS_OFFSET 0x0070
104#define XEON_SPAD_OFFSET 0x0080
105#define XEON_PBAR23SZ_OFFSET 0x00d0
106#define XEON_PBAR45SZ_OFFSET 0x00d1
107#define XEON_PBAR4SZ_OFFSET 0x00d1
108#define XEON_SBAR23SZ_OFFSET 0x00d2
109#define XEON_SBAR45SZ_OFFSET 0x00d3
110#define XEON_SBAR4SZ_OFFSET 0x00d3
111#define XEON_PPD_OFFSET 0x00d4
112#define XEON_PBAR5SZ_OFFSET 0x00d5
113#define XEON_SBAR5SZ_OFFSET 0x00d6
114#define XEON_WCCNTRL_OFFSET 0x00e0
115#define XEON_UNCERRSTS_OFFSET 0x014c
116#define XEON_CORERRSTS_OFFSET 0x0158
117#define XEON_LINK_STATUS_OFFSET 0x01a2
118#define XEON_SPCICMD_OFFSET 0x0504
119#define XEON_DEVCTRL_OFFSET 0x0598
120#define XEON_DEVSTS_OFFSET 0x059a
121#define XEON_SLINK_STATUS_OFFSET 0x05a2
122#define XEON_B2B_SPAD_OFFSET 0x0100
123#define XEON_B2B_DOORBELL_OFFSET 0x0140
124#define XEON_B2B_XLAT_OFFSETL 0x0144
125#define XEON_B2B_XLAT_OFFSETU 0x0148
126#define XEON_PPD_CONN_MASK 0x03
127#define XEON_PPD_CONN_TRANSPARENT 0x00
128#define XEON_PPD_CONN_B2B 0x01
129#define XEON_PPD_CONN_RP 0x02
130#define XEON_PPD_DEV_MASK 0x10
131#define XEON_PPD_DEV_USD 0x00
132#define XEON_PPD_DEV_DSD 0x10
133#define XEON_PPD_SPLIT_BAR_MASK 0x40
134
135#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
136#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
137#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
138#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
139#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
140#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
141#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
142
143#define XEON_MW_COUNT 2
144#define HSX_SPLIT_BAR_MW_COUNT 3
145#define XEON_DB_COUNT 15
146#define XEON_DB_LINK 15
147#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
148#define XEON_DB_MSIX_VECTOR_COUNT 4
149#define XEON_DB_MSIX_VECTOR_SHIFT 5
150#define XEON_DB_TOTAL_SHIFT 16
151#define XEON_SPAD_COUNT 16
152
153/* Intel Atom hardware */
154
155#define ATOM_SBAR2XLAT_OFFSET 0x0008
156#define ATOM_PDOORBELL_OFFSET 0x0020
157#define ATOM_PDBMSK_OFFSET 0x0028
158#define ATOM_NTBCNTL_OFFSET 0x0060
159#define ATOM_SPAD_OFFSET 0x0080
160#define ATOM_PPD_OFFSET 0x00d4
161#define ATOM_PBAR2XLAT_OFFSET 0x8008
162#define ATOM_B2B_DOORBELL_OFFSET 0x8020
163#define ATOM_B2B_SPAD_OFFSET 0x8080
164#define ATOM_SPCICMD_OFFSET 0xb004
165#define ATOM_LINK_STATUS_OFFSET 0xb052
166#define ATOM_ERRCORSTS_OFFSET 0xb110
167#define ATOM_IP_BASE 0xc000
168#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
169#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
170#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
171#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
172#define ATOM_MODPHY_PCSREG4 0x1c004
173#define ATOM_MODPHY_PCSREG6 0x1c006
174
175#define ATOM_PPD_INIT_LINK 0x0008
176#define ATOM_PPD_CONN_MASK 0x0300
177#define ATOM_PPD_CONN_TRANSPARENT 0x0000
178#define ATOM_PPD_CONN_B2B 0x0100
179#define ATOM_PPD_CONN_RP 0x0200
180#define ATOM_PPD_DEV_MASK 0x1000
181#define ATOM_PPD_DEV_USD 0x0000
182#define ATOM_PPD_DEV_DSD 0x1000
183#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK)
184#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD)
185#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD)
186#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD)
187#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD)
188#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD)
189#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD)
190
191#define ATOM_MW_COUNT 2
192#define ATOM_DB_COUNT 34
193#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1)
194#define ATOM_DB_MSIX_VECTOR_COUNT 34
195#define ATOM_DB_MSIX_VECTOR_SHIFT 1
196#define ATOM_DB_TOTAL_SHIFT 34
197#define ATOM_SPAD_COUNT 16
198
199#define ATOM_NTB_CTL_DOWN_BIT BIT(16)
200#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT)
201
202#define ATOM_DESKEWSTS_DBERR BIT(15)
203#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
204#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2)
205#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF
206
207#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
208#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500)
209
210/* Ntb control and link status */
211
212#define NTB_CTL_CFG_LOCK BIT(0)
213#define NTB_CTL_DISABLE BIT(1)
214#define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
215#define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
216#define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
217#define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
218#define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
219#define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
220
221#define NTB_LNK_STA_ACTIVE_BIT 0x2000
222#define NTB_LNK_STA_SPEED_MASK 0x000f
223#define NTB_LNK_STA_WIDTH_MASK 0x03f0
224#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
225#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
226#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
227
228/* Use the following addresses for translation between b2b ntb devices in case
229 * the hardware default values are not reliable. */
230#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
231#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
232#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
233#define XEON_B2B_BAR4_ADDR32 0x20000000u
234#define XEON_B2B_BAR5_ADDR32 0x40000000u
235
236/* The peer ntb secondary config space is 32KB fixed size */
237#define XEON_B2B_MIN_SIZE 0x8000
238
239/* flags to indicate hardware errata */
240#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
241#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
242#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
243
244/* flags to indicate unsafe api */
245#define NTB_UNSAFE_DB BIT_ULL(0)
246#define NTB_UNSAFE_SPAD BIT_ULL(1)
247
248#define NTB_BAR_MASK_64 ~(0xfull)
249#define NTB_BAR_MASK_32 ~(0xfu)
250
251struct intel_ntb_dev;
252
253struct intel_ntb_reg {
254 int (*poll_link)(struct intel_ntb_dev *ndev);
255 int (*link_is_up)(struct intel_ntb_dev *ndev);
256 u64 (*db_ioread)(void __iomem *mmio);
257 void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
258 unsigned long ntb_ctl;
259 resource_size_t db_size;
260 int mw_bar[];
261};
262
263struct intel_ntb_alt_reg {
264 unsigned long db_bell;
265 unsigned long db_mask;
266 unsigned long spad;
267};
268
269struct intel_ntb_xlat_reg {
270 unsigned long bar0_base;
271 unsigned long bar2_xlat;
272 unsigned long bar2_limit;
273};
274
275struct intel_b2b_addr {
276 phys_addr_t bar0_addr;
277 phys_addr_t bar2_addr64;
278 phys_addr_t bar4_addr64;
279 phys_addr_t bar4_addr32;
280 phys_addr_t bar5_addr32;
281};
282
283struct intel_ntb_vec {
284 struct intel_ntb_dev *ndev;
285 int num;
286};
287
288struct intel_ntb_dev {
289 struct ntb_dev ntb;
290
291 /* offset of peer bar0 in b2b bar */
292 unsigned long b2b_off;
293 /* mw idx used to access peer bar0 */
294 unsigned int b2b_idx;
295
296 /* BAR45 is split into BAR4 and BAR5 */
297 bool bar4_split;
298
299 u32 ntb_ctl;
300 u32 lnk_sta;
301
302 unsigned char mw_count;
303 unsigned char spad_count;
304 unsigned char db_count;
305 unsigned char db_vec_count;
306 unsigned char db_vec_shift;
307
308 u64 db_valid_mask;
309 u64 db_link_mask;
310 u64 db_mask;
311
312 /* synchronize rmw access of db_mask and hw reg */
313 spinlock_t db_mask_lock;
314
315 struct msix_entry *msix;
316 struct intel_ntb_vec *vec;
317
318 const struct intel_ntb_reg *reg;
319 const struct intel_ntb_alt_reg *self_reg;
320 const struct intel_ntb_alt_reg *peer_reg;
321 const struct intel_ntb_xlat_reg *xlat_reg;
322 void __iomem *self_mmio;
323 void __iomem *peer_mmio;
324 phys_addr_t peer_addr;
325
326 unsigned long last_ts;
327 struct delayed_work hb_timer;
328
329 unsigned long hwerr_flags;
330 unsigned long unsafe_flags;
331 unsigned long unsafe_flags_ignore;
332
333 struct dentry *debugfs_dir;
334 struct dentry *debugfs_info;
335};
336
337#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
338#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
339#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
340#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
341#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
342 hb_timer.work)
343
344#endif