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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6#ifndef ATH11K_HAL_RX_H
7#define ATH11K_HAL_RX_H
8
9struct hal_rx_wbm_rel_info {
10 u32 cookie;
11 enum hal_wbm_rel_src_module err_rel_src;
12 enum hal_reo_dest_ring_push_reason push_reason;
13 u32 err_code;
14 bool first_msdu;
15 bool last_msdu;
16};
17
18#define HAL_INVALID_PEERID 0xffff
19#define VHT_SIG_SU_NSS_MASK 0x7
20
21#define HAL_RX_MAX_MCS 12
22#define HAL_RX_MAX_NSS 8
23
24struct hal_rx_mon_status_tlv_hdr {
25 u32 hdr;
26 u8 value[];
27};
28
29enum hal_rx_su_mu_coding {
30 HAL_RX_SU_MU_CODING_BCC,
31 HAL_RX_SU_MU_CODING_LDPC,
32 HAL_RX_SU_MU_CODING_MAX,
33};
34
35enum hal_rx_gi {
36 HAL_RX_GI_0_8_US,
37 HAL_RX_GI_0_4_US,
38 HAL_RX_GI_1_6_US,
39 HAL_RX_GI_3_2_US,
40 HAL_RX_GI_MAX,
41};
42
43enum hal_rx_bw {
44 HAL_RX_BW_20MHZ,
45 HAL_RX_BW_40MHZ,
46 HAL_RX_BW_80MHZ,
47 HAL_RX_BW_160MHZ,
48 HAL_RX_BW_MAX,
49};
50
51enum hal_rx_preamble {
52 HAL_RX_PREAMBLE_11A,
53 HAL_RX_PREAMBLE_11B,
54 HAL_RX_PREAMBLE_11N,
55 HAL_RX_PREAMBLE_11AC,
56 HAL_RX_PREAMBLE_11AX,
57 HAL_RX_PREAMBLE_MAX,
58};
59
60enum hal_rx_reception_type {
61 HAL_RX_RECEPTION_TYPE_SU,
62 HAL_RX_RECEPTION_TYPE_MU_MIMO,
63 HAL_RX_RECEPTION_TYPE_MU_OFDMA,
64 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
65 HAL_RX_RECEPTION_TYPE_MAX,
66};
67
68#define HAL_RX_FCS_LEN 4
69
70enum hal_rx_mon_status {
71 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
72 HAL_RX_MON_STATUS_PPDU_DONE,
73 HAL_RX_MON_STATUS_BUF_DONE,
74};
75
76struct hal_rx_user_status {
77 u32 mcs:4,
78 nss:3,
79 ofdma_info_valid:1,
80 dl_ofdma_ru_start_index:7,
81 dl_ofdma_ru_width:7,
82 dl_ofdma_ru_size:8;
83 u32 ul_ofdma_user_v0_word0;
84 u32 ul_ofdma_user_v0_word1;
85 u32 ast_index;
86 u32 tid;
87 u16 tcp_msdu_count;
88 u16 udp_msdu_count;
89 u16 other_msdu_count;
90 u16 frame_control;
91 u8 frame_control_info_valid;
92 u8 data_sequence_control_info_valid;
93 u16 first_data_seq_ctrl;
94 u32 preamble_type;
95 u16 ht_flags;
96 u16 vht_flags;
97 u16 he_flags;
98 u8 rs_flags;
99 u32 mpdu_cnt_fcs_ok;
100 u32 mpdu_cnt_fcs_err;
101 u32 mpdu_fcs_ok_bitmap[8];
102 u32 mpdu_ok_byte_count;
103 u32 mpdu_err_byte_count;
104};
105
106#define HAL_TLV_STATUS_PPDU_NOT_DONE HAL_RX_MON_STATUS_PPDU_NOT_DONE
107#define HAL_TLV_STATUS_PPDU_DONE HAL_RX_MON_STATUS_PPDU_DONE
108#define HAL_TLV_STATUS_BUF_DONE HAL_RX_MON_STATUS_BUF_DONE
109
110struct hal_sw_mon_ring_entries {
111 dma_addr_t mon_dst_paddr;
112 dma_addr_t mon_status_paddr;
113 u32 mon_dst_sw_cookie;
114 u32 mon_status_sw_cookie;
115 void *dst_buf_addr_info;
116 void *status_buf_addr_info;
117 u16 ppdu_id;
118 u8 status_buf_count;
119 u8 msdu_cnt;
120 bool end_of_ppdu;
121 bool drop_ppdu;
122};
123
124struct hal_rx_mon_ppdu_info {
125 u32 ppdu_id;
126 u32 ppdu_ts;
127 u32 num_mpdu_fcs_ok;
128 u32 num_mpdu_fcs_err;
129 u32 preamble_type;
130 u16 chan_num;
131 u16 tcp_msdu_count;
132 u16 tcp_ack_msdu_count;
133 u16 udp_msdu_count;
134 u16 other_msdu_count;
135 u16 peer_id;
136 u8 rate;
137 u8 mcs;
138 u8 nss;
139 u8 bw;
140 u8 vht_flag_values1;
141 u8 vht_flag_values2;
142 u8 vht_flag_values3[4];
143 u8 vht_flag_values4;
144 u8 vht_flag_values5;
145 u16 vht_flag_values6;
146 u8 is_stbc;
147 u8 gi;
148 u8 ldpc;
149 u8 beamformed;
150 u8 rssi_comb;
151 u8 rssi_chain_pri20[HAL_RX_MAX_NSS];
152 u8 tid;
153 u16 ht_flags;
154 u16 vht_flags;
155 u16 he_flags;
156 u16 he_mu_flags;
157 u8 dcm;
158 u8 ru_alloc;
159 u8 reception_type;
160 u64 tsft;
161 u64 rx_duration;
162 u16 frame_control;
163 u32 ast_index;
164 u8 rs_fcs_err;
165 u8 rs_flags;
166 u8 cck_flag;
167 u8 ofdm_flag;
168 u8 ulofdma_flag;
169 u8 frame_control_info_valid;
170 u16 he_per_user_1;
171 u16 he_per_user_2;
172 u8 he_per_user_position;
173 u8 he_per_user_known;
174 u16 he_flags1;
175 u16 he_flags2;
176 u8 he_RU[4];
177 u16 he_data1;
178 u16 he_data2;
179 u16 he_data3;
180 u16 he_data4;
181 u16 he_data5;
182 u16 he_data6;
183 u32 ppdu_len;
184 u32 prev_ppdu_id;
185 u32 device_id;
186 u16 first_data_seq_ctrl;
187 u8 monitor_direct_used;
188 u8 data_sequence_control_info_valid;
189 u8 ltf_size;
190 u8 rxpcu_filter_pass;
191 char rssi_chain[8][8];
192 struct hal_rx_user_status userstats;
193};
194
195#define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
196
197struct hal_rx_ppdu_start {
198 __le32 info0;
199 __le32 chan_num;
200 __le32 ppdu_start_ts;
201} __packed;
202
203#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)
204
205#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)
206#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
207#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
208#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
209#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)
210
211#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
212#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
213
214#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
215
216#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
217#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
218
219#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
220#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
221
222#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
223#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
224
225#define HAL_RX_PPDU_END_USER_STATS_RSVD2_6_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
226#define HAL_RX_PPDU_END_USER_STATS_RSVD2_8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
227
228struct hal_rx_ppdu_end_user_stats {
229 __le32 rsvd0[2];
230 __le32 info0;
231 __le32 info1;
232 __le32 info2;
233 __le32 info3;
234 __le32 ht_ctrl;
235 __le32 rsvd1[2];
236 __le32 info4;
237 __le32 info5;
238 __le32 info6;
239 __le32 rsvd2[11];
240} __packed;
241
242struct hal_rx_ppdu_end_user_stats_ext {
243 u32 info0;
244 u32 info1;
245 u32 info2;
246 u32 info3;
247 u32 info4;
248 u32 info5;
249 u32 info6;
250} __packed;
251
252#define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
253#define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
254
255#define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
256#define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
257#define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
258
259struct hal_rx_ht_sig_info {
260 __le32 info0;
261 __le32 info1;
262} __packed;
263
264#define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
265#define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
266
267struct hal_rx_lsig_b_info {
268 __le32 info0;
269} __packed;
270
271#define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
272#define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
273#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
274
275struct hal_rx_lsig_a_info {
276 __le32 info0;
277} __packed;
278
279#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
280#define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
281#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
282#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
283
284#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
285#define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
286#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
287#define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
288
289struct hal_rx_vht_sig_a_info {
290 __le32 info0;
291 __le32 info1;
292} __packed;
293
294enum hal_rx_vht_sig_a_gi_setting {
295 HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
296 HAL_RX_VHT_SIG_A_SHORT_GI = 1,
297 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
298};
299
300#define HAL_RX_SU_MU_CODING_LDPC 0x01
301
302#define HE_GI_0_8 0
303#define HE_GI_0_4 1
304#define HE_GI_1_6 2
305#define HE_GI_3_2 3
306
307#define HE_LTF_1_X 0
308#define HE_LTF_2_X 1
309#define HE_LTF_4_X 2
310#define HE_LTF_UNKNOWN 3
311
312#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
313#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
314#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
315#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
316#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
317#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
318#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
319#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
320#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
321#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
322
323#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
324#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
325#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
326#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
327#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
328#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
329#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
330#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
331
332struct hal_rx_he_sig_a_su_info {
333 __le32 info0;
334 __le32 info1;
335} __packed;
336
337#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG BIT(1)
338#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB GENMASK(3, 1)
339#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB BIT(4)
340#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR GENMASK(10, 5)
341#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE GENMASK(14, 11)
342#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW GENMASK(17, 15)
343#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
344#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB BIT(22)
345#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE GENMASK(24, 23)
346#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION BIT(25)
347
348#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
349#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_CODING BIT(7)
350#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
351#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA BIT(11)
352#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC BIT(12)
353#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXBF BIT(10)
354#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
355#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM BIT(15)
356
357struct hal_rx_he_sig_a_mu_dl_info {
358 __le32 info0;
359 __le32 info1;
360} __packed;
361
362#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
363
364struct hal_rx_he_sig_b1_mu_info {
365 __le32 info0;
366} __packed;
367
368#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
369#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
370#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
371#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
372
373struct hal_rx_he_sig_b2_mu_info {
374 __le32 info0;
375} __packed;
376
377#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
378#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
379#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19)
380#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
381#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
382#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
383
384struct hal_rx_he_sig_b2_ofdma_info {
385 __le32 info0;
386} __packed;
387
388#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)
389
390#define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 GENMASK(7, 0)
391
392struct hal_rx_phyrx_chain_rssi {
393 __le32 rssi_2040;
394 __le32 rssi_80;
395} __packed;
396
397struct hal_rx_phyrx_rssi_legacy_info {
398 __le32 rsvd[3];
399 struct hal_rx_phyrx_chain_rssi pre_rssi[HAL_RX_MAX_NSS];
400 struct hal_rx_phyrx_chain_rssi preamble[HAL_RX_MAX_NSS];
401 __le32 info0;
402} __packed;
403
404#define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)
405#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0)
406#define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN GENMASK(13, 0)
407
408struct hal_rx_mpdu_info {
409 __le32 rsvd0;
410 __le32 info0;
411 __le32 rsvd1[11];
412 __le32 info1;
413 __le32 rsvd2[9];
414} __packed;
415
416struct hal_rx_mpdu_info_wcn6855 {
417 __le32 rsvd0[8];
418 __le32 info0;
419 __le32 rsvd1[14];
420} __packed;
421
422#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
423struct hal_rx_ppdu_end_duration {
424 __le32 rsvd0[9];
425 __le32 info0;
426 __le32 rsvd1[4];
427} __packed;
428
429struct hal_rx_rxpcu_classification_overview {
430 u32 rsvd0;
431} __packed;
432
433struct hal_rx_msdu_desc_info {
434 u32 msdu_flags;
435 u16 msdu_len; /* 14 bits for length */
436};
437
438#define HAL_RX_NUM_MSDU_DESC 6
439struct hal_rx_msdu_list {
440 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
441 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
442 u8 rbm[HAL_RX_NUM_MSDU_DESC];
443};
444
445void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
446 struct hal_reo_status *status);
447void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
448 struct hal_reo_status *status);
449void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
450 struct hal_reo_status *status);
451void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
452 struct hal_reo_status *status);
453void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
454 struct hal_reo_status *status);
455void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
456 u32 *reo_desc,
457 struct hal_reo_status *status);
458void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
459 u32 *reo_desc,
460 struct hal_reo_status *status);
461void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
462 u32 *reo_desc,
463 struct hal_reo_status *status);
464int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status);
465void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
466 u32 *msdu_cookies,
467 enum hal_rx_buf_return_buf_manager *rbm);
468void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
469 void *link_desc,
470 enum hal_wbm_rel_bm_act action);
471void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
472 u32 cookie, u8 manager);
473void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
474 u32 *cookie, u8 *rbm);
475int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
476 dma_addr_t *paddr, u32 *desc_bank);
477int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
478 struct hal_rx_wbm_rel_info *rel_info);
479void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
480 dma_addr_t *paddr, u32 *desc_bank);
481void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
482 dma_addr_t *paddr, u32 *sw_cookie,
483 void **pp_buf_addr_info, u8 *rbm,
484 u32 *msdu_cnt);
485void
486ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
487 struct hal_sw_mon_ring_entries *sw_mon_ent);
488enum hal_rx_mon_status
489ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
490 struct hal_rx_mon_ppdu_info *ppdu_info,
491 struct sk_buff *skb);
492
493#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
494#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
495#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
496#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
497#endif