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1// SPDX-License-Identifier: ISC
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 */
6
7#include <linux/pci.h>
8#include <linux/module.h>
9#include <linux/interrupt.h>
10#include <linux/spinlock.h>
11#include <linux/bitops.h>
12
13#include "core.h"
14#include "debug.h"
15#include "coredump.h"
16
17#include "targaddrs.h"
18#include "bmi.h"
19
20#include "hif.h"
21#include "htc.h"
22
23#include "ce.h"
24#include "pci.h"
25
26enum ath10k_pci_reset_mode {
27 ATH10K_PCI_RESET_AUTO = 0,
28 ATH10K_PCI_RESET_WARM_ONLY = 1,
29};
30
31static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
32static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
33
34module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
35MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
36
37module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
38MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
39
40/* how long wait to wait for target to initialise, in ms */
41#define ATH10K_PCI_TARGET_WAIT 3000
42#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
43
44/* Maximum number of bytes that can be handled atomically by
45 * diag read and write.
46 */
47#define ATH10K_DIAG_TRANSFER_LIMIT 0x5000
48
49#define QCA99X0_PCIE_BAR0_START_REG 0x81030
50#define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c
51#define QCA99X0_CPU_MEM_DATA_REG 0x4d010
52
53static const struct pci_device_id ath10k_pci_id_table[] = {
54 /* PCI-E QCA988X V2 (Ubiquiti branded) */
55 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) },
56
57 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
58 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
59 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
60 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
61 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
62 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
63 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
64 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
65 {0}
66};
67
68static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
69 /* QCA988X pre 2.0 chips are not supported because they need some nasty
70 * hacks. ath10k doesn't have them and these devices crash horribly
71 * because of that.
72 */
73 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV },
74 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
75
76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
78 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
79 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
81
82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
84 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
85 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
87
88 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
89
90 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
91
92 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
93
94 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
95 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
96
97 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
98};
99
100static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
101static int ath10k_pci_cold_reset(struct ath10k *ar);
102static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
103static int ath10k_pci_init_irq(struct ath10k *ar);
104static int ath10k_pci_deinit_irq(struct ath10k *ar);
105static int ath10k_pci_request_irq(struct ath10k *ar);
106static void ath10k_pci_free_irq(struct ath10k *ar);
107static int ath10k_pci_bmi_wait(struct ath10k *ar,
108 struct ath10k_ce_pipe *tx_pipe,
109 struct ath10k_ce_pipe *rx_pipe,
110 struct bmi_xfer *xfer);
111static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
112static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
113static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
114static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
115static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
116static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
117static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
118
119static const struct ce_attr pci_host_ce_config_wlan[] = {
120 /* CE0: host->target HTC control and raw streams */
121 {
122 .flags = CE_ATTR_FLAGS,
123 .src_nentries = 16,
124 .src_sz_max = 256,
125 .dest_nentries = 0,
126 .send_cb = ath10k_pci_htc_tx_cb,
127 },
128
129 /* CE1: target->host HTT + HTC control */
130 {
131 .flags = CE_ATTR_FLAGS,
132 .src_nentries = 0,
133 .src_sz_max = 2048,
134 .dest_nentries = 512,
135 .recv_cb = ath10k_pci_htt_htc_rx_cb,
136 },
137
138 /* CE2: target->host WMI */
139 {
140 .flags = CE_ATTR_FLAGS,
141 .src_nentries = 0,
142 .src_sz_max = 2048,
143 .dest_nentries = 128,
144 .recv_cb = ath10k_pci_htc_rx_cb,
145 },
146
147 /* CE3: host->target WMI */
148 {
149 .flags = CE_ATTR_FLAGS,
150 .src_nentries = 32,
151 .src_sz_max = 2048,
152 .dest_nentries = 0,
153 .send_cb = ath10k_pci_htc_tx_cb,
154 },
155
156 /* CE4: host->target HTT */
157 {
158 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
159 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
160 .src_sz_max = 256,
161 .dest_nentries = 0,
162 .send_cb = ath10k_pci_htt_tx_cb,
163 },
164
165 /* CE5: target->host HTT (HIF->HTT) */
166 {
167 .flags = CE_ATTR_FLAGS,
168 .src_nentries = 0,
169 .src_sz_max = 512,
170 .dest_nentries = 512,
171 .recv_cb = ath10k_pci_htt_rx_cb,
172 },
173
174 /* CE6: target autonomous hif_memcpy */
175 {
176 .flags = CE_ATTR_FLAGS,
177 .src_nentries = 0,
178 .src_sz_max = 0,
179 .dest_nentries = 0,
180 },
181
182 /* CE7: ce_diag, the Diagnostic Window */
183 {
184 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL,
185 .src_nentries = 2,
186 .src_sz_max = DIAG_TRANSFER_LIMIT,
187 .dest_nentries = 2,
188 },
189
190 /* CE8: target->host pktlog */
191 {
192 .flags = CE_ATTR_FLAGS,
193 .src_nentries = 0,
194 .src_sz_max = 2048,
195 .dest_nentries = 128,
196 .recv_cb = ath10k_pci_pktlog_rx_cb,
197 },
198
199 /* CE9 target autonomous qcache memcpy */
200 {
201 .flags = CE_ATTR_FLAGS,
202 .src_nentries = 0,
203 .src_sz_max = 0,
204 .dest_nentries = 0,
205 },
206
207 /* CE10: target autonomous hif memcpy */
208 {
209 .flags = CE_ATTR_FLAGS,
210 .src_nentries = 0,
211 .src_sz_max = 0,
212 .dest_nentries = 0,
213 },
214
215 /* CE11: target autonomous hif memcpy */
216 {
217 .flags = CE_ATTR_FLAGS,
218 .src_nentries = 0,
219 .src_sz_max = 0,
220 .dest_nentries = 0,
221 },
222};
223
224/* Target firmware's Copy Engine configuration. */
225static const struct ce_pipe_config pci_target_ce_config_wlan[] = {
226 /* CE0: host->target HTC control and raw streams */
227 {
228 .pipenum = __cpu_to_le32(0),
229 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
230 .nentries = __cpu_to_le32(32),
231 .nbytes_max = __cpu_to_le32(256),
232 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
233 .reserved = __cpu_to_le32(0),
234 },
235
236 /* CE1: target->host HTT + HTC control */
237 {
238 .pipenum = __cpu_to_le32(1),
239 .pipedir = __cpu_to_le32(PIPEDIR_IN),
240 .nentries = __cpu_to_le32(32),
241 .nbytes_max = __cpu_to_le32(2048),
242 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
243 .reserved = __cpu_to_le32(0),
244 },
245
246 /* CE2: target->host WMI */
247 {
248 .pipenum = __cpu_to_le32(2),
249 .pipedir = __cpu_to_le32(PIPEDIR_IN),
250 .nentries = __cpu_to_le32(64),
251 .nbytes_max = __cpu_to_le32(2048),
252 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
253 .reserved = __cpu_to_le32(0),
254 },
255
256 /* CE3: host->target WMI */
257 {
258 .pipenum = __cpu_to_le32(3),
259 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
260 .nentries = __cpu_to_le32(32),
261 .nbytes_max = __cpu_to_le32(2048),
262 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
263 .reserved = __cpu_to_le32(0),
264 },
265
266 /* CE4: host->target HTT */
267 {
268 .pipenum = __cpu_to_le32(4),
269 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
270 .nentries = __cpu_to_le32(256),
271 .nbytes_max = __cpu_to_le32(256),
272 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
273 .reserved = __cpu_to_le32(0),
274 },
275
276 /* NB: 50% of src nentries, since tx has 2 frags */
277
278 /* CE5: target->host HTT (HIF->HTT) */
279 {
280 .pipenum = __cpu_to_le32(5),
281 .pipedir = __cpu_to_le32(PIPEDIR_IN),
282 .nentries = __cpu_to_le32(32),
283 .nbytes_max = __cpu_to_le32(512),
284 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
285 .reserved = __cpu_to_le32(0),
286 },
287
288 /* CE6: Reserved for target autonomous hif_memcpy */
289 {
290 .pipenum = __cpu_to_le32(6),
291 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
292 .nentries = __cpu_to_le32(32),
293 .nbytes_max = __cpu_to_le32(4096),
294 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
295 .reserved = __cpu_to_le32(0),
296 },
297
298 /* CE7 used only by Host */
299 {
300 .pipenum = __cpu_to_le32(7),
301 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
302 .nentries = __cpu_to_le32(0),
303 .nbytes_max = __cpu_to_le32(0),
304 .flags = __cpu_to_le32(0),
305 .reserved = __cpu_to_le32(0),
306 },
307
308 /* CE8 target->host packtlog */
309 {
310 .pipenum = __cpu_to_le32(8),
311 .pipedir = __cpu_to_le32(PIPEDIR_IN),
312 .nentries = __cpu_to_le32(64),
313 .nbytes_max = __cpu_to_le32(2048),
314 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
315 .reserved = __cpu_to_le32(0),
316 },
317
318 /* CE9 target autonomous qcache memcpy */
319 {
320 .pipenum = __cpu_to_le32(9),
321 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
322 .nentries = __cpu_to_le32(32),
323 .nbytes_max = __cpu_to_le32(2048),
324 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
325 .reserved = __cpu_to_le32(0),
326 },
327
328 /* It not necessary to send target wlan configuration for CE10 & CE11
329 * as these CEs are not actively used in target.
330 */
331};
332
333/*
334 * Map from service/endpoint to Copy Engine.
335 * This table is derived from the CE_PCI TABLE, above.
336 * It is passed to the Target at startup for use by firmware.
337 */
338static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = {
339 {
340 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
341 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
342 __cpu_to_le32(3),
343 },
344 {
345 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
346 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
347 __cpu_to_le32(2),
348 },
349 {
350 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
351 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
352 __cpu_to_le32(3),
353 },
354 {
355 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
356 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
357 __cpu_to_le32(2),
358 },
359 {
360 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
361 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
362 __cpu_to_le32(3),
363 },
364 {
365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
366 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
367 __cpu_to_le32(2),
368 },
369 {
370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
371 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
372 __cpu_to_le32(3),
373 },
374 {
375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
376 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
377 __cpu_to_le32(2),
378 },
379 {
380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
381 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
382 __cpu_to_le32(3),
383 },
384 {
385 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
386 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
387 __cpu_to_le32(2),
388 },
389 {
390 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
391 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
392 __cpu_to_le32(0),
393 },
394 {
395 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
396 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
397 __cpu_to_le32(1),
398 },
399 { /* not used */
400 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
401 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
402 __cpu_to_le32(0),
403 },
404 { /* not used */
405 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
406 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
407 __cpu_to_le32(1),
408 },
409 {
410 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
411 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
412 __cpu_to_le32(4),
413 },
414 {
415 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
416 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
417 __cpu_to_le32(5),
418 },
419
420 /* (Additions here) */
421
422 { /* must be last */
423 __cpu_to_le32(0),
424 __cpu_to_le32(0),
425 __cpu_to_le32(0),
426 },
427};
428
429static bool ath10k_pci_is_awake(struct ath10k *ar)
430{
431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
432 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
433 RTC_STATE_ADDRESS);
434
435 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
436}
437
438static void __ath10k_pci_wake(struct ath10k *ar)
439{
440 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
441
442 lockdep_assert_held(&ar_pci->ps_lock);
443
444 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
445 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
446
447 iowrite32(PCIE_SOC_WAKE_V_MASK,
448 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
449 PCIE_SOC_WAKE_ADDRESS);
450}
451
452static void __ath10k_pci_sleep(struct ath10k *ar)
453{
454 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
455
456 lockdep_assert_held(&ar_pci->ps_lock);
457
458 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
459 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
460
461 iowrite32(PCIE_SOC_WAKE_RESET,
462 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
463 PCIE_SOC_WAKE_ADDRESS);
464 ar_pci->ps_awake = false;
465}
466
467static int ath10k_pci_wake_wait(struct ath10k *ar)
468{
469 int tot_delay = 0;
470 int curr_delay = 5;
471
472 while (tot_delay < PCIE_WAKE_TIMEOUT) {
473 if (ath10k_pci_is_awake(ar)) {
474 if (tot_delay > PCIE_WAKE_LATE_US)
475 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
476 tot_delay / 1000);
477 return 0;
478 }
479
480 udelay(curr_delay);
481 tot_delay += curr_delay;
482
483 if (curr_delay < 50)
484 curr_delay += 5;
485 }
486
487 return -ETIMEDOUT;
488}
489
490static int ath10k_pci_force_wake(struct ath10k *ar)
491{
492 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
493 unsigned long flags;
494 int ret = 0;
495
496 if (ar_pci->pci_ps)
497 return ret;
498
499 spin_lock_irqsave(&ar_pci->ps_lock, flags);
500
501 if (!ar_pci->ps_awake) {
502 iowrite32(PCIE_SOC_WAKE_V_MASK,
503 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
504 PCIE_SOC_WAKE_ADDRESS);
505
506 ret = ath10k_pci_wake_wait(ar);
507 if (ret == 0)
508 ar_pci->ps_awake = true;
509 }
510
511 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
512
513 return ret;
514}
515
516static void ath10k_pci_force_sleep(struct ath10k *ar)
517{
518 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
519 unsigned long flags;
520
521 spin_lock_irqsave(&ar_pci->ps_lock, flags);
522
523 iowrite32(PCIE_SOC_WAKE_RESET,
524 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
525 PCIE_SOC_WAKE_ADDRESS);
526 ar_pci->ps_awake = false;
527
528 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
529}
530
531static int ath10k_pci_wake(struct ath10k *ar)
532{
533 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
534 unsigned long flags;
535 int ret = 0;
536
537 if (ar_pci->pci_ps == 0)
538 return ret;
539
540 spin_lock_irqsave(&ar_pci->ps_lock, flags);
541
542 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
543 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
544
545 /* This function can be called very frequently. To avoid excessive
546 * CPU stalls for MMIO reads use a cache var to hold the device state.
547 */
548 if (!ar_pci->ps_awake) {
549 __ath10k_pci_wake(ar);
550
551 ret = ath10k_pci_wake_wait(ar);
552 if (ret == 0)
553 ar_pci->ps_awake = true;
554 }
555
556 if (ret == 0) {
557 ar_pci->ps_wake_refcount++;
558 WARN_ON(ar_pci->ps_wake_refcount == 0);
559 }
560
561 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
562
563 return ret;
564}
565
566static void ath10k_pci_sleep(struct ath10k *ar)
567{
568 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
569 unsigned long flags;
570
571 if (ar_pci->pci_ps == 0)
572 return;
573
574 spin_lock_irqsave(&ar_pci->ps_lock, flags);
575
576 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
577 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
578
579 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
580 goto skip;
581
582 ar_pci->ps_wake_refcount--;
583
584 mod_timer(&ar_pci->ps_timer, jiffies +
585 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
586
587skip:
588 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
589}
590
591static void ath10k_pci_ps_timer(struct timer_list *t)
592{
593 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer);
594 struct ath10k *ar = ar_pci->ar;
595 unsigned long flags;
596
597 spin_lock_irqsave(&ar_pci->ps_lock, flags);
598
599 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
600 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
601
602 if (ar_pci->ps_wake_refcount > 0)
603 goto skip;
604
605 __ath10k_pci_sleep(ar);
606
607skip:
608 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
609}
610
611static void ath10k_pci_sleep_sync(struct ath10k *ar)
612{
613 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
614 unsigned long flags;
615
616 if (ar_pci->pci_ps == 0) {
617 ath10k_pci_force_sleep(ar);
618 return;
619 }
620
621 del_timer_sync(&ar_pci->ps_timer);
622
623 spin_lock_irqsave(&ar_pci->ps_lock, flags);
624 WARN_ON(ar_pci->ps_wake_refcount > 0);
625 __ath10k_pci_sleep(ar);
626 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
627}
628
629static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
630{
631 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
632 int ret;
633
634 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
635 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
636 offset, offset + sizeof(value), ar_pci->mem_len);
637 return;
638 }
639
640 ret = ath10k_pci_wake(ar);
641 if (ret) {
642 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
643 value, offset, ret);
644 return;
645 }
646
647 iowrite32(value, ar_pci->mem + offset);
648 ath10k_pci_sleep(ar);
649}
650
651static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
652{
653 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
654 u32 val;
655 int ret;
656
657 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
658 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
659 offset, offset + sizeof(val), ar_pci->mem_len);
660 return 0;
661 }
662
663 ret = ath10k_pci_wake(ar);
664 if (ret) {
665 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
666 offset, ret);
667 return 0xffffffff;
668 }
669
670 val = ioread32(ar_pci->mem + offset);
671 ath10k_pci_sleep(ar);
672
673 return val;
674}
675
676inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
677{
678 struct ath10k_ce *ce = ath10k_ce_priv(ar);
679
680 ce->bus_ops->write32(ar, offset, value);
681}
682
683inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
684{
685 struct ath10k_ce *ce = ath10k_ce_priv(ar);
686
687 return ce->bus_ops->read32(ar, offset);
688}
689
690u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
691{
692 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
693}
694
695void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
696{
697 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
698}
699
700u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
701{
702 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
703}
704
705void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
706{
707 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
708}
709
710bool ath10k_pci_irq_pending(struct ath10k *ar)
711{
712 u32 cause;
713
714 /* Check if the shared legacy irq is for us */
715 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
716 PCIE_INTR_CAUSE_ADDRESS);
717 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
718 return true;
719
720 return false;
721}
722
723void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
724{
725 /* IMPORTANT: INTR_CLR register has to be set after
726 * INTR_ENABLE is set to 0, otherwise interrupt can not be
727 * really cleared.
728 */
729 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
730 0);
731 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
732 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
733
734 /* IMPORTANT: this extra read transaction is required to
735 * flush the posted write buffer.
736 */
737 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
738 PCIE_INTR_ENABLE_ADDRESS);
739}
740
741void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
742{
743 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
744 PCIE_INTR_ENABLE_ADDRESS,
745 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
746
747 /* IMPORTANT: this extra read transaction is required to
748 * flush the posted write buffer.
749 */
750 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
751 PCIE_INTR_ENABLE_ADDRESS);
752}
753
754static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
755{
756 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
757
758 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
759 return "msi";
760
761 return "legacy";
762}
763
764static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
765{
766 struct ath10k *ar = pipe->hif_ce_state;
767 struct ath10k_ce *ce = ath10k_ce_priv(ar);
768 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
769 struct sk_buff *skb;
770 dma_addr_t paddr;
771 int ret;
772
773 skb = dev_alloc_skb(pipe->buf_sz);
774 if (!skb)
775 return -ENOMEM;
776
777 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
778
779 paddr = dma_map_single(ar->dev, skb->data,
780 skb->len + skb_tailroom(skb),
781 DMA_FROM_DEVICE);
782 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
783 ath10k_warn(ar, "failed to dma map pci rx buf\n");
784 dev_kfree_skb_any(skb);
785 return -EIO;
786 }
787
788 ATH10K_SKB_RXCB(skb)->paddr = paddr;
789
790 spin_lock_bh(&ce->ce_lock);
791 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
792 spin_unlock_bh(&ce->ce_lock);
793 if (ret) {
794 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
795 DMA_FROM_DEVICE);
796 dev_kfree_skb_any(skb);
797 return ret;
798 }
799
800 return 0;
801}
802
803static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
804{
805 struct ath10k *ar = pipe->hif_ce_state;
806 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
807 struct ath10k_ce *ce = ath10k_ce_priv(ar);
808 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
809 int ret, num;
810
811 if (pipe->buf_sz == 0)
812 return;
813
814 if (!ce_pipe->dest_ring)
815 return;
816
817 spin_lock_bh(&ce->ce_lock);
818 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
819 spin_unlock_bh(&ce->ce_lock);
820
821 while (num >= 0) {
822 ret = __ath10k_pci_rx_post_buf(pipe);
823 if (ret) {
824 if (ret == -ENOSPC)
825 break;
826 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
827 mod_timer(&ar_pci->rx_post_retry, jiffies +
828 ATH10K_PCI_RX_POST_RETRY_MS);
829 break;
830 }
831 num--;
832 }
833}
834
835void ath10k_pci_rx_post(struct ath10k *ar)
836{
837 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
838 int i;
839
840 for (i = 0; i < CE_COUNT; i++)
841 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
842}
843
844void ath10k_pci_rx_replenish_retry(struct timer_list *t)
845{
846 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry);
847 struct ath10k *ar = ar_pci->ar;
848
849 ath10k_pci_rx_post(ar);
850}
851
852static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
853{
854 u32 val = 0, region = addr & 0xfffff;
855
856 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
857 & 0x7ff) << 21;
858 val |= 0x100000 | region;
859 return val;
860}
861
862/* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr.
863 * Support to access target space below 1M for qca6174 and qca9377.
864 * If target space is below 1M, the bit[20] of converted CE addr is 0.
865 * Otherwise bit[20] of converted CE addr is 1.
866 */
867static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
868{
869 u32 val = 0, region = addr & 0xfffff;
870
871 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
872 & 0x7ff) << 21;
873 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region;
874 return val;
875}
876
877static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
878{
879 u32 val = 0, region = addr & 0xfffff;
880
881 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
882 val |= 0x100000 | region;
883 return val;
884}
885
886static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
887{
888 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
889
890 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
891 return -ENOTSUPP;
892
893 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
894}
895
896/*
897 * Diagnostic read/write access is provided for startup/config/debug usage.
898 * Caller must guarantee proper alignment, when applicable, and single user
899 * at any moment.
900 */
901static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
902 int nbytes)
903{
904 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
905 int ret = 0;
906 u32 *buf;
907 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
908 struct ath10k_ce_pipe *ce_diag;
909 /* Host buffer address in CE space */
910 u32 ce_data;
911 dma_addr_t ce_data_base = 0;
912 void *data_buf;
913 int i;
914
915 mutex_lock(&ar_pci->ce_diag_mutex);
916 ce_diag = ar_pci->ce_diag;
917
918 /*
919 * Allocate a temporary bounce buffer to hold caller's data
920 * to be DMA'ed from Target. This guarantees
921 * 1) 4-byte alignment
922 * 2) Buffer in DMA-able space
923 */
924 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
925
926 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base,
927 GFP_ATOMIC);
928 if (!data_buf) {
929 ret = -ENOMEM;
930 goto done;
931 }
932
933 /* The address supplied by the caller is in the
934 * Target CPU virtual address space.
935 *
936 * In order to use this address with the diagnostic CE,
937 * convert it from Target CPU virtual address space
938 * to CE address space
939 */
940 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
941
942 remaining_bytes = nbytes;
943 ce_data = ce_data_base;
944 while (remaining_bytes) {
945 nbytes = min_t(unsigned int, remaining_bytes,
946 DIAG_TRANSFER_LIMIT);
947
948 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
949 if (ret != 0)
950 goto done;
951
952 /* Request CE to send from Target(!) address to Host buffer */
953 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0);
954 if (ret)
955 goto done;
956
957 i = 0;
958 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
959 udelay(DIAG_ACCESS_CE_WAIT_US);
960 i += DIAG_ACCESS_CE_WAIT_US;
961
962 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
963 ret = -EBUSY;
964 goto done;
965 }
966 }
967
968 i = 0;
969 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
970 &completed_nbytes) != 0) {
971 udelay(DIAG_ACCESS_CE_WAIT_US);
972 i += DIAG_ACCESS_CE_WAIT_US;
973
974 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
975 ret = -EBUSY;
976 goto done;
977 }
978 }
979
980 if (nbytes != completed_nbytes) {
981 ret = -EIO;
982 goto done;
983 }
984
985 if (*buf != ce_data) {
986 ret = -EIO;
987 goto done;
988 }
989
990 remaining_bytes -= nbytes;
991 memcpy(data, data_buf, nbytes);
992
993 address += nbytes;
994 data += nbytes;
995 }
996
997done:
998
999 if (data_buf)
1000 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1001 ce_data_base);
1002
1003 mutex_unlock(&ar_pci->ce_diag_mutex);
1004
1005 return ret;
1006}
1007
1008static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1009{
1010 __le32 val = 0;
1011 int ret;
1012
1013 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1014 *value = __le32_to_cpu(val);
1015
1016 return ret;
1017}
1018
1019static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1020 u32 src, u32 len)
1021{
1022 u32 host_addr, addr;
1023 int ret;
1024
1025 host_addr = host_interest_item_address(src);
1026
1027 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1028 if (ret != 0) {
1029 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1030 src, ret);
1031 return ret;
1032 }
1033
1034 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1035 if (ret != 0) {
1036 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1037 addr, len, ret);
1038 return ret;
1039 }
1040
1041 return 0;
1042}
1043
1044#define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1045 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1046
1047int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1048 const void *data, int nbytes)
1049{
1050 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1051 int ret = 0;
1052 u32 *buf;
1053 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
1054 struct ath10k_ce_pipe *ce_diag;
1055 void *data_buf;
1056 dma_addr_t ce_data_base = 0;
1057 int i;
1058
1059 mutex_lock(&ar_pci->ce_diag_mutex);
1060 ce_diag = ar_pci->ce_diag;
1061
1062 /*
1063 * Allocate a temporary bounce buffer to hold caller's data
1064 * to be DMA'ed to Target. This guarantees
1065 * 1) 4-byte alignment
1066 * 2) Buffer in DMA-able space
1067 */
1068 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
1069
1070 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base,
1071 GFP_ATOMIC);
1072 if (!data_buf) {
1073 ret = -ENOMEM;
1074 goto done;
1075 }
1076
1077 /*
1078 * The address supplied by the caller is in the
1079 * Target CPU virtual address space.
1080 *
1081 * In order to use this address with the diagnostic CE,
1082 * convert it from
1083 * Target CPU virtual address space
1084 * to
1085 * CE address space
1086 */
1087 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1088
1089 remaining_bytes = nbytes;
1090 while (remaining_bytes) {
1091 /* FIXME: check cast */
1092 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1093
1094 /* Copy caller's data to allocated DMA buf */
1095 memcpy(data_buf, data, nbytes);
1096
1097 /* Set up to receive directly into Target(!) address */
1098 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address);
1099 if (ret != 0)
1100 goto done;
1101
1102 /*
1103 * Request CE to send caller-supplied data that
1104 * was copied to bounce buffer to Target(!) address.
1105 */
1106 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0);
1107 if (ret != 0)
1108 goto done;
1109
1110 i = 0;
1111 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
1112 udelay(DIAG_ACCESS_CE_WAIT_US);
1113 i += DIAG_ACCESS_CE_WAIT_US;
1114
1115 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1116 ret = -EBUSY;
1117 goto done;
1118 }
1119 }
1120
1121 i = 0;
1122 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
1123 &completed_nbytes) != 0) {
1124 udelay(DIAG_ACCESS_CE_WAIT_US);
1125 i += DIAG_ACCESS_CE_WAIT_US;
1126
1127 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1128 ret = -EBUSY;
1129 goto done;
1130 }
1131 }
1132
1133 if (nbytes != completed_nbytes) {
1134 ret = -EIO;
1135 goto done;
1136 }
1137
1138 if (*buf != address) {
1139 ret = -EIO;
1140 goto done;
1141 }
1142
1143 remaining_bytes -= nbytes;
1144 address += nbytes;
1145 data += nbytes;
1146 }
1147
1148done:
1149 if (data_buf) {
1150 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1151 ce_data_base);
1152 }
1153
1154 if (ret != 0)
1155 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1156 address, ret);
1157
1158 mutex_unlock(&ar_pci->ce_diag_mutex);
1159
1160 return ret;
1161}
1162
1163static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1164{
1165 __le32 val = __cpu_to_le32(value);
1166
1167 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1168}
1169
1170/* Called by lower (CE) layer when a send to Target completes. */
1171static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1172{
1173 struct ath10k *ar = ce_state->ar;
1174 struct sk_buff_head list;
1175 struct sk_buff *skb;
1176
1177 __skb_queue_head_init(&list);
1178 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1179 /* no need to call tx completion for NULL pointers */
1180 if (skb == NULL)
1181 continue;
1182
1183 __skb_queue_tail(&list, skb);
1184 }
1185
1186 while ((skb = __skb_dequeue(&list)))
1187 ath10k_htc_tx_completion_handler(ar, skb);
1188}
1189
1190static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1191 void (*callback)(struct ath10k *ar,
1192 struct sk_buff *skb))
1193{
1194 struct ath10k *ar = ce_state->ar;
1195 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1196 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1197 struct sk_buff *skb;
1198 struct sk_buff_head list;
1199 void *transfer_context;
1200 unsigned int nbytes, max_nbytes;
1201
1202 __skb_queue_head_init(&list);
1203 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1204 &nbytes) == 0) {
1205 skb = transfer_context;
1206 max_nbytes = skb->len + skb_tailroom(skb);
1207 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1208 max_nbytes, DMA_FROM_DEVICE);
1209
1210 if (unlikely(max_nbytes < nbytes)) {
1211 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1212 nbytes, max_nbytes);
1213 dev_kfree_skb_any(skb);
1214 continue;
1215 }
1216
1217 skb_put(skb, nbytes);
1218 __skb_queue_tail(&list, skb);
1219 }
1220
1221 while ((skb = __skb_dequeue(&list))) {
1222 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1223 ce_state->id, skb->len);
1224 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1225 skb->data, skb->len);
1226
1227 callback(ar, skb);
1228 }
1229
1230 ath10k_pci_rx_post_pipe(pipe_info);
1231}
1232
1233static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1234 void (*callback)(struct ath10k *ar,
1235 struct sk_buff *skb))
1236{
1237 struct ath10k *ar = ce_state->ar;
1238 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1239 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1240 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1241 struct sk_buff *skb;
1242 struct sk_buff_head list;
1243 void *transfer_context;
1244 unsigned int nbytes, max_nbytes, nentries;
1245 int orig_len;
1246
1247 /* No need to acquire ce_lock for CE5, since this is the only place CE5
1248 * is processed other than init and deinit. Before releasing CE5
1249 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1250 */
1251 __skb_queue_head_init(&list);
1252 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1253 &nbytes) == 0) {
1254 skb = transfer_context;
1255 max_nbytes = skb->len + skb_tailroom(skb);
1256
1257 if (unlikely(max_nbytes < nbytes)) {
1258 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1259 nbytes, max_nbytes);
1260 continue;
1261 }
1262
1263 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1264 max_nbytes, DMA_FROM_DEVICE);
1265 skb_put(skb, nbytes);
1266 __skb_queue_tail(&list, skb);
1267 }
1268
1269 nentries = skb_queue_len(&list);
1270 while ((skb = __skb_dequeue(&list))) {
1271 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1272 ce_state->id, skb->len);
1273 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1274 skb->data, skb->len);
1275
1276 orig_len = skb->len;
1277 callback(ar, skb);
1278 skb_push(skb, orig_len - skb->len);
1279 skb_reset_tail_pointer(skb);
1280 skb_trim(skb, 0);
1281
1282 /*let device gain the buffer again*/
1283 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1284 skb->len + skb_tailroom(skb),
1285 DMA_FROM_DEVICE);
1286 }
1287 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1288}
1289
1290/* Called by lower (CE) layer when data is received from the Target. */
1291static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1292{
1293 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1294}
1295
1296static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1297{
1298 /* CE4 polling needs to be done whenever CE pipe which transports
1299 * HTT Rx (target->host) is processed.
1300 */
1301 ath10k_ce_per_engine_service(ce_state->ar, 4);
1302
1303 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1304}
1305
1306/* Called by lower (CE) layer when data is received from the Target.
1307 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1308 */
1309static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1310{
1311 ath10k_pci_process_rx_cb(ce_state,
1312 ath10k_htt_rx_pktlog_completion_handler);
1313}
1314
1315/* Called by lower (CE) layer when a send to HTT Target completes. */
1316static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1317{
1318 struct ath10k *ar = ce_state->ar;
1319 struct sk_buff *skb;
1320
1321 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1322 /* no need to call tx completion for NULL pointers */
1323 if (!skb)
1324 continue;
1325
1326 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1327 skb->len, DMA_TO_DEVICE);
1328 ath10k_htt_hif_tx_complete(ar, skb);
1329 }
1330}
1331
1332static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1333{
1334 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1335 ath10k_htt_t2h_msg_handler(ar, skb);
1336}
1337
1338/* Called by lower (CE) layer when HTT data is received from the Target. */
1339static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1340{
1341 /* CE4 polling needs to be done whenever CE pipe which transports
1342 * HTT Rx (target->host) is processed.
1343 */
1344 ath10k_ce_per_engine_service(ce_state->ar, 4);
1345
1346 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1347}
1348
1349int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1350 struct ath10k_hif_sg_item *items, int n_items)
1351{
1352 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1353 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1354 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1355 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1356 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1357 unsigned int nentries_mask;
1358 unsigned int sw_index;
1359 unsigned int write_index;
1360 int err, i = 0;
1361
1362 spin_lock_bh(&ce->ce_lock);
1363
1364 nentries_mask = src_ring->nentries_mask;
1365 sw_index = src_ring->sw_index;
1366 write_index = src_ring->write_index;
1367
1368 if (unlikely(CE_RING_DELTA(nentries_mask,
1369 write_index, sw_index - 1) < n_items)) {
1370 err = -ENOBUFS;
1371 goto err;
1372 }
1373
1374 for (i = 0; i < n_items - 1; i++) {
1375 ath10k_dbg(ar, ATH10K_DBG_PCI,
1376 "pci tx item %d paddr %pad len %d n_items %d\n",
1377 i, &items[i].paddr, items[i].len, n_items);
1378 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1379 items[i].vaddr, items[i].len);
1380
1381 err = ath10k_ce_send_nolock(ce_pipe,
1382 items[i].transfer_context,
1383 items[i].paddr,
1384 items[i].len,
1385 items[i].transfer_id,
1386 CE_SEND_FLAG_GATHER);
1387 if (err)
1388 goto err;
1389 }
1390
1391 /* `i` is equal to `n_items -1` after for() */
1392
1393 ath10k_dbg(ar, ATH10K_DBG_PCI,
1394 "pci tx item %d paddr %pad len %d n_items %d\n",
1395 i, &items[i].paddr, items[i].len, n_items);
1396 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1397 items[i].vaddr, items[i].len);
1398
1399 err = ath10k_ce_send_nolock(ce_pipe,
1400 items[i].transfer_context,
1401 items[i].paddr,
1402 items[i].len,
1403 items[i].transfer_id,
1404 0);
1405 if (err)
1406 goto err;
1407
1408 spin_unlock_bh(&ce->ce_lock);
1409 return 0;
1410
1411err:
1412 for (; i > 0; i--)
1413 __ath10k_ce_send_revert(ce_pipe);
1414
1415 spin_unlock_bh(&ce->ce_lock);
1416 return err;
1417}
1418
1419int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1420 size_t buf_len)
1421{
1422 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1423}
1424
1425u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1426{
1427 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1428
1429 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1430
1431 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1432}
1433
1434static void ath10k_pci_dump_registers(struct ath10k *ar,
1435 struct ath10k_fw_crash_data *crash_data)
1436{
1437 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1438 int i, ret;
1439
1440 lockdep_assert_held(&ar->dump_mutex);
1441
1442 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1443 hi_failure_state,
1444 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1445 if (ret) {
1446 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1447 return;
1448 }
1449
1450 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1451
1452 ath10k_err(ar, "firmware register dump:\n");
1453 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1454 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1455 i,
1456 __le32_to_cpu(reg_dump_values[i]),
1457 __le32_to_cpu(reg_dump_values[i + 1]),
1458 __le32_to_cpu(reg_dump_values[i + 2]),
1459 __le32_to_cpu(reg_dump_values[i + 3]));
1460
1461 if (!crash_data)
1462 return;
1463
1464 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1465 crash_data->registers[i] = reg_dump_values[i];
1466}
1467
1468static int ath10k_pci_dump_memory_section(struct ath10k *ar,
1469 const struct ath10k_mem_region *mem_region,
1470 u8 *buf, size_t buf_len)
1471{
1472 const struct ath10k_mem_section *cur_section, *next_section;
1473 unsigned int count, section_size, skip_size;
1474 int ret, i, j;
1475
1476 if (!mem_region || !buf)
1477 return 0;
1478
1479 cur_section = &mem_region->section_table.sections[0];
1480
1481 if (mem_region->start > cur_section->start) {
1482 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
1483 mem_region->start, cur_section->start);
1484 return 0;
1485 }
1486
1487 skip_size = cur_section->start - mem_region->start;
1488
1489 /* fill the gap between the first register section and register
1490 * start address
1491 */
1492 for (i = 0; i < skip_size; i++) {
1493 *buf = ATH10K_MAGIC_NOT_COPIED;
1494 buf++;
1495 }
1496
1497 count = 0;
1498
1499 for (i = 0; cur_section != NULL; i++) {
1500 section_size = cur_section->end - cur_section->start;
1501
1502 if (section_size <= 0) {
1503 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
1504 cur_section->start,
1505 cur_section->end);
1506 break;
1507 }
1508
1509 if ((i + 1) == mem_region->section_table.size) {
1510 /* last section */
1511 next_section = NULL;
1512 skip_size = 0;
1513 } else {
1514 next_section = cur_section + 1;
1515
1516 if (cur_section->end > next_section->start) {
1517 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
1518 next_section->start,
1519 cur_section->end);
1520 break;
1521 }
1522
1523 skip_size = next_section->start - cur_section->end;
1524 }
1525
1526 if (buf_len < (skip_size + section_size)) {
1527 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len);
1528 break;
1529 }
1530
1531 buf_len -= skip_size + section_size;
1532
1533 /* read section to dest memory */
1534 ret = ath10k_pci_diag_read_mem(ar, cur_section->start,
1535 buf, section_size);
1536 if (ret) {
1537 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
1538 cur_section->start, ret);
1539 break;
1540 }
1541
1542 buf += section_size;
1543 count += section_size;
1544
1545 /* fill in the gap between this section and the next */
1546 for (j = 0; j < skip_size; j++) {
1547 *buf = ATH10K_MAGIC_NOT_COPIED;
1548 buf++;
1549 }
1550
1551 count += skip_size;
1552
1553 if (!next_section)
1554 /* this was the last section */
1555 break;
1556
1557 cur_section = next_section;
1558 }
1559
1560 return count;
1561}
1562
1563static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config)
1564{
1565 u32 val;
1566
1567 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1568 FW_RAM_CONFIG_ADDRESS, config);
1569
1570 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1571 FW_RAM_CONFIG_ADDRESS);
1572 if (val != config) {
1573 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n",
1574 val, config);
1575 return -EIO;
1576 }
1577
1578 return 0;
1579}
1580
1581/* Always returns the length */
1582static int ath10k_pci_dump_memory_sram(struct ath10k *ar,
1583 const struct ath10k_mem_region *region,
1584 u8 *buf)
1585{
1586 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1587 u32 base_addr, i;
1588
1589 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG);
1590 base_addr += region->start;
1591
1592 for (i = 0; i < region->len; i += 4) {
1593 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG);
1594 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG);
1595 }
1596
1597 return region->len;
1598}
1599
1600/* if an error happened returns < 0, otherwise the length */
1601static int ath10k_pci_dump_memory_reg(struct ath10k *ar,
1602 const struct ath10k_mem_region *region,
1603 u8 *buf)
1604{
1605 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1606 u32 i;
1607 int ret;
1608
1609 mutex_lock(&ar->conf_mutex);
1610 if (ar->state != ATH10K_STATE_ON) {
1611 ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n");
1612 ret = -EIO;
1613 goto done;
1614 }
1615
1616 for (i = 0; i < region->len; i += 4)
1617 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i);
1618
1619 ret = region->len;
1620done:
1621 mutex_unlock(&ar->conf_mutex);
1622 return ret;
1623}
1624
1625/* if an error happened returns < 0, otherwise the length */
1626static int ath10k_pci_dump_memory_generic(struct ath10k *ar,
1627 const struct ath10k_mem_region *current_region,
1628 u8 *buf)
1629{
1630 int ret;
1631
1632 if (current_region->section_table.size > 0)
1633 /* Copy each section individually. */
1634 return ath10k_pci_dump_memory_section(ar,
1635 current_region,
1636 buf,
1637 current_region->len);
1638
1639 /* No individiual memory sections defined so we can
1640 * copy the entire memory region.
1641 */
1642 ret = ath10k_pci_diag_read_mem(ar,
1643 current_region->start,
1644 buf,
1645 current_region->len);
1646 if (ret) {
1647 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
1648 current_region->name, ret);
1649 return ret;
1650 }
1651
1652 return current_region->len;
1653}
1654
1655static void ath10k_pci_dump_memory(struct ath10k *ar,
1656 struct ath10k_fw_crash_data *crash_data)
1657{
1658 const struct ath10k_hw_mem_layout *mem_layout;
1659 const struct ath10k_mem_region *current_region;
1660 struct ath10k_dump_ram_data_hdr *hdr;
1661 u32 count, shift;
1662 size_t buf_len;
1663 int ret, i;
1664 u8 *buf;
1665
1666 lockdep_assert_held(&ar->dump_mutex);
1667
1668 if (!crash_data)
1669 return;
1670
1671 mem_layout = ath10k_coredump_get_mem_layout(ar);
1672 if (!mem_layout)
1673 return;
1674
1675 current_region = &mem_layout->region_table.regions[0];
1676
1677 buf = crash_data->ramdump_buf;
1678 buf_len = crash_data->ramdump_buf_len;
1679
1680 memset(buf, 0, buf_len);
1681
1682 for (i = 0; i < mem_layout->region_table.size; i++) {
1683 count = 0;
1684
1685 if (current_region->len > buf_len) {
1686 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n",
1687 current_region->name,
1688 current_region->len,
1689 buf_len);
1690 break;
1691 }
1692
1693 /* To get IRAM dump, the host driver needs to switch target
1694 * ram config from DRAM to IRAM.
1695 */
1696 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 ||
1697 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) {
1698 shift = current_region->start >> 20;
1699
1700 ret = ath10k_pci_set_ram_config(ar, shift);
1701 if (ret) {
1702 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n",
1703 current_region->name, ret);
1704 break;
1705 }
1706 }
1707
1708 /* Reserve space for the header. */
1709 hdr = (void *)buf;
1710 buf += sizeof(*hdr);
1711 buf_len -= sizeof(*hdr);
1712
1713 switch (current_region->type) {
1714 case ATH10K_MEM_REGION_TYPE_IOSRAM:
1715 count = ath10k_pci_dump_memory_sram(ar, current_region, buf);
1716 break;
1717 case ATH10K_MEM_REGION_TYPE_IOREG:
1718 ret = ath10k_pci_dump_memory_reg(ar, current_region, buf);
1719 if (ret < 0)
1720 break;
1721
1722 count = ret;
1723 break;
1724 default:
1725 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf);
1726 if (ret < 0)
1727 break;
1728
1729 count = ret;
1730 break;
1731 }
1732
1733 hdr->region_type = cpu_to_le32(current_region->type);
1734 hdr->start = cpu_to_le32(current_region->start);
1735 hdr->length = cpu_to_le32(count);
1736
1737 if (count == 0)
1738 /* Note: the header remains, just with zero length. */
1739 break;
1740
1741 buf += count;
1742 buf_len -= count;
1743
1744 current_region++;
1745 }
1746}
1747
1748static void ath10k_pci_fw_dump_work(struct work_struct *work)
1749{
1750 struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci,
1751 dump_work);
1752 struct ath10k_fw_crash_data *crash_data;
1753 struct ath10k *ar = ar_pci->ar;
1754 char guid[UUID_STRING_LEN + 1];
1755
1756 mutex_lock(&ar->dump_mutex);
1757
1758 spin_lock_bh(&ar->data_lock);
1759 ar->stats.fw_crash_counter++;
1760 spin_unlock_bh(&ar->data_lock);
1761
1762 crash_data = ath10k_coredump_new(ar);
1763
1764 if (crash_data)
1765 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1766 else
1767 scnprintf(guid, sizeof(guid), "n/a");
1768
1769 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1770 ath10k_print_driver_info(ar);
1771 ath10k_pci_dump_registers(ar, crash_data);
1772 ath10k_ce_dump_registers(ar, crash_data);
1773 ath10k_pci_dump_memory(ar, crash_data);
1774
1775 mutex_unlock(&ar->dump_mutex);
1776
1777 ath10k_core_start_recovery(ar);
1778}
1779
1780static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1781{
1782 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1783
1784 queue_work(ar->workqueue, &ar_pci->dump_work);
1785}
1786
1787void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1788 int force)
1789{
1790 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1791
1792 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1793
1794 if (!force) {
1795 int resources;
1796 /*
1797 * Decide whether to actually poll for completions, or just
1798 * wait for a later chance.
1799 * If there seem to be plenty of resources left, then just wait
1800 * since checking involves reading a CE register, which is a
1801 * relatively expensive operation.
1802 */
1803 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1804
1805 /*
1806 * If at least 50% of the total resources are still available,
1807 * don't bother checking again yet.
1808 */
1809 if (resources > (ar_pci->attr[pipe].src_nentries >> 1))
1810 return;
1811 }
1812 ath10k_ce_per_engine_service(ar, pipe);
1813}
1814
1815static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1816{
1817 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1818
1819 del_timer_sync(&ar_pci->rx_post_retry);
1820}
1821
1822int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1823 u8 *ul_pipe, u8 *dl_pipe)
1824{
1825 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1826 const struct ce_service_to_pipe *entry;
1827 bool ul_set = false, dl_set = false;
1828 int i;
1829
1830 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1831
1832 for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) {
1833 entry = &ar_pci->serv_to_pipe[i];
1834
1835 if (__le32_to_cpu(entry->service_id) != service_id)
1836 continue;
1837
1838 switch (__le32_to_cpu(entry->pipedir)) {
1839 case PIPEDIR_NONE:
1840 break;
1841 case PIPEDIR_IN:
1842 WARN_ON(dl_set);
1843 *dl_pipe = __le32_to_cpu(entry->pipenum);
1844 dl_set = true;
1845 break;
1846 case PIPEDIR_OUT:
1847 WARN_ON(ul_set);
1848 *ul_pipe = __le32_to_cpu(entry->pipenum);
1849 ul_set = true;
1850 break;
1851 case PIPEDIR_INOUT:
1852 WARN_ON(dl_set);
1853 WARN_ON(ul_set);
1854 *dl_pipe = __le32_to_cpu(entry->pipenum);
1855 *ul_pipe = __le32_to_cpu(entry->pipenum);
1856 dl_set = true;
1857 ul_set = true;
1858 break;
1859 }
1860 }
1861
1862 if (!ul_set || !dl_set)
1863 return -ENOENT;
1864
1865 return 0;
1866}
1867
1868void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1869 u8 *ul_pipe, u8 *dl_pipe)
1870{
1871 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1872
1873 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1874 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1875 ul_pipe, dl_pipe);
1876}
1877
1878void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1879{
1880 u32 val;
1881
1882 switch (ar->hw_rev) {
1883 case ATH10K_HW_QCA988X:
1884 case ATH10K_HW_QCA9887:
1885 case ATH10K_HW_QCA6174:
1886 case ATH10K_HW_QCA9377:
1887 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1888 CORE_CTRL_ADDRESS);
1889 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1890 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1891 CORE_CTRL_ADDRESS, val);
1892 break;
1893 case ATH10K_HW_QCA99X0:
1894 case ATH10K_HW_QCA9984:
1895 case ATH10K_HW_QCA9888:
1896 case ATH10K_HW_QCA4019:
1897 /* TODO: Find appropriate register configuration for QCA99X0
1898 * to mask irq/MSI.
1899 */
1900 break;
1901 case ATH10K_HW_WCN3990:
1902 break;
1903 }
1904}
1905
1906static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1907{
1908 u32 val;
1909
1910 switch (ar->hw_rev) {
1911 case ATH10K_HW_QCA988X:
1912 case ATH10K_HW_QCA9887:
1913 case ATH10K_HW_QCA6174:
1914 case ATH10K_HW_QCA9377:
1915 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1916 CORE_CTRL_ADDRESS);
1917 val |= CORE_CTRL_PCIE_REG_31_MASK;
1918 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1919 CORE_CTRL_ADDRESS, val);
1920 break;
1921 case ATH10K_HW_QCA99X0:
1922 case ATH10K_HW_QCA9984:
1923 case ATH10K_HW_QCA9888:
1924 case ATH10K_HW_QCA4019:
1925 /* TODO: Find appropriate register configuration for QCA99X0
1926 * to unmask irq/MSI.
1927 */
1928 break;
1929 case ATH10K_HW_WCN3990:
1930 break;
1931 }
1932}
1933
1934static void ath10k_pci_irq_disable(struct ath10k *ar)
1935{
1936 ath10k_ce_disable_interrupts(ar);
1937 ath10k_pci_disable_and_clear_legacy_irq(ar);
1938 ath10k_pci_irq_msi_fw_mask(ar);
1939}
1940
1941static void ath10k_pci_irq_sync(struct ath10k *ar)
1942{
1943 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1944
1945 synchronize_irq(ar_pci->pdev->irq);
1946}
1947
1948static void ath10k_pci_irq_enable(struct ath10k *ar)
1949{
1950 ath10k_ce_enable_interrupts(ar);
1951 ath10k_pci_enable_legacy_irq(ar);
1952 ath10k_pci_irq_msi_fw_unmask(ar);
1953}
1954
1955static int ath10k_pci_hif_start(struct ath10k *ar)
1956{
1957 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1958
1959 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1960
1961 ath10k_core_napi_enable(ar);
1962
1963 ath10k_pci_irq_enable(ar);
1964 ath10k_pci_rx_post(ar);
1965
1966 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1967 ar_pci->link_ctl);
1968
1969 return 0;
1970}
1971
1972static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1973{
1974 struct ath10k *ar;
1975 struct ath10k_ce_pipe *ce_pipe;
1976 struct ath10k_ce_ring *ce_ring;
1977 struct sk_buff *skb;
1978 int i;
1979
1980 ar = pci_pipe->hif_ce_state;
1981 ce_pipe = pci_pipe->ce_hdl;
1982 ce_ring = ce_pipe->dest_ring;
1983
1984 if (!ce_ring)
1985 return;
1986
1987 if (!pci_pipe->buf_sz)
1988 return;
1989
1990 for (i = 0; i < ce_ring->nentries; i++) {
1991 skb = ce_ring->per_transfer_context[i];
1992 if (!skb)
1993 continue;
1994
1995 ce_ring->per_transfer_context[i] = NULL;
1996
1997 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1998 skb->len + skb_tailroom(skb),
1999 DMA_FROM_DEVICE);
2000 dev_kfree_skb_any(skb);
2001 }
2002}
2003
2004static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
2005{
2006 struct ath10k *ar;
2007 struct ath10k_ce_pipe *ce_pipe;
2008 struct ath10k_ce_ring *ce_ring;
2009 struct sk_buff *skb;
2010 int i;
2011
2012 ar = pci_pipe->hif_ce_state;
2013 ce_pipe = pci_pipe->ce_hdl;
2014 ce_ring = ce_pipe->src_ring;
2015
2016 if (!ce_ring)
2017 return;
2018
2019 if (!pci_pipe->buf_sz)
2020 return;
2021
2022 for (i = 0; i < ce_ring->nentries; i++) {
2023 skb = ce_ring->per_transfer_context[i];
2024 if (!skb)
2025 continue;
2026
2027 ce_ring->per_transfer_context[i] = NULL;
2028
2029 ath10k_htc_tx_completion_handler(ar, skb);
2030 }
2031}
2032
2033/*
2034 * Cleanup residual buffers for device shutdown:
2035 * buffers that were enqueued for receive
2036 * buffers that were to be sent
2037 * Note: Buffers that had completed but which were
2038 * not yet processed are on a completion queue. They
2039 * are handled when the completion thread shuts down.
2040 */
2041static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
2042{
2043 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2044 int pipe_num;
2045
2046 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
2047 struct ath10k_pci_pipe *pipe_info;
2048
2049 pipe_info = &ar_pci->pipe_info[pipe_num];
2050 ath10k_pci_rx_pipe_cleanup(pipe_info);
2051 ath10k_pci_tx_pipe_cleanup(pipe_info);
2052 }
2053}
2054
2055void ath10k_pci_ce_deinit(struct ath10k *ar)
2056{
2057 int i;
2058
2059 for (i = 0; i < CE_COUNT; i++)
2060 ath10k_ce_deinit_pipe(ar, i);
2061}
2062
2063void ath10k_pci_flush(struct ath10k *ar)
2064{
2065 ath10k_pci_rx_retry_sync(ar);
2066 ath10k_pci_buffer_cleanup(ar);
2067}
2068
2069static void ath10k_pci_hif_stop(struct ath10k *ar)
2070{
2071 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2072 unsigned long flags;
2073
2074 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
2075
2076 ath10k_pci_irq_disable(ar);
2077 ath10k_pci_irq_sync(ar);
2078
2079 ath10k_core_napi_sync_disable(ar);
2080
2081 cancel_work_sync(&ar_pci->dump_work);
2082
2083 /* Most likely the device has HTT Rx ring configured. The only way to
2084 * prevent the device from accessing (and possible corrupting) host
2085 * memory is to reset the chip now.
2086 *
2087 * There's also no known way of masking MSI interrupts on the device.
2088 * For ranged MSI the CE-related interrupts can be masked. However
2089 * regardless how many MSI interrupts are assigned the first one
2090 * is always used for firmware indications (crashes) and cannot be
2091 * masked. To prevent the device from asserting the interrupt reset it
2092 * before proceeding with cleanup.
2093 */
2094 ath10k_pci_safe_chip_reset(ar);
2095
2096 ath10k_pci_flush(ar);
2097
2098 spin_lock_irqsave(&ar_pci->ps_lock, flags);
2099 WARN_ON(ar_pci->ps_wake_refcount > 0);
2100 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
2101}
2102
2103int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
2104 void *req, u32 req_len,
2105 void *resp, u32 *resp_len)
2106{
2107 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2108 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
2109 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
2110 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
2111 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
2112 dma_addr_t req_paddr = 0;
2113 dma_addr_t resp_paddr = 0;
2114 struct bmi_xfer xfer = {};
2115 void *treq, *tresp = NULL;
2116 int ret = 0;
2117
2118 might_sleep();
2119
2120 if (resp && !resp_len)
2121 return -EINVAL;
2122
2123 if (resp && resp_len && *resp_len == 0)
2124 return -EINVAL;
2125
2126 treq = kmemdup(req, req_len, GFP_KERNEL);
2127 if (!treq)
2128 return -ENOMEM;
2129
2130 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
2131 ret = dma_mapping_error(ar->dev, req_paddr);
2132 if (ret) {
2133 ret = -EIO;
2134 goto err_dma;
2135 }
2136
2137 if (resp && resp_len) {
2138 tresp = kzalloc(*resp_len, GFP_KERNEL);
2139 if (!tresp) {
2140 ret = -ENOMEM;
2141 goto err_req;
2142 }
2143
2144 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
2145 DMA_FROM_DEVICE);
2146 ret = dma_mapping_error(ar->dev, resp_paddr);
2147 if (ret) {
2148 ret = -EIO;
2149 goto err_req;
2150 }
2151
2152 xfer.wait_for_resp = true;
2153 xfer.resp_len = 0;
2154
2155 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
2156 }
2157
2158 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
2159 if (ret)
2160 goto err_resp;
2161
2162 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
2163 if (ret) {
2164 dma_addr_t unused_buffer;
2165 unsigned int unused_nbytes;
2166 unsigned int unused_id;
2167
2168 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
2169 &unused_nbytes, &unused_id);
2170 } else {
2171 /* non-zero means we did not time out */
2172 ret = 0;
2173 }
2174
2175err_resp:
2176 if (resp) {
2177 dma_addr_t unused_buffer;
2178
2179 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
2180 dma_unmap_single(ar->dev, resp_paddr,
2181 *resp_len, DMA_FROM_DEVICE);
2182 }
2183err_req:
2184 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
2185
2186 if (ret == 0 && resp_len) {
2187 *resp_len = min(*resp_len, xfer.resp_len);
2188 memcpy(resp, tresp, *resp_len);
2189 }
2190err_dma:
2191 kfree(treq);
2192 kfree(tresp);
2193
2194 return ret;
2195}
2196
2197static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
2198{
2199 struct bmi_xfer *xfer;
2200
2201 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
2202 return;
2203
2204 xfer->tx_done = true;
2205}
2206
2207static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
2208{
2209 struct ath10k *ar = ce_state->ar;
2210 struct bmi_xfer *xfer;
2211 unsigned int nbytes;
2212
2213 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
2214 &nbytes))
2215 return;
2216
2217 if (WARN_ON_ONCE(!xfer))
2218 return;
2219
2220 if (!xfer->wait_for_resp) {
2221 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
2222 return;
2223 }
2224
2225 xfer->resp_len = nbytes;
2226 xfer->rx_done = true;
2227}
2228
2229static int ath10k_pci_bmi_wait(struct ath10k *ar,
2230 struct ath10k_ce_pipe *tx_pipe,
2231 struct ath10k_ce_pipe *rx_pipe,
2232 struct bmi_xfer *xfer)
2233{
2234 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
2235 unsigned long started = jiffies;
2236 unsigned long dur;
2237 int ret;
2238
2239 while (time_before_eq(jiffies, timeout)) {
2240 ath10k_pci_bmi_send_done(tx_pipe);
2241 ath10k_pci_bmi_recv_data(rx_pipe);
2242
2243 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
2244 ret = 0;
2245 goto out;
2246 }
2247
2248 schedule();
2249 }
2250
2251 ret = -ETIMEDOUT;
2252
2253out:
2254 dur = jiffies - started;
2255 if (dur > HZ)
2256 ath10k_dbg(ar, ATH10K_DBG_BMI,
2257 "bmi cmd took %lu jiffies hz %d ret %d\n",
2258 dur, HZ, ret);
2259 return ret;
2260}
2261
2262/*
2263 * Send an interrupt to the device to wake up the Target CPU
2264 * so it has an opportunity to notice any changed state.
2265 */
2266static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
2267{
2268 u32 addr, val;
2269
2270 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
2271 val = ath10k_pci_read32(ar, addr);
2272 val |= CORE_CTRL_CPU_INTR_MASK;
2273 ath10k_pci_write32(ar, addr, val);
2274
2275 return 0;
2276}
2277
2278static int ath10k_pci_get_num_banks(struct ath10k *ar)
2279{
2280 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2281
2282 switch (ar_pci->pdev->device) {
2283 case QCA988X_2_0_DEVICE_ID_UBNT:
2284 case QCA988X_2_0_DEVICE_ID:
2285 case QCA99X0_2_0_DEVICE_ID:
2286 case QCA9888_2_0_DEVICE_ID:
2287 case QCA9984_1_0_DEVICE_ID:
2288 case QCA9887_1_0_DEVICE_ID:
2289 return 1;
2290 case QCA6164_2_1_DEVICE_ID:
2291 case QCA6174_2_1_DEVICE_ID:
2292 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) {
2293 case QCA6174_HW_1_0_CHIP_ID_REV:
2294 case QCA6174_HW_1_1_CHIP_ID_REV:
2295 case QCA6174_HW_2_1_CHIP_ID_REV:
2296 case QCA6174_HW_2_2_CHIP_ID_REV:
2297 return 3;
2298 case QCA6174_HW_1_3_CHIP_ID_REV:
2299 return 2;
2300 case QCA6174_HW_3_0_CHIP_ID_REV:
2301 case QCA6174_HW_3_1_CHIP_ID_REV:
2302 case QCA6174_HW_3_2_CHIP_ID_REV:
2303 return 9;
2304 }
2305 break;
2306 case QCA9377_1_0_DEVICE_ID:
2307 return 9;
2308 }
2309
2310 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2311 return 1;
2312}
2313
2314static int ath10k_bus_get_num_banks(struct ath10k *ar)
2315{
2316 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2317
2318 return ce->bus_ops->get_num_banks(ar);
2319}
2320
2321int ath10k_pci_init_config(struct ath10k *ar)
2322{
2323 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2324 u32 interconnect_targ_addr;
2325 u32 pcie_state_targ_addr = 0;
2326 u32 pipe_cfg_targ_addr = 0;
2327 u32 svc_to_pipe_map = 0;
2328 u32 pcie_config_flags = 0;
2329 u32 ealloc_value;
2330 u32 ealloc_targ_addr;
2331 u32 flag2_value;
2332 u32 flag2_targ_addr;
2333 int ret = 0;
2334
2335 /* Download to Target the CE Config and the service-to-CE map */
2336 interconnect_targ_addr =
2337 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2338
2339 /* Supply Target-side CE configuration */
2340 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2341 &pcie_state_targ_addr);
2342 if (ret != 0) {
2343 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2344 return ret;
2345 }
2346
2347 if (pcie_state_targ_addr == 0) {
2348 ret = -EIO;
2349 ath10k_err(ar, "Invalid pcie state addr\n");
2350 return ret;
2351 }
2352
2353 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2354 offsetof(struct pcie_state,
2355 pipe_cfg_addr)),
2356 &pipe_cfg_targ_addr);
2357 if (ret != 0) {
2358 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2359 return ret;
2360 }
2361
2362 if (pipe_cfg_targ_addr == 0) {
2363 ret = -EIO;
2364 ath10k_err(ar, "Invalid pipe cfg addr\n");
2365 return ret;
2366 }
2367
2368 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2369 ar_pci->pipe_config,
2370 sizeof(struct ce_pipe_config) *
2371 NUM_TARGET_CE_CONFIG_WLAN);
2372
2373 if (ret != 0) {
2374 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2375 return ret;
2376 }
2377
2378 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2379 offsetof(struct pcie_state,
2380 svc_to_pipe_map)),
2381 &svc_to_pipe_map);
2382 if (ret != 0) {
2383 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2384 return ret;
2385 }
2386
2387 if (svc_to_pipe_map == 0) {
2388 ret = -EIO;
2389 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2390 return ret;
2391 }
2392
2393 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2394 ar_pci->serv_to_pipe,
2395 sizeof(pci_target_service_to_ce_map_wlan));
2396 if (ret != 0) {
2397 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2398 return ret;
2399 }
2400
2401 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2402 offsetof(struct pcie_state,
2403 config_flags)),
2404 &pcie_config_flags);
2405 if (ret != 0) {
2406 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2407 return ret;
2408 }
2409
2410 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2411
2412 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2413 offsetof(struct pcie_state,
2414 config_flags)),
2415 pcie_config_flags);
2416 if (ret != 0) {
2417 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2418 return ret;
2419 }
2420
2421 /* configure early allocation */
2422 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2423
2424 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2425 if (ret != 0) {
2426 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2427 return ret;
2428 }
2429
2430 /* first bank is switched to IRAM */
2431 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2432 HI_EARLY_ALLOC_MAGIC_MASK);
2433 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2434 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2435 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2436
2437 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2438 if (ret != 0) {
2439 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2440 return ret;
2441 }
2442
2443 /* Tell Target to proceed with initialization */
2444 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2445
2446 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2447 if (ret != 0) {
2448 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2449 return ret;
2450 }
2451
2452 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2453
2454 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2455 if (ret != 0) {
2456 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2457 return ret;
2458 }
2459
2460 return 0;
2461}
2462
2463static void ath10k_pci_override_ce_config(struct ath10k *ar)
2464{
2465 struct ce_attr *attr;
2466 struct ce_pipe_config *config;
2467 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2468
2469 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2470 * since it is currently used for other feature.
2471 */
2472
2473 /* Override Host's Copy Engine 5 configuration */
2474 attr = &ar_pci->attr[5];
2475 attr->src_sz_max = 0;
2476 attr->dest_nentries = 0;
2477
2478 /* Override Target firmware's Copy Engine configuration */
2479 config = &ar_pci->pipe_config[5];
2480 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2481 config->nbytes_max = __cpu_to_le32(2048);
2482
2483 /* Map from service/endpoint to Copy Engine */
2484 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1);
2485}
2486
2487int ath10k_pci_alloc_pipes(struct ath10k *ar)
2488{
2489 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2490 struct ath10k_pci_pipe *pipe;
2491 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2492 int i, ret;
2493
2494 for (i = 0; i < CE_COUNT; i++) {
2495 pipe = &ar_pci->pipe_info[i];
2496 pipe->ce_hdl = &ce->ce_states[i];
2497 pipe->pipe_num = i;
2498 pipe->hif_ce_state = ar;
2499
2500 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]);
2501 if (ret) {
2502 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2503 i, ret);
2504 return ret;
2505 }
2506
2507 /* Last CE is Diagnostic Window */
2508 if (i == CE_DIAG_PIPE) {
2509 ar_pci->ce_diag = pipe->ce_hdl;
2510 continue;
2511 }
2512
2513 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max);
2514 }
2515
2516 return 0;
2517}
2518
2519void ath10k_pci_free_pipes(struct ath10k *ar)
2520{
2521 int i;
2522
2523 for (i = 0; i < CE_COUNT; i++)
2524 ath10k_ce_free_pipe(ar, i);
2525}
2526
2527int ath10k_pci_init_pipes(struct ath10k *ar)
2528{
2529 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2530 int i, ret;
2531
2532 for (i = 0; i < CE_COUNT; i++) {
2533 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]);
2534 if (ret) {
2535 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2536 i, ret);
2537 return ret;
2538 }
2539 }
2540
2541 return 0;
2542}
2543
2544static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2545{
2546 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2547 FW_IND_EVENT_PENDING;
2548}
2549
2550static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2551{
2552 u32 val;
2553
2554 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2555 val &= ~FW_IND_EVENT_PENDING;
2556 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2557}
2558
2559static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2560{
2561 u32 val;
2562
2563 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2564 return (val == 0xffffffff);
2565}
2566
2567/* this function effectively clears target memory controller assert line */
2568static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2569{
2570 u32 val;
2571
2572 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2573 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2574 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2575 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2576
2577 msleep(10);
2578
2579 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2580 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2581 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2582 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2583
2584 msleep(10);
2585}
2586
2587static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2588{
2589 u32 val;
2590
2591 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2592
2593 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2594 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2595 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2596}
2597
2598static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2599{
2600 u32 val;
2601
2602 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2603
2604 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2605 val | SOC_RESET_CONTROL_CE_RST_MASK);
2606 msleep(10);
2607 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2608 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2609}
2610
2611static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2612{
2613 u32 val;
2614
2615 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);
2616 ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS,
2617 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2618}
2619
2620static int ath10k_pci_warm_reset(struct ath10k *ar)
2621{
2622 int ret;
2623
2624 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2625
2626 spin_lock_bh(&ar->data_lock);
2627 ar->stats.fw_warm_reset_counter++;
2628 spin_unlock_bh(&ar->data_lock);
2629
2630 ath10k_pci_irq_disable(ar);
2631
2632 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2633 * were to access copy engine while host performs copy engine reset
2634 * then it is possible for the device to confuse pci-e controller to
2635 * the point of bringing host system to a complete stop (i.e. hang).
2636 */
2637 ath10k_pci_warm_reset_si0(ar);
2638 ath10k_pci_warm_reset_cpu(ar);
2639 ath10k_pci_init_pipes(ar);
2640 ath10k_pci_wait_for_target_init(ar);
2641
2642 ath10k_pci_warm_reset_clear_lf(ar);
2643 ath10k_pci_warm_reset_ce(ar);
2644 ath10k_pci_warm_reset_cpu(ar);
2645 ath10k_pci_init_pipes(ar);
2646
2647 ret = ath10k_pci_wait_for_target_init(ar);
2648 if (ret) {
2649 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2650 return ret;
2651 }
2652
2653 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2654
2655 return 0;
2656}
2657
2658static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2659{
2660 ath10k_pci_irq_disable(ar);
2661 return ath10k_pci_qca99x0_chip_reset(ar);
2662}
2663
2664static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2665{
2666 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2667
2668 if (!ar_pci->pci_soft_reset)
2669 return -ENOTSUPP;
2670
2671 return ar_pci->pci_soft_reset(ar);
2672}
2673
2674static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2675{
2676 int i, ret;
2677 u32 val;
2678
2679 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2680
2681 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2682 * It is thus preferred to use warm reset which is safer but may not be
2683 * able to recover the device from all possible fail scenarios.
2684 *
2685 * Warm reset doesn't always work on first try so attempt it a few
2686 * times before giving up.
2687 */
2688 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2689 ret = ath10k_pci_warm_reset(ar);
2690 if (ret) {
2691 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2692 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2693 ret);
2694 continue;
2695 }
2696
2697 /* FIXME: Sometimes copy engine doesn't recover after warm
2698 * reset. In most cases this needs cold reset. In some of these
2699 * cases the device is in such a state that a cold reset may
2700 * lock up the host.
2701 *
2702 * Reading any host interest register via copy engine is
2703 * sufficient to verify if device is capable of booting
2704 * firmware blob.
2705 */
2706 ret = ath10k_pci_init_pipes(ar);
2707 if (ret) {
2708 ath10k_warn(ar, "failed to init copy engine: %d\n",
2709 ret);
2710 continue;
2711 }
2712
2713 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2714 &val);
2715 if (ret) {
2716 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2717 ret);
2718 continue;
2719 }
2720
2721 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2722 return 0;
2723 }
2724
2725 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2726 ath10k_warn(ar, "refusing cold reset as requested\n");
2727 return -EPERM;
2728 }
2729
2730 ret = ath10k_pci_cold_reset(ar);
2731 if (ret) {
2732 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2733 return ret;
2734 }
2735
2736 ret = ath10k_pci_wait_for_target_init(ar);
2737 if (ret) {
2738 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2739 ret);
2740 return ret;
2741 }
2742
2743 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2744
2745 return 0;
2746}
2747
2748static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2749{
2750 int ret;
2751
2752 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2753
2754 /* FIXME: QCA6174 requires cold + warm reset to work. */
2755
2756 ret = ath10k_pci_cold_reset(ar);
2757 if (ret) {
2758 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2759 return ret;
2760 }
2761
2762 ret = ath10k_pci_wait_for_target_init(ar);
2763 if (ret) {
2764 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2765 ret);
2766 return ret;
2767 }
2768
2769 ret = ath10k_pci_warm_reset(ar);
2770 if (ret) {
2771 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2772 return ret;
2773 }
2774
2775 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2776
2777 return 0;
2778}
2779
2780static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2781{
2782 int ret;
2783
2784 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2785
2786 ret = ath10k_pci_cold_reset(ar);
2787 if (ret) {
2788 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2789 return ret;
2790 }
2791
2792 ret = ath10k_pci_wait_for_target_init(ar);
2793 if (ret) {
2794 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2795 ret);
2796 return ret;
2797 }
2798
2799 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2800
2801 return 0;
2802}
2803
2804static int ath10k_pci_chip_reset(struct ath10k *ar)
2805{
2806 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2807
2808 if (WARN_ON(!ar_pci->pci_hard_reset))
2809 return -ENOTSUPP;
2810
2811 return ar_pci->pci_hard_reset(ar);
2812}
2813
2814static int ath10k_pci_hif_power_up(struct ath10k *ar,
2815 enum ath10k_firmware_mode fw_mode)
2816{
2817 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2818 int ret;
2819
2820 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2821
2822 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2823 &ar_pci->link_ctl);
2824 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2825 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2826
2827 /*
2828 * Bring the target up cleanly.
2829 *
2830 * The target may be in an undefined state with an AUX-powered Target
2831 * and a Host in WoW mode. If the Host crashes, loses power, or is
2832 * restarted (without unloading the driver) then the Target is left
2833 * (aux) powered and running. On a subsequent driver load, the Target
2834 * is in an unexpected state. We try to catch that here in order to
2835 * reset the Target and retry the probe.
2836 */
2837 ret = ath10k_pci_chip_reset(ar);
2838 if (ret) {
2839 if (ath10k_pci_has_fw_crashed(ar)) {
2840 ath10k_warn(ar, "firmware crashed during chip reset\n");
2841 ath10k_pci_fw_crashed_clear(ar);
2842 ath10k_pci_fw_crashed_dump(ar);
2843 }
2844
2845 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2846 goto err_sleep;
2847 }
2848
2849 ret = ath10k_pci_init_pipes(ar);
2850 if (ret) {
2851 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2852 goto err_sleep;
2853 }
2854
2855 ret = ath10k_pci_init_config(ar);
2856 if (ret) {
2857 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2858 goto err_ce;
2859 }
2860
2861 ret = ath10k_pci_wake_target_cpu(ar);
2862 if (ret) {
2863 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2864 goto err_ce;
2865 }
2866
2867 return 0;
2868
2869err_ce:
2870 ath10k_pci_ce_deinit(ar);
2871
2872err_sleep:
2873 return ret;
2874}
2875
2876void ath10k_pci_hif_power_down(struct ath10k *ar)
2877{
2878 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2879
2880 /* Currently hif_power_up performs effectively a reset and hif_stop
2881 * resets the chip as well so there's no point in resetting here.
2882 */
2883}
2884
2885static int ath10k_pci_hif_suspend(struct ath10k *ar)
2886{
2887 /* Nothing to do; the important stuff is in the driver suspend. */
2888 return 0;
2889}
2890
2891static int ath10k_pci_suspend(struct ath10k *ar)
2892{
2893 /* The grace timer can still be counting down and ar->ps_awake be true.
2894 * It is known that the device may be asleep after resuming regardless
2895 * of the SoC powersave state before suspending. Hence make sure the
2896 * device is asleep before proceeding.
2897 */
2898 ath10k_pci_sleep_sync(ar);
2899
2900 return 0;
2901}
2902
2903static int ath10k_pci_hif_resume(struct ath10k *ar)
2904{
2905 /* Nothing to do; the important stuff is in the driver resume. */
2906 return 0;
2907}
2908
2909static int ath10k_pci_resume(struct ath10k *ar)
2910{
2911 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2912 struct pci_dev *pdev = ar_pci->pdev;
2913 u32 val;
2914 int ret = 0;
2915
2916 ret = ath10k_pci_force_wake(ar);
2917 if (ret) {
2918 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2919 return ret;
2920 }
2921
2922 /* Suspend/Resume resets the PCI configuration space, so we have to
2923 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2924 * from interfering with C3 CPU state. pci_restore_state won't help
2925 * here since it only restores the first 64 bytes pci config header.
2926 */
2927 pci_read_config_dword(pdev, 0x40, &val);
2928 if ((val & 0x0000ff00) != 0)
2929 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2930
2931 return ret;
2932}
2933
2934static bool ath10k_pci_validate_cal(void *data, size_t size)
2935{
2936 __le16 *cal_words = data;
2937 u16 checksum = 0;
2938 size_t i;
2939
2940 if (size % 2 != 0)
2941 return false;
2942
2943 for (i = 0; i < size / 2; i++)
2944 checksum ^= le16_to_cpu(cal_words[i]);
2945
2946 return checksum == 0xffff;
2947}
2948
2949static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2950{
2951 /* Enable SI clock */
2952 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2953
2954 /* Configure GPIOs for I2C operation */
2955 ath10k_pci_write32(ar,
2956 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2957 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2958 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2959 GPIO_PIN0_CONFIG) |
2960 SM(1, GPIO_PIN0_PAD_PULL));
2961
2962 ath10k_pci_write32(ar,
2963 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2964 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2965 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2966 SM(1, GPIO_PIN0_PAD_PULL));
2967
2968 ath10k_pci_write32(ar,
2969 GPIO_BASE_ADDRESS +
2970 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2971 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2972
2973 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2974 ath10k_pci_write32(ar,
2975 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2976 SM(1, SI_CONFIG_ERR_INT) |
2977 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2978 SM(1, SI_CONFIG_I2C) |
2979 SM(1, SI_CONFIG_POS_SAMPLE) |
2980 SM(1, SI_CONFIG_INACTIVE_DATA) |
2981 SM(1, SI_CONFIG_INACTIVE_CLK) |
2982 SM(8, SI_CONFIG_DIVIDER));
2983}
2984
2985static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2986{
2987 u32 reg;
2988 int wait_limit;
2989
2990 /* set device select byte and for the read operation */
2991 reg = QCA9887_EEPROM_SELECT_READ |
2992 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2993 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2994 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2995
2996 /* write transmit data, transfer length, and START bit */
2997 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2998 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2999 SM(4, SI_CS_TX_CNT));
3000
3001 /* wait max 1 sec */
3002 wait_limit = 100000;
3003
3004 /* wait for SI_CS_DONE_INT */
3005 do {
3006 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
3007 if (MS(reg, SI_CS_DONE_INT))
3008 break;
3009
3010 wait_limit--;
3011 udelay(10);
3012 } while (wait_limit > 0);
3013
3014 if (!MS(reg, SI_CS_DONE_INT)) {
3015 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
3016 addr);
3017 return -ETIMEDOUT;
3018 }
3019
3020 /* clear SI_CS_DONE_INT */
3021 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
3022
3023 if (MS(reg, SI_CS_DONE_ERR)) {
3024 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
3025 return -EIO;
3026 }
3027
3028 /* extract receive data */
3029 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
3030 *out = reg;
3031
3032 return 0;
3033}
3034
3035static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
3036 size_t *data_len)
3037{
3038 u8 *caldata = NULL;
3039 size_t calsize, i;
3040 int ret;
3041
3042 if (!QCA_REV_9887(ar))
3043 return -EOPNOTSUPP;
3044
3045 calsize = ar->hw_params.cal_data_len;
3046 caldata = kmalloc(calsize, GFP_KERNEL);
3047 if (!caldata)
3048 return -ENOMEM;
3049
3050 ath10k_pci_enable_eeprom(ar);
3051
3052 for (i = 0; i < calsize; i++) {
3053 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
3054 if (ret)
3055 goto err_free;
3056 }
3057
3058 if (!ath10k_pci_validate_cal(caldata, calsize))
3059 goto err_free;
3060
3061 *data = caldata;
3062 *data_len = calsize;
3063
3064 return 0;
3065
3066err_free:
3067 kfree(caldata);
3068
3069 return -EINVAL;
3070}
3071
3072static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
3073 .tx_sg = ath10k_pci_hif_tx_sg,
3074 .diag_read = ath10k_pci_hif_diag_read,
3075 .diag_write = ath10k_pci_diag_write_mem,
3076 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
3077 .start = ath10k_pci_hif_start,
3078 .stop = ath10k_pci_hif_stop,
3079 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
3080 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
3081 .send_complete_check = ath10k_pci_hif_send_complete_check,
3082 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
3083 .power_up = ath10k_pci_hif_power_up,
3084 .power_down = ath10k_pci_hif_power_down,
3085 .read32 = ath10k_pci_read32,
3086 .write32 = ath10k_pci_write32,
3087 .suspend = ath10k_pci_hif_suspend,
3088 .resume = ath10k_pci_hif_resume,
3089 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
3090};
3091
3092/*
3093 * Top-level interrupt handler for all PCI interrupts from a Target.
3094 * When a block of MSI interrupts is allocated, this top-level handler
3095 * is not used; instead, we directly call the correct sub-handler.
3096 */
3097static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
3098{
3099 struct ath10k *ar = arg;
3100 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3101 int ret;
3102
3103 if (ath10k_pci_has_device_gone(ar))
3104 return IRQ_NONE;
3105
3106 ret = ath10k_pci_force_wake(ar);
3107 if (ret) {
3108 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
3109 return IRQ_NONE;
3110 }
3111
3112 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
3113 !ath10k_pci_irq_pending(ar))
3114 return IRQ_NONE;
3115
3116 ath10k_pci_disable_and_clear_legacy_irq(ar);
3117 ath10k_pci_irq_msi_fw_mask(ar);
3118 napi_schedule(&ar->napi);
3119
3120 return IRQ_HANDLED;
3121}
3122
3123static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
3124{
3125 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
3126 int done = 0;
3127
3128 if (ath10k_pci_has_fw_crashed(ar)) {
3129 ath10k_pci_fw_crashed_clear(ar);
3130 ath10k_pci_fw_crashed_dump(ar);
3131 napi_complete(ctx);
3132 return done;
3133 }
3134
3135 ath10k_ce_per_engine_service_any(ar);
3136
3137 done = ath10k_htt_txrx_compl_task(ar, budget);
3138
3139 if (done < budget) {
3140 napi_complete_done(ctx, done);
3141 /* In case of MSI, it is possible that interrupts are received
3142 * while NAPI poll is inprogress. So pending interrupts that are
3143 * received after processing all copy engine pipes by NAPI poll
3144 * will not be handled again. This is causing failure to
3145 * complete boot sequence in x86 platform. So before enabling
3146 * interrupts safer to check for pending interrupts for
3147 * immediate servicing.
3148 */
3149 if (ath10k_ce_interrupt_summary(ar)) {
3150 napi_reschedule(ctx);
3151 goto out;
3152 }
3153 ath10k_pci_enable_legacy_irq(ar);
3154 ath10k_pci_irq_msi_fw_unmask(ar);
3155 }
3156
3157out:
3158 return done;
3159}
3160
3161static int ath10k_pci_request_irq_msi(struct ath10k *ar)
3162{
3163 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3164 int ret;
3165
3166 ret = request_irq(ar_pci->pdev->irq,
3167 ath10k_pci_interrupt_handler,
3168 IRQF_SHARED, "ath10k_pci", ar);
3169 if (ret) {
3170 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
3171 ar_pci->pdev->irq, ret);
3172 return ret;
3173 }
3174
3175 return 0;
3176}
3177
3178static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
3179{
3180 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3181 int ret;
3182
3183 ret = request_irq(ar_pci->pdev->irq,
3184 ath10k_pci_interrupt_handler,
3185 IRQF_SHARED, "ath10k_pci", ar);
3186 if (ret) {
3187 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
3188 ar_pci->pdev->irq, ret);
3189 return ret;
3190 }
3191
3192 return 0;
3193}
3194
3195static int ath10k_pci_request_irq(struct ath10k *ar)
3196{
3197 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3198
3199 switch (ar_pci->oper_irq_mode) {
3200 case ATH10K_PCI_IRQ_LEGACY:
3201 return ath10k_pci_request_irq_legacy(ar);
3202 case ATH10K_PCI_IRQ_MSI:
3203 return ath10k_pci_request_irq_msi(ar);
3204 default:
3205 return -EINVAL;
3206 }
3207}
3208
3209static void ath10k_pci_free_irq(struct ath10k *ar)
3210{
3211 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3212
3213 free_irq(ar_pci->pdev->irq, ar);
3214}
3215
3216void ath10k_pci_init_napi(struct ath10k *ar)
3217{
3218 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll);
3219}
3220
3221static int ath10k_pci_init_irq(struct ath10k *ar)
3222{
3223 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3224 int ret;
3225
3226 ath10k_pci_init_napi(ar);
3227
3228 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
3229 ath10k_info(ar, "limiting irq mode to: %d\n",
3230 ath10k_pci_irq_mode);
3231
3232 /* Try MSI */
3233 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
3234 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
3235 ret = pci_enable_msi(ar_pci->pdev);
3236 if (ret == 0)
3237 return 0;
3238
3239 /* MHI failed, try legacy irq next */
3240 }
3241
3242 /* Try legacy irq
3243 *
3244 * A potential race occurs here: The CORE_BASE write
3245 * depends on target correctly decoding AXI address but
3246 * host won't know when target writes BAR to CORE_CTRL.
3247 * This write might get lost if target has NOT written BAR.
3248 * For now, fix the race by repeating the write in below
3249 * synchronization checking.
3250 */
3251 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
3252
3253 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3254 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
3255
3256 return 0;
3257}
3258
3259static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
3260{
3261 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3262 0);
3263}
3264
3265static int ath10k_pci_deinit_irq(struct ath10k *ar)
3266{
3267 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3268
3269 switch (ar_pci->oper_irq_mode) {
3270 case ATH10K_PCI_IRQ_LEGACY:
3271 ath10k_pci_deinit_irq_legacy(ar);
3272 break;
3273 default:
3274 pci_disable_msi(ar_pci->pdev);
3275 break;
3276 }
3277
3278 return 0;
3279}
3280
3281int ath10k_pci_wait_for_target_init(struct ath10k *ar)
3282{
3283 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3284 unsigned long timeout;
3285 u32 val;
3286
3287 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
3288
3289 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
3290
3291 do {
3292 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3293
3294 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
3295 val);
3296
3297 /* target should never return this */
3298 if (val == 0xffffffff)
3299 continue;
3300
3301 /* the device has crashed so don't bother trying anymore */
3302 if (val & FW_IND_EVENT_PENDING)
3303 break;
3304
3305 if (val & FW_IND_INITIALIZED)
3306 break;
3307
3308 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
3309 /* Fix potential race by repeating CORE_BASE writes */
3310 ath10k_pci_enable_legacy_irq(ar);
3311
3312 mdelay(10);
3313 } while (time_before(jiffies, timeout));
3314
3315 ath10k_pci_disable_and_clear_legacy_irq(ar);
3316 ath10k_pci_irq_msi_fw_mask(ar);
3317
3318 if (val == 0xffffffff) {
3319 ath10k_err(ar, "failed to read device register, device is gone\n");
3320 return -EIO;
3321 }
3322
3323 if (val & FW_IND_EVENT_PENDING) {
3324 ath10k_warn(ar, "device has crashed during init\n");
3325 return -ECOMM;
3326 }
3327
3328 if (!(val & FW_IND_INITIALIZED)) {
3329 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3330 val);
3331 return -ETIMEDOUT;
3332 }
3333
3334 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3335 return 0;
3336}
3337
3338static int ath10k_pci_cold_reset(struct ath10k *ar)
3339{
3340 u32 val;
3341
3342 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3343
3344 spin_lock_bh(&ar->data_lock);
3345
3346 ar->stats.fw_cold_reset_counter++;
3347
3348 spin_unlock_bh(&ar->data_lock);
3349
3350 /* Put Target, including PCIe, into RESET. */
3351 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3352 val |= 1;
3353 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3354
3355 /* After writing into SOC_GLOBAL_RESET to put device into
3356 * reset and pulling out of reset pcie may not be stable
3357 * for any immediate pcie register access and cause bus error,
3358 * add delay before any pcie access request to fix this issue.
3359 */
3360 msleep(20);
3361
3362 /* Pull Target, including PCIe, out of RESET. */
3363 val &= ~1;
3364 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3365
3366 msleep(20);
3367
3368 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3369
3370 return 0;
3371}
3372
3373static int ath10k_pci_claim(struct ath10k *ar)
3374{
3375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3376 struct pci_dev *pdev = ar_pci->pdev;
3377 int ret;
3378
3379 pci_set_drvdata(pdev, ar);
3380
3381 ret = pci_enable_device(pdev);
3382 if (ret) {
3383 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3384 return ret;
3385 }
3386
3387 ret = pci_request_region(pdev, BAR_NUM, "ath");
3388 if (ret) {
3389 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3390 ret);
3391 goto err_device;
3392 }
3393
3394 /* Target expects 32 bit DMA. Enforce it. */
3395 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3396 if (ret) {
3397 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3398 goto err_region;
3399 }
3400
3401 pci_set_master(pdev);
3402
3403 /* Arrange for access to Target SoC registers. */
3404 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3405 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3406 if (!ar_pci->mem) {
3407 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3408 ret = -EIO;
3409 goto err_master;
3410 }
3411
3412 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3413 return 0;
3414
3415err_master:
3416 pci_clear_master(pdev);
3417
3418err_region:
3419 pci_release_region(pdev, BAR_NUM);
3420
3421err_device:
3422 pci_disable_device(pdev);
3423
3424 return ret;
3425}
3426
3427static void ath10k_pci_release(struct ath10k *ar)
3428{
3429 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3430 struct pci_dev *pdev = ar_pci->pdev;
3431
3432 pci_iounmap(pdev, ar_pci->mem);
3433 pci_release_region(pdev, BAR_NUM);
3434 pci_clear_master(pdev);
3435 pci_disable_device(pdev);
3436}
3437
3438static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3439{
3440 const struct ath10k_pci_supp_chip *supp_chip;
3441 int i;
3442 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3443
3444 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3445 supp_chip = &ath10k_pci_supp_chips[i];
3446
3447 if (supp_chip->dev_id == dev_id &&
3448 supp_chip->rev_id == rev_id)
3449 return true;
3450 }
3451
3452 return false;
3453}
3454
3455int ath10k_pci_setup_resource(struct ath10k *ar)
3456{
3457 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3458 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3459 int ret;
3460
3461 spin_lock_init(&ce->ce_lock);
3462 spin_lock_init(&ar_pci->ps_lock);
3463 mutex_init(&ar_pci->ce_diag_mutex);
3464
3465 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work);
3466
3467 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3468
3469 ar_pci->attr = kmemdup(pci_host_ce_config_wlan,
3470 sizeof(pci_host_ce_config_wlan),
3471 GFP_KERNEL);
3472 if (!ar_pci->attr)
3473 return -ENOMEM;
3474
3475 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan,
3476 sizeof(pci_target_ce_config_wlan),
3477 GFP_KERNEL);
3478 if (!ar_pci->pipe_config) {
3479 ret = -ENOMEM;
3480 goto err_free_attr;
3481 }
3482
3483 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan,
3484 sizeof(pci_target_service_to_ce_map_wlan),
3485 GFP_KERNEL);
3486 if (!ar_pci->serv_to_pipe) {
3487 ret = -ENOMEM;
3488 goto err_free_pipe_config;
3489 }
3490
3491 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3492 ath10k_pci_override_ce_config(ar);
3493
3494 ret = ath10k_pci_alloc_pipes(ar);
3495 if (ret) {
3496 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3497 ret);
3498 goto err_free_serv_to_pipe;
3499 }
3500
3501 return 0;
3502
3503err_free_serv_to_pipe:
3504 kfree(ar_pci->serv_to_pipe);
3505err_free_pipe_config:
3506 kfree(ar_pci->pipe_config);
3507err_free_attr:
3508 kfree(ar_pci->attr);
3509 return ret;
3510}
3511
3512void ath10k_pci_release_resource(struct ath10k *ar)
3513{
3514 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3515
3516 ath10k_pci_rx_retry_sync(ar);
3517 netif_napi_del(&ar->napi);
3518 ath10k_pci_ce_deinit(ar);
3519 ath10k_pci_free_pipes(ar);
3520 kfree(ar_pci->attr);
3521 kfree(ar_pci->pipe_config);
3522 kfree(ar_pci->serv_to_pipe);
3523}
3524
3525static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3526 .read32 = ath10k_bus_pci_read32,
3527 .write32 = ath10k_bus_pci_write32,
3528 .get_num_banks = ath10k_pci_get_num_banks,
3529};
3530
3531static int ath10k_pci_probe(struct pci_dev *pdev,
3532 const struct pci_device_id *pci_dev)
3533{
3534 int ret = 0;
3535 struct ath10k *ar;
3536 struct ath10k_pci *ar_pci;
3537 enum ath10k_hw_rev hw_rev;
3538 struct ath10k_bus_params bus_params = {};
3539 bool pci_ps, is_qca988x = false;
3540 int (*pci_soft_reset)(struct ath10k *ar);
3541 int (*pci_hard_reset)(struct ath10k *ar);
3542 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3543
3544 switch (pci_dev->device) {
3545 case QCA988X_2_0_DEVICE_ID_UBNT:
3546 case QCA988X_2_0_DEVICE_ID:
3547 hw_rev = ATH10K_HW_QCA988X;
3548 pci_ps = false;
3549 is_qca988x = true;
3550 pci_soft_reset = ath10k_pci_warm_reset;
3551 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3552 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3553 break;
3554 case QCA9887_1_0_DEVICE_ID:
3555 hw_rev = ATH10K_HW_QCA9887;
3556 pci_ps = false;
3557 pci_soft_reset = ath10k_pci_warm_reset;
3558 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3559 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3560 break;
3561 case QCA6164_2_1_DEVICE_ID:
3562 case QCA6174_2_1_DEVICE_ID:
3563 hw_rev = ATH10K_HW_QCA6174;
3564 pci_ps = true;
3565 pci_soft_reset = ath10k_pci_warm_reset;
3566 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3567 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3568 break;
3569 case QCA99X0_2_0_DEVICE_ID:
3570 hw_rev = ATH10K_HW_QCA99X0;
3571 pci_ps = false;
3572 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3573 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3574 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3575 break;
3576 case QCA9984_1_0_DEVICE_ID:
3577 hw_rev = ATH10K_HW_QCA9984;
3578 pci_ps = false;
3579 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3580 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3581 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3582 break;
3583 case QCA9888_2_0_DEVICE_ID:
3584 hw_rev = ATH10K_HW_QCA9888;
3585 pci_ps = false;
3586 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3587 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3588 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3589 break;
3590 case QCA9377_1_0_DEVICE_ID:
3591 hw_rev = ATH10K_HW_QCA9377;
3592 pci_ps = true;
3593 pci_soft_reset = ath10k_pci_warm_reset;
3594 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3595 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3596 break;
3597 default:
3598 WARN_ON(1);
3599 return -ENOTSUPP;
3600 }
3601
3602 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3603 hw_rev, &ath10k_pci_hif_ops);
3604 if (!ar) {
3605 dev_err(&pdev->dev, "failed to allocate core\n");
3606 return -ENOMEM;
3607 }
3608
3609 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3610 pdev->vendor, pdev->device,
3611 pdev->subsystem_vendor, pdev->subsystem_device);
3612
3613 ar_pci = ath10k_pci_priv(ar);
3614 ar_pci->pdev = pdev;
3615 ar_pci->dev = &pdev->dev;
3616 ar_pci->ar = ar;
3617 ar->dev_id = pci_dev->device;
3618 ar_pci->pci_ps = pci_ps;
3619 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3620 ar_pci->pci_soft_reset = pci_soft_reset;
3621 ar_pci->pci_hard_reset = pci_hard_reset;
3622 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3623 ar->ce_priv = &ar_pci->ce;
3624
3625 ar->id.vendor = pdev->vendor;
3626 ar->id.device = pdev->device;
3627 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3628 ar->id.subsystem_device = pdev->subsystem_device;
3629
3630 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0);
3631
3632 ret = ath10k_pci_setup_resource(ar);
3633 if (ret) {
3634 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3635 goto err_core_destroy;
3636 }
3637
3638 ret = ath10k_pci_claim(ar);
3639 if (ret) {
3640 ath10k_err(ar, "failed to claim device: %d\n", ret);
3641 goto err_free_pipes;
3642 }
3643
3644 ret = ath10k_pci_force_wake(ar);
3645 if (ret) {
3646 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3647 goto err_sleep;
3648 }
3649
3650 ath10k_pci_ce_deinit(ar);
3651 ath10k_pci_irq_disable(ar);
3652
3653 ret = ath10k_pci_init_irq(ar);
3654 if (ret) {
3655 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3656 goto err_sleep;
3657 }
3658
3659 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3660 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3661 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3662
3663 ret = ath10k_pci_request_irq(ar);
3664 if (ret) {
3665 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3666 goto err_deinit_irq;
3667 }
3668
3669 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
3670 bus_params.link_can_suspend = true;
3671 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that
3672 * fall off the bus during chip_reset. These chips have the same pci
3673 * device id as the QCA9880 BR4A or 2R4E. So that's why the check.
3674 */
3675 if (is_qca988x) {
3676 bus_params.chip_id =
3677 ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3678 if (bus_params.chip_id != 0xffffffff) {
3679 if (!ath10k_pci_chip_is_supported(pdev->device,
3680 bus_params.chip_id)) {
3681 ret = -ENODEV;
3682 goto err_unsupported;
3683 }
3684 }
3685 }
3686
3687 ret = ath10k_pci_chip_reset(ar);
3688 if (ret) {
3689 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3690 goto err_free_irq;
3691 }
3692
3693 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3694 if (bus_params.chip_id == 0xffffffff) {
3695 ret = -ENODEV;
3696 goto err_unsupported;
3697 }
3698
3699 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
3700 ret = -ENODEV;
3701 goto err_unsupported;
3702 }
3703
3704 ret = ath10k_core_register(ar, &bus_params);
3705 if (ret) {
3706 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3707 goto err_free_irq;
3708 }
3709
3710 return 0;
3711
3712err_unsupported:
3713 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3714 pdev->device, bus_params.chip_id);
3715
3716err_free_irq:
3717 ath10k_pci_free_irq(ar);
3718
3719err_deinit_irq:
3720 ath10k_pci_release_resource(ar);
3721
3722err_sleep:
3723 ath10k_pci_sleep_sync(ar);
3724 ath10k_pci_release(ar);
3725
3726err_free_pipes:
3727 ath10k_pci_free_pipes(ar);
3728
3729err_core_destroy:
3730 ath10k_core_destroy(ar);
3731
3732 return ret;
3733}
3734
3735static void ath10k_pci_remove(struct pci_dev *pdev)
3736{
3737 struct ath10k *ar = pci_get_drvdata(pdev);
3738
3739 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3740
3741 if (!ar)
3742 return;
3743
3744 ath10k_core_unregister(ar);
3745 ath10k_pci_free_irq(ar);
3746 ath10k_pci_deinit_irq(ar);
3747 ath10k_pci_release_resource(ar);
3748 ath10k_pci_sleep_sync(ar);
3749 ath10k_pci_release(ar);
3750 ath10k_core_destroy(ar);
3751}
3752
3753MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3754
3755static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3756{
3757 struct ath10k *ar = dev_get_drvdata(dev);
3758 int ret;
3759
3760 ret = ath10k_pci_suspend(ar);
3761 if (ret)
3762 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3763
3764 return ret;
3765}
3766
3767static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3768{
3769 struct ath10k *ar = dev_get_drvdata(dev);
3770 int ret;
3771
3772 ret = ath10k_pci_resume(ar);
3773 if (ret)
3774 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3775
3776 return ret;
3777}
3778
3779static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3780 ath10k_pci_pm_suspend,
3781 ath10k_pci_pm_resume);
3782
3783static struct pci_driver ath10k_pci_driver = {
3784 .name = "ath10k_pci",
3785 .id_table = ath10k_pci_id_table,
3786 .probe = ath10k_pci_probe,
3787 .remove = ath10k_pci_remove,
3788#ifdef CONFIG_PM
3789 .driver.pm = &ath10k_pci_pm_ops,
3790#endif
3791};
3792
3793static int __init ath10k_pci_init(void)
3794{
3795 int ret1, ret2;
3796
3797 ret1 = pci_register_driver(&ath10k_pci_driver);
3798 if (ret1)
3799 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3800 ret1);
3801
3802 ret2 = ath10k_ahb_init();
3803 if (ret2)
3804 printk(KERN_ERR "ahb init failed: %d\n", ret2);
3805
3806 if (ret1 && ret2)
3807 return ret1;
3808
3809 /* registered to at least one bus */
3810 return 0;
3811}
3812module_init(ath10k_pci_init);
3813
3814static void __exit ath10k_pci_exit(void)
3815{
3816 pci_unregister_driver(&ath10k_pci_driver);
3817 ath10k_ahb_exit();
3818}
3819
3820module_exit(ath10k_pci_exit);
3821
3822MODULE_AUTHOR("Qualcomm Atheros");
3823MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3824MODULE_LICENSE("Dual BSD/GPL");
3825
3826/* QCA988x 2.0 firmware files */
3827MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3828MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3829MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3830MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3831MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3832MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3833
3834/* QCA9887 1.0 firmware files */
3835MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3836MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
3837MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3838
3839/* QCA6174 2.1 firmware files */
3840MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3841MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3842MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3843MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3844
3845/* QCA6174 3.1 firmware files */
3846MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3847MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3848MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3849MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3850MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3851
3852/* QCA9377 1.0 firmware files */
3853MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3854MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3855MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);
1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/bitops.h>
23
24#include "core.h"
25#include "debug.h"
26
27#include "targaddrs.h"
28#include "bmi.h"
29
30#include "hif.h"
31#include "htc.h"
32
33#include "ce.h"
34#include "pci.h"
35
36enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
40};
41
42enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45};
46
47static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
48static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
49
50module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
52
53module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
55
56/* how long wait to wait for target to initialise, in ms */
57#define ATH10K_PCI_TARGET_WAIT 3000
58#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
59
60static const struct pci_device_id ath10k_pci_id_table[] = {
61 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
62 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
63 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
64 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
65 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
66 {0}
67};
68
69static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
70 /* QCA988X pre 2.0 chips are not supported because they need some nasty
71 * hacks. ath10k doesn't have them and these devices crash horribly
72 * because of that.
73 */
74 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
75
76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
78 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
79 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
81
82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
84 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
85 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
87
88 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
89
90 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
92};
93
94static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
95static int ath10k_pci_cold_reset(struct ath10k *ar);
96static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
97static int ath10k_pci_init_irq(struct ath10k *ar);
98static int ath10k_pci_deinit_irq(struct ath10k *ar);
99static int ath10k_pci_request_irq(struct ath10k *ar);
100static void ath10k_pci_free_irq(struct ath10k *ar);
101static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
102 struct ath10k_ce_pipe *rx_pipe,
103 struct bmi_xfer *xfer);
104static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
105static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
106static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
107static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
108static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
109static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
110static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
111
112static struct ce_attr host_ce_config_wlan[] = {
113 /* CE0: host->target HTC control and raw streams */
114 {
115 .flags = CE_ATTR_FLAGS,
116 .src_nentries = 16,
117 .src_sz_max = 256,
118 .dest_nentries = 0,
119 .send_cb = ath10k_pci_htc_tx_cb,
120 },
121
122 /* CE1: target->host HTT + HTC control */
123 {
124 .flags = CE_ATTR_FLAGS,
125 .src_nentries = 0,
126 .src_sz_max = 2048,
127 .dest_nentries = 512,
128 .recv_cb = ath10k_pci_htt_htc_rx_cb,
129 },
130
131 /* CE2: target->host WMI */
132 {
133 .flags = CE_ATTR_FLAGS,
134 .src_nentries = 0,
135 .src_sz_max = 2048,
136 .dest_nentries = 128,
137 .recv_cb = ath10k_pci_htc_rx_cb,
138 },
139
140 /* CE3: host->target WMI */
141 {
142 .flags = CE_ATTR_FLAGS,
143 .src_nentries = 32,
144 .src_sz_max = 2048,
145 .dest_nentries = 0,
146 .send_cb = ath10k_pci_htc_tx_cb,
147 },
148
149 /* CE4: host->target HTT */
150 {
151 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
152 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
153 .src_sz_max = 256,
154 .dest_nentries = 0,
155 .send_cb = ath10k_pci_htt_tx_cb,
156 },
157
158 /* CE5: target->host HTT (HIF->HTT) */
159 {
160 .flags = CE_ATTR_FLAGS,
161 .src_nentries = 0,
162 .src_sz_max = 512,
163 .dest_nentries = 512,
164 .recv_cb = ath10k_pci_htt_rx_cb,
165 },
166
167 /* CE6: target autonomous hif_memcpy */
168 {
169 .flags = CE_ATTR_FLAGS,
170 .src_nentries = 0,
171 .src_sz_max = 0,
172 .dest_nentries = 0,
173 },
174
175 /* CE7: ce_diag, the Diagnostic Window */
176 {
177 .flags = CE_ATTR_FLAGS,
178 .src_nentries = 2,
179 .src_sz_max = DIAG_TRANSFER_LIMIT,
180 .dest_nentries = 2,
181 },
182
183 /* CE8: target->host pktlog */
184 {
185 .flags = CE_ATTR_FLAGS,
186 .src_nentries = 0,
187 .src_sz_max = 2048,
188 .dest_nentries = 128,
189 .recv_cb = ath10k_pci_pktlog_rx_cb,
190 },
191
192 /* CE9 target autonomous qcache memcpy */
193 {
194 .flags = CE_ATTR_FLAGS,
195 .src_nentries = 0,
196 .src_sz_max = 0,
197 .dest_nentries = 0,
198 },
199
200 /* CE10: target autonomous hif memcpy */
201 {
202 .flags = CE_ATTR_FLAGS,
203 .src_nentries = 0,
204 .src_sz_max = 0,
205 .dest_nentries = 0,
206 },
207
208 /* CE11: target autonomous hif memcpy */
209 {
210 .flags = CE_ATTR_FLAGS,
211 .src_nentries = 0,
212 .src_sz_max = 0,
213 .dest_nentries = 0,
214 },
215};
216
217/* Target firmware's Copy Engine configuration. */
218static struct ce_pipe_config target_ce_config_wlan[] = {
219 /* CE0: host->target HTC control and raw streams */
220 {
221 .pipenum = __cpu_to_le32(0),
222 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
223 .nentries = __cpu_to_le32(32),
224 .nbytes_max = __cpu_to_le32(256),
225 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
226 .reserved = __cpu_to_le32(0),
227 },
228
229 /* CE1: target->host HTT + HTC control */
230 {
231 .pipenum = __cpu_to_le32(1),
232 .pipedir = __cpu_to_le32(PIPEDIR_IN),
233 .nentries = __cpu_to_le32(32),
234 .nbytes_max = __cpu_to_le32(2048),
235 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
236 .reserved = __cpu_to_le32(0),
237 },
238
239 /* CE2: target->host WMI */
240 {
241 .pipenum = __cpu_to_le32(2),
242 .pipedir = __cpu_to_le32(PIPEDIR_IN),
243 .nentries = __cpu_to_le32(64),
244 .nbytes_max = __cpu_to_le32(2048),
245 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
246 .reserved = __cpu_to_le32(0),
247 },
248
249 /* CE3: host->target WMI */
250 {
251 .pipenum = __cpu_to_le32(3),
252 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
253 .nentries = __cpu_to_le32(32),
254 .nbytes_max = __cpu_to_le32(2048),
255 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
256 .reserved = __cpu_to_le32(0),
257 },
258
259 /* CE4: host->target HTT */
260 {
261 .pipenum = __cpu_to_le32(4),
262 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
263 .nentries = __cpu_to_le32(256),
264 .nbytes_max = __cpu_to_le32(256),
265 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
266 .reserved = __cpu_to_le32(0),
267 },
268
269 /* NB: 50% of src nentries, since tx has 2 frags */
270
271 /* CE5: target->host HTT (HIF->HTT) */
272 {
273 .pipenum = __cpu_to_le32(5),
274 .pipedir = __cpu_to_le32(PIPEDIR_IN),
275 .nentries = __cpu_to_le32(32),
276 .nbytes_max = __cpu_to_le32(512),
277 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
278 .reserved = __cpu_to_le32(0),
279 },
280
281 /* CE6: Reserved for target autonomous hif_memcpy */
282 {
283 .pipenum = __cpu_to_le32(6),
284 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
285 .nentries = __cpu_to_le32(32),
286 .nbytes_max = __cpu_to_le32(4096),
287 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
288 .reserved = __cpu_to_le32(0),
289 },
290
291 /* CE7 used only by Host */
292 {
293 .pipenum = __cpu_to_le32(7),
294 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
295 .nentries = __cpu_to_le32(0),
296 .nbytes_max = __cpu_to_le32(0),
297 .flags = __cpu_to_le32(0),
298 .reserved = __cpu_to_le32(0),
299 },
300
301 /* CE8 target->host packtlog */
302 {
303 .pipenum = __cpu_to_le32(8),
304 .pipedir = __cpu_to_le32(PIPEDIR_IN),
305 .nentries = __cpu_to_le32(64),
306 .nbytes_max = __cpu_to_le32(2048),
307 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
308 .reserved = __cpu_to_le32(0),
309 },
310
311 /* CE9 target autonomous qcache memcpy */
312 {
313 .pipenum = __cpu_to_le32(9),
314 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
315 .nentries = __cpu_to_le32(32),
316 .nbytes_max = __cpu_to_le32(2048),
317 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
318 .reserved = __cpu_to_le32(0),
319 },
320
321 /* It not necessary to send target wlan configuration for CE10 & CE11
322 * as these CEs are not actively used in target.
323 */
324};
325
326/*
327 * Map from service/endpoint to Copy Engine.
328 * This table is derived from the CE_PCI TABLE, above.
329 * It is passed to the Target at startup for use by firmware.
330 */
331static struct service_to_pipe target_service_to_ce_map_wlan[] = {
332 {
333 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
334 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
335 __cpu_to_le32(3),
336 },
337 {
338 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
339 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
340 __cpu_to_le32(2),
341 },
342 {
343 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
344 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
345 __cpu_to_le32(3),
346 },
347 {
348 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
349 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
350 __cpu_to_le32(2),
351 },
352 {
353 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
354 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
355 __cpu_to_le32(3),
356 },
357 {
358 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
359 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
360 __cpu_to_le32(2),
361 },
362 {
363 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
364 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
365 __cpu_to_le32(3),
366 },
367 {
368 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
369 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
370 __cpu_to_le32(2),
371 },
372 {
373 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
374 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
375 __cpu_to_le32(3),
376 },
377 {
378 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
379 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
380 __cpu_to_le32(2),
381 },
382 {
383 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
384 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
385 __cpu_to_le32(0),
386 },
387 {
388 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
389 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
390 __cpu_to_le32(1),
391 },
392 { /* not used */
393 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
394 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
395 __cpu_to_le32(0),
396 },
397 { /* not used */
398 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
399 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
400 __cpu_to_le32(1),
401 },
402 {
403 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
404 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
405 __cpu_to_le32(4),
406 },
407 {
408 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
409 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
410 __cpu_to_le32(5),
411 },
412
413 /* (Additions here) */
414
415 { /* must be last */
416 __cpu_to_le32(0),
417 __cpu_to_le32(0),
418 __cpu_to_le32(0),
419 },
420};
421
422static bool ath10k_pci_is_awake(struct ath10k *ar)
423{
424 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
425 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
426 RTC_STATE_ADDRESS);
427
428 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
429}
430
431static void __ath10k_pci_wake(struct ath10k *ar)
432{
433 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
434
435 lockdep_assert_held(&ar_pci->ps_lock);
436
437 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
438 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
439
440 iowrite32(PCIE_SOC_WAKE_V_MASK,
441 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
442 PCIE_SOC_WAKE_ADDRESS);
443}
444
445static void __ath10k_pci_sleep(struct ath10k *ar)
446{
447 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
448
449 lockdep_assert_held(&ar_pci->ps_lock);
450
451 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
452 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
453
454 iowrite32(PCIE_SOC_WAKE_RESET,
455 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
456 PCIE_SOC_WAKE_ADDRESS);
457 ar_pci->ps_awake = false;
458}
459
460static int ath10k_pci_wake_wait(struct ath10k *ar)
461{
462 int tot_delay = 0;
463 int curr_delay = 5;
464
465 while (tot_delay < PCIE_WAKE_TIMEOUT) {
466 if (ath10k_pci_is_awake(ar)) {
467 if (tot_delay > PCIE_WAKE_LATE_US)
468 ath10k_warn(ar, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n",
469 tot_delay / 1000);
470 return 0;
471 }
472
473 udelay(curr_delay);
474 tot_delay += curr_delay;
475
476 if (curr_delay < 50)
477 curr_delay += 5;
478 }
479
480 return -ETIMEDOUT;
481}
482
483static int ath10k_pci_force_wake(struct ath10k *ar)
484{
485 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
486 unsigned long flags;
487 int ret = 0;
488
489 if (ar_pci->pci_ps)
490 return ret;
491
492 spin_lock_irqsave(&ar_pci->ps_lock, flags);
493
494 if (!ar_pci->ps_awake) {
495 iowrite32(PCIE_SOC_WAKE_V_MASK,
496 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
497 PCIE_SOC_WAKE_ADDRESS);
498
499 ret = ath10k_pci_wake_wait(ar);
500 if (ret == 0)
501 ar_pci->ps_awake = true;
502 }
503
504 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
505
506 return ret;
507}
508
509static void ath10k_pci_force_sleep(struct ath10k *ar)
510{
511 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
512 unsigned long flags;
513
514 spin_lock_irqsave(&ar_pci->ps_lock, flags);
515
516 iowrite32(PCIE_SOC_WAKE_RESET,
517 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
518 PCIE_SOC_WAKE_ADDRESS);
519 ar_pci->ps_awake = false;
520
521 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
522}
523
524static int ath10k_pci_wake(struct ath10k *ar)
525{
526 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
527 unsigned long flags;
528 int ret = 0;
529
530 if (ar_pci->pci_ps == 0)
531 return ret;
532
533 spin_lock_irqsave(&ar_pci->ps_lock, flags);
534
535 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
536 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
537
538 /* This function can be called very frequently. To avoid excessive
539 * CPU stalls for MMIO reads use a cache var to hold the device state.
540 */
541 if (!ar_pci->ps_awake) {
542 __ath10k_pci_wake(ar);
543
544 ret = ath10k_pci_wake_wait(ar);
545 if (ret == 0)
546 ar_pci->ps_awake = true;
547 }
548
549 if (ret == 0) {
550 ar_pci->ps_wake_refcount++;
551 WARN_ON(ar_pci->ps_wake_refcount == 0);
552 }
553
554 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
555
556 return ret;
557}
558
559static void ath10k_pci_sleep(struct ath10k *ar)
560{
561 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
562 unsigned long flags;
563
564 if (ar_pci->pci_ps == 0)
565 return;
566
567 spin_lock_irqsave(&ar_pci->ps_lock, flags);
568
569 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
570 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
571
572 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
573 goto skip;
574
575 ar_pci->ps_wake_refcount--;
576
577 mod_timer(&ar_pci->ps_timer, jiffies +
578 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
579
580skip:
581 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
582}
583
584static void ath10k_pci_ps_timer(unsigned long ptr)
585{
586 struct ath10k *ar = (void *)ptr;
587 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
588 unsigned long flags;
589
590 spin_lock_irqsave(&ar_pci->ps_lock, flags);
591
592 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
593 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
594
595 if (ar_pci->ps_wake_refcount > 0)
596 goto skip;
597
598 __ath10k_pci_sleep(ar);
599
600skip:
601 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
602}
603
604static void ath10k_pci_sleep_sync(struct ath10k *ar)
605{
606 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
607 unsigned long flags;
608
609 if (ar_pci->pci_ps == 0) {
610 ath10k_pci_force_sleep(ar);
611 return;
612 }
613
614 del_timer_sync(&ar_pci->ps_timer);
615
616 spin_lock_irqsave(&ar_pci->ps_lock, flags);
617 WARN_ON(ar_pci->ps_wake_refcount > 0);
618 __ath10k_pci_sleep(ar);
619 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
620}
621
622static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
623{
624 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
625 int ret;
626
627 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
628 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
629 offset, offset + sizeof(value), ar_pci->mem_len);
630 return;
631 }
632
633 ret = ath10k_pci_wake(ar);
634 if (ret) {
635 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
636 value, offset, ret);
637 return;
638 }
639
640 iowrite32(value, ar_pci->mem + offset);
641 ath10k_pci_sleep(ar);
642}
643
644static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
645{
646 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
647 u32 val;
648 int ret;
649
650 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
651 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
652 offset, offset + sizeof(val), ar_pci->mem_len);
653 return 0;
654 }
655
656 ret = ath10k_pci_wake(ar);
657 if (ret) {
658 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
659 offset, ret);
660 return 0xffffffff;
661 }
662
663 val = ioread32(ar_pci->mem + offset);
664 ath10k_pci_sleep(ar);
665
666 return val;
667}
668
669inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
670{
671 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
672
673 ar_pci->bus_ops->write32(ar, offset, value);
674}
675
676inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
677{
678 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
679
680 return ar_pci->bus_ops->read32(ar, offset);
681}
682
683u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
684{
685 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
686}
687
688void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
689{
690 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
691}
692
693u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
694{
695 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
696}
697
698void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
699{
700 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
701}
702
703bool ath10k_pci_irq_pending(struct ath10k *ar)
704{
705 u32 cause;
706
707 /* Check if the shared legacy irq is for us */
708 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
709 PCIE_INTR_CAUSE_ADDRESS);
710 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
711 return true;
712
713 return false;
714}
715
716void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
717{
718 /* IMPORTANT: INTR_CLR register has to be set after
719 * INTR_ENABLE is set to 0, otherwise interrupt can not be
720 * really cleared. */
721 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
722 0);
723 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
724 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
725
726 /* IMPORTANT: this extra read transaction is required to
727 * flush the posted write buffer. */
728 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
729 PCIE_INTR_ENABLE_ADDRESS);
730}
731
732void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
733{
734 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
735 PCIE_INTR_ENABLE_ADDRESS,
736 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
737
738 /* IMPORTANT: this extra read transaction is required to
739 * flush the posted write buffer. */
740 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
741 PCIE_INTR_ENABLE_ADDRESS);
742}
743
744static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
745{
746 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
747
748 if (ar_pci->num_msi_intrs > 1)
749 return "msi-x";
750
751 if (ar_pci->num_msi_intrs == 1)
752 return "msi";
753
754 return "legacy";
755}
756
757static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
758{
759 struct ath10k *ar = pipe->hif_ce_state;
760 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
761 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
762 struct sk_buff *skb;
763 dma_addr_t paddr;
764 int ret;
765
766 skb = dev_alloc_skb(pipe->buf_sz);
767 if (!skb)
768 return -ENOMEM;
769
770 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
771
772 paddr = dma_map_single(ar->dev, skb->data,
773 skb->len + skb_tailroom(skb),
774 DMA_FROM_DEVICE);
775 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
776 ath10k_warn(ar, "failed to dma map pci rx buf\n");
777 dev_kfree_skb_any(skb);
778 return -EIO;
779 }
780
781 ATH10K_SKB_RXCB(skb)->paddr = paddr;
782
783 spin_lock_bh(&ar_pci->ce_lock);
784 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
785 spin_unlock_bh(&ar_pci->ce_lock);
786 if (ret) {
787 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
788 DMA_FROM_DEVICE);
789 dev_kfree_skb_any(skb);
790 return ret;
791 }
792
793 return 0;
794}
795
796static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
797{
798 struct ath10k *ar = pipe->hif_ce_state;
799 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
800 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
801 int ret, num;
802
803 if (pipe->buf_sz == 0)
804 return;
805
806 if (!ce_pipe->dest_ring)
807 return;
808
809 spin_lock_bh(&ar_pci->ce_lock);
810 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
811 spin_unlock_bh(&ar_pci->ce_lock);
812 while (num--) {
813 ret = __ath10k_pci_rx_post_buf(pipe);
814 if (ret) {
815 if (ret == -ENOSPC)
816 break;
817 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
818 mod_timer(&ar_pci->rx_post_retry, jiffies +
819 ATH10K_PCI_RX_POST_RETRY_MS);
820 break;
821 }
822 }
823}
824
825void ath10k_pci_rx_post(struct ath10k *ar)
826{
827 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
828 int i;
829
830 for (i = 0; i < CE_COUNT; i++)
831 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
832}
833
834void ath10k_pci_rx_replenish_retry(unsigned long ptr)
835{
836 struct ath10k *ar = (void *)ptr;
837
838 ath10k_pci_rx_post(ar);
839}
840
841static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
842{
843 u32 val = 0;
844
845 switch (ar->hw_rev) {
846 case ATH10K_HW_QCA988X:
847 case ATH10K_HW_QCA6174:
848 case ATH10K_HW_QCA9377:
849 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
850 CORE_CTRL_ADDRESS) &
851 0x7ff) << 21;
852 break;
853 case ATH10K_HW_QCA99X0:
854 case ATH10K_HW_QCA4019:
855 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
856 break;
857 }
858
859 val |= 0x100000 | (addr & 0xfffff);
860 return val;
861}
862
863/*
864 * Diagnostic read/write access is provided for startup/config/debug usage.
865 * Caller must guarantee proper alignment, when applicable, and single user
866 * at any moment.
867 */
868static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
869 int nbytes)
870{
871 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
872 int ret = 0;
873 u32 buf;
874 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
875 unsigned int id;
876 unsigned int flags;
877 struct ath10k_ce_pipe *ce_diag;
878 /* Host buffer address in CE space */
879 u32 ce_data;
880 dma_addr_t ce_data_base = 0;
881 void *data_buf = NULL;
882 int i;
883
884 spin_lock_bh(&ar_pci->ce_lock);
885
886 ce_diag = ar_pci->ce_diag;
887
888 /*
889 * Allocate a temporary bounce buffer to hold caller's data
890 * to be DMA'ed from Target. This guarantees
891 * 1) 4-byte alignment
892 * 2) Buffer in DMA-able space
893 */
894 orig_nbytes = nbytes;
895 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
896 orig_nbytes,
897 &ce_data_base,
898 GFP_ATOMIC);
899
900 if (!data_buf) {
901 ret = -ENOMEM;
902 goto done;
903 }
904 memset(data_buf, 0, orig_nbytes);
905
906 remaining_bytes = orig_nbytes;
907 ce_data = ce_data_base;
908 while (remaining_bytes) {
909 nbytes = min_t(unsigned int, remaining_bytes,
910 DIAG_TRANSFER_LIMIT);
911
912 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
913 if (ret != 0)
914 goto done;
915
916 /* Request CE to send from Target(!) address to Host buffer */
917 /*
918 * The address supplied by the caller is in the
919 * Target CPU virtual address space.
920 *
921 * In order to use this address with the diagnostic CE,
922 * convert it from Target CPU virtual address space
923 * to CE address space
924 */
925 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
926
927 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
928 0);
929 if (ret)
930 goto done;
931
932 i = 0;
933 while (ath10k_ce_completed_send_next_nolock(ce_diag,
934 NULL) != 0) {
935 mdelay(1);
936 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
937 ret = -EBUSY;
938 goto done;
939 }
940 }
941
942 i = 0;
943 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
944 &completed_nbytes,
945 &id, &flags) != 0) {
946 mdelay(1);
947
948 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
949 ret = -EBUSY;
950 goto done;
951 }
952 }
953
954 if (nbytes != completed_nbytes) {
955 ret = -EIO;
956 goto done;
957 }
958
959 if (buf != ce_data) {
960 ret = -EIO;
961 goto done;
962 }
963
964 remaining_bytes -= nbytes;
965 address += nbytes;
966 ce_data += nbytes;
967 }
968
969done:
970 if (ret == 0)
971 memcpy(data, data_buf, orig_nbytes);
972 else
973 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
974 address, ret);
975
976 if (data_buf)
977 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
978 ce_data_base);
979
980 spin_unlock_bh(&ar_pci->ce_lock);
981
982 return ret;
983}
984
985static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
986{
987 __le32 val = 0;
988 int ret;
989
990 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
991 *value = __le32_to_cpu(val);
992
993 return ret;
994}
995
996static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
997 u32 src, u32 len)
998{
999 u32 host_addr, addr;
1000 int ret;
1001
1002 host_addr = host_interest_item_address(src);
1003
1004 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1005 if (ret != 0) {
1006 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1007 src, ret);
1008 return ret;
1009 }
1010
1011 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1012 if (ret != 0) {
1013 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1014 addr, len, ret);
1015 return ret;
1016 }
1017
1018 return 0;
1019}
1020
1021#define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1022 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1023
1024int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1025 const void *data, int nbytes)
1026{
1027 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1028 int ret = 0;
1029 u32 buf;
1030 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1031 unsigned int id;
1032 unsigned int flags;
1033 struct ath10k_ce_pipe *ce_diag;
1034 void *data_buf = NULL;
1035 u32 ce_data; /* Host buffer address in CE space */
1036 dma_addr_t ce_data_base = 0;
1037 int i;
1038
1039 spin_lock_bh(&ar_pci->ce_lock);
1040
1041 ce_diag = ar_pci->ce_diag;
1042
1043 /*
1044 * Allocate a temporary bounce buffer to hold caller's data
1045 * to be DMA'ed to Target. This guarantees
1046 * 1) 4-byte alignment
1047 * 2) Buffer in DMA-able space
1048 */
1049 orig_nbytes = nbytes;
1050 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1051 orig_nbytes,
1052 &ce_data_base,
1053 GFP_ATOMIC);
1054 if (!data_buf) {
1055 ret = -ENOMEM;
1056 goto done;
1057 }
1058
1059 /* Copy caller's data to allocated DMA buf */
1060 memcpy(data_buf, data, orig_nbytes);
1061
1062 /*
1063 * The address supplied by the caller is in the
1064 * Target CPU virtual address space.
1065 *
1066 * In order to use this address with the diagnostic CE,
1067 * convert it from
1068 * Target CPU virtual address space
1069 * to
1070 * CE address space
1071 */
1072 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1073
1074 remaining_bytes = orig_nbytes;
1075 ce_data = ce_data_base;
1076 while (remaining_bytes) {
1077 /* FIXME: check cast */
1078 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1079
1080 /* Set up to receive directly into Target(!) address */
1081 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address);
1082 if (ret != 0)
1083 goto done;
1084
1085 /*
1086 * Request CE to send caller-supplied data that
1087 * was copied to bounce buffer to Target(!) address.
1088 */
1089 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1090 nbytes, 0, 0);
1091 if (ret != 0)
1092 goto done;
1093
1094 i = 0;
1095 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1096 NULL) != 0) {
1097 mdelay(1);
1098
1099 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1100 ret = -EBUSY;
1101 goto done;
1102 }
1103 }
1104
1105 i = 0;
1106 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
1107 &completed_nbytes,
1108 &id, &flags) != 0) {
1109 mdelay(1);
1110
1111 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1112 ret = -EBUSY;
1113 goto done;
1114 }
1115 }
1116
1117 if (nbytes != completed_nbytes) {
1118 ret = -EIO;
1119 goto done;
1120 }
1121
1122 if (buf != address) {
1123 ret = -EIO;
1124 goto done;
1125 }
1126
1127 remaining_bytes -= nbytes;
1128 address += nbytes;
1129 ce_data += nbytes;
1130 }
1131
1132done:
1133 if (data_buf) {
1134 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1135 ce_data_base);
1136 }
1137
1138 if (ret != 0)
1139 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1140 address, ret);
1141
1142 spin_unlock_bh(&ar_pci->ce_lock);
1143
1144 return ret;
1145}
1146
1147static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1148{
1149 __le32 val = __cpu_to_le32(value);
1150
1151 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1152}
1153
1154/* Called by lower (CE) layer when a send to Target completes. */
1155static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1156{
1157 struct ath10k *ar = ce_state->ar;
1158 struct sk_buff_head list;
1159 struct sk_buff *skb;
1160
1161 __skb_queue_head_init(&list);
1162 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1163 /* no need to call tx completion for NULL pointers */
1164 if (skb == NULL)
1165 continue;
1166
1167 __skb_queue_tail(&list, skb);
1168 }
1169
1170 while ((skb = __skb_dequeue(&list)))
1171 ath10k_htc_tx_completion_handler(ar, skb);
1172}
1173
1174static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1175 void (*callback)(struct ath10k *ar,
1176 struct sk_buff *skb))
1177{
1178 struct ath10k *ar = ce_state->ar;
1179 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1180 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1181 struct sk_buff *skb;
1182 struct sk_buff_head list;
1183 void *transfer_context;
1184 u32 ce_data;
1185 unsigned int nbytes, max_nbytes;
1186 unsigned int transfer_id;
1187 unsigned int flags;
1188
1189 __skb_queue_head_init(&list);
1190 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1191 &ce_data, &nbytes, &transfer_id,
1192 &flags) == 0) {
1193 skb = transfer_context;
1194 max_nbytes = skb->len + skb_tailroom(skb);
1195 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1196 max_nbytes, DMA_FROM_DEVICE);
1197
1198 if (unlikely(max_nbytes < nbytes)) {
1199 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1200 nbytes, max_nbytes);
1201 dev_kfree_skb_any(skb);
1202 continue;
1203 }
1204
1205 skb_put(skb, nbytes);
1206 __skb_queue_tail(&list, skb);
1207 }
1208
1209 while ((skb = __skb_dequeue(&list))) {
1210 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1211 ce_state->id, skb->len);
1212 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1213 skb->data, skb->len);
1214
1215 callback(ar, skb);
1216 }
1217
1218 ath10k_pci_rx_post_pipe(pipe_info);
1219}
1220
1221/* Called by lower (CE) layer when data is received from the Target. */
1222static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1223{
1224 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1225}
1226
1227static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1228{
1229 /* CE4 polling needs to be done whenever CE pipe which transports
1230 * HTT Rx (target->host) is processed.
1231 */
1232 ath10k_ce_per_engine_service(ce_state->ar, 4);
1233
1234 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1235}
1236
1237/* Called by lower (CE) layer when data is received from the Target.
1238 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1239 */
1240static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1241{
1242 ath10k_pci_process_rx_cb(ce_state,
1243 ath10k_htt_rx_pktlog_completion_handler);
1244}
1245
1246/* Called by lower (CE) layer when a send to HTT Target completes. */
1247static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1248{
1249 struct ath10k *ar = ce_state->ar;
1250 struct sk_buff *skb;
1251
1252 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1253 /* no need to call tx completion for NULL pointers */
1254 if (!skb)
1255 continue;
1256
1257 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1258 skb->len, DMA_TO_DEVICE);
1259 ath10k_htt_hif_tx_complete(ar, skb);
1260 }
1261}
1262
1263static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1264{
1265 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1266 ath10k_htt_t2h_msg_handler(ar, skb);
1267}
1268
1269/* Called by lower (CE) layer when HTT data is received from the Target. */
1270static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1271{
1272 /* CE4 polling needs to be done whenever CE pipe which transports
1273 * HTT Rx (target->host) is processed.
1274 */
1275 ath10k_ce_per_engine_service(ce_state->ar, 4);
1276
1277 ath10k_pci_process_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1278}
1279
1280int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1281 struct ath10k_hif_sg_item *items, int n_items)
1282{
1283 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1284 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1285 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1286 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1287 unsigned int nentries_mask;
1288 unsigned int sw_index;
1289 unsigned int write_index;
1290 int err, i = 0;
1291
1292 spin_lock_bh(&ar_pci->ce_lock);
1293
1294 nentries_mask = src_ring->nentries_mask;
1295 sw_index = src_ring->sw_index;
1296 write_index = src_ring->write_index;
1297
1298 if (unlikely(CE_RING_DELTA(nentries_mask,
1299 write_index, sw_index - 1) < n_items)) {
1300 err = -ENOBUFS;
1301 goto err;
1302 }
1303
1304 for (i = 0; i < n_items - 1; i++) {
1305 ath10k_dbg(ar, ATH10K_DBG_PCI,
1306 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1307 i, items[i].paddr, items[i].len, n_items);
1308 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1309 items[i].vaddr, items[i].len);
1310
1311 err = ath10k_ce_send_nolock(ce_pipe,
1312 items[i].transfer_context,
1313 items[i].paddr,
1314 items[i].len,
1315 items[i].transfer_id,
1316 CE_SEND_FLAG_GATHER);
1317 if (err)
1318 goto err;
1319 }
1320
1321 /* `i` is equal to `n_items -1` after for() */
1322
1323 ath10k_dbg(ar, ATH10K_DBG_PCI,
1324 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1325 i, items[i].paddr, items[i].len, n_items);
1326 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1327 items[i].vaddr, items[i].len);
1328
1329 err = ath10k_ce_send_nolock(ce_pipe,
1330 items[i].transfer_context,
1331 items[i].paddr,
1332 items[i].len,
1333 items[i].transfer_id,
1334 0);
1335 if (err)
1336 goto err;
1337
1338 spin_unlock_bh(&ar_pci->ce_lock);
1339 return 0;
1340
1341err:
1342 for (; i > 0; i--)
1343 __ath10k_ce_send_revert(ce_pipe);
1344
1345 spin_unlock_bh(&ar_pci->ce_lock);
1346 return err;
1347}
1348
1349int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1350 size_t buf_len)
1351{
1352 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1353}
1354
1355u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1356{
1357 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1358
1359 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1360
1361 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1362}
1363
1364static void ath10k_pci_dump_registers(struct ath10k *ar,
1365 struct ath10k_fw_crash_data *crash_data)
1366{
1367 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1368 int i, ret;
1369
1370 lockdep_assert_held(&ar->data_lock);
1371
1372 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1373 hi_failure_state,
1374 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1375 if (ret) {
1376 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1377 return;
1378 }
1379
1380 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1381
1382 ath10k_err(ar, "firmware register dump:\n");
1383 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1384 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1385 i,
1386 __le32_to_cpu(reg_dump_values[i]),
1387 __le32_to_cpu(reg_dump_values[i + 1]),
1388 __le32_to_cpu(reg_dump_values[i + 2]),
1389 __le32_to_cpu(reg_dump_values[i + 3]));
1390
1391 if (!crash_data)
1392 return;
1393
1394 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1395 crash_data->registers[i] = reg_dump_values[i];
1396}
1397
1398static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1399{
1400 struct ath10k_fw_crash_data *crash_data;
1401 char uuid[50];
1402
1403 spin_lock_bh(&ar->data_lock);
1404
1405 ar->stats.fw_crash_counter++;
1406
1407 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1408
1409 if (crash_data)
1410 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1411 else
1412 scnprintf(uuid, sizeof(uuid), "n/a");
1413
1414 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1415 ath10k_print_driver_info(ar);
1416 ath10k_pci_dump_registers(ar, crash_data);
1417
1418 spin_unlock_bh(&ar->data_lock);
1419
1420 queue_work(ar->workqueue, &ar->restart_work);
1421}
1422
1423void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1424 int force)
1425{
1426 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1427
1428 if (!force) {
1429 int resources;
1430 /*
1431 * Decide whether to actually poll for completions, or just
1432 * wait for a later chance.
1433 * If there seem to be plenty of resources left, then just wait
1434 * since checking involves reading a CE register, which is a
1435 * relatively expensive operation.
1436 */
1437 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1438
1439 /*
1440 * If at least 50% of the total resources are still available,
1441 * don't bother checking again yet.
1442 */
1443 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1444 return;
1445 }
1446 ath10k_ce_per_engine_service(ar, pipe);
1447}
1448
1449void ath10k_pci_kill_tasklet(struct ath10k *ar)
1450{
1451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1452 int i;
1453
1454 tasklet_kill(&ar_pci->intr_tq);
1455 tasklet_kill(&ar_pci->msi_fw_err);
1456
1457 for (i = 0; i < CE_COUNT; i++)
1458 tasklet_kill(&ar_pci->pipe_info[i].intr);
1459
1460 del_timer_sync(&ar_pci->rx_post_retry);
1461}
1462
1463int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1464 u8 *ul_pipe, u8 *dl_pipe)
1465{
1466 const struct service_to_pipe *entry;
1467 bool ul_set = false, dl_set = false;
1468 int i;
1469
1470 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1471
1472 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1473 entry = &target_service_to_ce_map_wlan[i];
1474
1475 if (__le32_to_cpu(entry->service_id) != service_id)
1476 continue;
1477
1478 switch (__le32_to_cpu(entry->pipedir)) {
1479 case PIPEDIR_NONE:
1480 break;
1481 case PIPEDIR_IN:
1482 WARN_ON(dl_set);
1483 *dl_pipe = __le32_to_cpu(entry->pipenum);
1484 dl_set = true;
1485 break;
1486 case PIPEDIR_OUT:
1487 WARN_ON(ul_set);
1488 *ul_pipe = __le32_to_cpu(entry->pipenum);
1489 ul_set = true;
1490 break;
1491 case PIPEDIR_INOUT:
1492 WARN_ON(dl_set);
1493 WARN_ON(ul_set);
1494 *dl_pipe = __le32_to_cpu(entry->pipenum);
1495 *ul_pipe = __le32_to_cpu(entry->pipenum);
1496 dl_set = true;
1497 ul_set = true;
1498 break;
1499 }
1500 }
1501
1502 if (WARN_ON(!ul_set || !dl_set))
1503 return -ENOENT;
1504
1505 return 0;
1506}
1507
1508void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1509 u8 *ul_pipe, u8 *dl_pipe)
1510{
1511 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1512
1513 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1514 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1515 ul_pipe, dl_pipe);
1516}
1517
1518static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1519{
1520 u32 val;
1521
1522 switch (ar->hw_rev) {
1523 case ATH10K_HW_QCA988X:
1524 case ATH10K_HW_QCA6174:
1525 case ATH10K_HW_QCA9377:
1526 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1527 CORE_CTRL_ADDRESS);
1528 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1529 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1530 CORE_CTRL_ADDRESS, val);
1531 break;
1532 case ATH10K_HW_QCA99X0:
1533 case ATH10K_HW_QCA4019:
1534 /* TODO: Find appropriate register configuration for QCA99X0
1535 * to mask irq/MSI.
1536 */
1537 break;
1538 }
1539}
1540
1541static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1542{
1543 u32 val;
1544
1545 switch (ar->hw_rev) {
1546 case ATH10K_HW_QCA988X:
1547 case ATH10K_HW_QCA6174:
1548 case ATH10K_HW_QCA9377:
1549 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1550 CORE_CTRL_ADDRESS);
1551 val |= CORE_CTRL_PCIE_REG_31_MASK;
1552 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1553 CORE_CTRL_ADDRESS, val);
1554 break;
1555 case ATH10K_HW_QCA99X0:
1556 case ATH10K_HW_QCA4019:
1557 /* TODO: Find appropriate register configuration for QCA99X0
1558 * to unmask irq/MSI.
1559 */
1560 break;
1561 }
1562}
1563
1564static void ath10k_pci_irq_disable(struct ath10k *ar)
1565{
1566 ath10k_ce_disable_interrupts(ar);
1567 ath10k_pci_disable_and_clear_legacy_irq(ar);
1568 ath10k_pci_irq_msi_fw_mask(ar);
1569}
1570
1571static void ath10k_pci_irq_sync(struct ath10k *ar)
1572{
1573 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1574 int i;
1575
1576 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1577 synchronize_irq(ar_pci->pdev->irq + i);
1578}
1579
1580static void ath10k_pci_irq_enable(struct ath10k *ar)
1581{
1582 ath10k_ce_enable_interrupts(ar);
1583 ath10k_pci_enable_legacy_irq(ar);
1584 ath10k_pci_irq_msi_fw_unmask(ar);
1585}
1586
1587static int ath10k_pci_hif_start(struct ath10k *ar)
1588{
1589 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1590
1591 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1592
1593 ath10k_pci_irq_enable(ar);
1594 ath10k_pci_rx_post(ar);
1595
1596 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1597 ar_pci->link_ctl);
1598
1599 return 0;
1600}
1601
1602static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1603{
1604 struct ath10k *ar;
1605 struct ath10k_ce_pipe *ce_pipe;
1606 struct ath10k_ce_ring *ce_ring;
1607 struct sk_buff *skb;
1608 int i;
1609
1610 ar = pci_pipe->hif_ce_state;
1611 ce_pipe = pci_pipe->ce_hdl;
1612 ce_ring = ce_pipe->dest_ring;
1613
1614 if (!ce_ring)
1615 return;
1616
1617 if (!pci_pipe->buf_sz)
1618 return;
1619
1620 for (i = 0; i < ce_ring->nentries; i++) {
1621 skb = ce_ring->per_transfer_context[i];
1622 if (!skb)
1623 continue;
1624
1625 ce_ring->per_transfer_context[i] = NULL;
1626
1627 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1628 skb->len + skb_tailroom(skb),
1629 DMA_FROM_DEVICE);
1630 dev_kfree_skb_any(skb);
1631 }
1632}
1633
1634static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1635{
1636 struct ath10k *ar;
1637 struct ath10k_pci *ar_pci;
1638 struct ath10k_ce_pipe *ce_pipe;
1639 struct ath10k_ce_ring *ce_ring;
1640 struct sk_buff *skb;
1641 int i;
1642
1643 ar = pci_pipe->hif_ce_state;
1644 ar_pci = ath10k_pci_priv(ar);
1645 ce_pipe = pci_pipe->ce_hdl;
1646 ce_ring = ce_pipe->src_ring;
1647
1648 if (!ce_ring)
1649 return;
1650
1651 if (!pci_pipe->buf_sz)
1652 return;
1653
1654 for (i = 0; i < ce_ring->nentries; i++) {
1655 skb = ce_ring->per_transfer_context[i];
1656 if (!skb)
1657 continue;
1658
1659 ce_ring->per_transfer_context[i] = NULL;
1660
1661 ath10k_htc_tx_completion_handler(ar, skb);
1662 }
1663}
1664
1665/*
1666 * Cleanup residual buffers for device shutdown:
1667 * buffers that were enqueued for receive
1668 * buffers that were to be sent
1669 * Note: Buffers that had completed but which were
1670 * not yet processed are on a completion queue. They
1671 * are handled when the completion thread shuts down.
1672 */
1673static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1674{
1675 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1676 int pipe_num;
1677
1678 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1679 struct ath10k_pci_pipe *pipe_info;
1680
1681 pipe_info = &ar_pci->pipe_info[pipe_num];
1682 ath10k_pci_rx_pipe_cleanup(pipe_info);
1683 ath10k_pci_tx_pipe_cleanup(pipe_info);
1684 }
1685}
1686
1687void ath10k_pci_ce_deinit(struct ath10k *ar)
1688{
1689 int i;
1690
1691 for (i = 0; i < CE_COUNT; i++)
1692 ath10k_ce_deinit_pipe(ar, i);
1693}
1694
1695void ath10k_pci_flush(struct ath10k *ar)
1696{
1697 ath10k_pci_kill_tasklet(ar);
1698 ath10k_pci_buffer_cleanup(ar);
1699}
1700
1701static void ath10k_pci_hif_stop(struct ath10k *ar)
1702{
1703 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1704 unsigned long flags;
1705
1706 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1707
1708 /* Most likely the device has HTT Rx ring configured. The only way to
1709 * prevent the device from accessing (and possible corrupting) host
1710 * memory is to reset the chip now.
1711 *
1712 * There's also no known way of masking MSI interrupts on the device.
1713 * For ranged MSI the CE-related interrupts can be masked. However
1714 * regardless how many MSI interrupts are assigned the first one
1715 * is always used for firmware indications (crashes) and cannot be
1716 * masked. To prevent the device from asserting the interrupt reset it
1717 * before proceeding with cleanup.
1718 */
1719 ath10k_pci_safe_chip_reset(ar);
1720
1721 ath10k_pci_irq_disable(ar);
1722 ath10k_pci_irq_sync(ar);
1723 ath10k_pci_flush(ar);
1724
1725 spin_lock_irqsave(&ar_pci->ps_lock, flags);
1726 WARN_ON(ar_pci->ps_wake_refcount > 0);
1727 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1728}
1729
1730int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1731 void *req, u32 req_len,
1732 void *resp, u32 *resp_len)
1733{
1734 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1735 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1736 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1737 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1738 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1739 dma_addr_t req_paddr = 0;
1740 dma_addr_t resp_paddr = 0;
1741 struct bmi_xfer xfer = {};
1742 void *treq, *tresp = NULL;
1743 int ret = 0;
1744
1745 might_sleep();
1746
1747 if (resp && !resp_len)
1748 return -EINVAL;
1749
1750 if (resp && resp_len && *resp_len == 0)
1751 return -EINVAL;
1752
1753 treq = kmemdup(req, req_len, GFP_KERNEL);
1754 if (!treq)
1755 return -ENOMEM;
1756
1757 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1758 ret = dma_mapping_error(ar->dev, req_paddr);
1759 if (ret) {
1760 ret = -EIO;
1761 goto err_dma;
1762 }
1763
1764 if (resp && resp_len) {
1765 tresp = kzalloc(*resp_len, GFP_KERNEL);
1766 if (!tresp) {
1767 ret = -ENOMEM;
1768 goto err_req;
1769 }
1770
1771 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1772 DMA_FROM_DEVICE);
1773 ret = dma_mapping_error(ar->dev, resp_paddr);
1774 if (ret) {
1775 ret = -EIO;
1776 goto err_req;
1777 }
1778
1779 xfer.wait_for_resp = true;
1780 xfer.resp_len = 0;
1781
1782 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1783 }
1784
1785 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1786 if (ret)
1787 goto err_resp;
1788
1789 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1790 if (ret) {
1791 u32 unused_buffer;
1792 unsigned int unused_nbytes;
1793 unsigned int unused_id;
1794
1795 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1796 &unused_nbytes, &unused_id);
1797 } else {
1798 /* non-zero means we did not time out */
1799 ret = 0;
1800 }
1801
1802err_resp:
1803 if (resp) {
1804 u32 unused_buffer;
1805
1806 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1807 dma_unmap_single(ar->dev, resp_paddr,
1808 *resp_len, DMA_FROM_DEVICE);
1809 }
1810err_req:
1811 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1812
1813 if (ret == 0 && resp_len) {
1814 *resp_len = min(*resp_len, xfer.resp_len);
1815 memcpy(resp, tresp, xfer.resp_len);
1816 }
1817err_dma:
1818 kfree(treq);
1819 kfree(tresp);
1820
1821 return ret;
1822}
1823
1824static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1825{
1826 struct bmi_xfer *xfer;
1827
1828 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
1829 return;
1830
1831 xfer->tx_done = true;
1832}
1833
1834static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1835{
1836 struct ath10k *ar = ce_state->ar;
1837 struct bmi_xfer *xfer;
1838 u32 ce_data;
1839 unsigned int nbytes;
1840 unsigned int transfer_id;
1841 unsigned int flags;
1842
1843 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1844 &nbytes, &transfer_id, &flags))
1845 return;
1846
1847 if (WARN_ON_ONCE(!xfer))
1848 return;
1849
1850 if (!xfer->wait_for_resp) {
1851 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1852 return;
1853 }
1854
1855 xfer->resp_len = nbytes;
1856 xfer->rx_done = true;
1857}
1858
1859static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1860 struct ath10k_ce_pipe *rx_pipe,
1861 struct bmi_xfer *xfer)
1862{
1863 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1864
1865 while (time_before_eq(jiffies, timeout)) {
1866 ath10k_pci_bmi_send_done(tx_pipe);
1867 ath10k_pci_bmi_recv_data(rx_pipe);
1868
1869 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1870 return 0;
1871
1872 schedule();
1873 }
1874
1875 return -ETIMEDOUT;
1876}
1877
1878/*
1879 * Send an interrupt to the device to wake up the Target CPU
1880 * so it has an opportunity to notice any changed state.
1881 */
1882static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1883{
1884 u32 addr, val;
1885
1886 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1887 val = ath10k_pci_read32(ar, addr);
1888 val |= CORE_CTRL_CPU_INTR_MASK;
1889 ath10k_pci_write32(ar, addr, val);
1890
1891 return 0;
1892}
1893
1894static int ath10k_pci_get_num_banks(struct ath10k *ar)
1895{
1896 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1897
1898 switch (ar_pci->pdev->device) {
1899 case QCA988X_2_0_DEVICE_ID:
1900 case QCA99X0_2_0_DEVICE_ID:
1901 return 1;
1902 case QCA6164_2_1_DEVICE_ID:
1903 case QCA6174_2_1_DEVICE_ID:
1904 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
1905 case QCA6174_HW_1_0_CHIP_ID_REV:
1906 case QCA6174_HW_1_1_CHIP_ID_REV:
1907 case QCA6174_HW_2_1_CHIP_ID_REV:
1908 case QCA6174_HW_2_2_CHIP_ID_REV:
1909 return 3;
1910 case QCA6174_HW_1_3_CHIP_ID_REV:
1911 return 2;
1912 case QCA6174_HW_3_0_CHIP_ID_REV:
1913 case QCA6174_HW_3_1_CHIP_ID_REV:
1914 case QCA6174_HW_3_2_CHIP_ID_REV:
1915 return 9;
1916 }
1917 break;
1918 case QCA9377_1_0_DEVICE_ID:
1919 return 2;
1920 }
1921
1922 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
1923 return 1;
1924}
1925
1926static int ath10k_bus_get_num_banks(struct ath10k *ar)
1927{
1928 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1929
1930 return ar_pci->bus_ops->get_num_banks(ar);
1931}
1932
1933int ath10k_pci_init_config(struct ath10k *ar)
1934{
1935 u32 interconnect_targ_addr;
1936 u32 pcie_state_targ_addr = 0;
1937 u32 pipe_cfg_targ_addr = 0;
1938 u32 svc_to_pipe_map = 0;
1939 u32 pcie_config_flags = 0;
1940 u32 ealloc_value;
1941 u32 ealloc_targ_addr;
1942 u32 flag2_value;
1943 u32 flag2_targ_addr;
1944 int ret = 0;
1945
1946 /* Download to Target the CE Config and the service-to-CE map */
1947 interconnect_targ_addr =
1948 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1949
1950 /* Supply Target-side CE configuration */
1951 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
1952 &pcie_state_targ_addr);
1953 if (ret != 0) {
1954 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1955 return ret;
1956 }
1957
1958 if (pcie_state_targ_addr == 0) {
1959 ret = -EIO;
1960 ath10k_err(ar, "Invalid pcie state addr\n");
1961 return ret;
1962 }
1963
1964 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1965 offsetof(struct pcie_state,
1966 pipe_cfg_addr)),
1967 &pipe_cfg_targ_addr);
1968 if (ret != 0) {
1969 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1970 return ret;
1971 }
1972
1973 if (pipe_cfg_targ_addr == 0) {
1974 ret = -EIO;
1975 ath10k_err(ar, "Invalid pipe cfg addr\n");
1976 return ret;
1977 }
1978
1979 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1980 target_ce_config_wlan,
1981 sizeof(struct ce_pipe_config) *
1982 NUM_TARGET_CE_CONFIG_WLAN);
1983
1984 if (ret != 0) {
1985 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1986 return ret;
1987 }
1988
1989 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1990 offsetof(struct pcie_state,
1991 svc_to_pipe_map)),
1992 &svc_to_pipe_map);
1993 if (ret != 0) {
1994 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1995 return ret;
1996 }
1997
1998 if (svc_to_pipe_map == 0) {
1999 ret = -EIO;
2000 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2001 return ret;
2002 }
2003
2004 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2005 target_service_to_ce_map_wlan,
2006 sizeof(target_service_to_ce_map_wlan));
2007 if (ret != 0) {
2008 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2009 return ret;
2010 }
2011
2012 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2013 offsetof(struct pcie_state,
2014 config_flags)),
2015 &pcie_config_flags);
2016 if (ret != 0) {
2017 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2018 return ret;
2019 }
2020
2021 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2022
2023 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2024 offsetof(struct pcie_state,
2025 config_flags)),
2026 pcie_config_flags);
2027 if (ret != 0) {
2028 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2029 return ret;
2030 }
2031
2032 /* configure early allocation */
2033 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2034
2035 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2036 if (ret != 0) {
2037 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
2038 return ret;
2039 }
2040
2041 /* first bank is switched to IRAM */
2042 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2043 HI_EARLY_ALLOC_MAGIC_MASK);
2044 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2045 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2046 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2047
2048 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2049 if (ret != 0) {
2050 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2051 return ret;
2052 }
2053
2054 /* Tell Target to proceed with initialization */
2055 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2056
2057 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2058 if (ret != 0) {
2059 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2060 return ret;
2061 }
2062
2063 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2064
2065 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2066 if (ret != 0) {
2067 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2068 return ret;
2069 }
2070
2071 return 0;
2072}
2073
2074static void ath10k_pci_override_ce_config(struct ath10k *ar)
2075{
2076 struct ce_attr *attr;
2077 struct ce_pipe_config *config;
2078
2079 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2080 * since it is currently used for other feature.
2081 */
2082
2083 /* Override Host's Copy Engine 5 configuration */
2084 attr = &host_ce_config_wlan[5];
2085 attr->src_sz_max = 0;
2086 attr->dest_nentries = 0;
2087
2088 /* Override Target firmware's Copy Engine configuration */
2089 config = &target_ce_config_wlan[5];
2090 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2091 config->nbytes_max = __cpu_to_le32(2048);
2092
2093 /* Map from service/endpoint to Copy Engine */
2094 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2095}
2096
2097int ath10k_pci_alloc_pipes(struct ath10k *ar)
2098{
2099 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2100 struct ath10k_pci_pipe *pipe;
2101 int i, ret;
2102
2103 for (i = 0; i < CE_COUNT; i++) {
2104 pipe = &ar_pci->pipe_info[i];
2105 pipe->ce_hdl = &ar_pci->ce_states[i];
2106 pipe->pipe_num = i;
2107 pipe->hif_ce_state = ar;
2108
2109 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2110 if (ret) {
2111 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2112 i, ret);
2113 return ret;
2114 }
2115
2116 /* Last CE is Diagnostic Window */
2117 if (i == CE_DIAG_PIPE) {
2118 ar_pci->ce_diag = pipe->ce_hdl;
2119 continue;
2120 }
2121
2122 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2123 }
2124
2125 return 0;
2126}
2127
2128void ath10k_pci_free_pipes(struct ath10k *ar)
2129{
2130 int i;
2131
2132 for (i = 0; i < CE_COUNT; i++)
2133 ath10k_ce_free_pipe(ar, i);
2134}
2135
2136int ath10k_pci_init_pipes(struct ath10k *ar)
2137{
2138 int i, ret;
2139
2140 for (i = 0; i < CE_COUNT; i++) {
2141 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2142 if (ret) {
2143 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2144 i, ret);
2145 return ret;
2146 }
2147 }
2148
2149 return 0;
2150}
2151
2152static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2153{
2154 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2155 FW_IND_EVENT_PENDING;
2156}
2157
2158static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2159{
2160 u32 val;
2161
2162 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2163 val &= ~FW_IND_EVENT_PENDING;
2164 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2165}
2166
2167/* this function effectively clears target memory controller assert line */
2168static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2169{
2170 u32 val;
2171
2172 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2173 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2174 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2175 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2176
2177 msleep(10);
2178
2179 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2180 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2181 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2182 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2183
2184 msleep(10);
2185}
2186
2187static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2188{
2189 u32 val;
2190
2191 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2192
2193 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2194 SOC_RESET_CONTROL_ADDRESS);
2195 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2196 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2197}
2198
2199static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2200{
2201 u32 val;
2202
2203 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2204 SOC_RESET_CONTROL_ADDRESS);
2205
2206 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2207 val | SOC_RESET_CONTROL_CE_RST_MASK);
2208 msleep(10);
2209 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2210 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2211}
2212
2213static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2214{
2215 u32 val;
2216
2217 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2218 SOC_LF_TIMER_CONTROL0_ADDRESS);
2219 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2220 SOC_LF_TIMER_CONTROL0_ADDRESS,
2221 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2222}
2223
2224static int ath10k_pci_warm_reset(struct ath10k *ar)
2225{
2226 int ret;
2227
2228 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2229
2230 spin_lock_bh(&ar->data_lock);
2231 ar->stats.fw_warm_reset_counter++;
2232 spin_unlock_bh(&ar->data_lock);
2233
2234 ath10k_pci_irq_disable(ar);
2235
2236 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2237 * were to access copy engine while host performs copy engine reset
2238 * then it is possible for the device to confuse pci-e controller to
2239 * the point of bringing host system to a complete stop (i.e. hang).
2240 */
2241 ath10k_pci_warm_reset_si0(ar);
2242 ath10k_pci_warm_reset_cpu(ar);
2243 ath10k_pci_init_pipes(ar);
2244 ath10k_pci_wait_for_target_init(ar);
2245
2246 ath10k_pci_warm_reset_clear_lf(ar);
2247 ath10k_pci_warm_reset_ce(ar);
2248 ath10k_pci_warm_reset_cpu(ar);
2249 ath10k_pci_init_pipes(ar);
2250
2251 ret = ath10k_pci_wait_for_target_init(ar);
2252 if (ret) {
2253 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2254 return ret;
2255 }
2256
2257 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2258
2259 return 0;
2260}
2261
2262static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2263{
2264 if (QCA_REV_988X(ar) || QCA_REV_6174(ar)) {
2265 return ath10k_pci_warm_reset(ar);
2266 } else if (QCA_REV_99X0(ar)) {
2267 ath10k_pci_irq_disable(ar);
2268 return ath10k_pci_qca99x0_chip_reset(ar);
2269 } else {
2270 return -ENOTSUPP;
2271 }
2272}
2273
2274static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2275{
2276 int i, ret;
2277 u32 val;
2278
2279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2280
2281 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2282 * It is thus preferred to use warm reset which is safer but may not be
2283 * able to recover the device from all possible fail scenarios.
2284 *
2285 * Warm reset doesn't always work on first try so attempt it a few
2286 * times before giving up.
2287 */
2288 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2289 ret = ath10k_pci_warm_reset(ar);
2290 if (ret) {
2291 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2292 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2293 ret);
2294 continue;
2295 }
2296
2297 /* FIXME: Sometimes copy engine doesn't recover after warm
2298 * reset. In most cases this needs cold reset. In some of these
2299 * cases the device is in such a state that a cold reset may
2300 * lock up the host.
2301 *
2302 * Reading any host interest register via copy engine is
2303 * sufficient to verify if device is capable of booting
2304 * firmware blob.
2305 */
2306 ret = ath10k_pci_init_pipes(ar);
2307 if (ret) {
2308 ath10k_warn(ar, "failed to init copy engine: %d\n",
2309 ret);
2310 continue;
2311 }
2312
2313 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2314 &val);
2315 if (ret) {
2316 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2317 ret);
2318 continue;
2319 }
2320
2321 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2322 return 0;
2323 }
2324
2325 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2326 ath10k_warn(ar, "refusing cold reset as requested\n");
2327 return -EPERM;
2328 }
2329
2330 ret = ath10k_pci_cold_reset(ar);
2331 if (ret) {
2332 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2333 return ret;
2334 }
2335
2336 ret = ath10k_pci_wait_for_target_init(ar);
2337 if (ret) {
2338 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2339 ret);
2340 return ret;
2341 }
2342
2343 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2344
2345 return 0;
2346}
2347
2348static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2349{
2350 int ret;
2351
2352 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2353
2354 /* FIXME: QCA6174 requires cold + warm reset to work. */
2355
2356 ret = ath10k_pci_cold_reset(ar);
2357 if (ret) {
2358 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2359 return ret;
2360 }
2361
2362 ret = ath10k_pci_wait_for_target_init(ar);
2363 if (ret) {
2364 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2365 ret);
2366 return ret;
2367 }
2368
2369 ret = ath10k_pci_warm_reset(ar);
2370 if (ret) {
2371 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2372 return ret;
2373 }
2374
2375 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2376
2377 return 0;
2378}
2379
2380static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2381{
2382 int ret;
2383
2384 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2385
2386 ret = ath10k_pci_cold_reset(ar);
2387 if (ret) {
2388 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2389 return ret;
2390 }
2391
2392 ret = ath10k_pci_wait_for_target_init(ar);
2393 if (ret) {
2394 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2395 ret);
2396 return ret;
2397 }
2398
2399 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2400
2401 return 0;
2402}
2403
2404static int ath10k_pci_chip_reset(struct ath10k *ar)
2405{
2406 if (QCA_REV_988X(ar))
2407 return ath10k_pci_qca988x_chip_reset(ar);
2408 else if (QCA_REV_6174(ar))
2409 return ath10k_pci_qca6174_chip_reset(ar);
2410 else if (QCA_REV_9377(ar))
2411 return ath10k_pci_qca6174_chip_reset(ar);
2412 else if (QCA_REV_99X0(ar))
2413 return ath10k_pci_qca99x0_chip_reset(ar);
2414 else
2415 return -ENOTSUPP;
2416}
2417
2418static int ath10k_pci_hif_power_up(struct ath10k *ar)
2419{
2420 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2421 int ret;
2422
2423 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2424
2425 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2426 &ar_pci->link_ctl);
2427 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2428 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2429
2430 /*
2431 * Bring the target up cleanly.
2432 *
2433 * The target may be in an undefined state with an AUX-powered Target
2434 * and a Host in WoW mode. If the Host crashes, loses power, or is
2435 * restarted (without unloading the driver) then the Target is left
2436 * (aux) powered and running. On a subsequent driver load, the Target
2437 * is in an unexpected state. We try to catch that here in order to
2438 * reset the Target and retry the probe.
2439 */
2440 ret = ath10k_pci_chip_reset(ar);
2441 if (ret) {
2442 if (ath10k_pci_has_fw_crashed(ar)) {
2443 ath10k_warn(ar, "firmware crashed during chip reset\n");
2444 ath10k_pci_fw_crashed_clear(ar);
2445 ath10k_pci_fw_crashed_dump(ar);
2446 }
2447
2448 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2449 goto err_sleep;
2450 }
2451
2452 ret = ath10k_pci_init_pipes(ar);
2453 if (ret) {
2454 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2455 goto err_sleep;
2456 }
2457
2458 ret = ath10k_pci_init_config(ar);
2459 if (ret) {
2460 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2461 goto err_ce;
2462 }
2463
2464 ret = ath10k_pci_wake_target_cpu(ar);
2465 if (ret) {
2466 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2467 goto err_ce;
2468 }
2469
2470 return 0;
2471
2472err_ce:
2473 ath10k_pci_ce_deinit(ar);
2474
2475err_sleep:
2476 return ret;
2477}
2478
2479void ath10k_pci_hif_power_down(struct ath10k *ar)
2480{
2481 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2482
2483 /* Currently hif_power_up performs effectively a reset and hif_stop
2484 * resets the chip as well so there's no point in resetting here.
2485 */
2486}
2487
2488#ifdef CONFIG_PM
2489
2490static int ath10k_pci_hif_suspend(struct ath10k *ar)
2491{
2492 /* The grace timer can still be counting down and ar->ps_awake be true.
2493 * It is known that the device may be asleep after resuming regardless
2494 * of the SoC powersave state before suspending. Hence make sure the
2495 * device is asleep before proceeding.
2496 */
2497 ath10k_pci_sleep_sync(ar);
2498
2499 return 0;
2500}
2501
2502static int ath10k_pci_hif_resume(struct ath10k *ar)
2503{
2504 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2505 struct pci_dev *pdev = ar_pci->pdev;
2506 u32 val;
2507 int ret = 0;
2508
2509 ret = ath10k_pci_force_wake(ar);
2510 if (ret) {
2511 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2512 return ret;
2513 }
2514
2515 /* Suspend/Resume resets the PCI configuration space, so we have to
2516 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2517 * from interfering with C3 CPU state. pci_restore_state won't help
2518 * here since it only restores the first 64 bytes pci config header.
2519 */
2520 pci_read_config_dword(pdev, 0x40, &val);
2521 if ((val & 0x0000ff00) != 0)
2522 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2523
2524 return ret;
2525}
2526#endif
2527
2528static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2529 .tx_sg = ath10k_pci_hif_tx_sg,
2530 .diag_read = ath10k_pci_hif_diag_read,
2531 .diag_write = ath10k_pci_diag_write_mem,
2532 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2533 .start = ath10k_pci_hif_start,
2534 .stop = ath10k_pci_hif_stop,
2535 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2536 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2537 .send_complete_check = ath10k_pci_hif_send_complete_check,
2538 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2539 .power_up = ath10k_pci_hif_power_up,
2540 .power_down = ath10k_pci_hif_power_down,
2541 .read32 = ath10k_pci_read32,
2542 .write32 = ath10k_pci_write32,
2543#ifdef CONFIG_PM
2544 .suspend = ath10k_pci_hif_suspend,
2545 .resume = ath10k_pci_hif_resume,
2546#endif
2547};
2548
2549static void ath10k_pci_ce_tasklet(unsigned long ptr)
2550{
2551 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2552 struct ath10k_pci *ar_pci = pipe->ar_pci;
2553
2554 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2555}
2556
2557static void ath10k_msi_err_tasklet(unsigned long data)
2558{
2559 struct ath10k *ar = (struct ath10k *)data;
2560
2561 if (!ath10k_pci_has_fw_crashed(ar)) {
2562 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
2563 return;
2564 }
2565
2566 ath10k_pci_irq_disable(ar);
2567 ath10k_pci_fw_crashed_clear(ar);
2568 ath10k_pci_fw_crashed_dump(ar);
2569}
2570
2571/*
2572 * Handler for a per-engine interrupt on a PARTICULAR CE.
2573 * This is used in cases where each CE has a private MSI interrupt.
2574 */
2575static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2576{
2577 struct ath10k *ar = arg;
2578 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2579 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2580
2581 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2582 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
2583 ce_id);
2584 return IRQ_HANDLED;
2585 }
2586
2587 /*
2588 * NOTE: We are able to derive ce_id from irq because we
2589 * use a one-to-one mapping for CE's 0..5.
2590 * CE's 6 & 7 do not use interrupts at all.
2591 *
2592 * This mapping must be kept in sync with the mapping
2593 * used by firmware.
2594 */
2595 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2596 return IRQ_HANDLED;
2597}
2598
2599static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2600{
2601 struct ath10k *ar = arg;
2602 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2603
2604 tasklet_schedule(&ar_pci->msi_fw_err);
2605 return IRQ_HANDLED;
2606}
2607
2608/*
2609 * Top-level interrupt handler for all PCI interrupts from a Target.
2610 * When a block of MSI interrupts is allocated, this top-level handler
2611 * is not used; instead, we directly call the correct sub-handler.
2612 */
2613static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2614{
2615 struct ath10k *ar = arg;
2616 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2617 int ret;
2618
2619 ret = ath10k_pci_force_wake(ar);
2620 if (ret) {
2621 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
2622 return IRQ_NONE;
2623 }
2624
2625 if (ar_pci->num_msi_intrs == 0) {
2626 if (!ath10k_pci_irq_pending(ar))
2627 return IRQ_NONE;
2628
2629 ath10k_pci_disable_and_clear_legacy_irq(ar);
2630 }
2631
2632 tasklet_schedule(&ar_pci->intr_tq);
2633
2634 return IRQ_HANDLED;
2635}
2636
2637static void ath10k_pci_tasklet(unsigned long data)
2638{
2639 struct ath10k *ar = (struct ath10k *)data;
2640 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2641
2642 if (ath10k_pci_has_fw_crashed(ar)) {
2643 ath10k_pci_irq_disable(ar);
2644 ath10k_pci_fw_crashed_clear(ar);
2645 ath10k_pci_fw_crashed_dump(ar);
2646 return;
2647 }
2648
2649 ath10k_ce_per_engine_service_any(ar);
2650
2651 /* Re-enable legacy irq that was disabled in the irq handler */
2652 if (ar_pci->num_msi_intrs == 0)
2653 ath10k_pci_enable_legacy_irq(ar);
2654}
2655
2656static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2657{
2658 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2659 int ret, i;
2660
2661 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2662 ath10k_pci_msi_fw_handler,
2663 IRQF_SHARED, "ath10k_pci", ar);
2664 if (ret) {
2665 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2666 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2667 return ret;
2668 }
2669
2670 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2671 ret = request_irq(ar_pci->pdev->irq + i,
2672 ath10k_pci_per_engine_handler,
2673 IRQF_SHARED, "ath10k_pci", ar);
2674 if (ret) {
2675 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2676 ar_pci->pdev->irq + i, ret);
2677
2678 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2679 free_irq(ar_pci->pdev->irq + i, ar);
2680
2681 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2682 return ret;
2683 }
2684 }
2685
2686 return 0;
2687}
2688
2689static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2690{
2691 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2692 int ret;
2693
2694 ret = request_irq(ar_pci->pdev->irq,
2695 ath10k_pci_interrupt_handler,
2696 IRQF_SHARED, "ath10k_pci", ar);
2697 if (ret) {
2698 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2699 ar_pci->pdev->irq, ret);
2700 return ret;
2701 }
2702
2703 return 0;
2704}
2705
2706static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2707{
2708 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2709 int ret;
2710
2711 ret = request_irq(ar_pci->pdev->irq,
2712 ath10k_pci_interrupt_handler,
2713 IRQF_SHARED, "ath10k_pci", ar);
2714 if (ret) {
2715 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2716 ar_pci->pdev->irq, ret);
2717 return ret;
2718 }
2719
2720 return 0;
2721}
2722
2723static int ath10k_pci_request_irq(struct ath10k *ar)
2724{
2725 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2726
2727 switch (ar_pci->num_msi_intrs) {
2728 case 0:
2729 return ath10k_pci_request_irq_legacy(ar);
2730 case 1:
2731 return ath10k_pci_request_irq_msi(ar);
2732 default:
2733 return ath10k_pci_request_irq_msix(ar);
2734 }
2735}
2736
2737static void ath10k_pci_free_irq(struct ath10k *ar)
2738{
2739 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2740 int i;
2741
2742 /* There's at least one interrupt irregardless whether its legacy INTR
2743 * or MSI or MSI-X */
2744 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2745 free_irq(ar_pci->pdev->irq + i, ar);
2746}
2747
2748void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2749{
2750 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2751 int i;
2752
2753 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2754 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2755 (unsigned long)ar);
2756
2757 for (i = 0; i < CE_COUNT; i++) {
2758 ar_pci->pipe_info[i].ar_pci = ar_pci;
2759 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2760 (unsigned long)&ar_pci->pipe_info[i]);
2761 }
2762}
2763
2764static int ath10k_pci_init_irq(struct ath10k *ar)
2765{
2766 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2767 int ret;
2768
2769 ath10k_pci_init_irq_tasklets(ar);
2770
2771 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2772 ath10k_info(ar, "limiting irq mode to: %d\n",
2773 ath10k_pci_irq_mode);
2774
2775 /* Try MSI-X */
2776 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2777 ar_pci->num_msi_intrs = MSI_ASSIGN_CE_MAX + 1;
2778 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2779 ar_pci->num_msi_intrs);
2780 if (ret > 0)
2781 return 0;
2782
2783 /* fall-through */
2784 }
2785
2786 /* Try MSI */
2787 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2788 ar_pci->num_msi_intrs = 1;
2789 ret = pci_enable_msi(ar_pci->pdev);
2790 if (ret == 0)
2791 return 0;
2792
2793 /* fall-through */
2794 }
2795
2796 /* Try legacy irq
2797 *
2798 * A potential race occurs here: The CORE_BASE write
2799 * depends on target correctly decoding AXI address but
2800 * host won't know when target writes BAR to CORE_CTRL.
2801 * This write might get lost if target has NOT written BAR.
2802 * For now, fix the race by repeating the write in below
2803 * synchronization checking. */
2804 ar_pci->num_msi_intrs = 0;
2805
2806 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2807 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2808
2809 return 0;
2810}
2811
2812static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2813{
2814 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2815 0);
2816}
2817
2818static int ath10k_pci_deinit_irq(struct ath10k *ar)
2819{
2820 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2821
2822 switch (ar_pci->num_msi_intrs) {
2823 case 0:
2824 ath10k_pci_deinit_irq_legacy(ar);
2825 break;
2826 default:
2827 pci_disable_msi(ar_pci->pdev);
2828 break;
2829 }
2830
2831 return 0;
2832}
2833
2834int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2835{
2836 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2837 unsigned long timeout;
2838 u32 val;
2839
2840 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2841
2842 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2843
2844 do {
2845 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2846
2847 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2848 val);
2849
2850 /* target should never return this */
2851 if (val == 0xffffffff)
2852 continue;
2853
2854 /* the device has crashed so don't bother trying anymore */
2855 if (val & FW_IND_EVENT_PENDING)
2856 break;
2857
2858 if (val & FW_IND_INITIALIZED)
2859 break;
2860
2861 if (ar_pci->num_msi_intrs == 0)
2862 /* Fix potential race by repeating CORE_BASE writes */
2863 ath10k_pci_enable_legacy_irq(ar);
2864
2865 mdelay(10);
2866 } while (time_before(jiffies, timeout));
2867
2868 ath10k_pci_disable_and_clear_legacy_irq(ar);
2869 ath10k_pci_irq_msi_fw_mask(ar);
2870
2871 if (val == 0xffffffff) {
2872 ath10k_err(ar, "failed to read device register, device is gone\n");
2873 return -EIO;
2874 }
2875
2876 if (val & FW_IND_EVENT_PENDING) {
2877 ath10k_warn(ar, "device has crashed during init\n");
2878 return -ECOMM;
2879 }
2880
2881 if (!(val & FW_IND_INITIALIZED)) {
2882 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2883 val);
2884 return -ETIMEDOUT;
2885 }
2886
2887 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2888 return 0;
2889}
2890
2891static int ath10k_pci_cold_reset(struct ath10k *ar)
2892{
2893 u32 val;
2894
2895 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2896
2897 spin_lock_bh(&ar->data_lock);
2898
2899 ar->stats.fw_cold_reset_counter++;
2900
2901 spin_unlock_bh(&ar->data_lock);
2902
2903 /* Put Target, including PCIe, into RESET. */
2904 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2905 val |= 1;
2906 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2907
2908 /* After writing into SOC_GLOBAL_RESET to put device into
2909 * reset and pulling out of reset pcie may not be stable
2910 * for any immediate pcie register access and cause bus error,
2911 * add delay before any pcie access request to fix this issue.
2912 */
2913 msleep(20);
2914
2915 /* Pull Target, including PCIe, out of RESET. */
2916 val &= ~1;
2917 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2918
2919 msleep(20);
2920
2921 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
2922
2923 return 0;
2924}
2925
2926static int ath10k_pci_claim(struct ath10k *ar)
2927{
2928 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2929 struct pci_dev *pdev = ar_pci->pdev;
2930 int ret;
2931
2932 pci_set_drvdata(pdev, ar);
2933
2934 ret = pci_enable_device(pdev);
2935 if (ret) {
2936 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2937 return ret;
2938 }
2939
2940 ret = pci_request_region(pdev, BAR_NUM, "ath");
2941 if (ret) {
2942 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2943 ret);
2944 goto err_device;
2945 }
2946
2947 /* Target expects 32 bit DMA. Enforce it. */
2948 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2949 if (ret) {
2950 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2951 goto err_region;
2952 }
2953
2954 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2955 if (ret) {
2956 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2957 ret);
2958 goto err_region;
2959 }
2960
2961 pci_set_master(pdev);
2962
2963 /* Arrange for access to Target SoC registers. */
2964 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
2965 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2966 if (!ar_pci->mem) {
2967 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2968 ret = -EIO;
2969 goto err_master;
2970 }
2971
2972 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2973 return 0;
2974
2975err_master:
2976 pci_clear_master(pdev);
2977
2978err_region:
2979 pci_release_region(pdev, BAR_NUM);
2980
2981err_device:
2982 pci_disable_device(pdev);
2983
2984 return ret;
2985}
2986
2987static void ath10k_pci_release(struct ath10k *ar)
2988{
2989 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2990 struct pci_dev *pdev = ar_pci->pdev;
2991
2992 pci_iounmap(pdev, ar_pci->mem);
2993 pci_release_region(pdev, BAR_NUM);
2994 pci_clear_master(pdev);
2995 pci_disable_device(pdev);
2996}
2997
2998static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
2999{
3000 const struct ath10k_pci_supp_chip *supp_chip;
3001 int i;
3002 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3003
3004 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3005 supp_chip = &ath10k_pci_supp_chips[i];
3006
3007 if (supp_chip->dev_id == dev_id &&
3008 supp_chip->rev_id == rev_id)
3009 return true;
3010 }
3011
3012 return false;
3013}
3014
3015int ath10k_pci_setup_resource(struct ath10k *ar)
3016{
3017 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3018 int ret;
3019
3020 spin_lock_init(&ar_pci->ce_lock);
3021 spin_lock_init(&ar_pci->ps_lock);
3022
3023 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
3024 (unsigned long)ar);
3025
3026 if (QCA_REV_6174(ar))
3027 ath10k_pci_override_ce_config(ar);
3028
3029 ret = ath10k_pci_alloc_pipes(ar);
3030 if (ret) {
3031 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3032 ret);
3033 return ret;
3034 }
3035
3036 return 0;
3037}
3038
3039void ath10k_pci_release_resource(struct ath10k *ar)
3040{
3041 ath10k_pci_kill_tasklet(ar);
3042 ath10k_pci_ce_deinit(ar);
3043 ath10k_pci_free_pipes(ar);
3044}
3045
3046static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3047 .read32 = ath10k_bus_pci_read32,
3048 .write32 = ath10k_bus_pci_write32,
3049 .get_num_banks = ath10k_pci_get_num_banks,
3050};
3051
3052static int ath10k_pci_probe(struct pci_dev *pdev,
3053 const struct pci_device_id *pci_dev)
3054{
3055 int ret = 0;
3056 struct ath10k *ar;
3057 struct ath10k_pci *ar_pci;
3058 enum ath10k_hw_rev hw_rev;
3059 u32 chip_id;
3060 bool pci_ps;
3061
3062 switch (pci_dev->device) {
3063 case QCA988X_2_0_DEVICE_ID:
3064 hw_rev = ATH10K_HW_QCA988X;
3065 pci_ps = false;
3066 break;
3067 case QCA6164_2_1_DEVICE_ID:
3068 case QCA6174_2_1_DEVICE_ID:
3069 hw_rev = ATH10K_HW_QCA6174;
3070 pci_ps = true;
3071 break;
3072 case QCA99X0_2_0_DEVICE_ID:
3073 hw_rev = ATH10K_HW_QCA99X0;
3074 pci_ps = false;
3075 break;
3076 case QCA9377_1_0_DEVICE_ID:
3077 hw_rev = ATH10K_HW_QCA9377;
3078 pci_ps = true;
3079 break;
3080 default:
3081 WARN_ON(1);
3082 return -ENOTSUPP;
3083 }
3084
3085 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3086 hw_rev, &ath10k_pci_hif_ops);
3087 if (!ar) {
3088 dev_err(&pdev->dev, "failed to allocate core\n");
3089 return -ENOMEM;
3090 }
3091
3092 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3093 pdev->vendor, pdev->device,
3094 pdev->subsystem_vendor, pdev->subsystem_device);
3095
3096 ar_pci = ath10k_pci_priv(ar);
3097 ar_pci->pdev = pdev;
3098 ar_pci->dev = &pdev->dev;
3099 ar_pci->ar = ar;
3100 ar->dev_id = pci_dev->device;
3101 ar_pci->pci_ps = pci_ps;
3102 ar_pci->bus_ops = &ath10k_pci_bus_ops;
3103
3104 ar->id.vendor = pdev->vendor;
3105 ar->id.device = pdev->device;
3106 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3107 ar->id.subsystem_device = pdev->subsystem_device;
3108
3109 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
3110 (unsigned long)ar);
3111
3112 ret = ath10k_pci_setup_resource(ar);
3113 if (ret) {
3114 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3115 goto err_core_destroy;
3116 }
3117
3118 ret = ath10k_pci_claim(ar);
3119 if (ret) {
3120 ath10k_err(ar, "failed to claim device: %d\n", ret);
3121 goto err_free_pipes;
3122 }
3123
3124 ret = ath10k_pci_force_wake(ar);
3125 if (ret) {
3126 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3127 goto err_sleep;
3128 }
3129
3130 ath10k_pci_ce_deinit(ar);
3131 ath10k_pci_irq_disable(ar);
3132
3133 ret = ath10k_pci_init_irq(ar);
3134 if (ret) {
3135 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3136 goto err_sleep;
3137 }
3138
3139 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
3140 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
3141 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3142
3143 ret = ath10k_pci_request_irq(ar);
3144 if (ret) {
3145 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3146 goto err_deinit_irq;
3147 }
3148
3149 ret = ath10k_pci_chip_reset(ar);
3150 if (ret) {
3151 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3152 goto err_free_irq;
3153 }
3154
3155 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3156 if (chip_id == 0xffffffff) {
3157 ath10k_err(ar, "failed to get chip id\n");
3158 goto err_free_irq;
3159 }
3160
3161 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3162 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3163 pdev->device, chip_id);
3164 goto err_free_irq;
3165 }
3166
3167 ret = ath10k_core_register(ar, chip_id);
3168 if (ret) {
3169 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3170 goto err_free_irq;
3171 }
3172
3173 return 0;
3174
3175err_free_irq:
3176 ath10k_pci_free_irq(ar);
3177 ath10k_pci_kill_tasklet(ar);
3178
3179err_deinit_irq:
3180 ath10k_pci_deinit_irq(ar);
3181
3182err_sleep:
3183 ath10k_pci_sleep_sync(ar);
3184 ath10k_pci_release(ar);
3185
3186err_free_pipes:
3187 ath10k_pci_free_pipes(ar);
3188
3189err_core_destroy:
3190 ath10k_core_destroy(ar);
3191
3192 return ret;
3193}
3194
3195static void ath10k_pci_remove(struct pci_dev *pdev)
3196{
3197 struct ath10k *ar = pci_get_drvdata(pdev);
3198 struct ath10k_pci *ar_pci;
3199
3200 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3201
3202 if (!ar)
3203 return;
3204
3205 ar_pci = ath10k_pci_priv(ar);
3206
3207 if (!ar_pci)
3208 return;
3209
3210 ath10k_core_unregister(ar);
3211 ath10k_pci_free_irq(ar);
3212 ath10k_pci_deinit_irq(ar);
3213 ath10k_pci_release_resource(ar);
3214 ath10k_pci_sleep_sync(ar);
3215 ath10k_pci_release(ar);
3216 ath10k_core_destroy(ar);
3217}
3218
3219MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3220
3221static struct pci_driver ath10k_pci_driver = {
3222 .name = "ath10k_pci",
3223 .id_table = ath10k_pci_id_table,
3224 .probe = ath10k_pci_probe,
3225 .remove = ath10k_pci_remove,
3226};
3227
3228static int __init ath10k_pci_init(void)
3229{
3230 int ret;
3231
3232 ret = pci_register_driver(&ath10k_pci_driver);
3233 if (ret)
3234 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3235 ret);
3236
3237 ret = ath10k_ahb_init();
3238 if (ret)
3239 printk(KERN_ERR "ahb init failed: %d\n", ret);
3240
3241 return ret;
3242}
3243module_init(ath10k_pci_init);
3244
3245static void __exit ath10k_pci_exit(void)
3246{
3247 pci_unregister_driver(&ath10k_pci_driver);
3248 ath10k_ahb_exit();
3249}
3250
3251module_exit(ath10k_pci_exit);
3252
3253MODULE_AUTHOR("Qualcomm Atheros");
3254MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
3255MODULE_LICENSE("Dual BSD/GPL");
3256
3257/* QCA988x 2.0 firmware files */
3258MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
3259MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3260MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3261MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3262MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3263MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3264MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3265
3266/* QCA6174 2.1 firmware files */
3267MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3268MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3269MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3270MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3271
3272/* QCA6174 3.1 firmware files */
3273MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3274MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3275MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3276MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3277
3278/* QCA9377 1.0 firmware files */
3279MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3280MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);