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1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2015-2017 Broadcom
3
4#include <linux/bitops.h>
5#include <linux/gpio/driver.h>
6#include <linux/of_device.h>
7#include <linux/of_irq.h>
8#include <linux/module.h>
9#include <linux/irqdomain.h>
10#include <linux/irqchip/chained_irq.h>
11#include <linux/interrupt.h>
12
13enum gio_reg_index {
14 GIO_REG_ODEN = 0,
15 GIO_REG_DATA,
16 GIO_REG_IODIR,
17 GIO_REG_EC,
18 GIO_REG_EI,
19 GIO_REG_MASK,
20 GIO_REG_LEVEL,
21 GIO_REG_STAT,
22 NUMBER_OF_GIO_REGISTERS
23};
24
25#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
26#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
27#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
28#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
29#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
30#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
31#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
32#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
33#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
34#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
35
36struct brcmstb_gpio_bank {
37 struct list_head node;
38 int id;
39 struct gpio_chip gc;
40 struct brcmstb_gpio_priv *parent_priv;
41 u32 width;
42 u32 wake_active;
43 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
44};
45
46struct brcmstb_gpio_priv {
47 struct list_head bank_list;
48 void __iomem *reg_base;
49 struct platform_device *pdev;
50 struct irq_domain *irq_domain;
51 struct irq_chip irq_chip;
52 int parent_irq;
53 int gpio_base;
54 int num_gpios;
55 int parent_wake_irq;
56};
57
58#define MAX_GPIO_PER_BANK 32
59#define GPIO_BANK(gpio) ((gpio) >> 5)
60/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
61#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
62
63static inline struct brcmstb_gpio_priv *
64brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
65{
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
67 return bank->parent_priv;
68}
69
70static unsigned long
71__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
72{
73 void __iomem *reg_base = bank->parent_priv->reg_base;
74
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
77}
78
79static unsigned long
80brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
81{
82 unsigned long status;
83 unsigned long flags;
84
85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
86 status = __brcmstb_gpio_get_active_irqs(bank);
87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
88
89 return status;
90}
91
92static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
93 struct brcmstb_gpio_bank *bank)
94{
95 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
96}
97
98static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
99 unsigned int hwirq, bool enable)
100{
101 struct gpio_chip *gc = &bank->gc;
102 struct brcmstb_gpio_priv *priv = bank->parent_priv;
103 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
104 u32 imask;
105 unsigned long flags;
106
107 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
109 if (enable)
110 imask |= mask;
111 else
112 imask &= ~mask;
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
114 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
115}
116
117static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
118{
119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
120 /* gc_offset is relative to this gpio_chip; want real offset */
121 int hwirq = offset + (gc->base - priv->gpio_base);
122
123 if (hwirq >= priv->num_gpios)
124 return -ENXIO;
125 return irq_create_mapping(priv->irq_domain, hwirq);
126}
127
128/* -------------------- IRQ chip functions -------------------- */
129
130static void brcmstb_gpio_irq_mask(struct irq_data *d)
131{
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
134
135 brcmstb_gpio_set_imask(bank, d->hwirq, false);
136}
137
138static void brcmstb_gpio_irq_unmask(struct irq_data *d)
139{
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
142
143 brcmstb_gpio_set_imask(bank, d->hwirq, true);
144}
145
146static void brcmstb_gpio_irq_ack(struct irq_data *d)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
150 struct brcmstb_gpio_priv *priv = bank->parent_priv;
151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
152
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
154}
155
156static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
157{
158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
162 u32 edge_insensitive, iedge_insensitive;
163 u32 edge_config, iedge_config;
164 u32 level, ilevel;
165 unsigned long flags;
166
167 switch (type) {
168 case IRQ_TYPE_LEVEL_LOW:
169 level = mask;
170 edge_config = 0;
171 edge_insensitive = 0;
172 break;
173 case IRQ_TYPE_LEVEL_HIGH:
174 level = mask;
175 edge_config = mask;
176 edge_insensitive = 0;
177 break;
178 case IRQ_TYPE_EDGE_FALLING:
179 level = 0;
180 edge_config = 0;
181 edge_insensitive = 0;
182 break;
183 case IRQ_TYPE_EDGE_RISING:
184 level = 0;
185 edge_config = mask;
186 edge_insensitive = 0;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 level = 0;
190 edge_config = 0; /* don't care, but want known value */
191 edge_insensitive = mask;
192 break;
193 default:
194 return -EINVAL;
195 }
196
197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
198
199 iedge_config = bank->gc.read_reg(priv->reg_base +
200 GIO_EC(bank->id)) & ~mask;
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
202 GIO_EI(bank->id)) & ~mask;
203 ilevel = bank->gc.read_reg(priv->reg_base +
204 GIO_LEVEL(bank->id)) & ~mask;
205
206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
207 iedge_config | edge_config);
208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
209 iedge_insensitive | edge_insensitive);
210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
211 ilevel | level);
212
213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
214 return 0;
215}
216
217static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
218 unsigned int enable)
219{
220 int ret = 0;
221
222 if (enable)
223 ret = enable_irq_wake(priv->parent_wake_irq);
224 else
225 ret = disable_irq_wake(priv->parent_wake_irq);
226 if (ret)
227 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
228 enable ? "enable" : "disable");
229 return ret;
230}
231
232static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
233{
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
236 struct brcmstb_gpio_priv *priv = bank->parent_priv;
237 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
238
239 /*
240 * Do not do anything specific for now, suspend/resume callbacks will
241 * configure the interrupt mask appropriately
242 */
243 if (enable)
244 bank->wake_active |= mask;
245 else
246 bank->wake_active &= ~mask;
247
248 return brcmstb_gpio_priv_set_wake(priv, enable);
249}
250
251static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
252{
253 struct brcmstb_gpio_priv *priv = data;
254
255 if (!priv || irq != priv->parent_wake_irq)
256 return IRQ_NONE;
257
258 /* Nothing to do */
259 return IRQ_HANDLED;
260}
261
262static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
263{
264 struct brcmstb_gpio_priv *priv = bank->parent_priv;
265 struct irq_domain *domain = priv->irq_domain;
266 int hwbase = bank->gc.base - priv->gpio_base;
267 unsigned long status;
268
269 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
270 unsigned int offset;
271
272 for_each_set_bit(offset, &status, 32) {
273 if (offset >= bank->width)
274 dev_warn(&priv->pdev->dev,
275 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
276 bank->id, offset);
277 generic_handle_domain_irq(domain, hwbase + offset);
278 }
279 }
280}
281
282/* Each UPG GIO block has one IRQ for all banks */
283static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
284{
285 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
286 struct irq_chip *chip = irq_desc_get_chip(desc);
287 struct brcmstb_gpio_bank *bank;
288
289 /* Interrupts weren't properly cleared during probe */
290 BUG_ON(!priv || !chip);
291
292 chained_irq_enter(chip, desc);
293 list_for_each_entry(bank, &priv->bank_list, node)
294 brcmstb_gpio_irq_bank_handler(bank);
295 chained_irq_exit(chip, desc);
296}
297
298static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
299 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
300{
301 struct brcmstb_gpio_bank *bank;
302 int i = 0;
303
304 /* banks are in descending order */
305 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
306 i += bank->gc.ngpio;
307 if (hwirq < i)
308 return bank;
309 }
310 return NULL;
311}
312
313/*
314 * This lock class tells lockdep that GPIO irqs are in a different
315 * category than their parents, so it won't report false recursion.
316 */
317static struct lock_class_key brcmstb_gpio_irq_lock_class;
318static struct lock_class_key brcmstb_gpio_irq_request_class;
319
320
321static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
322 irq_hw_number_t hwirq)
323{
324 struct brcmstb_gpio_priv *priv = d->host_data;
325 struct brcmstb_gpio_bank *bank =
326 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
327 struct platform_device *pdev = priv->pdev;
328 int ret;
329
330 if (!bank)
331 return -EINVAL;
332
333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
334 irq, (int)hwirq, bank->id);
335 ret = irq_set_chip_data(irq, &bank->gc);
336 if (ret < 0)
337 return ret;
338 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
339 &brcmstb_gpio_irq_request_class);
340 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
341 irq_set_noprobe(irq);
342 return 0;
343}
344
345static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
346{
347 irq_set_chip_and_handler(irq, NULL, NULL);
348 irq_set_chip_data(irq, NULL);
349}
350
351static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
352 .map = brcmstb_gpio_irq_map,
353 .unmap = brcmstb_gpio_irq_unmap,
354 .xlate = irq_domain_xlate_twocell,
355};
356
357/* Make sure that the number of banks matches up between properties */
358static int brcmstb_gpio_sanity_check_banks(struct device *dev,
359 struct device_node *np, struct resource *res)
360{
361 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
362 int num_banks =
363 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
364
365 if (res_num_banks != num_banks) {
366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
367 res_num_banks, num_banks);
368 return -EINVAL;
369 } else {
370 return 0;
371 }
372}
373
374static int brcmstb_gpio_remove(struct platform_device *pdev)
375{
376 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
377 struct brcmstb_gpio_bank *bank;
378 int offset, virq;
379
380 if (priv->parent_irq > 0)
381 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
382
383 /* Remove all IRQ mappings and delete the domain */
384 if (priv->irq_domain) {
385 for (offset = 0; offset < priv->num_gpios; offset++) {
386 virq = irq_find_mapping(priv->irq_domain, offset);
387 irq_dispose_mapping(virq);
388 }
389 irq_domain_remove(priv->irq_domain);
390 }
391
392 /*
393 * You can lose return values below, but we report all errors, and it's
394 * more important to actually perform all of the steps.
395 */
396 list_for_each_entry(bank, &priv->bank_list, node)
397 gpiochip_remove(&bank->gc);
398
399 return 0;
400}
401
402static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
403 const struct of_phandle_args *gpiospec, u32 *flags)
404{
405 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
406 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
407 int offset;
408
409 if (gc->of_gpio_n_cells != 2) {
410 WARN_ON(1);
411 return -EINVAL;
412 }
413
414 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
415 return -EINVAL;
416
417 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
418 if (offset >= gc->ngpio || offset < 0)
419 return -EINVAL;
420
421 if (unlikely(offset >= bank->width)) {
422 dev_warn_ratelimited(&priv->pdev->dev,
423 "Received request for invalid GPIO offset %d\n",
424 gpiospec->args[0]);
425 }
426
427 if (flags)
428 *flags = gpiospec->args[1];
429
430 return offset;
431}
432
433/* priv->parent_irq and priv->num_gpios must be set before calling */
434static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
435 struct brcmstb_gpio_priv *priv)
436{
437 struct device *dev = &pdev->dev;
438 struct device_node *np = dev->of_node;
439 int err;
440
441 priv->irq_domain =
442 irq_domain_add_linear(np, priv->num_gpios,
443 &brcmstb_gpio_irq_domain_ops,
444 priv);
445 if (!priv->irq_domain) {
446 dev_err(dev, "Couldn't allocate IRQ domain\n");
447 return -ENXIO;
448 }
449
450 if (of_property_read_bool(np, "wakeup-source")) {
451 priv->parent_wake_irq = platform_get_irq(pdev, 1);
452 if (priv->parent_wake_irq < 0) {
453 priv->parent_wake_irq = 0;
454 dev_warn(dev,
455 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
456 } else {
457 /*
458 * Set wakeup capability so we can process boot-time
459 * "wakeups" (e.g., from S5 cold boot)
460 */
461 device_set_wakeup_capable(dev, true);
462 device_wakeup_enable(dev);
463 err = devm_request_irq(dev, priv->parent_wake_irq,
464 brcmstb_gpio_wake_irq_handler,
465 IRQF_SHARED,
466 "brcmstb-gpio-wake", priv);
467
468 if (err < 0) {
469 dev_err(dev, "Couldn't request wake IRQ");
470 goto out_free_domain;
471 }
472 }
473 }
474
475 priv->irq_chip.name = dev_name(dev);
476 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
477 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
478 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
479 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
480 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
481
482 if (priv->parent_wake_irq)
483 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
484
485 irq_set_chained_handler_and_data(priv->parent_irq,
486 brcmstb_gpio_irq_handler, priv);
487 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
488
489 return 0;
490
491out_free_domain:
492 irq_domain_remove(priv->irq_domain);
493
494 return err;
495}
496
497static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
498 struct brcmstb_gpio_bank *bank)
499{
500 struct gpio_chip *gc = &bank->gc;
501 unsigned int i;
502
503 for (i = 0; i < GIO_REG_STAT; i++)
504 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
505 GIO_BANK_OFF(bank->id, i));
506}
507
508static void brcmstb_gpio_quiesce(struct device *dev, bool save)
509{
510 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
511 struct brcmstb_gpio_bank *bank;
512 struct gpio_chip *gc;
513 u32 imask;
514
515 /* disable non-wake interrupt */
516 if (priv->parent_irq >= 0)
517 disable_irq(priv->parent_irq);
518
519 list_for_each_entry(bank, &priv->bank_list, node) {
520 gc = &bank->gc;
521
522 if (save)
523 brcmstb_gpio_bank_save(priv, bank);
524
525 /* Unmask GPIOs which have been flagged as wake-up sources */
526 if (priv->parent_wake_irq)
527 imask = bank->wake_active;
528 else
529 imask = 0;
530 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
531 imask);
532 }
533}
534
535static void brcmstb_gpio_shutdown(struct platform_device *pdev)
536{
537 /* Enable GPIO for S5 cold boot */
538 brcmstb_gpio_quiesce(&pdev->dev, false);
539}
540
541#ifdef CONFIG_PM_SLEEP
542static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
543 struct brcmstb_gpio_bank *bank)
544{
545 struct gpio_chip *gc = &bank->gc;
546 unsigned int i;
547
548 for (i = 0; i < GIO_REG_STAT; i++)
549 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
550 bank->saved_regs[i]);
551}
552
553static int brcmstb_gpio_suspend(struct device *dev)
554{
555 brcmstb_gpio_quiesce(dev, true);
556 return 0;
557}
558
559static int brcmstb_gpio_resume(struct device *dev)
560{
561 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
562 struct brcmstb_gpio_bank *bank;
563 bool need_wakeup_event = false;
564
565 list_for_each_entry(bank, &priv->bank_list, node) {
566 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
567 brcmstb_gpio_bank_restore(priv, bank);
568 }
569
570 if (priv->parent_wake_irq && need_wakeup_event)
571 pm_wakeup_event(dev, 0);
572
573 /* enable non-wake interrupt */
574 if (priv->parent_irq >= 0)
575 enable_irq(priv->parent_irq);
576
577 return 0;
578}
579
580#else
581#define brcmstb_gpio_suspend NULL
582#define brcmstb_gpio_resume NULL
583#endif /* CONFIG_PM_SLEEP */
584
585static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
586 .suspend_noirq = brcmstb_gpio_suspend,
587 .resume_noirq = brcmstb_gpio_resume,
588};
589
590static int brcmstb_gpio_probe(struct platform_device *pdev)
591{
592 struct device *dev = &pdev->dev;
593 struct device_node *np = dev->of_node;
594 void __iomem *reg_base;
595 struct brcmstb_gpio_priv *priv;
596 struct resource *res;
597 struct property *prop;
598 const __be32 *p;
599 u32 bank_width;
600 int num_banks = 0;
601 int err;
602 static int gpio_base;
603 unsigned long flags = 0;
604 bool need_wakeup_event = false;
605
606 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
607 if (!priv)
608 return -ENOMEM;
609 platform_set_drvdata(pdev, priv);
610 INIT_LIST_HEAD(&priv->bank_list);
611
612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
613 reg_base = devm_ioremap_resource(dev, res);
614 if (IS_ERR(reg_base))
615 return PTR_ERR(reg_base);
616
617 priv->gpio_base = gpio_base;
618 priv->reg_base = reg_base;
619 priv->pdev = pdev;
620
621 if (of_property_read_bool(np, "interrupt-controller")) {
622 priv->parent_irq = platform_get_irq(pdev, 0);
623 if (priv->parent_irq <= 0)
624 return -ENOENT;
625 } else {
626 priv->parent_irq = -ENOENT;
627 }
628
629 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
630 return -EINVAL;
631
632 /*
633 * MIPS endianness is configured by boot strap, which also reverses all
634 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
635 * endian I/O).
636 *
637 * Other architectures (e.g., ARM) either do not support big endian, or
638 * else leave I/O in little endian mode.
639 */
640#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
641 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
642#endif
643
644 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
645 bank_width) {
646 struct brcmstb_gpio_bank *bank;
647 struct gpio_chip *gc;
648
649 /*
650 * If bank_width is 0, then there is an empty bank in the
651 * register block. Special handling for this case.
652 */
653 if (bank_width == 0) {
654 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
655 num_banks);
656 num_banks++;
657 gpio_base += MAX_GPIO_PER_BANK;
658 continue;
659 }
660
661 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
662 if (!bank) {
663 err = -ENOMEM;
664 goto fail;
665 }
666
667 bank->parent_priv = priv;
668 bank->id = num_banks;
669 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
670 dev_err(dev, "Invalid bank width %d\n", bank_width);
671 err = -EINVAL;
672 goto fail;
673 } else {
674 bank->width = bank_width;
675 }
676
677 /*
678 * Regs are 4 bytes wide, have data reg, no set/clear regs,
679 * and direction bits have 0 = output and 1 = input
680 */
681 gc = &bank->gc;
682 err = bgpio_init(gc, dev, 4,
683 reg_base + GIO_DATA(bank->id),
684 NULL, NULL, NULL,
685 reg_base + GIO_IODIR(bank->id), flags);
686 if (err) {
687 dev_err(dev, "bgpio_init() failed\n");
688 goto fail;
689 }
690
691 gc->owner = THIS_MODULE;
692 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
693 if (!gc->label) {
694 err = -ENOMEM;
695 goto fail;
696 }
697 gc->base = gpio_base;
698 gc->of_gpio_n_cells = 2;
699 gc->of_xlate = brcmstb_gpio_of_xlate;
700 /* not all ngpio lines are valid, will use bank width later */
701 gc->ngpio = MAX_GPIO_PER_BANK;
702 gc->offset = bank->id * MAX_GPIO_PER_BANK;
703 if (priv->parent_irq > 0)
704 gc->to_irq = brcmstb_gpio_to_irq;
705
706 /*
707 * Mask all interrupts by default, since wakeup interrupts may
708 * be retained from S5 cold boot
709 */
710 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
711 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
712
713 err = gpiochip_add_data(gc, bank);
714 if (err) {
715 dev_err(dev, "Could not add gpiochip for bank %d\n",
716 bank->id);
717 goto fail;
718 }
719 gpio_base += gc->ngpio;
720
721 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
722 gc->base, gc->ngpio, bank->width);
723
724 /* Everything looks good, so add bank to list */
725 list_add(&bank->node, &priv->bank_list);
726
727 num_banks++;
728 }
729
730 priv->num_gpios = gpio_base - priv->gpio_base;
731 if (priv->parent_irq > 0) {
732 err = brcmstb_gpio_irq_setup(pdev, priv);
733 if (err)
734 goto fail;
735 }
736
737 if (priv->parent_wake_irq && need_wakeup_event)
738 pm_wakeup_event(dev, 0);
739
740 return 0;
741
742fail:
743 (void) brcmstb_gpio_remove(pdev);
744 return err;
745}
746
747static const struct of_device_id brcmstb_gpio_of_match[] = {
748 { .compatible = "brcm,brcmstb-gpio" },
749 {},
750};
751
752MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
753
754static struct platform_driver brcmstb_gpio_driver = {
755 .driver = {
756 .name = "brcmstb-gpio",
757 .of_match_table = brcmstb_gpio_of_match,
758 .pm = &brcmstb_gpio_pm_ops,
759 },
760 .probe = brcmstb_gpio_probe,
761 .remove = brcmstb_gpio_remove,
762 .shutdown = brcmstb_gpio_shutdown,
763};
764module_platform_driver(brcmstb_gpio_driver);
765
766MODULE_AUTHOR("Gregory Fong");
767MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
768MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/gpio/driver.h>
16#include <linux/of_device.h>
17#include <linux/of_irq.h>
18#include <linux/module.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/interrupt.h>
22#include <linux/reboot.h>
23
24#define GIO_BANK_SIZE 0x20
25#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
26#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
27#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
28#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
29#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
30#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
31#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
32#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
33
34struct brcmstb_gpio_bank {
35 struct list_head node;
36 int id;
37 struct gpio_chip gc;
38 struct brcmstb_gpio_priv *parent_priv;
39 u32 width;
40 struct irq_chip irq_chip;
41};
42
43struct brcmstb_gpio_priv {
44 struct list_head bank_list;
45 void __iomem *reg_base;
46 struct platform_device *pdev;
47 int parent_irq;
48 int gpio_base;
49 bool can_wake;
50 int parent_wake_irq;
51 struct notifier_block reboot_notifier;
52};
53
54#define MAX_GPIO_PER_BANK 32
55#define GPIO_BANK(gpio) ((gpio) >> 5)
56/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
57#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
58
59static inline struct brcmstb_gpio_priv *
60brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
61{
62 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
63 return bank->parent_priv;
64}
65
66static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
67 unsigned int offset, bool enable)
68{
69 struct gpio_chip *gc = &bank->gc;
70 struct brcmstb_gpio_priv *priv = bank->parent_priv;
71 u32 mask = gc->pin2mask(gc, offset);
72 u32 imask;
73 unsigned long flags;
74
75 spin_lock_irqsave(&gc->bgpio_lock, flags);
76 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
77 if (enable)
78 imask |= mask;
79 else
80 imask &= ~mask;
81 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
82 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
83}
84
85/* -------------------- IRQ chip functions -------------------- */
86
87static void brcmstb_gpio_irq_mask(struct irq_data *d)
88{
89 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
90 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
91
92 brcmstb_gpio_set_imask(bank, d->hwirq, false);
93}
94
95static void brcmstb_gpio_irq_unmask(struct irq_data *d)
96{
97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
98 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
99
100 brcmstb_gpio_set_imask(bank, d->hwirq, true);
101}
102
103static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
104{
105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
107 struct brcmstb_gpio_priv *priv = bank->parent_priv;
108 u32 mask = BIT(d->hwirq);
109 u32 edge_insensitive, iedge_insensitive;
110 u32 edge_config, iedge_config;
111 u32 level, ilevel;
112 unsigned long flags;
113
114 switch (type) {
115 case IRQ_TYPE_LEVEL_LOW:
116 level = 0;
117 edge_config = 0;
118 edge_insensitive = 0;
119 break;
120 case IRQ_TYPE_LEVEL_HIGH:
121 level = mask;
122 edge_config = 0;
123 edge_insensitive = 0;
124 break;
125 case IRQ_TYPE_EDGE_FALLING:
126 level = 0;
127 edge_config = 0;
128 edge_insensitive = 0;
129 break;
130 case IRQ_TYPE_EDGE_RISING:
131 level = 0;
132 edge_config = mask;
133 edge_insensitive = 0;
134 break;
135 case IRQ_TYPE_EDGE_BOTH:
136 level = 0;
137 edge_config = 0; /* don't care, but want known value */
138 edge_insensitive = mask;
139 break;
140 default:
141 return -EINVAL;
142 }
143
144 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
145
146 iedge_config = bank->gc.read_reg(priv->reg_base +
147 GIO_EC(bank->id)) & ~mask;
148 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
149 GIO_EI(bank->id)) & ~mask;
150 ilevel = bank->gc.read_reg(priv->reg_base +
151 GIO_LEVEL(bank->id)) & ~mask;
152
153 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
154 iedge_config | edge_config);
155 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
156 iedge_insensitive | edge_insensitive);
157 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
158 ilevel | level);
159
160 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
161 return 0;
162}
163
164static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
165 unsigned int enable)
166{
167 int ret = 0;
168
169 /*
170 * Only enable wake IRQ once for however many hwirqs can wake
171 * since they all use the same wake IRQ. Mask will be set
172 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
173 */
174 if (enable)
175 ret = enable_irq_wake(priv->parent_wake_irq);
176 else
177 ret = disable_irq_wake(priv->parent_wake_irq);
178 if (ret)
179 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
180 enable ? "enable" : "disable");
181 return ret;
182}
183
184static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
185{
186 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
187 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
188
189 return brcmstb_gpio_priv_set_wake(priv, enable);
190}
191
192static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
193{
194 struct brcmstb_gpio_priv *priv = data;
195
196 if (!priv || irq != priv->parent_wake_irq)
197 return IRQ_NONE;
198 pm_wakeup_event(&priv->pdev->dev, 0);
199 return IRQ_HANDLED;
200}
201
202static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
203{
204 struct brcmstb_gpio_priv *priv = bank->parent_priv;
205 struct irq_domain *irq_domain = bank->gc.irqdomain;
206 void __iomem *reg_base = priv->reg_base;
207 unsigned long status;
208 unsigned long flags;
209
210 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
211 while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
212 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
213 int bit;
214
215 for_each_set_bit(bit, &status, 32) {
216 u32 stat = bank->gc.read_reg(reg_base +
217 GIO_STAT(bank->id));
218 if (bit >= bank->width)
219 dev_warn(&priv->pdev->dev,
220 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
221 bank->id, bit);
222 bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
223 stat | BIT(bit));
224 generic_handle_irq(irq_find_mapping(irq_domain, bit));
225 }
226 }
227 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
228}
229
230/* Each UPG GIO block has one IRQ for all banks */
231static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
232{
233 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
234 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
235 struct irq_chip *chip = irq_desc_get_chip(desc);
236 struct brcmstb_gpio_bank *bank;
237
238 /* Interrupts weren't properly cleared during probe */
239 BUG_ON(!priv || !chip);
240
241 chained_irq_enter(chip, desc);
242 list_for_each_entry(bank, &priv->bank_list, node)
243 brcmstb_gpio_irq_bank_handler(bank);
244 chained_irq_exit(chip, desc);
245}
246
247static int brcmstb_gpio_reboot(struct notifier_block *nb,
248 unsigned long action, void *data)
249{
250 struct brcmstb_gpio_priv *priv =
251 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
252
253 /* Enable GPIO for S5 cold boot */
254 if (action == SYS_POWER_OFF)
255 brcmstb_gpio_priv_set_wake(priv, 1);
256
257 return NOTIFY_DONE;
258}
259
260/* Make sure that the number of banks matches up between properties */
261static int brcmstb_gpio_sanity_check_banks(struct device *dev,
262 struct device_node *np, struct resource *res)
263{
264 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
265 int num_banks =
266 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
267
268 if (res_num_banks != num_banks) {
269 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
270 res_num_banks, num_banks);
271 return -EINVAL;
272 } else {
273 return 0;
274 }
275}
276
277static int brcmstb_gpio_remove(struct platform_device *pdev)
278{
279 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
280 struct brcmstb_gpio_bank *bank;
281 int ret = 0;
282
283 if (!priv) {
284 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
285 return -EFAULT;
286 }
287
288 /*
289 * You can lose return values below, but we report all errors, and it's
290 * more important to actually perform all of the steps.
291 */
292 list_for_each_entry(bank, &priv->bank_list, node)
293 gpiochip_remove(&bank->gc);
294
295 if (priv->reboot_notifier.notifier_call) {
296 ret = unregister_reboot_notifier(&priv->reboot_notifier);
297 if (ret)
298 dev_err(&pdev->dev,
299 "failed to unregister reboot notifier\n");
300 }
301 return ret;
302}
303
304static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
305 const struct of_phandle_args *gpiospec, u32 *flags)
306{
307 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
308 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
309 int offset;
310
311 if (gc->of_gpio_n_cells != 2) {
312 WARN_ON(1);
313 return -EINVAL;
314 }
315
316 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
317 return -EINVAL;
318
319 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
320 if (offset >= gc->ngpio || offset < 0)
321 return -EINVAL;
322
323 if (unlikely(offset >= bank->width)) {
324 dev_warn_ratelimited(&priv->pdev->dev,
325 "Received request for invalid GPIO offset %d\n",
326 gpiospec->args[0]);
327 }
328
329 if (flags)
330 *flags = gpiospec->args[1];
331
332 return offset;
333}
334
335/* Before calling, must have bank->parent_irq set and gpiochip registered */
336static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
337 struct brcmstb_gpio_bank *bank)
338{
339 struct brcmstb_gpio_priv *priv = bank->parent_priv;
340 struct device *dev = &pdev->dev;
341 struct device_node *np = dev->of_node;
342
343 bank->irq_chip.name = dev_name(dev);
344 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
345 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
346 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
347
348 /* Ensures that all non-wakeup IRQs are disabled at suspend */
349 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
350
351 if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
352 of_property_read_bool(np, "wakeup-source")) {
353 priv->parent_wake_irq = platform_get_irq(pdev, 1);
354 if (priv->parent_wake_irq < 0) {
355 dev_warn(dev,
356 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
357 } else {
358 int err;
359
360 /*
361 * Set wakeup capability before requesting wakeup
362 * interrupt, so we can process boot-time "wakeups"
363 * (e.g., from S5 cold boot)
364 */
365 device_set_wakeup_capable(dev, true);
366 device_wakeup_enable(dev);
367 err = devm_request_irq(dev, priv->parent_wake_irq,
368 brcmstb_gpio_wake_irq_handler, 0,
369 "brcmstb-gpio-wake", priv);
370
371 if (err < 0) {
372 dev_err(dev, "Couldn't request wake IRQ");
373 return err;
374 }
375
376 priv->reboot_notifier.notifier_call =
377 brcmstb_gpio_reboot;
378 register_reboot_notifier(&priv->reboot_notifier);
379 priv->can_wake = true;
380 }
381 }
382
383 if (priv->can_wake)
384 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
385
386 gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
387 handle_simple_irq, IRQ_TYPE_NONE);
388 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
389 priv->parent_irq, brcmstb_gpio_irq_handler);
390
391 return 0;
392}
393
394static int brcmstb_gpio_probe(struct platform_device *pdev)
395{
396 struct device *dev = &pdev->dev;
397 struct device_node *np = dev->of_node;
398 void __iomem *reg_base;
399 struct brcmstb_gpio_priv *priv;
400 struct resource *res;
401 struct property *prop;
402 const __be32 *p;
403 u32 bank_width;
404 int num_banks = 0;
405 int err;
406 static int gpio_base;
407 unsigned long flags = 0;
408
409 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
410 if (!priv)
411 return -ENOMEM;
412 platform_set_drvdata(pdev, priv);
413 INIT_LIST_HEAD(&priv->bank_list);
414
415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
416 reg_base = devm_ioremap_resource(dev, res);
417 if (IS_ERR(reg_base))
418 return PTR_ERR(reg_base);
419
420 priv->gpio_base = gpio_base;
421 priv->reg_base = reg_base;
422 priv->pdev = pdev;
423
424 if (of_property_read_bool(np, "interrupt-controller")) {
425 priv->parent_irq = platform_get_irq(pdev, 0);
426 if (priv->parent_irq <= 0) {
427 dev_err(dev, "Couldn't get IRQ");
428 return -ENOENT;
429 }
430 } else {
431 priv->parent_irq = -ENOENT;
432 }
433
434 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
435 return -EINVAL;
436
437 /*
438 * MIPS endianness is configured by boot strap, which also reverses all
439 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
440 * endian I/O).
441 *
442 * Other architectures (e.g., ARM) either do not support big endian, or
443 * else leave I/O in little endian mode.
444 */
445#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
446 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
447#endif
448
449 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
450 bank_width) {
451 struct brcmstb_gpio_bank *bank;
452 struct gpio_chip *gc;
453
454 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
455 if (!bank) {
456 err = -ENOMEM;
457 goto fail;
458 }
459
460 bank->parent_priv = priv;
461 bank->id = num_banks;
462 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
463 dev_err(dev, "Invalid bank width %d\n", bank_width);
464 goto fail;
465 } else {
466 bank->width = bank_width;
467 }
468
469 /*
470 * Regs are 4 bytes wide, have data reg, no set/clear regs,
471 * and direction bits have 0 = output and 1 = input
472 */
473 gc = &bank->gc;
474 err = bgpio_init(gc, dev, 4,
475 reg_base + GIO_DATA(bank->id),
476 NULL, NULL, NULL,
477 reg_base + GIO_IODIR(bank->id), flags);
478 if (err) {
479 dev_err(dev, "bgpio_init() failed\n");
480 goto fail;
481 }
482
483 gc->of_node = np;
484 gc->owner = THIS_MODULE;
485 gc->label = np->full_name;
486 gc->base = gpio_base;
487 gc->of_gpio_n_cells = 2;
488 gc->of_xlate = brcmstb_gpio_of_xlate;
489 /* not all ngpio lines are valid, will use bank width later */
490 gc->ngpio = MAX_GPIO_PER_BANK;
491
492 /*
493 * Mask all interrupts by default, since wakeup interrupts may
494 * be retained from S5 cold boot
495 */
496 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
497
498 err = gpiochip_add_data(gc, bank);
499 if (err) {
500 dev_err(dev, "Could not add gpiochip for bank %d\n",
501 bank->id);
502 goto fail;
503 }
504 gpio_base += gc->ngpio;
505
506 if (priv->parent_irq > 0) {
507 err = brcmstb_gpio_irq_setup(pdev, bank);
508 if (err)
509 goto fail;
510 }
511
512 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
513 gc->base, gc->ngpio, bank->width);
514
515 /* Everything looks good, so add bank to list */
516 list_add(&bank->node, &priv->bank_list);
517
518 num_banks++;
519 }
520
521 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
522 num_banks, priv->gpio_base, gpio_base - 1);
523
524 return 0;
525
526fail:
527 (void) brcmstb_gpio_remove(pdev);
528 return err;
529}
530
531static const struct of_device_id brcmstb_gpio_of_match[] = {
532 { .compatible = "brcm,brcmstb-gpio" },
533 {},
534};
535
536MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
537
538static struct platform_driver brcmstb_gpio_driver = {
539 .driver = {
540 .name = "brcmstb-gpio",
541 .of_match_table = brcmstb_gpio_of_match,
542 },
543 .probe = brcmstb_gpio_probe,
544 .remove = brcmstb_gpio_remove,
545};
546module_platform_driver(brcmstb_gpio_driver);
547
548MODULE_AUTHOR("Gregory Fong");
549MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
550MODULE_LICENSE("GPL v2");