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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-IDI-48 family
4 * Copyright (C) 2015 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
8 */
9#include <linux/bits.h>
10#include <linux/device.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/interrupt.h>
16#include <linux/irqdesc.h>
17#include <linux/isa.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/spinlock.h>
22#include <linux/types.h>
23
24#include "gpio-i8255.h"
25
26MODULE_IMPORT_NS(I8255);
27
28#define IDI_48_EXTENT 8
29#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
30
31static unsigned int base[MAX_NUM_IDI_48];
32static unsigned int num_idi_48;
33module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
34MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
35
36static unsigned int irq[MAX_NUM_IDI_48];
37static unsigned int num_irq;
38module_param_hw_array(irq, uint, irq, &num_irq, 0);
39MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
40
41/**
42 * struct idi_48_reg - device register structure
43 * @port0: Port 0 Inputs
44 * @unused: Unused
45 * @port1: Port 1 Inputs
46 * @irq: Read: IRQ Status Register/IRQ Clear
47 * Write: IRQ Enable/Disable
48 */
49struct idi_48_reg {
50 u8 port0[3];
51 u8 unused;
52 u8 port1[3];
53 u8 irq;
54};
55
56/**
57 * struct idi_48_gpio - GPIO device private data structure
58 * @chip: instance of the gpio_chip
59 * @lock: synchronization lock to prevent I/O race conditions
60 * @irq_mask: input bits affected by interrupts
61 * @reg: I/O address offset for the device registers
62 * @cos_enb: Change-Of-State IRQ enable boundaries mask
63 */
64struct idi_48_gpio {
65 struct gpio_chip chip;
66 spinlock_t lock;
67 unsigned char irq_mask[6];
68 struct idi_48_reg __iomem *reg;
69 unsigned char cos_enb;
70};
71
72static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
73{
74 return GPIO_LINE_DIRECTION_IN;
75}
76
77static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
78{
79 return 0;
80}
81
82static int idi_48_gpio_get(struct gpio_chip *chip, unsigned int offset)
83{
84 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
85 void __iomem *const ppi = idi48gpio->reg;
86
87 return i8255_get(ppi, offset);
88}
89
90static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
91 unsigned long *bits)
92{
93 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
94 void __iomem *const ppi = idi48gpio->reg;
95
96 i8255_get_multiple(ppi, mask, bits, chip->ngpio);
97
98 return 0;
99}
100
101static void idi_48_irq_ack(struct irq_data *data)
102{
103}
104
105static void idi_48_irq_mask(struct irq_data *data)
106{
107 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
108 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
109 const unsigned int offset = irqd_to_hwirq(data);
110 const unsigned long boundary = offset / 8;
111 const unsigned long mask = BIT(offset % 8);
112 unsigned long flags;
113
114 spin_lock_irqsave(&idi48gpio->lock, flags);
115
116 idi48gpio->irq_mask[boundary] &= ~mask;
117 gpiochip_disable_irq(chip, offset);
118
119 /* Exit early if there are still input lines with IRQ unmasked */
120 if (idi48gpio->irq_mask[boundary])
121 goto exit;
122
123 idi48gpio->cos_enb &= ~BIT(boundary);
124
125 iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
126
127exit:
128 spin_unlock_irqrestore(&idi48gpio->lock, flags);
129}
130
131static void idi_48_irq_unmask(struct irq_data *data)
132{
133 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
134 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
135 const unsigned int offset = irqd_to_hwirq(data);
136 const unsigned long boundary = offset / 8;
137 const unsigned long mask = BIT(offset % 8);
138 unsigned int prev_irq_mask;
139 unsigned long flags;
140
141 spin_lock_irqsave(&idi48gpio->lock, flags);
142
143 prev_irq_mask = idi48gpio->irq_mask[boundary];
144
145 gpiochip_enable_irq(chip, offset);
146 idi48gpio->irq_mask[boundary] |= mask;
147
148 /* Exit early if IRQ was already unmasked for this boundary */
149 if (prev_irq_mask)
150 goto exit;
151
152 idi48gpio->cos_enb |= BIT(boundary);
153
154 iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
155
156exit:
157 spin_unlock_irqrestore(&idi48gpio->lock, flags);
158}
159
160static int idi_48_irq_set_type(struct irq_data *data, unsigned int flow_type)
161{
162 /* The only valid irq types are none and both-edges */
163 if (flow_type != IRQ_TYPE_NONE &&
164 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
165 return -EINVAL;
166
167 return 0;
168}
169
170static const struct irq_chip idi_48_irqchip = {
171 .name = "104-idi-48",
172 .irq_ack = idi_48_irq_ack,
173 .irq_mask = idi_48_irq_mask,
174 .irq_unmask = idi_48_irq_unmask,
175 .irq_set_type = idi_48_irq_set_type,
176 .flags = IRQCHIP_IMMUTABLE,
177 GPIOCHIP_IRQ_RESOURCE_HELPERS,
178};
179
180static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
181{
182 struct idi_48_gpio *const idi48gpio = dev_id;
183 unsigned long cos_status;
184 unsigned long boundary;
185 unsigned long irq_mask;
186 unsigned long bit_num;
187 unsigned long gpio;
188 struct gpio_chip *const chip = &idi48gpio->chip;
189
190 spin_lock(&idi48gpio->lock);
191
192 cos_status = ioread8(&idi48gpio->reg->irq);
193
194 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
195 if (cos_status & BIT(6)) {
196 spin_unlock(&idi48gpio->lock);
197 return IRQ_NONE;
198 }
199
200 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
201 cos_status &= 0x3F;
202
203 for_each_set_bit(boundary, &cos_status, 6) {
204 irq_mask = idi48gpio->irq_mask[boundary];
205
206 for_each_set_bit(bit_num, &irq_mask, 8) {
207 gpio = bit_num + boundary * 8;
208
209 generic_handle_domain_irq(chip->irq.domain,
210 gpio);
211 }
212 }
213
214 spin_unlock(&idi48gpio->lock);
215
216 return IRQ_HANDLED;
217}
218
219#define IDI48_NGPIO 48
220static const char *idi48_names[IDI48_NGPIO] = {
221 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
222 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
223 "Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
224 "Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
225 "Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
226 "Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
227 "Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
228 "Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
229};
230
231static int idi_48_irq_init_hw(struct gpio_chip *gc)
232{
233 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
234
235 /* Disable IRQ by default */
236 iowrite8(0, &idi48gpio->reg->irq);
237 ioread8(&idi48gpio->reg->irq);
238
239 return 0;
240}
241
242static int idi_48_probe(struct device *dev, unsigned int id)
243{
244 struct idi_48_gpio *idi48gpio;
245 const char *const name = dev_name(dev);
246 struct gpio_irq_chip *girq;
247 int err;
248
249 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
250 if (!idi48gpio)
251 return -ENOMEM;
252
253 if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
254 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
255 base[id], base[id] + IDI_48_EXTENT);
256 return -EBUSY;
257 }
258
259 idi48gpio->reg = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
260 if (!idi48gpio->reg)
261 return -ENOMEM;
262
263 idi48gpio->chip.label = name;
264 idi48gpio->chip.parent = dev;
265 idi48gpio->chip.owner = THIS_MODULE;
266 idi48gpio->chip.base = -1;
267 idi48gpio->chip.ngpio = IDI48_NGPIO;
268 idi48gpio->chip.names = idi48_names;
269 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
270 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
271 idi48gpio->chip.get = idi_48_gpio_get;
272 idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
273
274 girq = &idi48gpio->chip.irq;
275 gpio_irq_chip_set_chip(girq, &idi_48_irqchip);
276 /* This will let us handle the parent IRQ in the driver */
277 girq->parent_handler = NULL;
278 girq->num_parents = 0;
279 girq->parents = NULL;
280 girq->default_type = IRQ_TYPE_NONE;
281 girq->handler = handle_edge_irq;
282 girq->init_hw = idi_48_irq_init_hw;
283
284 spin_lock_init(&idi48gpio->lock);
285
286 err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
287 if (err) {
288 dev_err(dev, "GPIO registering failed (%d)\n", err);
289 return err;
290 }
291
292 err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
293 name, idi48gpio);
294 if (err) {
295 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
296 return err;
297 }
298
299 return 0;
300}
301
302static struct isa_driver idi_48_driver = {
303 .probe = idi_48_probe,
304 .driver = {
305 .name = "104-idi-48"
306 },
307};
308module_isa_driver_with_irq(idi_48_driver, num_idi_48, num_irq);
309
310MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
311MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
312MODULE_LICENSE("GPL v2");
1/*
2 * GPIO driver for the ACCES 104-IDI-48 family
3 * Copyright (C) 2015 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitops.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/irqdesc.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27
28static unsigned idi_48_base;
29module_param(idi_48_base, uint, 0);
30MODULE_PARM_DESC(idi_48_base, "ACCES 104-IDI-48 base address");
31static unsigned idi_48_irq;
32module_param(idi_48_irq, uint, 0);
33MODULE_PARM_DESC(idi_48_irq, "ACCES 104-IDI-48 interrupt line number");
34
35/**
36 * struct idi_48_gpio - GPIO device private data structure
37 * @chip: instance of the gpio_chip
38 * @lock: synchronization lock to prevent I/O race conditions
39 * @ack_lock: synchronization lock to prevent IRQ handler race conditions
40 * @irq_mask: input bits affected by interrupts
41 * @base: base port address of the GPIO device
42 * @irq: Interrupt line number
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
44 */
45struct idi_48_gpio {
46 struct gpio_chip chip;
47 spinlock_t lock;
48 spinlock_t ack_lock;
49 unsigned char irq_mask[6];
50 unsigned base;
51 unsigned irq;
52 unsigned char cos_enb;
53};
54
55static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
56{
57 return 1;
58}
59
60static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
61{
62 return 0;
63}
64
65static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
66{
67 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
68 unsigned i;
69 const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
70 unsigned base_offset;
71 unsigned mask;
72
73 for (i = 0; i < 48; i += 8)
74 if (offset < i + 8) {
75 base_offset = register_offset[i / 8];
76 mask = BIT(offset - i);
77
78 return !!(inb(idi48gpio->base + base_offset) & mask);
79 }
80
81 /* The following line should never execute since offset < 48 */
82 return 0;
83}
84
85static void idi_48_irq_ack(struct irq_data *data)
86{
87}
88
89static void idi_48_irq_mask(struct irq_data *data)
90{
91 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
92 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
93 const unsigned offset = irqd_to_hwirq(data);
94 unsigned i;
95 unsigned mask;
96 unsigned boundary;
97 unsigned long flags;
98
99 for (i = 0; i < 48; i += 8)
100 if (offset < i + 8) {
101 mask = BIT(offset - i);
102 boundary = i / 8;
103
104 idi48gpio->irq_mask[boundary] &= ~mask;
105
106 if (!idi48gpio->irq_mask[boundary]) {
107 idi48gpio->cos_enb &= ~BIT(boundary);
108
109 spin_lock_irqsave(&idi48gpio->lock, flags);
110
111 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
112
113 spin_unlock_irqrestore(&idi48gpio->lock, flags);
114 }
115
116 return;
117 }
118}
119
120static void idi_48_irq_unmask(struct irq_data *data)
121{
122 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
123 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
124 const unsigned offset = irqd_to_hwirq(data);
125 unsigned i;
126 unsigned mask;
127 unsigned boundary;
128 unsigned prev_irq_mask;
129 unsigned long flags;
130
131 for (i = 0; i < 48; i += 8)
132 if (offset < i + 8) {
133 mask = BIT(offset - i);
134 boundary = i / 8;
135 prev_irq_mask = idi48gpio->irq_mask[boundary];
136
137 idi48gpio->irq_mask[boundary] |= mask;
138
139 if (!prev_irq_mask) {
140 idi48gpio->cos_enb |= BIT(boundary);
141
142 spin_lock_irqsave(&idi48gpio->lock, flags);
143
144 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
145
146 spin_unlock_irqrestore(&idi48gpio->lock, flags);
147 }
148
149 return;
150 }
151}
152
153static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
154{
155 /* The only valid irq types are none and both-edges */
156 if (flow_type != IRQ_TYPE_NONE &&
157 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
158 return -EINVAL;
159
160 return 0;
161}
162
163static struct irq_chip idi_48_irqchip = {
164 .name = "104-idi-48",
165 .irq_ack = idi_48_irq_ack,
166 .irq_mask = idi_48_irq_mask,
167 .irq_unmask = idi_48_irq_unmask,
168 .irq_set_type = idi_48_irq_set_type
169};
170
171static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
172{
173 struct idi_48_gpio *const idi48gpio = dev_id;
174 unsigned long cos_status;
175 unsigned long boundary;
176 unsigned long irq_mask;
177 unsigned long bit_num;
178 unsigned long gpio;
179 struct gpio_chip *const chip = &idi48gpio->chip;
180
181 spin_lock(&idi48gpio->ack_lock);
182
183 spin_lock(&idi48gpio->lock);
184
185 cos_status = inb(idi48gpio->base + 7);
186
187 spin_unlock(&idi48gpio->lock);
188
189 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
190 if (cos_status & BIT(6)) {
191 spin_unlock(&idi48gpio->ack_lock);
192 return IRQ_NONE;
193 }
194
195 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
196 cos_status &= 0x3F;
197
198 for_each_set_bit(boundary, &cos_status, 6) {
199 irq_mask = idi48gpio->irq_mask[boundary];
200
201 for_each_set_bit(bit_num, &irq_mask, 8) {
202 gpio = bit_num + boundary * 8;
203
204 generic_handle_irq(irq_find_mapping(chip->irqdomain,
205 gpio));
206 }
207 }
208
209 spin_unlock(&idi48gpio->ack_lock);
210
211 return IRQ_HANDLED;
212}
213
214static int __init idi_48_probe(struct platform_device *pdev)
215{
216 struct device *dev = &pdev->dev;
217 struct idi_48_gpio *idi48gpio;
218 const unsigned base = idi_48_base;
219 const unsigned extent = 8;
220 const char *const name = dev_name(dev);
221 int err;
222 const unsigned irq = idi_48_irq;
223
224 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
225 if (!idi48gpio)
226 return -ENOMEM;
227
228 if (!devm_request_region(dev, base, extent, name)) {
229 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
230 base, base + extent);
231 return -EBUSY;
232 }
233
234 idi48gpio->chip.label = name;
235 idi48gpio->chip.parent = dev;
236 idi48gpio->chip.owner = THIS_MODULE;
237 idi48gpio->chip.base = -1;
238 idi48gpio->chip.ngpio = 48;
239 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
240 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
241 idi48gpio->chip.get = idi_48_gpio_get;
242 idi48gpio->base = base;
243 idi48gpio->irq = irq;
244
245 spin_lock_init(&idi48gpio->lock);
246
247 dev_set_drvdata(dev, idi48gpio);
248
249 err = gpiochip_add_data(&idi48gpio->chip, idi48gpio);
250 if (err) {
251 dev_err(dev, "GPIO registering failed (%d)\n", err);
252 return err;
253 }
254
255 /* Disable IRQ by default */
256 outb(0, base + 7);
257 inb(base + 7);
258
259 err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
260 handle_edge_irq, IRQ_TYPE_NONE);
261 if (err) {
262 dev_err(dev, "Could not add irqchip (%d)\n", err);
263 goto err_gpiochip_remove;
264 }
265
266 err = request_irq(irq, idi_48_irq_handler, IRQF_SHARED, name,
267 idi48gpio);
268 if (err) {
269 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
270 goto err_gpiochip_remove;
271 }
272
273 return 0;
274
275err_gpiochip_remove:
276 gpiochip_remove(&idi48gpio->chip);
277 return err;
278}
279
280static int idi_48_remove(struct platform_device *pdev)
281{
282 struct idi_48_gpio *const idi48gpio = platform_get_drvdata(pdev);
283
284 free_irq(idi48gpio->irq, idi48gpio);
285 gpiochip_remove(&idi48gpio->chip);
286
287 return 0;
288}
289
290static struct platform_device *idi_48_device;
291
292static struct platform_driver idi_48_driver = {
293 .driver = {
294 .name = "104-idi-48"
295 },
296 .remove = idi_48_remove
297};
298
299static void __exit idi_48_exit(void)
300{
301 platform_device_unregister(idi_48_device);
302 platform_driver_unregister(&idi_48_driver);
303}
304
305static int __init idi_48_init(void)
306{
307 int err;
308
309 idi_48_device = platform_device_alloc(idi_48_driver.driver.name, -1);
310 if (!idi_48_device)
311 return -ENOMEM;
312
313 err = platform_device_add(idi_48_device);
314 if (err)
315 goto err_platform_device;
316
317 err = platform_driver_probe(&idi_48_driver, idi_48_probe);
318 if (err)
319 goto err_platform_driver;
320
321 return 0;
322
323err_platform_driver:
324 platform_device_del(idi_48_device);
325err_platform_device:
326 platform_device_put(idi_48_device);
327 return err;
328}
329
330module_init(idi_48_init);
331module_exit(idi_48_exit);
332
333MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
334MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
335MODULE_LICENSE("GPL v2");