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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_IO_APIC_H
3#define _ASM_X86_IO_APIC_H
4
5#include <linux/types.h>
6#include <asm/mpspec.h>
7#include <asm/apicdef.h>
8#include <asm/irq_vectors.h>
9#include <asm/x86_init.h>
10/*
11 * Intel IO-APIC support for SMP and UP systems.
12 *
13 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
14 */
15
16/*
17 * The structure of the IO-APIC:
18 */
19union IO_APIC_reg_00 {
20 u32 raw;
21 struct {
22 u32 __reserved_2 : 14,
23 LTS : 1,
24 delivery_type : 1,
25 __reserved_1 : 8,
26 ID : 8;
27 } __attribute__ ((packed)) bits;
28};
29
30union IO_APIC_reg_01 {
31 u32 raw;
32 struct {
33 u32 version : 8,
34 __reserved_2 : 7,
35 PRQ : 1,
36 entries : 8,
37 __reserved_1 : 8;
38 } __attribute__ ((packed)) bits;
39};
40
41union IO_APIC_reg_02 {
42 u32 raw;
43 struct {
44 u32 __reserved_2 : 24,
45 arbitration : 4,
46 __reserved_1 : 4;
47 } __attribute__ ((packed)) bits;
48};
49
50union IO_APIC_reg_03 {
51 u32 raw;
52 struct {
53 u32 boot_DT : 1,
54 __reserved_1 : 31;
55 } __attribute__ ((packed)) bits;
56};
57
58struct IO_APIC_route_entry {
59 union {
60 struct {
61 u64 vector : 8,
62 delivery_mode : 3,
63 dest_mode_logical : 1,
64 delivery_status : 1,
65 active_low : 1,
66 irr : 1,
67 is_level : 1,
68 masked : 1,
69 reserved_0 : 15,
70 reserved_1 : 17,
71 virt_destid_8_14 : 7,
72 destid_0_7 : 8;
73 };
74 struct {
75 u64 ir_shared_0 : 8,
76 ir_zero : 3,
77 ir_index_15 : 1,
78 ir_shared_1 : 5,
79 ir_reserved_0 : 31,
80 ir_format : 1,
81 ir_index_0_14 : 15;
82 };
83 struct {
84 u64 w1 : 32,
85 w2 : 32;
86 };
87 };
88} __attribute__ ((packed));
89
90struct irq_alloc_info;
91struct ioapic_domain_cfg;
92
93#define IOAPIC_MAP_ALLOC 0x1
94#define IOAPIC_MAP_CHECK 0x2
95
96#ifdef CONFIG_X86_IO_APIC
97
98/*
99 * # of IO-APICs and # of IRQ routing registers
100 */
101extern int nr_ioapics;
102
103extern int mpc_ioapic_id(int ioapic);
104extern unsigned int mpc_ioapic_addr(int ioapic);
105
106/* # of MP IRQ source entries */
107extern int mp_irq_entries;
108
109/* MP IRQ source entries */
110extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
111
112/* 1 if "noapic" boot option passed */
113extern int skip_ioapic_setup;
114
115/* 1 if "noapic" boot option passed */
116extern int noioapicquirk;
117
118/* -1 if "noapic" boot option passed */
119extern int noioapicreroute;
120
121extern u32 gsi_top;
122
123extern unsigned long io_apic_irqs;
124
125#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
126
127/*
128 * If we use the IO-APIC for IRQ routing, disable automatic
129 * assignment of PCI IRQ's.
130 */
131#define io_apic_assign_pci_irqs \
132 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
133
134struct irq_cfg;
135extern void ioapic_insert_resources(void);
136extern int arch_early_ioapic_init(void);
137
138extern int save_ioapic_entries(void);
139extern void mask_ioapic_entries(void);
140extern int restore_ioapic_entries(void);
141
142extern void setup_ioapic_ids_from_mpc(void);
143extern void setup_ioapic_ids_from_mpc_nocheck(void);
144
145extern int mp_find_ioapic(u32 gsi);
146extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
147extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
148 struct irq_alloc_info *info);
149extern void mp_unmap_irq(int irq);
150extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
151 struct ioapic_domain_cfg *cfg);
152extern int mp_unregister_ioapic(u32 gsi_base);
153extern int mp_ioapic_registered(u32 gsi_base);
154
155extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
156 int node, int trigger, int polarity);
157
158extern void mp_save_irq(struct mpc_intsrc *m);
159
160extern void disable_ioapic_support(void);
161
162extern void __init io_apic_init_mappings(void);
163extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
164extern void native_restore_boot_irq_mode(void);
165
166static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
167{
168 return x86_apic_ops.io_apic_read(apic, reg);
169}
170
171extern void setup_IO_APIC(void);
172extern void enable_IO_APIC(void);
173extern void clear_IO_APIC(void);
174extern void restore_boot_irq_mode(void);
175extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
176extern void print_IO_APICs(void);
177#else /* !CONFIG_X86_IO_APIC */
178
179#define IO_APIC_IRQ(x) 0
180#define io_apic_assign_pci_irqs 0
181#define setup_ioapic_ids_from_mpc x86_init_noop
182static inline void ioapic_insert_resources(void) { }
183static inline int arch_early_ioapic_init(void) { return 0; }
184static inline void print_IO_APICs(void) {}
185#define gsi_top (NR_IRQS_LEGACY)
186static inline int mp_find_ioapic(u32 gsi) { return 0; }
187static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
188 struct irq_alloc_info *info)
189{
190 return gsi;
191}
192
193static inline void mp_unmap_irq(int irq) { }
194
195static inline int save_ioapic_entries(void)
196{
197 return -ENOMEM;
198}
199
200static inline void mask_ioapic_entries(void) { }
201static inline int restore_ioapic_entries(void)
202{
203 return -ENOMEM;
204}
205
206static inline void mp_save_irq(struct mpc_intsrc *m) { }
207static inline void disable_ioapic_support(void) { }
208static inline void io_apic_init_mappings(void) { }
209#define native_io_apic_read NULL
210#define native_restore_boot_irq_mode NULL
211
212static inline void setup_IO_APIC(void) { }
213static inline void enable_IO_APIC(void) { }
214static inline void restore_boot_irq_mode(void) { }
215
216#endif
217
218#endif /* _ASM_X86_IO_APIC_H */
1#ifndef _ASM_X86_IO_APIC_H
2#define _ASM_X86_IO_APIC_H
3
4#include <linux/types.h>
5#include <asm/mpspec.h>
6#include <asm/apicdef.h>
7#include <asm/irq_vectors.h>
8#include <asm/x86_init.h>
9/*
10 * Intel IO-APIC support for SMP and UP systems.
11 *
12 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
13 */
14
15/* I/O Unit Redirection Table */
16#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
17#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
18#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
19#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
20#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
21#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
22#define IO_APIC_REDIR_MASKED (1 << 16)
23
24/*
25 * The structure of the IO-APIC:
26 */
27union IO_APIC_reg_00 {
28 u32 raw;
29 struct {
30 u32 __reserved_2 : 14,
31 LTS : 1,
32 delivery_type : 1,
33 __reserved_1 : 8,
34 ID : 8;
35 } __attribute__ ((packed)) bits;
36};
37
38union IO_APIC_reg_01 {
39 u32 raw;
40 struct {
41 u32 version : 8,
42 __reserved_2 : 7,
43 PRQ : 1,
44 entries : 8,
45 __reserved_1 : 8;
46 } __attribute__ ((packed)) bits;
47};
48
49union IO_APIC_reg_02 {
50 u32 raw;
51 struct {
52 u32 __reserved_2 : 24,
53 arbitration : 4,
54 __reserved_1 : 4;
55 } __attribute__ ((packed)) bits;
56};
57
58union IO_APIC_reg_03 {
59 u32 raw;
60 struct {
61 u32 boot_DT : 1,
62 __reserved_1 : 31;
63 } __attribute__ ((packed)) bits;
64};
65
66struct IO_APIC_route_entry {
67 __u32 vector : 8,
68 delivery_mode : 3, /* 000: FIXED
69 * 001: lowest prio
70 * 111: ExtINT
71 */
72 dest_mode : 1, /* 0: physical, 1: logical */
73 delivery_status : 1,
74 polarity : 1,
75 irr : 1,
76 trigger : 1, /* 0: edge, 1: level */
77 mask : 1, /* 0: enabled, 1: disabled */
78 __reserved_2 : 15;
79
80 __u32 __reserved_3 : 24,
81 dest : 8;
82} __attribute__ ((packed));
83
84struct IR_IO_APIC_route_entry {
85 __u64 vector : 8,
86 zero : 3,
87 index2 : 1,
88 delivery_status : 1,
89 polarity : 1,
90 irr : 1,
91 trigger : 1,
92 mask : 1,
93 reserved : 31,
94 format : 1,
95 index : 15;
96} __attribute__ ((packed));
97
98struct irq_alloc_info;
99struct ioapic_domain_cfg;
100
101#define IOAPIC_AUTO -1
102#define IOAPIC_EDGE 0
103#define IOAPIC_LEVEL 1
104
105#define IOAPIC_MASKED 1
106#define IOAPIC_UNMASKED 0
107
108#define IOAPIC_POL_HIGH 0
109#define IOAPIC_POL_LOW 1
110
111#define IOAPIC_DEST_MODE_PHYSICAL 0
112#define IOAPIC_DEST_MODE_LOGICAL 1
113
114#define IOAPIC_MAP_ALLOC 0x1
115#define IOAPIC_MAP_CHECK 0x2
116
117#ifdef CONFIG_X86_IO_APIC
118
119/*
120 * # of IO-APICs and # of IRQ routing registers
121 */
122extern int nr_ioapics;
123
124extern int mpc_ioapic_id(int ioapic);
125extern unsigned int mpc_ioapic_addr(int ioapic);
126
127/* # of MP IRQ source entries */
128extern int mp_irq_entries;
129
130/* MP IRQ source entries */
131extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
132
133/* 1 if "noapic" boot option passed */
134extern int skip_ioapic_setup;
135
136/* 1 if "noapic" boot option passed */
137extern int noioapicquirk;
138
139/* -1 if "noapic" boot option passed */
140extern int noioapicreroute;
141
142extern u32 gsi_top;
143
144extern unsigned long io_apic_irqs;
145
146#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
147
148/*
149 * If we use the IO-APIC for IRQ routing, disable automatic
150 * assignment of PCI IRQ's.
151 */
152#define io_apic_assign_pci_irqs \
153 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
154
155struct irq_cfg;
156extern void ioapic_insert_resources(void);
157extern int arch_early_ioapic_init(void);
158
159extern int save_ioapic_entries(void);
160extern void mask_ioapic_entries(void);
161extern int restore_ioapic_entries(void);
162
163extern void setup_ioapic_ids_from_mpc(void);
164extern void setup_ioapic_ids_from_mpc_nocheck(void);
165
166extern int mp_find_ioapic(u32 gsi);
167extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
168extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
169 struct irq_alloc_info *info);
170extern void mp_unmap_irq(int irq);
171extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
172 struct ioapic_domain_cfg *cfg);
173extern int mp_unregister_ioapic(u32 gsi_base);
174extern int mp_ioapic_registered(u32 gsi_base);
175
176extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
177 int node, int trigger, int polarity);
178
179extern void mp_save_irq(struct mpc_intsrc *m);
180
181extern void disable_ioapic_support(void);
182
183extern void __init io_apic_init_mappings(void);
184extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
185extern void native_disable_io_apic(void);
186
187static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
188{
189 return x86_io_apic_ops.read(apic, reg);
190}
191
192extern void setup_IO_APIC(void);
193extern void enable_IO_APIC(void);
194extern void disable_IO_APIC(void);
195extern void setup_ioapic_dest(void);
196extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
197extern void print_IO_APICs(void);
198#else /* !CONFIG_X86_IO_APIC */
199
200#define IO_APIC_IRQ(x) 0
201#define io_apic_assign_pci_irqs 0
202#define setup_ioapic_ids_from_mpc x86_init_noop
203static inline void ioapic_insert_resources(void) { }
204static inline int arch_early_ioapic_init(void) { return 0; }
205static inline void print_IO_APICs(void) {}
206#define gsi_top (NR_IRQS_LEGACY)
207static inline int mp_find_ioapic(u32 gsi) { return 0; }
208static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
209 struct irq_alloc_info *info)
210{
211 return gsi;
212}
213
214static inline void mp_unmap_irq(int irq) { }
215
216static inline int save_ioapic_entries(void)
217{
218 return -ENOMEM;
219}
220
221static inline void mask_ioapic_entries(void) { }
222static inline int restore_ioapic_entries(void)
223{
224 return -ENOMEM;
225}
226
227static inline void mp_save_irq(struct mpc_intsrc *m) { }
228static inline void disable_ioapic_support(void) { }
229static inline void io_apic_init_mappings(void) { }
230#define native_io_apic_read NULL
231#define native_disable_io_apic NULL
232
233static inline void setup_IO_APIC(void) { }
234static inline void enable_IO_APIC(void) { }
235static inline void setup_ioapic_dest(void) { }
236
237#endif
238
239#endif /* _ASM_X86_IO_APIC_H */